Preliminary Data Sheet PD60214 Rev B

IR20153S & (PbF)

HIGH SIDE DRIVER WITH RECHARGE

Features Product Summary

• Floating channel designed for bootstrap operation
Fully operational up to 150V VOFFSET 150V max.
Tolerant to negative transient voltage, dV/dt immune
• Gate drive supply range from 5V to 20V
• Undervoltage lockout IO+/- 400mA @ VBS=7V,
• Internal recharge FET for bootstrap refresh 1.5A @ VBS=16V
• Internal deadtime of 11µs and 0.8µs
• CMOS Schmitt-triggered input logic VOUT 5-20V
• Output out of phase with input
• Reset input
ton/off 1.0 and 0.3 µs
• Split pull-up and pull-down gate drive pins
• Also available LEAD-FREE (PbF)
Package
Description
The IR20153S is a high voltage, high speed power MOSFET driver . Proprietary HVIC
and latch immune CMOS technologies enable ruggedized monolithic construction. The
logic input is compatible with standard CMOS output down to 3.3V. The output driver
features a high pulse current buffer stage designed for minimum cross-conduction. The
floating channel can be used to drive an N-channel power MOSFET in the high or low 8-Lead SOIC
side configuration which operates up to 150 volts.

Typical Connection

up to 150V

VCC VCC VB

IN IN HOH

GND HOL

RESET RESET VS

(Refer to Lead Assignments Load

for correct configuration).
This/These diagram(s) show
electrical connections only.
Please refer to our Applica-
tion Notes and DesignTips
for proper circuit board lay-
out.

www.irf.com 1
IR20153S & (PbF)

Absolute Maximum Ratings

Absolute maximum ratings indicate sustained limits beyond which damage to the device may occur. All voltage param-
eters are absolute voltages referenced to GND, all currents are defined positive into any lead. This is a stress only rating
and operation of the device at these or any conditions exceeding those indicated in the operational sections of this
specifications is not implied.

Symbol Definition Min. Max. Units

VB High side driver output stage voltage -5.0 170
VS High side floating supply offset voltage - 8.0 150
V
VHO Output voltage gate high connection VS - 0.3 VB + 0.3
VCC Low side fixed supply voltage -0.3 25
VIN Input voltage (IN and RESET) -0.3 VCC +0.3
dV/dt Allowable offset voltage slew rate — 50 V/nsec
TJ Junction temperature -55 150
TS Storage temperature -55 150
TL Lead temperature (soldering, 10 seconds) — 300 °C

Recommended Operating Conditions

The input/output logic timing diagram is shown in Fig. 2. For proper operation the device should be used within the
recommended conditions. All voltage parameters are absolute voltages referenced to GND. The VS offset rating is tested
with all suppliers biased at Vcc=5V and VBS=7V.
Symbol Definition Min. Max. Units
VB High side driver output stage voltage VS + 5 VS + 20
VS High side floating supply offset voltage -1.6 150
VHO Output voltage gate high connection VS VB V
VCC Supply voltage 5 20
VIN Input voltage (IN and RESET) 0 Vcc
TA Ambient temperature -55 150 °C

2 www.irf.com
 IR20153S & (PbF)

Electrical Characteristics
Unless otherwise specified, VCC = 5V, VBS = 7V, VS = 0V, IN = 0V, RES = 5V, load R = 50Ω, C = 6.8nF (see Figure 3).
Unless otherwise noted, these specifications apply for an operating ambient temperature of TA =25°C.

Symbol Definition Min. Typ. Max. Units Test Conditions

VCC Supply Characteristics
VCCUV+ VCC supply undervoltage positive going threshold — — 4.3 VCC rising from 0V

V
VCCUV- VCC supply undervoltage negative going threshold 2.5 — — VCC dropping
from 5V
VCCUVHYS VCC supply undervoltage lockout hysteresis 0.01 0.3 0.60
IQCC VCC supply current — — 400 uA VCC = 3.6V & 6.5V
VBS Supply Characteristics
VBSUV+ VBS supply undervoltage positive going threshold — — 4.3 V VBS rising from 0V
VBSUV- VBS supply undervoltage negative going threshold 2.5 — — VBS dropping
from 5V
VBSUVHYS VBS supply undervoltage lockout hysteresis 0.01 0.3 0.60
IQBS1 VBS supply current — — 100 µA static mode, VBS =
7V, IN = 0V or 5V
IQBS2 VBS supply current — — 200 µA static mode, VBS =
16V, IN = 0V or 5V
VB. VS Supply Characteristics
ILK Offset supply leakage current — — 50 µA VB = VS = 150V
Gate Driver Characteristics
Io+1 Peak output source current 250 400 — mA
Io+2 Peak output source current 800 1500 — mA VBS = 16V
tr1 Output rise time — 0.2 0.4 µsec
tr2 Output rise time — 0.1 0.2 µsec VBS = 16V
Io-1 Peak output sink current 250 400 — mA IN = 5V
Io-2 Peak output sink current 800 1500 — mA VBS = 16V, IN = 5V
tf1 Output fall time — 0.2 0.4 µsec IN = 5V
tf2 Output fall time — 0.1 0.2 µsec VBS = 16V, IN = 5V
ton Input-to-Output Turn-on propogation delay — 1.0 2.0 µsec
(50% input level to 10% output level)
toff Input-to-Output Turn-off propogation delay — 0.3 0.9 µsec
(50% input level to 90% output level)
tres,off RES-to-Output Turn-off propogation delay — 0.3 0.9 µsec
(50% input level to 90% [tphl] output levels)

www.irf.com 3
IR20153S & (PbF)

Electrical Characteristics
Unless otherwise specified, VCC = 5V, VBS = 7V, VS = 0V, IN = 0V, RES = 5V, load R = 50Ω, C = 6.8nF (see Figure 3).
Unless otherwise noted, these specifications apply for an operating ambient temperature of TA =25°C.

Symbol Definition Min. Typ. Max. Units Test Conditions

Gate
V Driver Characteristics
CC Supply Characteristics cont.
tres,on RES-to-Output Turn-On Propogation Delay - 1.0 2.0 µsec
(50% input level to 10% [tplh] output levels)
Input Characteristics
VINH High Logic Level Input Threshold 3 - - V
VINL Low Logic Level Input Threshold - - 1.4 V
RIN High Logic Level Input Resistance 40 100 220 kΩ
VH_RES High Logic Level RES Input Threshold 3 - - V
VL_RES Low Logic Level RES Input Threshold - - 1.4 V
RRES High Logic Level RES Input Resistance 40 100 220 kΩ
Recharge Characteristics (see Figure 3a)
ton_rech Recharge Transistor Turn-On Propogation Delay 7 11 15 µsec VS = 5V
toff_rech Recharge Transistor Turn-Off Propogation Delay - 0.3 0.9 µsec
VRECH Recharge Output Transistor On-State Voltage Drop - - 1.2 V IS = 1mA, IN = 5V
Deadtime Characteristics
DTHOFF High Side Turn-Off to Recharge gate Turn-On 7 11 15 µsec
DTHON Recharge gate Turn-Off to High Side Turn-On0. 0.4 0.8 1.5 µsec

4 www.irf.com
 IR20153S & (PbF)

A True table for Vcc, VBS, RESET, IN, HO and RechFET is shown as follows. This truth table is for ACTIVE
LOW IN.
Vcc VBS RESET- IN- HO RechFET
<VccUVLO- <VBSUVLO- HIGH HIGH OFF ON

<VccUVLO- <VBSUVLO- HIGH LOW OFF ON

<VccUVLO- <VBSUVLO- LOW HIGH OFF ON

<VccUVLO- <VBSUVLO- LOW LOW OFF ON

<VccUVLO- >VBSUVLO+ HIGH HIGH OFF ON

<VccUVLO- >VBSUVLO+ HIGH LOW OFF ON

<VccUVLO- >VBSUVLO+ LOW HIGH OFF ON

<VccUVLO- >VBSUVLO+ LOW LOW OFF ON

>VccUVLO+ <VBSUVLO- HIGH HIGH OFF ON

>VccUVLO+ <VBSUVLO- HIGH LOW OFF OFF

>VccUVLO+ <VBSUVLO- LOW HIGH OFF ON

>VccUVLO+ <VBSUVLO- LOW LOW OFF ON

>VccUVLO+ >VBSUVLO+ HIGH HIGH OFF ON1

>VccUVLO+ >VBSUVLO+ HIGH LOW ON OFF1

>VccUVLO+ >VBSUVLO+ LOW HIGH OFF ON1

>VccUVLO+ >VBSUVLO+ LOW LOW OFF ON1

RESET = HIGH indicates that high side MOSFET is allowed to be turned on.
RESET = LOW indicates that high side MOSFET is OFF.
IN = LOW indicates that high side MOSFET is on.
IN = HIGH indicates that high side MOSFET is off.
RechFET = ON indicates that the recharge MOSFET is on.
RechFET = OFF indicates that the recharge MOSFET is off.
1
Note: Refer to the RESET functionality graph of Figure 7, for VCC and VBS voltage ranges under which
the functionality is normal.

www.irf.com 5
IR20153S & (PbF)

Functional Block Diagram

VB

UV
DETECT

HV
LEVEL
SHIFT R Q
VCC PULSE R HOH
FILTER S
HOL

UV
DETECT PULSE
GEN
VS

RESET

LOGIC
DELAYS
RECHARGE
IN SWITCH

Lead Definitions and Assignments

Symbol Description
VCC Driver Supply
I IN- Driver Control Signal Input 1 VCC VB 8
GND Ground 2 IN- HOH 7
RESET Driver Enable Signal Input
3 GND HOL 6
VS MOSFET Source Connection
HOL MOSFET Gate Low Connection 4 RESET- VS 5
HOH MOSFET Gate High Connection
8-Lead SOIC
VB Driver Output Stage Supply

6 www.irf.com
 IR20153S & (PbF)

IN-

RESET-

HO-VS

Figure 1. Input/Output Functional Diagram

IN

RES

HOH,L

Tres,on Tres,off

Figure 1a. Reset Timing Diagram

www.irf.com 7
IR20153S & (PbF)

IN

RESET
5V

Vs

HOH,L
T on T off

Recharge OFF ON
FET
T off_rech Ton_rech

Figure 2. Input/Output Timing Diagram

90% 90%

10% 10%

Tr T
f

Figure 2a. Output Timing Diagram

8 www.irf.com
 IR20153S & (PbF)

5V 7V

VCC VB
50ohm

IN- HOH

GND HOL

50ohm 6.8nF
RESET- VS

Figure 3. Switching Time Test Circuit

5V 7V

VCC VB
50ohm

IN- HOH

GND HOL

50ohm 6.8nF
RESET- VS

5V

Figure 3a. Ton_rech and Toff_rech Test Circuit

www.irf.com 9
 IR20153S & (PbF)

3.4 2.8

3.2
2.5
3
Vinth+ (V)

VINth- (V)
2.2
2.8
1.9
2.6

2.4 1.6

2.2 1.3
4.4 4.7 5 5.3 5.6 5.9 6.2 6.5 4.4 4.7 5 5.3 5.6 5.9 6.2 6.5
Vsupply (V) Vsupply (V)

Figure 4. Positive Input and Reset Figure 5. Negative Input and Reset
Threshold Voltage vs. Vsupply Threshold Voltage vs. Vsupply

160 2.2

140 1.9

120 1.6
RIN (kohm)

I (mA)

100 1.3

80 1

60 0.7

40 0.4
-50 -25 0 25 50 75 100 125 0.6 0.8 1 1.2 1.4
T ( oC ) V (V)

Figure 6. Input and Reset Impedance Figure 7. Recharge FET I-V Curve
vs. Tem perature

10 www.irf.com
 IR20153S & (PbF)

35 2200

Output Sink Current (mA)

30 125oC 25oC -40C
-40oC 1800
25
1400
VBS (V)

20
125C
15 1000

10 600
5
200
0 5 10 15 20
3.4 3.8 4.2 4.6 5
VBS (V)
VCC (V)

Figure 9. Output Sink Current

Figure 8. Reset Functionality
vs. VBS
This graph explains the functionality limitation as a
function of VCC, VBS and temperature. Each curve on
the graph represents VCC Vs. VBS, for a particular
temperature. For each particular temperature and VCC,
the output is non-functional for any value of VBS above
the drawn curve. But for any value of VBS below the
curve the functionality is fine.

700 1300
Turn-on Propagation Delay (ns)
Output Source Current (mA)

650 1200
600
1100
550
1000
500
900
450

400 800
-50 0 50 100 150 -50 0 50 100 150

Temperature C)(o Temperature ( C)

o

Figure 10. Output Source Current Figure 11. Turn-on Propagation Delay
vs. Tem perature, VBS=7V vs. Tem perature, VBS=7V

www.irf.com 11
 IR20153S & (PbF)

RES-to-Output Turn-on Propagation Delay

320 1300
Turn-off Propagation Delay (ns)

1200
280
1100

(ns)
1000
240
900

200 800
-50 0 50 100 150 -50 0 50 100 150

Temperature ( C)
o Temperature ( C)
o

Figure 12. Turn-off Propagation Delay Figure 13. RES-to-Output Turn-on Propagation
vs. Tem perature, VBS=7V Delay vs. Tem perature, VBS=7V
High Logic Level Input Resistance (kohm
RES-to-Output Turn-off Propagation

350 200

300 175

250 150
Delay (ns)

200 125

150 100

100 75

50 50
-50 0 50 100 150 -50 0 50 100 150

Temperature (oC) Temperature (oC)

Figure 14. RES-to-Output Turn-off Propagation Figure 15. High Logic Level Input Resistance
Delay vs. Tem perature, VBS=7V vs. Tem perature, VBS=7V

12 www.irf.com
 IR20153S & (PbF)
High Logic Level RES Input Resistance

Recharge Transistor Turn-on Propagation

175 12

150
11

125
(kohm)

Delay (us)
10
100

9
75

50 8
-50 0 50 100 150 -50 0 50 100 150
Temperature ( C)
o Temperature ( C)
o

Figure 16. High Logic Level RES Input Resistance Figure 17. Recharge Transistor Turn-on
vs. Tem perature, VBS=7V Propagation Delay vs. Temperature, VBS=7V
High Side Turn-off to Recharge Gate Turn
Recharge Transistor Turn-off Propagation

320 11

300 10.5

280 10
Delay (ns)

260 9.5
on (us)

240 9

220 8.5

200 8
-50 0 50 100 150 -50 0 50 100 150
Temperature (oC) Temperature (oC)

Figure 18. Recharge Transistor Turn-off Figure 19. High Side Turn-off to Recharge Gate
Propagation Delay vs. Tem perature, VBS=7V Turn-on vs. Tem perature, VBS=7V

www.irf.com 13
IR20153S & (PbF)

Recharge Gate Turn-off to High Side Turn

1200

1000

800
on (ns)

600

400
-50 0 50 100 150
Temperature (oC)

Figure 20. Recharge Gate Turn-off to High Side

Turn-on vs. Tem perature, VBS=7V

Case outline
INCHES MILLIMETERS
D B DIM
MIN MAX MIN MAX
A 5 FOOTPRINT A .0532 .0688 1.35 1.75
A1 .0040 .0098 0.10 0.25
8X 0.72 [.028]
b .013 .020 0.33 0.51
8 7 6 5 c .0075 .0098 0.19 0.25
6 H D .189 .1968 4.80 5.00
E E .1497 .1574 3.80 4.00
0.25 [.010] A
1 2 3 4 6.46 [.255] e .050 BASIC 1.27 BASIC
e1 .025 BASIC 0.635 BASIC
H .2284 .2440 5.80 6.20
K .0099 .0196 0.25 0.50
L .016 .050 0.40 1.27
6X e 3X 1.27 [.050]
8X 1.78 [.070] y 0° 8° 0° 8°

e1 K x 45°
A
C y

0.10 [.004]
A1 8X L 8X c
8X b
7
0.25 [.010] C A B

NOTES: 5 DIMENSION DOES NOT INCLUDE MOLD PROTRUSIONS.

1. DIMENSIONING & TOLERANCING PER ASME Y14.5M-1994. MOLD PROTRUSIONS NOT TO EXCEED 0.15 [.006].
2. CONTROLLING DIMENSION: MILLIMETER 6 DIMENSION DOES NOT INCLUDE MOLD PROTRUSIONS.
MOLD PROTRUSIONS NOT TO EXCEED 0.25 [.010].
3. DIMENSIONS ARE SHOWN IN MILLIMETERS [INCHES].
7 DIMENSION IS THE LENGTH OF LEAD FOR SOLDERING TO
4. OUTLINE C ONFORMS TO JEDEC OUTLINE MS-012AA.
A SUBSTRATE.
01-6027
8-Lead SOIC 01-0021 11 (MS-012AA)

14 www.irf.com
 IR20153S & (PbF)

LEADFREE PART MARKING INFORMATION

Part number IRxxxxxx

Date code YWW? IR logo

Pin 1 ?XXXX
Identifier
Lot Code
? MARKING CODE (Prod mode - 4 digit SPN code)
P Lead Free Released
Non-Lead Free
Released
Assembly site code
Per SCOP 200-002

ORDER INFORMATION

Basic Part (Non-Lead Free) Leadfree Part

8-Lead SOIC IR20153S order IR20153S 8-Lead SOIC IR20153S order IR20153SPbF

Thisproduct has been designed and qualified for the industrial market.
Qualification Standards can be found on IR’s Web Site http://www.irf.com
Data and specifications subject to change without notice.
IR WORLD HEADQUARTERS: 233 Kansas St., El Segundo, California 90245 Tel: (310) 252-7105
10/25/2004

www.irf.com 15