COMPUTER SYSTEM ARCHITECTURE SET 1

Questions 1 To 10

1. For two variables, n=2 , the number of possible Boolean functions is

(a) 4
(b) 8
(c) 16
(d) 12
(e) 2.
2. The one major advantage of CMOS is its,
(a) Low propagation delay
(b) High propagation delay
(c) Very low propagation delay
(d) Very high propagation delay
(e) No delay.
3. 64K memory contains how many words of 8 bits each?
(a) 65,536
(b) 64,536
(c) 65,436
(d) 65,546
(e) 65,556.
4. The simplest way to determine cache locations in which to store memory blocks is
the,
(a) Associative Mapping technique
(b) Direct Mapping technique
(c) Set-Associative Mapping technique
(d) Indirect Mapping technique
(e) Paging technique.
5. The sum of -6 and -13 using 2’s complement addition is,
(a) 11100011
(b) 11110011
(c) 11001100
(d) 11101101
(e) 11100001.
6. Which one of the following CPU registers holds the address of the instructions
(instructions in the program stored in memory) to be executed next?
(a) MAR (Memory address register)
(b) MBR (Memory Buffer Register)
(c) AC (Accumulator)
(d) IR (Instruction Register)
(e) PC (Program Counter).
7. What are the major components of a CPU?
(a) Control Unit, Register Set, Arithmetic Logic Unit
 (b) Control Unit, Memory Unit, Arithmetic Logic Unit
(c) Memory Unit, Arithmetic Logic Unit, Auxiliary Memory
(d) Register Set, Control Unit, Memory Unit
(e) Register Set, Control Unit, Auxiliary Memory.
8. Given the characteristic table of a JK flip-flop, find the missing output value.
J        K       Q(t+1)
0       0        Q(t)
0       1        0
1       0        1
1       1        ---
(a) Q(t)
(b) Q’(t+1)
(c) 1
(d) Q’(t)
(e) Q(t+1).
9. What is Q, when S = 1 and R = 1 for SR flip-flop?
(a) No Change
(b) Clear to 0
(c) Set to 1
(d) Complement of previous output
(e) Indeterminate.
10 What does T stands for in T flip-flop?
. (a) Top
(b) Type
(c) Toggle
(d) Tickle
(e) Tip.

Answers

1. Answer :       (a)

Reason : The AND, and OR functions are only two of a total of 16 possible functions
formed with two binary variables. Therefore, for two variables n=2, and the
number of possible Boolean functions is 16.
2. Answer :       (a)
Reason : This means that it is not practical for use in systems requiring high-speed
operations. The characteristic parameters for the CMOS gate depend on the power
supply voltage VDD that is used. The power dissipation increases with increase in
voltage supply. The propagation delay decreases with increase in voltage supply
and the noise margin is estimated to be about 40% of the voltage supply value.
3. Answer :       (a)
Reason : Consider the 20-bit logical address. The 4-bit segment number specifies one of
 16 possible segments. The 8-bit page number can specify up to 256 pages, and the
8-bit word field implies a page size of 256 words. This configuration allows each
segment to have any number of pages up to 256. the smallest possible segment
will have one page of 256 words. The largest possible segment will have 256
pages, for a total of 256*256 = 65,536 which means 64K words.
4. Answer :       (b)
Reason : Associative memories are expensive compared to random-access memories
because of the added logic associated with each cell. Therefore, the simplest way
to determine cache locations in which to store memory blocks is the Direct
Mapping.
5. Answer :       (d)
Reason : 2’s complement of -6  =  11111010
2’s complement of -13 = 11110011
Add the two numbers in their 2’s complement form, including their sign bits and
discard any carry out of the sign (leftmost) bit position. So the answer is
11101101 (-19).
-6    11111010
-13  11110011
----------------------
-19  11101101
6. Answer :       (e)
Reason : Program Counter (PC) keeps track of the instruction of the program stored in
memory.
7. Answer :       (a)
Reason :   The major components of CPU are Control Unit, Register Set, and Arithmetic
Logic Unit.
8. Answer :       (d)
Reason :   The next state is a complement state.
9. Answer :       (e)
Reason : When R = 1 and S = 1, race will always end with Master Latch in the logic 1
state, but this will not be certain with real components.
10 Answer :       (c)
. Reason : Toggle flip-flop as it changes its output on each clock edge.
COMPUTER SYSTEM ARCHITECTURE SET 2
Questions 11 To 20

11 In which type of flip-flop the indeterminate condition of the SR flip-flop (when S=R=1) is
. eliminated?
(a) Edge-triggered flip-flop
(b) JK flip-flop
(c) D flip-flop
(d) T flip-flop
(e) Master-slave flipflop.
12 The bulk of the binary information in a digital computer is stored in memory, but all
. computations are done in
(a) Timing Control
(b) Memory Registers
(c) Processor Registers
(d) Program Control
(e) Secondary Memory.
13 Information transfer from one register to another is designated in symbolic form by means of
. (a) Control Function
(b) Op Code
(c) Registers
(d) Replacement Operator
(e) Arrow Operator.
14 The registers found in the processor unit are
. (a) Operational registers
(b) Memory registers
(c) Storage registers
(d) Binary registers
(e) Temporary registers.
15 Techniques that automatically move program and data blocks into the physical main memory
. when they are required for execution are called
(a) Associative-Mapping techniques
(b) Main Memory techniques
(c) Virtual Memory techniques
(d) Cache Memory techniques
(e) Paging techniques.
16 What digit is added to the Excess-3 code generation?
. (a) 3
(b) 4
(c) 2
(d) 1
(e) 0.
17 The processor, ---------- and I/O Devices are interconnected by means of a common bus.
 . (a) Cache Memory
(b) Auxiliary Memory
(c) Virtual Memory
(d) Main Memory
(e) Extended Memory.
18 System Software usually includes a program called a --------, which helps the programmer
. find errors in a program.
(a) Write Buffer
(b) Read Buffer
(c) Debugger
(d) Both (a) and (c) above
(e) Both (b) and (c) above.
19 To convert octal code to binary code which of the following digital functions should be used?
. (a) Decoder
(b) Encoder
(c) Multiplexer
(d) Demultiplexer
(e) Binary adder.
20 A full-adder is simply a connection of two half-adders joined by
. (a) AND gate
(b) OR gate
(c) NAND gate
(d) NOR gate
(e) XOR gate.

Answers

11 Answer :       (b)

.
Reason : To SR flip-flop two new connections from Q and Q’ outputs back to original input gates
eliminate the indeterminate condition.
12 Answer :       (c)
.
Reason : The operation part of an instruction code specifies the operation to be performed. This
operation must be executed on some data stored in memory and/or processor registers.
An instruction code, therefore, must specify not only the operation, but also the register
or memory words where the operands are to be found, as well as the register or memory
words where the result is to be stored. For this reason, the bulk of binary information in a
digital computer is stored in memory, but all computations are done in Processor
Registers.
13 Answer :       (d)
.
Reason : A replacement operator consisting of the information transfer from one register to
another, is designated in symbolic form.
14 Answer :       (a)
.
Reason : Registers found in processor are called operational registers and in memory unit are
called storage registers.
 15 Answer :       (c)
.
Reason : A virtual memory system provides a mechanism for translating program-generated
addresses into correct main memory locations. This is done dynamically, while programs
are being executed in the CPU. The translation or mapping is handled automatically by
the hardware by means of a mapping table.
16 Answer :       (a)
.
Reason : Excess-3code generation takes 3 as excess to the binary code.
17 Answer :       (a)
. Reason : The Bus master is allowed to initiate data transfer on the bus.
18 Answer :       (c)
. Reason : Debugger is a program, which finds errors in program.
19 Answer :       (a)
.
Reason : Multiplexer is called as Data Selector in computers where Dynamic memory uses the
same address lines for both row and column addressing and a set of multiplexers is used
to first select row address and then switch to column address.
20 Answer :       (b)
.
Reason : A full-adder is simply a connection of two half-adders joined by a OR gate, and other
half-adder simplify the AND gate also.

COMPUTER SYSTEM ARCHITECTURE SET 3

Questions 21 to 30

21 A combinational circuit that converts binary information from n input lines to a maximum of  unique
. output lines is,

(a) Decoder
(b) Encoder
(c) Full-adder
(d) Full-subtractor
(e) Half-subtractor.

22 The correspondence between the main memory blocks and those in the cache is specified by
.
(a) Mapping function
(b) Replacement algorithm
 (c) Hit rate
(d) Miss penalty
(e) Segment function.

23 The CPU nearly delays its operation for one memory cycle, to allow direct memory I/O transfer. This
. process is called,

(a) Burst transfer

(b) Cycle waiting
(c) Cycle stealing
(d) Cycle interrupting
(e) Cycle execution.

24 The control condition is terminated with

.
(a) Comma
(b) Semicolon
(c) Colon
(d) Hash
(e) Dot.

25 What are the missing values in the truth table of a half-adder given below?
.
x       y       C      S

0       0       --       --

0       1       0       1

1       0       0       1

1       1       1       0

(a) x
(b) y
(c) 0
(d) 1
(e) Indeterminate.

26 What are the building blocks of combinational circuits?

.
(a) Flip-flops
(b) Logical gates
 (c) Latches
(d) Registers
(e) Decoders.

27 x + xy = x is called,
.
(a) Commutative Law
(b) Associative Law
(c) Distributive Law
(d) Absorption Law
(e) Identity Law.

28 What is BCO equivalent of 011111000?

.
(a) 370
(b) 307
(c) 703
(d) 730
(e) None of the above.

29 Boolean functions expressed as a --------- of minterms or ---------- of maxterms are said to be in a

. canonical form.

(a) Product, Sum

(b) Sum, Product
(c) Subtract, Divide
(d) Divide, Subtract
(e) Product, Divide.

30 Which of the following modes are used to handle data transfer to and from peripherals?
.
(a) Programmed I/O
(b) Interrupted-initiated I/O
(c) Direct memory access
(d) Programmed I/O, Interrupted-initiated I/O, Direct memory access
(e) Programmed I/O, Direct memory access.
 Answers

21 Answer :       (a)

.
Reason : Decoder uses address inputs as binary numbers and produces an output signal.

22 Answer :       (a)

.
Reason : The correspondence between the main memory blocks and those in the cache is specified by a
mapping function, because the basic characteristic of cache memory is fast access time.
Therefore, very little or no time must be wasted when searching for words in the cache.

23 Answer :       (c)

.
Reason : A technique called cycle stealing allows the DMA controller to transfer one data word at a time,
after which it must return control of buses to the CPU.

24 Answer :       (c)

.
Reason : The control condition is terminated with a colon.

25 Answer :       (c)

.
Reason :   When x = 0, y = 0 the corresponding carry and sum are 0,0.

26 Answer :       (b)

.
Reason : Logical gates are building blocks of combinational circuits whereas, flipflops are combination of
logic gates, registers are memory storages.

27 Answer :       (d)

.
Reason :   Absorption law :- x + xy = x = x (1+y)

28 Answer :       (a)

.
Reason : The binary number 011 111 000 represents the octal digits 3, 7, 0 from left to right distrubution
by three bits.

29 Answer :       (b)

.
Reason : Boolean functions expressed as a sum (ORing of terms) of minterms or maxterms (ANDing of
terms) are said to be in canonical form.

30 Answer :       (d)

.
Reason : All the options are used to handle data transfer to and from peripherals.