iW1710

Digital PWM Current-Mode Controller for Quasi-Resonant Operation

1.0 Features 2.0 Description

●● Primary-side feedback eliminates opto-isolators and The iW1710 is a high performance AC/DC power supply
simplifies design controller which uses digital control technology to build
peak current mode PWM flyback power supplies. The
●● Quasi-resonant operation for highest overall efficiency
device operates in quasi-resonant mode at heavy load to
●● EZ-EMI ® design to easily meet global EMI standards provide high efficiency along with a number of key built-in
protection features while minimizing the external component
●● Up to 130 kHz switching frequency enables small
count, simplifying EMI design and lowering the total bill of
adapter size
material cost. The iW1710 removes the need for secondary
●● Very tight output voltage regulation feedback circuitry while achieving excellent line and load
regulation. It also eliminates the need for loop compensation
●● No external compensation components required
components while maintaining stability over all operating
●● Complies with CEC/EPA no-load power consumption conditions. Pulse-by-pulse waveform analysis allows for a
and average efficiency regulations loop response that is much faster than traditional solutions,
resulting in improved dynamic load response. The built-in
●● Built-in output constant-current control with primary-side
current limit function enables optimized transformer design
feedback
in universal off-line applications over a wide input voltage
●● Low start-up current (10 µA typical) range.
●● Built-in soft start The ultra-low operating current at light load ensures that
●● Built-in short circuit protection and output overvoltage the iW1710 is ideal for applications targeting the newest
protection regulatory standards for average efficiency and standby
power.
●● Optional AC line under/overvoltage protection
●● PFM operation at light load 3.0 Applications
●● Current sense resistor short protection
●● Cable/DSL modems, WLAN access points and VOIP
●● Overtemperature Protection gateways.

N
VOUT
+
+
RTN

1 NC VCC 8

2 VSENSE OUTPUT 7

3 VIN ISENSE 6

4 SD GND 5

Optional U1
NTC iW1710
Thermistor

Figure 3.1 : Typical Application Circuit

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Digital PWM Current-Mode Controller for Quasi-Resonant Operation

4.0 Pinout Description

iW1710
1 NC VCC 8

2 VSENSE OUTPUT 7

3 VIN ISENSE 6

4 SD GND 5

Pin # Name Type Pin Description

1 NC - No connection.

2 VSENSE Analog Input Auxiliary voltage sense (used for primary side regulation).
3 VIN Analog Input Rectified AC line average voltage sense.
External shutdown control. Connect to ground through a resistor if not used.
4 SD Analog Input
(see section 10.16)
5 GND Ground Ground.

6 ISENSE Analog Input Primary current sense (used for cycle-by-cycle peak current control and limit).

7 OUTPUT Output Gate drive for external MOSFET switch.

8 VCC Power Input Power supply for control logic and voltage sense for power-on reset circuitry.

5.0 Absolute Maximum Ratings

Absolute maximum ratings are the parameter values or ranges which can cause permanent damage if exceeded. For
maximum safe operating conditions, refer to Electrical Characteristics in Section 6.0.

Parameter Symbol Value Units

DC supply voltage range (pin 8, ICC = 20mA max) VCC -0.3 to 18 V

DC supply current at VCC pin ICC 20 mA

Output (pin 7) -0.3 to 18 V

VSENSE input (pin 2, IVsense ≤ 10 mA) -0.7 to 4.0 V

VIN input (pin 3) -0.3 to 18 V

ISENSE input (pin 6) -0.3 to 4.0 V

SD input (pin 4) -0.3 to 18 V

Power dissipation at TA ≤ 25°C PD 526 mW

Maximum junction temperature TJ MAX 125 °C

Storage temperature TSTG –65 to 150 °C

Thermal Resistance Junction-to-Ambient θJA 160 °C/W

ESD rating per JEDEC JESD22-A114 2,000 V

Latch-Up test per JEDEC 78 ±100 mA

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Digital PWM Current-Mode Controller for Quasi-Resonant Operation

6.0 Electrical Characteristics

VCC = 12 V, -40°C ≤ TA ≤ 85°C, unless otherwise specified (Note 1)

Parameter Symbol Test Conditions Min Typ Max Unit

VIN SECTION (Pin 3)
Start-up low voltage threshold VINSTLOW TA= 25°C, positive edge 335 369 406 mV

Start-up current IINST VIN = 10 V, CVCC = 10 µF 10 15 µA

Shutdown low voltage threshold VUVDC TA= 25°C, negative edge 201 221 243 mV

Input impedance ZIN After start-up 25 kW

VSENSE SECTION (Pin 2)

Input leakage current IBVS VSENSE = 2 V 1 μA

Nominal voltage threshold VSENSE(NOM) TA=25°C, negative edge 1.523 1.538 1.553 V

Output OVP threshold - 01 (Note 2) VSENSE(MAX) TA=25°C, negative edge 1.754 1.846 1.938 V

TA=25°C, negative edge,

Output OVP threshold - 11 (Note 2) VSENSE(MAX) 1.797 1.892 1.987 V
Load = 100%

TA=25°C, negative edge,

Output OVP threshold - 21 (Note 2) VSENSE(MAX) 1.836 1.933 2.030 V
Load = 100 %

OUTPUT SECTION (Pin 7)

Output low level ON-resistance RDS(ON)LO ISINK = 5 mA 40 W

Output high level ON-resistance RDS(ON)-HP ISOURCE = 5 mA 75 W

TA = 25°C, CL = 330 pF
Rise time (Note 2) tR 200 300 ns
10% to 90%
TA = 25°C, CL = 330 pF
Fall time (Note 2) tF 40 60 ns
90% to 10%
Maximum switching frequency Any combination of
fSW(MAX) 130 140 kHz
-01, -11, -21 (Note 3) line and load
VCC SECTION (Pin 8)

Maximum operating voltage (Note 2) VCC(MAX) 16 V

Start-up threshold VCC(ST) VCC rising 10.8 12 13.2 V

Undervoltage lockout threshold VCC(UVL) VCC falling 5.5 6.0 6.6 V

ICCQ CL = 330 pF,
Operating current 3.5 5 mA
VSENSE = 1.5 V

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Digital PWM Current-Mode Controller for Quasi-Resonant Operation

6.0 Electrical Characteristics (cont.)

VCC = 12 V, -40°C ≤ TA ≤ 85°C, unless otherwise specified (Note 1)

Parameter Symbol Test Conditions Min Typ Max Unit

ISENSE SECTION (Pin 6)

Peak limit threshold VPEAK 1.045 1.1 1.155 V

Isense short protection reference VRSNS 0.127 0.15 0.173 V

CC regulation threshold limit (Note 2) VREG-TH 1.0 V

SD SECTION (Pin 4)

Shutdown threshold VSD-TH TA = 25°C 0.95 1.0 1.05 V

Shutdown threshold in Startup (Note 2) VSD-TH(ST) 1.2 V

Input leakage current IBVSD VSD = 1.0 V 1 µA

Pull down resistance RSD TA = 25°C 7916 8333 8750 W

Pull up current source ISD TA = 25°C 96 107 118 µA

Notes:
Note 1. Adjust VCC above the start-up threshold before setting at 12 V.
Note 2. These parameters are not 100% tested, guaranteed by design and characterization.
Note 3. Operating frequency varies based on the line and load conditions, see Theory of Operation for more details.

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Digital PWM Current-Mode Controller for Quasi-Resonant Operation

7.0 Typical Performance Characteristics

VCC Supply Start-up Current (µA)

VCC Start-up Threshold (V)

9.0 12.2

6.0 12.0

3.0 11.8

0.0 11.6
0.0 2.0 4.0 6.0 8.0 10.0 12.0 14.0 -50 -25 0 25 50 75 100 125
VCC (V) Ambient Temperature (°C)

Figure 7.1 : VCC vs. VCC Supply Start-up Current Figure 7.2 : Start-Up Threshold vs. Temperature
% Deviation of Switching Frequency from Ideal

Internal Reference Voltage (V)

0.3 % 1.548

-0.3 % 1.538

-0.9 % 1.528

-1.5 % 1.518
-50 -25 0 25 50 75 100 125 -50 -25 0 25 50 75 100 125
Ambient Temperature (°C) Ambient Temperature (°C)

Figure 7.3 : % Deviation of Switching Frequency to Figure 7.4 : Internal Reference vs. Temperature
Ideal Switching Frequency vs. Temperature

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Digital PWM Current-Mode Controller for Quasi-Resonant Operation

8.0 Functional Block Diagram

VIN 3 8 VCC

ENABLE ENABLE Start-up

ADC
ZVin VIN_A
25 kΩ 0.2 V ~ 2.0 V

Gate
7 OUTPUT
VVMS Driver
Digital
Signal 60 kΩ
VSENSE 2 VFB Logic
Conditioning
Control
ISD
Detection Switch

+ 6 ISENSE
VOCP 1.1 V
–
+
SD 4
– DAC
VSD-TH
RSD
IPEAK +
– –
GND VIPK
5 0V~1V

Figure 8.1 : iW1710 Functional Block Diagram

9.0 Theory of Operation

The iW1710 is a digital controller which uses a proprietary control algorithm to reduce system design time and improve
primary-side control technology to eliminate the opto- reliability.
isolated feedback and secondary regulation circuits required
in traditional designs. This results in a low-cost solution for Furthermore, accurate secondary constant-current operation
AC/DC adapters. The iW1710 uses Critical Discontinuous is achieved without the need for any secondary-side sense
Conduction Mode (CDCM) or Pulse Width Modulation and control circuits.
(PWM) mode at high output power levels and switches to
Pulse Frequency Modulation (PFM) mode at light load to The built-in protection features include overvoltage protection
minimize power dissipation to meet EPA 2.0 specification. (OVP), output short circuit protection (SCP) and soft-start,
Furthermore, iWatt’s digital control technology enables fast AC line brown out, overcurrent protection, and Isense fault
dynamic response, tight output regulation, and full featured protection. Also the iW1710 automatically shuts down if it
circuit protection with primary-side control. detects any of its sense pins to be either open or short.

Referring to the block diagram in Figure 8.1, the digital logic iWatt’s digital control scheme is specifically designed to
control block generates the switching on-time and off-time address the challenges and trade-offs of power conversion
information based on the line voltage and the output voltage design. This innovative technology is ideal for balancing new
feedback signal and provides commands to dynamically regulatory requirements for green mode operation with more
control the external MOSFET current. The system loop is practical design considerations such as lowest possible cost,
compensated internally by a digital error amplifier. Adequate smallest size and highest performance output control.
system phase and gain margin are guaranteed by design
and no external analog components are required for loop
compensation. The iW1710 uses an advanced digital

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9.1 Pin Detail If at any time the VCC voltage drops below VCC(UVL) threshold
then all the digital logic is reset. At this time VIN switch turns
Pin 2 – VSENSE off so that the VCC capacitor can be charged up again towards
Sense signal input from auxiliary winding. This provides the the start-up threshold.
secondary voltage feedback used for output regulation. Start-up
Sequencing
Pin 3 – VIN

Sense signal input from the rectified line voltage. VIN is used
VIN
for line regulation. The input line voltage is scaled down
using a resistor network. It is used for input undervoltage VCC(ST)
and overvoltage protection. This pin also provides the supply
current to the IC during start-up.
VCC
Pin 4 – SD

External shutdown control. If the shutdown control is not

used, this pin should be connected to GND via a resistor. ENABLE
(see Section 10.16).

Pin 5 – GND Figure 9.1 : Start-up Sequencing Diagram

Ground. 9.3 Understanding Primary Feedback

Pin 6 – ISENSE Figure 9.2 illustrates a simplified flyback converter. When the
switch Q1 conducts during tON(t), the current ig(t) is directly
Primary current sense. Used for cycle by cycle peak current drawn from rectified sinusoid vg(t). The energy Eg(t) is stored
control. in the magnetizing inductance LM. The rectifying diode D1 is
reverse biased and the load current IO is supplied by the
Pin 7 – OUTPUT secondary capacitor CO. When Q1 turns off, D1 conducts
Gate drive for the external MOSFET switch. and the stored energy Eg(t) is delivered to the output.
iin(t) ig(t) N:1 id(t)
+ VO
Pin 8 – VCC +
D1 IO
CO
Power supply for the controller during normal operation. The vg(t)
controller will start up when VCC reaches 12 V (typical) and vin(t) VAUX

will shut-down when the VCC voltage is below 6 V (typical). A – VAUX
decoupling capacitor should be connected between the VCC TS(t) Q1
pin and GND.

9.2 Start-up Figure 9.2 : Simplified Flyback Converter

Prior to start-up the VIN pin charges up the VCC capacitor
In order to tightly regulate the output voltage, the information
through the diode between VIN and VCC (see Figure 8.1).
about the output voltage and load current needs to be
When VCC is fully charged to a voltage higher than the start- accurately sensed. In the DCM flyback converter, this
up threshold VCC(ST), the ENABLE signal becomes active and information can be read via the auxiliary winding. During the
enables the control logic; the VIN switch turns on, and the Q1 on-time, the load current is supplied from the output filter
analog-to-digital converter begins to sense the input voltage. capacitor CO. The voltage across LM is vg(t), assuming the
Once the voltage on the VIN pin is above VINSTLOW, the iW1710 voltage dropped across Q1 is zero. The current in Q1 ramps
commences soft start function. An adaptive soft-start control up linearly at a rate of:
algorithm is applied at startup state, during which the initial
dig (t ) vg (t )
output pulses will be small and gradually get larger until the = (9.1)
full pulse width is achieved. The peak current is limited cycle dt LM

by cycle by Ipeak comparator.

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Digital PWM Current-Mode Controller for Quasi-Resonant Operation
At the end of on-time, the current has ramped up to: The real-time waveform analyzer in the iW1710 reads the
auxiliary waveform information cycle by cycle. The part then
vg (t ) × tON generates a feedback voltage VFB. The VFB signal precisely
ig _ peak (tON ) = (9.2)
LM represents the output voltage and is used to regulate the

output voltage.
This current represents a stored energy of:
9.4 Constant Voltage Operation
LM (9.3) After soft-start has been completed, the digital control block
E
= g × ig _ peak (tON ) 2
2 measures the output conditions. It determines output power
levels and adjusts the control system according to a light
When Q1 turns off, ig(t) in LM forces a reversal of polarities on load or a heavy load. If this is in the normal range, the device
all windings. Ignoring the communication-time caused by the operates in the Constant Voltage (CV) mode, and changes
leakage inductance LK at the instant of turn-off, the primary the pulse width (TON), and off time (TOFF) in order to meet the
current transfers to the secondary at a peak amplitude of: output voltage regulation requirements. During this mode
the PWM switching frequency is between 30 kHz and 130
NP
id =
(t ) × ig _ peak (tON ) kHz, depending on the line and load conditions.
NS
(9.4)
If less than 0.2 V is detected on VSENSE it is assumed that the
Assuming the secondary winding is master and the auxiliary auxiliary winding of the transformer is either open or shorted
winding is slave. and the iW1710 shuts down.

VAUX = VO x
NAUX 9.5 Dynamic Load Transient
NS
There are three components that compose the voltage drop
during a load transient event.

VDROP(cable) is the drop in voltage due to the increased current

going through the connector and/or the cable.
VAUX
0V VDROP= RCABLE × ∆I OUT
( cable )
(9.6)

The second component which affects the voltage drop during

NAUX load transient is VDROP(sense). This voltage drop is the drop in
VAUX = -VIN x
NP voltage before the VSENSE signal is able to show a significant
drop in output voltage. This is determined by Vmin or the
Figure 9.3 : Auxiliary Voltage Waveforms reference voltage at which a load transient is detected. The
smaller the Vmin is the smaller this drop in voltage is.
The auxiliary voltage is given by:
VOUT ( PCB )
N AUX ( )
VDROP ( sense ) = VSENSE ( nom ) − VSENSE (min) ×
VSENSE ( nom )
VAUX
= (VO + ∆V ) (9.5) (9.7)
NS

Keep in mind that a smaller Vmin is less tolerant of noise and
and reflects the output voltage as shown in Figure 9.3. distortions in VSENSE than a larger one.

The voltage at the load differs from the secondary voltage by The final drop in voltage is due to the time from when VSENSE
a diode drop and IR losses. The diode drop is a function of drops Vmin to when the next VSENSE signal appears. In the
current, as are IR losses. Thus, if the secondary voltage is worst case condition this is how much voltage drops during
always read at a constant secondary current, the difference the longest switching period.
between the output voltage and the secondary voltage will
be a fixed ΔV. Furthermore, if the voltage can be read when I OUT × TP (No load)
VDROP ( IC ) =
the secondary current is small; for example, at the knee of COUT
(9.8)
the auxiliary waveform (see Figure 9.3), then ΔV will also be
small. With the iW1710, ΔV can be ignored. A larger output capacitance in this case greatly reduces the
VDROP(IC).

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When the iW1710 detects the output voltage to be significantly To achieve this regulation the iW1710 senses the load
higher than the nominal output voltage, the device begins current indirectly through the primary current. The primary
to increase the switching period which lowers the output current is detected by the ISENSE pin through a resistor from
voltage. TPERIOD(CLAMP) refers to the maximum switching period the MOSFET source to ground.
to which the iW1710 increases to when an output voltage is
detected to be significantly over the nominal.
CV mode
During fast load changes the output voltage may not have VNOM

time to settle before the load is changed. Thus for this

Output Voltage
case when the power supply goes from light load to heavy
load prior to output voltage settling TPERIOD(CLAMP) substitutes

CC mode
TPERIOD(PFM) in equation 9.8.

9.6 Valley Mode Switching

In order to reduce switching losses in the MOSFET and
EMI, the iW1710 employs valley mode switching when
IOUT is above 50%. In valley mode switching, the MOSFET
switch is turned on at the point where the resonant voltage IOUT(CC)

across the drain and source of the MOSFET is at its lowest Output Current
point (see Figure 9.4). By switching at the lowest VDS, the Figure 9.5 : Power Envelope
switching loss will be minimized.

Gate
9.8 PFM Mode at Light Load
The iW1710 normally operates in a fixed frequency PWM or
critical discontinuous conduction mode when IOUT is greater
than approximately 10% of the specified maximum load
current. As the output load IOUT is reduced, the on-time tON
is decreased. At the moment that the load current drops
VDS below 10% of nominal, the controller transitions to Pulse
Frequency Modulation (PFM) mode. Thereafter, the on-
Figure 9.4 : Valley Mode Switching time will be modulated by the line voltage and the off-time
Turning on at the lowest VDS generates lowest dV/dt, thus is modulated by the load current. The device automatically
valley mode switching can also reduce EMI. To limit the returns to PWM mode when the load current increases.
switching frequency range, the iW1710 can skips valleys
(seen in the first cycle in Figure 9.4) when the switching 9.9 Variable Frequency Operation
frequency becomes too high. At each of the switching cycles, the falling edge of VSENSE
will be checked. If the falling edge of VSENSE is not detected,
iW1710 provides valley mode switching during constant the off-time will be extended until the falling edge of VSENSE
output current operation. So, the EMI and switching losses is detected. The maximum allowed transformer reset time
are still minimized during CC mode. This feature is superior is 120 µs. When the transformer reset time reaches this
to other quasi-resonant technologies which only support maximum reset time, the iW1710 immediately shuts off.
valley mode switching during constant voltage operation.
This is beneficial to applications, such as chargers, where 9.10 Internal Loop Compensation
the power supply mainly operates in CC mode.
The iW1710 incorporates an internal Digital Error Amplifier
9.7 Constant Current Operation with no requirement for external loop compensation. For a
typical power supply design, the loop stability is guaranteed
The constant current mode (CC mode) is useful in battery to provide at least 45 degrees of phase margin and –20dB
charging applications. During this mode of operation the of gain margin.
iW1710 will regulate the output current at a constant level
regardless of the output voltage, while avoiding continuous
conduction mode.

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9.11 Voltage Protection Functions OVP

Detection
OTP
Detection

The iW1710 includes functions that protect against input

line undervoltage (UV) and the output overvoltage (OVP). Vgate

The input voltage is monitored by the VIN pin and the output
voltage is monitored by the VSENSE pin. If the voltage at these Detection Switch
pins exceed their respective undervoltage or overvoltage
thresholds the iW1710 shuts down immediately. However, Detection Switch:
When switch is low SD pin is connected to R SD
the IC remains biased which discharges the VCC supply. Once When switch is high SD pin is connected to a current source ISD

VCC drops below the UVLO threshold, the controller resets

itself and then initiates a new soft-start cycle. The controller Figure 9.6 : SD Pin Detection Cycles
continues attempting start-up until the fault condition is
During an overvoltage monitor cycle the SD pin is connected
removed.
to a resistance internal to the chip, RSD, to ground and the
voltage on the SD pin is observed.
9.12 PCL, OC and SRS Protection
Peak-current limit (PCL), over-current protection (OCP) and
sense-resistor short protection (SRSP) are features built-into iW1710
the iW1710. With the ISENSE pin the iW1710 is able to monitor ISD
the primary peak current. This allows for cycle by cycle peak
current control and limit. When the primary peak current OVP / OTP
SD pin
multiplied by the ISENSE sense resistor is greater than 1.1 V Fault Detect

over current is detected and the IC will immediately turn

VSD-TH
off the gate drive until the next cycle. The output driver will
send out switching pulse in the next cycle, and the switching
pulse will continue if the OCP threshold is not reached; or,
the switching pulse will turn off again if the OCP threshold is
still reached.

If the ISENSE sense resistor is shorted there is a potential

danger of the over current condition not being detected. Figure 9.7 : Internal Function of SD Pin
Thus the IC is designed to detect this sense-resistor-short
fault after the start up, and shutdown immediately. The
VCC will be discharged since the IC remains biased. Once
VCC drops below the UVLO threshold, the controller resets
itself and then initiates a new soft-start cycle. The controller
continues attempting start-up, but does not fully start-up until
the fault condition is removed.

9.13 Shutdown
The shutdown (SD) pin in the iW1710 provides protection
against overtemperature (OTP) and additional overvoltage
(OVP) for the power supply.

The iW1710 switches between monitoring overtemperature

fault and overvoltage fault. In order to detect the resistance in
the NTC for an overtemperature fault, the iW1710 connects
a current source to the SD pin and checks the voltage on the
pin. To ensure that the current source is settled before the
voltage is checked both OTP and OVP are detected on the
last cycle, as depicted in figure 9.6.

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10.0 Design Example

10.1 Design Procedure Parameter Symbol Range
This design example gives the procedure for a flyback Input Voltage VIN 85 - 264 VRMS
converter using iW1710. Refer to Figure 12.1 for the
application circuit. The design objectives for this adapter are Frequency fIN 47 - 64 Hz
given in table 10.1. It meets UL, IEC, and CEC requirements. No Load Input PIN 100 mW
Output Voltage VOUT(Cable) 12.0 V
Determine the Design Specifications Output Current IOUT 1.2 A
(Vout, Iout_max, Vin_max, Vin_min, ƒline, Ripple specification)
Output Ripple VRIPPLE < 100 mV
Power Out POUT 15 W
Determine Part Number
EPA 2.0
h 80%
Efficiency
Determine Rvin Resistors

Table 10.1 : iW1710 Design Specification Table

Determine Turns Ratio
10.2 Determine Part Number
Based on design specifications, choose the most suitable
Determine Operating VinTon Limit
part for the design. For more information on the options see
section 14.0.
Determine Magnetizing Inductance
Use equation 10.1 for VOUT in the following calculations,
where VFD is the forward voltage of the output diode.
Determine Primary Turns
VOUT = VOUT (Cable) + VCableDrop + VFD
(10.1)
Determine Secondary Turns
For this example there is no cable so VCableDrop is 0 V ,
assuming VFD is 0.5, VOUT is:
Determine Bias Turns and Vcc Capacitance Determine Vsense Resistors VOUT= 12.0V + 0V + 0.5V= 12.5V

No
10.3 Input Selection
Can you wind this transformer ?

Yes
VIN resistors are chosen primarily to scale down the input
voltage for the IC. The default scale factor for the input
Determine Current Sensing Resistor voltage in the IC is 0.0043 and the internal impedance of
this pin is ZIN (25 kW). Therefore, the VIN resistors should
Determine Input Bulk Capacitance
equate to:
Z IN
RVin
= − Z IN
Determine Output Capacitance 0.0043 (10.2)

From equation 10.2, ideally RVin should be 5.79 MW. A lower

Determine Snubber Network
value of RVin can decrease the startup time of the power
supply. The value of RVin affects the (VINTON) limits of the IC.
Determine Current Sensing Filter
720V ⋅ms
(VIN ⋅ TON )limit =0.0043 × Z
IN
Finish ( RVin + Z IN )
(10.3)
135V ⋅ms
(VIN ⋅ TON )PFM =0.0043 ×
Z IN
Figure 10.1 : iW1710 Design Flow Chart
( RVin + Z IN )
(10.4)

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Digital PWM Current-Mode Controller for Quasi-Resonant Operation
For this example RVin is chosen to be 5.1 MΩ therefore, approximately 2 μs as a starting point and then adjusted
after the power supply is tested.
720V ⋅ ms
(VIN ⋅ TON )=
limit
0.0043 ×
25k W
= 635V ⋅ ms
( 5.1M W + 25k W )
Gate
135V ⋅ ms
(VIN ⋅ TON )PFM
= 0.0043 ×
25k W
= 119V ⋅ ms
( 5.1M W + 25k W )

Keep in mind, by changing RVin to be something other than

5.79 MW the minimum and maximum input voltage for start-
up also changes.
VDS
Since the iW1710 uses the exact scaled value of VIN for its TRESET TRES
calculations, there should be a filter capacitor on the input TON

pin to filter out any noise that may appear on the VIN signal. TPERIOD
This is especially important for line in surge conditions.
Figure 10.2 : VDS Timing
10.4 Turns Ratio
When both criterion are met then (VINTON)MAX can be
The maximum allowable turns ratio between the primary and
secondary winding is determined by the minimum detectable determined by equation 10.8.
−1
reset time of the transformer during PFM mode. (VIN ⋅ TON )max=
 
 f SW (max op) × 
1
+
1 

 VINDC (min) NTR × VOUT 
  
(VIN ⋅ TON )PFM 1
NTR (max) = where, f SW (max op) =
TP (QRmin) (10.8)
TRESET (min) × VOUT
(10.5)
Where VINDC(min) is the minimum input voltage across the bulk
Setting TRESET(min) at 1.5 μs,
capacitor. In order to avoid input undervoltage detection
119V ⋅ms during normal operation, VINDC(min) should be set above the
NTR (max)
= = 6.3
1.5ms × 12.5V
input undervoltage shutdown limit.
For this example a turns ratio of 6 is chosen. RVin + Z IN
(10.9)
VINDC (min) > ⋅ VUVDC
Z IN
Keep in mind in valley mode switching the higher the turns
ratio the lower the VDS turn-on voltage, which means less Assuming TRES is 2 μs then:
switch turn-on power loss. Also consider the voltage stress TP ( QR min ) > 10ms
on the MOSFET (VDS) is higher with an increase in turns
1
ratio. The voltage stress on the output diode is lower with TP' (QR min) > + 2ms= 11.1ms
110kHz
an increase in turns ratio respectively.
5.1M W + 25k W
10.5 Operating Maximum (VINTON) VINDC (min) >
25k W
× 0.369V =
76V

Maximum operating VINTON or (VINTON)MAX for valley mode To give some margin, we use 79 V for VINDC(min) in equation
switching is traditionally designed at full load and lowest 10.8,
input voltage. For the iW1710, two constraints (equation 72kHz and TP (QR min) =
Choosing, ƒ SW(max op) = 14ms
10.6 and 10.7) need to be satisfied so that indeed (VINTON)MAX −1

occurs at full load and lowest input voltage.

(VIN ⋅ TON )=
max
72kHz ×
 ( 791V + 6×12.5
1
V )
= 534V ⋅ms

1
TP (QR min) > (10.6) Also, to provide enough margin for component values,
100kHz
usually:
1
TP' (QR min) > + TRES (10.7)
110kHz (VIN ⋅ TON )max < (VIN ⋅ TON )limit × 0.85 (10.10)
TRES is the VDS resonant period as shown in Figure 10.2.
(VIN ⋅ TON )max < 635V ⋅ms × 0.85
= 540V ⋅ms
TRES can be estimated to be
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Digital PWM Current-Mode Controller for Quasi-Resonant Operation

Since we calculated 534 V·μs as our VIN·TON we have enough (VIN ⋅ TON )max
N PRI ≥
margin. Bmax × Ae
(10.13)
10.6 Magnetizing Inductance Where BMAX is maximum allowed flux density and Ae is the
A feature of the iW1710 is the lack of dependence on the core area. From the transformer core datasheet we find that
magnetizing inductance for the CC curve. for this example BMAX is 300 mT. For an EE19 core, Ae is
22.6 mm2.
Although the constant current limit does not depend on the
534V ⋅ms
magnetizing inductance, there are still restrictions on the N PRI ≥ 83.0T
=
magnetizing inductance. The maximum LM is limited by the 320mT × 20.1mm 2
amount of power that needs to come out of the transformer
For this example, we choose 90 primary turns.
in order for the power supply to regulate. This is given by:

LM (max) =
(VIN ⋅ TON )2max × f sw(max op) 10.8 Secondary Winding
2 × PXFMR (max)
(10.11) From the primary winding turns, we obtain the secondary
VOUT × I OUT
PXFMR (max) = winding.
hX
N PRI
N SEC =
NTR
Where ηX is the efficiency of the transformer, for this example (10.14)
we assume it’s 87 %.
Thus, in our example:
12.5V × 1.2 A
PXFMR (max) = 17.2W
=
0.87 90T
N=
SEC = 15T
2 6
( 534V ⋅ ms )
× 72kHz
=LM (max) = 0.597mH
2 × 17.2W
10.9 Bias Winding and VCC Capacitance
The minimum LM is limited by the maximum allowable peak VCC is the supply to the iW1710 and should be below 16 V.
primary current. VREG-TH corresponds to the maximum ISENSE The bias winding needs to ensure than VCC does not exceed
voltage. See section 10.11 to calculate RIsense. Therefore LM 16 V during normal operation.
is limited by:
N SEC (VCC + VFD )
2 × PXFMR ( max ) N BIAS =
LM (min) = VOUT
2 (10.15)
V
f SW (max op) ×  REG −TH 
 RIsense 
(10.12) Set VCC at around 10 V
2 × 12.5V × 1.2 A 15T × 10.5V
=LM (min) = 0.486mH N BIAS
= = 12T
( )
2
72kHz × 1.0V 12.5V
1.08W
Choose a value for NBIAS to be close to this number, for this
For this example, we choose LM to be 0.577 mH. example we choose 12 turns.
If these limits do not give enough tolerance for LM, increasing The VCC capacitor (CVcc) stores the VCC charge during IC
(VINTON)max can raise the maximum limit on LM. Take care not operation and the controller checks this voltage and makes
to go above (VINTON)limit. Also, keep in mind that if equation sure it is within range before starting and operating. The
10.6 and 10.7 are not met then (VINTON)max does not occur at startup time is a function of how quickly this capacitor can
full load and lowest input voltage, thus some of the equations charge up.
here would be invalid.
CVCC × VCC ( ST )
tSTART −UP =
10.7 Primary Winding VINAC × 2
− I INST
RVin
In order to keep the transformer from saturation, the (10.16)
maximum flux density must not be exceeded. Therefore the
minimum primary winding must meet: 10.10 VSENSE Resistors and Winding
The output voltage regulation is mainly determined by the
feedback signal VSENSE.
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Digital PWM Current-Mode Controller for Quasi-Resonant Operation
VSENSE VOUT _ PCB × K SENSE
= 6 × 0.5V
(10.17) RISNS = × 0.87 =1.08W
2 × 1.2 A
Where:
We recommend using ±1% tolerance resistors for RIsense.
RBVsns N
=K SENSE × Vsense
( RBVsns + RTVsns ) N SEC 10.12 Input Bulk Capacitor
(10.18)
The input bulk capacitor, CBULK is chosen to maintain enough
Internally, VSENSE is compared to a reference voltage input power to sustain constant output power even as the
VSENSE(nom). Where, VSENSE(nom) is 1.538 V. input voltage is dropping. In order for this to be true CBULK
VSENSE ( nom )
must be:
K SENSE =
VOUT _ PCB 
(10.19)
2 × PIN × 0.25 + 21π × arcsin  INDC (min)
V 
2 ×VINAC (min) 
  
1.538V CBULK =
K=
SENSE = 0.128
12.0V ( 2
2 × VINAC 2
(min) − VINDC (min) × f line ) (10.24)
VOUT (Cable ) × I OUT
From here we can find the ratio necessary for RBVsns and PIN =
RTVsns. For this example we set RTVsns to be 24 kΩ. Assuming hpower supply
we use the same winding for both VSENSE and VCC:
VINAC(min) is the minimum input voltage (rms) to be inputted
RBVSNS 12T into the power supply and fline is the lowest line frequency for
=0.128 ×
RBVSNS + 24k W 15T
the power supply (in this case 47 Hz). VINDC(min) is calculated
→ RBVSNS =4.57 k W from equation 10.9.

At this point the transformer design is complete. This would 12.5V × 1.2 A
= PIN = 20.8W
be a good time to confirm that this transformer is feasible to 0.72
build. 2 × 20.8W × 0.25 + 21π × arcsin
CBULK= 
( 79V
2 ×85Vac )= 39mF
10.11 Current Sense Resistor ( 2 × (85V ac )2 − ( 79V )2 ) × 47 Hz
The ISENSE resistor determines the maximum current output
of the power supply. The output current of the power supply 10.13 Output Capacitance
is determined by: The output capacitance affects both the steady state ripple
TRESET and the dynamic response of the power supply.
1
I OUT = 2
× NTR × I PRI ( pk ) × × hX
TPERIOD
(10.20) Assuming an ideal capacitor where ESR (equivalent series
resistance) and ESL (equivalent series inductance) are
When the maximum current output is achieved the voltage negligible then:
seen on the ISENSE pin (VIsense) should reach its maximum.
Thus, at constant current limit: QOUT
COUT (Steady State) =
VOUT ( ripple)
VIsense (CC ) (10.25)
I PRI ( pk ) =
RIsense
(10.21) The output capacitor supplies the load current when the
secondary current is below the output current.
Substituting this into equation 10.20 we get:
( )
2
TPERIOD LM × I SEC ( pk ) − I OUT
VIsense
= (CC ) × KC QOUT =
TRESET 2
2 × NTR × h X × VOUT
(10.22) (10.26)
For iW1710 KC is 0.5 V, therefore RIsense depends on the The ISEC(pk) is:
maximum output current by;
(VIN ⋅ TON )MAX
NTR × KC I SEC ( pk )
= × NTR × h X
RIsense
= × hX LM
2 × I OUT (10.27)
(10.23)
So to keep VOUT(ripple) to be 100 mV,
From table 10.1 IOUT is given to be 1.2 A, therefore RIsense is:

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Digital PWM Current-Mode Controller for Quasi-Resonant Operation
534V ⋅ ms 0.5 A × 461ms
I=
SEC ( pk ) × 0.87 5.152 A
× 6= COUT ( Dynamic
= ) = 504mF
0.541mH 1.0V − 0V − 0.543V

0.541mH ( 5.152 A − 1.2 A )

2
Pick the larger capacitance value between COUT(Dynamic) and
QOUT
= = 10.8mC
2 × 62 × 0.87 × 12.5V COUT(Steady State). In this case COUT is chosen to be 680 μF.

COUT (Steady State)

=
10.8mC
= 208mF
10.14 Snubber Network
100mV
The snubber network is implemented to reduce the voltage
stress on the MOSFET immediately following the turn off of
In this calculation ESR and ESL are ignored; the reason this
the gate drive. The goal is to dissipate the energy from the
calculation is still valid is because of the second stage LC
leakage inductance of the transformer. For simplicity and
filter on the output of the supply. These two components
a more conservative design first assume the energy of the
reduce the ESR and ESL ripple; however keep in mind that
leakage inductance is only dissipated through the snubber.
the ripple is a little higher in reality than this calculation would
Thus:
suggest.
1 2
× Llk × I PRI 1  2 2 
( pk ) =2 × CSNUB × VSnub ( pk ) − VSnub ( val ) 
Assume that the load transient goes from no load to 2
(10.31)
IOUT(HIGH). Then from section 9.5, equation 9.8 we find that
the relationship between output capacitance (COUT(Dynamic)) Llk can be measured from the transformer and VDS is the
and VDROP(IC) is : voltage across the MOSFET. VSnub(pk) and VSnub(val) refer to the
voltage measured across the snubber capacitor. Choose
I OUT ( HIGH ) × TP (No load)
COUT ( Dynamic ) = a CSNUB, keeping in mind that the larger the value of CSNUB
VDROP ( IC ) the lower the voltage stress is on the MOSFET. However,
(10.28)
capacitors are more expensive the larger their capacitance.
Then solving for VDROP(IC) from Figure 9.4, where VDynamic(DROP) Choose CSNUB based on these two criteria and select VSnub(pk)
is the maximum allowable drop in voltage for the design and VSnub(val). Now a resistor needs to be selected to dissipate
during dynamic response, VDROP(Cable) is the drop in voltage VSnub(pk) to VSnub(val) during the on-time of the gate driver. The
due to the cable resistance, and VDROP(sense) is the drop in dissipation of this resistor is given by:
voltage before VSENSE signal is low enough to register a
VSnub (val ) − TP ( min op)
dynamic transient. =e RSNUB ⋅CSNUB

VSnub ( pk )
(10.32)
I OUT ( HIGH ) × TP (No load)
COUT ( Dynamic ) =
VDynamic ( Drop ) − VDROP (Cable ) − VDROP ( sense )
(10.29) Using equation 10.32 solve for RSNUB. This gives a
conservative estimate of what CSNUB and RSNUB should be.
Where TP(No load) is the maximum period under no load
condition, given by equation 10.30: Included in the snubber network is also a resistor in series with
a diode. The diode directs current to the snubber capacitor
RPreload × (VIN ⋅ TON ) PFM
2
when the MOSFET is turned off; however there is some
=TP ( No load ) 2
× hNo load reverse current that goes through the diode immediately
2 × LM × VOUT
(10.30) after the MOSFET is turned back on. This reverse current
Assume that we want no more than 1.0 V drop on VOUT(PCB) occurs because there is a short period of time when the
during load transient from no load to 50% load and the diode still conducts after switching from forward biased to
efficiency of the power supply at no load (ηNo load) is 50% , reverse biased. This conduction distorts the falling edge of
then COUT(Dynamic) is: the VSENSE signal and affects the operation of the IC. So,
the resistor in series with the diode is there to diminish the
5.6k W × (119V ⋅ms )
2 reverse current that goes through the diode immediately
TP ( PFM=
) = 2
461ms after the MOSFET is turned on.
2 × 0.541mH × (12.5V )

10.15 TON Delay Filter

Since there is no cable, VDROP(cable) is 0 V.
iW1710 also contains a feature that allows for adjustment
12.0V to match high line and low line constant current curves.
VDROP ( sense ) = (1.538V − 1.48V ) × = 0.543V
1.538V The mismatch in high line and low line is due to the delay
from the IC propagation delay, driver turn-on delay, and the
Plug everything into equation 10.19: MOSFET turn-on delay. The driver turn-on delay maybe

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iW1710
Digital PWM Current-Mode Controller for Quasi-Resonant Operation
further increased by a gate resistor to the MOSFET. To
adjust for these delays the iW1710 factors these delays into ( RNTC +RSD(ext ) ) × I SD > VSD−TH (10.34)
its calculations and slightly over compensates for them to
provide flexibility. RDly and CDly provide extra delay in the in order not to trigger OTP fault during normal operation.
circuit to tweak the compensation. To determine values RDly
and CDly follow these steps: OVP Only

1.  Measure the difference between high line and low line For the other four cycles, the iW1710 connects the SD pin
constant current limit without filter components. to RSD to ground (see section 9.13). At the last cycle the
iW1710 observes the voltage on the SD pin and detects an
2.  Find the curve that best matches this difference from OVP fault if the voltage is higher than VSD-TH, 1 V. In order to
Figure 11.1. not trigger OVP fault, assuming 0 V drop across the series
diode, RSD(ext) must meet:
3.  Find the LM that matches the power supply, and find the
tRC. VOUT _ PCB RSD
× N AUX × < VSD −TH
N SEC RSD + RSD (ext )
4.  Find RDly and CDly from equation 10.33 (10.35)
t RC = RDly × CDly
(10.33) where, RSD = 8.333 kΩ

10.16 SD Protection
The SD pin can be configured to provide three different Both OTP and OVP
types of protection: OTP protection, OVP protection and To find RSD1(ext) so that OVP can be detected, use equation
both OVP and OTP Protection. Figure 10.3 shows the three 10.35. To find RSD2(ext) in series with the NTC use equation
configurations plus the configuration for no OTP and OVP 10.34.
protection.
No OTP and OVP

If OTP and OVP from the SD pin are not needed, simply
RSD1(ext)
SD pin SD pin place a resistor, RSD(ext) to ground from the SD pin. Make
RNTC sure RSD(ext) meets equation 10.36 so OTP protection does
RNTC
RSD2(ext) not trip.
RSD(ext)
(optional)
OUTPUT
RSD (ext ) × I SD > VSD −TH
(10.36)
a) Overtemperature Protection only b) Overtemperature Protection
and Overvoltage Protection Note that this means OVP is not detected through the SD
pin; however, OVP from VSENSE pin is still active and the
SD pin
iW1710still shuts down if overvoltage condition is detected.
RSD(ext)
RSD(ext) Since for this example OTP and OVP are not necessary we
SD pin place a resistor from SD pin to ground and calculate its value
from equation 10.36.
c) Overvoltage Protection only d) No Overtemperature Protection
and no overvoltage protection RSD (ext ) > 1.2V 12k W
=
100mA

Figure 10.3 : SD Pin Application Configurations

10.17 PCB Layout
OTP Only
In the iW1710, there are two signals that are important to
To detect an overtemperature protection the iW1710 sends control the output performance; these are the ISENSE signal
a 107 mA current (ISD) to the SD pin every four cycles (see and the VSENSE signal. The ISENSE resistor should be close to
section 9.13). On the last cycle the iW1710 observes the the source of the MOSFET to avoid any trace resistance from
voltage on the SD pin and detects an OTP fault if the voltage contaminating the ISENSE signal. Also, the ISENSE signal should
is lower than VSD-TH, 1.0 V during normal operation and 1.2 V be placed close to the ISENSE pin. The VSENSE signal should
during startup. So RSD(ext) in series with NTC must meet be placed close to the transformer to improve the quality of
the sensing signal. Also for better output performance all
Rev. 2.5 iW1710 Page 16
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iW1710
Digital PWM Current-Mode Controller for Quasi-Resonant Operation
bypass capacitors should be placed close to their respective
pins.

To reduce EMI, switching loops need to be minimized. These

loops include:

1.  The input bulk capacitor, primary winding, MOSFET and

RIsense loop.

2.  The output diode, output capacitor and secondary

winding loop.

3.  VCC winding and rectifier diode loop.

L

N
VOUT
+
+ 2)
RTN

1)

3)

1 NC VCC 8

2 VSENSE OUTPUT 7

3 VIN ISENSE 6

4 SD GND 5

Optional U1
NTC iW1710
Thermistor

Figure 10.4 : Switching Loops

To improve ESD performance provide a low impedance path

from the ground pin of the transformer to the ac power source
and make sure this path does not go through the IC ground
pin. A discharge spark gap helps to transfer ESD and EOS
energy from the secondary side of the power supply directly
to the external ac power source.

In a switch-mode power supply there are several ground

signals, namely: the power ground, the switching ground
and the control logic ground. These ground signals should
be connected by a star connection. Ground traces should
be kept as short as possible. A thick trace on the switching
ground helps to lessen switching losses.

Rev. 2.5 iW1710 Page 17

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Digital PWM Current-Mode Controller for Quasi-Resonant Operation

11.0 Design Example Performance Characteristics

120
∆IOUT (Note1)
50 mA
100 40 mA

(RDly x CDly), τRC (ns)

30 mA
20 mA
80 10 mA

60

40

20

0
0.0 0.5 1.0 1.5 2.0 2.5 3.0
Magnetizing Inductance LM (mH)

Figure 11.1 : TON Compensation Chart

12.0 Application Circuit

1 A / 250 V
L

N 470 µH
VOUT
10 kΩ
Cout + Rpreload
+ + Rsnub Csnub 680 µF 5.6 kΩ
Cbulk Cbulk Rvin 75 kΩ 1 nF RTN
10 µF 33 µF 2.7 MΩ

68 Ω
Rvin
2.4 MΩ

+ 4.7 Ω
470 pF Cvcc
4.7 µF

Rtvsns
24.0 kΩ 1 NC VCC 8 Rgate
22 Ω
2 VSENSE OUTPUT 7
Rbvsns 22 pF
4.57 kΩ 3 VIN ISENSE 6
Rdly (opt)
4 SD GND 5 1000 Ω
Cdly (opt) Risense
U1 33 pF 1.08 Ω
iW1710 (opt): optional
Rntc
20 kΩ

Figure 12.1 : Typical Application Circuit

Note 1: ΔIOUT refers to the difference in constant current limit between 264 Vac and 90 Vac when no RDLY and CDLY are applied.

Rev. 2.5 iW1710 Page 18

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iW1710
Digital PWM Current-Mode Controller for Quasi-Resonant Operation

13.0 Physical Dimensions

8-Lead Small Outline (SOIC) Package

D Inches

Symbol
Millimeters
MIN MAX MIN MAX
A 0.053 0.069 1.35 1.75
8 5
A1 0.0040 0.010 0.10 0.25
E H
1 4 A2 0.049 0.059 1.25 1.50
B 0.014 0.019 0.35 0.49
C 0.007 0.010 0.19 0.25
e D 0.189 0.197 4.80 5.00
h x 45° E 0.150 0.157 3.80 4.00
A1 e 0.050 BSC 1.27 BSC
A2 A
H 0.228 0.244 5.80 6.20
α L
h 0.10 0.020 0.25 0.50
B SEATING
C L 0.016 0.049 0.4 1.25
COPLANARITY PLANE
0.10 (0.004) α 0° 8°

Figure 13.1 : Physical dimensions, 8-lead SOIC package

Compliant to JEDEC Standard MS12F

Controlling dimensions are in inches; millimeter dimensions are for reference only

This product is RoHS compliant and Halide free.

Soldering Temperature Resistance:

[a] Package is IPC/JEDEC Std 020D Moisture Sensitivity Level 1
[b] Package exceeds JEDEC Std No. 22-A111 for Solder Immersion Resistance; package can withstand
10 s immersion < 270˚C

Dimension D does not include mold flash, protrusions or gate burrs. Mold flash, protrusions or gate burrs shall
not exceed 0.15 mm per end. Dimension E1 does not include interlead flash or protrusion. Interlead flash or
protrusion shall not exceed 0.25 mm per side.

The package top may be smaller than the package bottom. Dimensions D and E1 are determined at the
outermost extremes of the plastic bocy exclusive of mold flash, tie bar burrs, gate burrs and interlead flash, but
including any mismatch between the top and bottom of the plastic body.

14.0 Ordering Information

Part Number Options Package Description

iW1710-01 Cable Comp = 0 mV SOIC-8 Tape & Reel1

iW1710-21 Cable Comp = 300 mV SOIC-8 Tape & Reel1

Note 1: Tape & Reel packing quantity is 2,500/reel.

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iW1710
Digital PWM Current-Mode Controller for Quasi-Resonant Operation

Trademark Information
© 2012 iWatt Inc. All rights reserved. iWatt, BroadLED, EZ-EMI, Flickerless, Intelligent AC-DC and LED Power, and
PrimAccurate are trademarks of iWatt Inc. All other trademarks and registered trademarks are the property of their respective
owners.

Contact Information
Web: https://www.iwatt.com
E-mail: info@iwatt.com
Phone: +1 (408) 374-4200
Fax: +1 (408) 341-0455
iWatt Inc.
675 Campbell Technology Parkway, Suite 150
Campbell, CA 95008

Disclaimer and Legal Notices

iWatt reserves the right to make changes to its products and to discontinue products without notice. The applications
information, schematic diagrams, and other reference information included herein is provided as a design aid only and are
therefore provided as-is. iWatt makes no warranties with respect to this information and disclaims any implied warranties of
merchantability or non-infringement of third-party intellectual property rights.

This product is covered by the following patents: 6,385,059; 6,730,039; 6,862,198; 6,900,995; 6,956,750; 6,990,900; 7,443,700; 7,505,287;
7,589,983; 6,972,969; 7,724,547; 7,876,582; 7,880,447; 7,974,109; 8,018,743; 8,049,481. A full list of iWatt patents can be found at www.
iwatt.com.

Certain applications using semiconductor products may involve potential risks of death, personal injury, or severe property
or environmental damage (“Critical Applications”).

iWATT SEMICONDUCTOR PRODUCTS ARE NOT DESIGNED, INTENDED, AUTHORIZED, OR WARRANTED TO BE

SUITABLE FOR USE IN LIFE‑SUPPORT APPLICATIONS, DEVICES OR SYSTEMS, OR OTHER CRITICAL APPLICATIONS.

Inclusion of iWatt products in critical applications is understood to be fully at the risk of the customer. Questions concerning
potential risk applications should be directed to iWatt Inc.

iWatt semiconductors are typically used in power supplies in which high voltages are present during operation. High-voltage
safety precautions should be observed in design and operation to minimize the chance of injury.

Rev. 2.5 iW1710 Page 20

November 27, 2012