Jyothishmathi Institute of Technology & Science: Unit V ARM Cortex-M3 Processor

Jyothishmathi Institute of Technology & Science
Karimnagar
Department of Electronics and Communication Engineering

Microprocessors and Microcontrollers
Year / Sem : III/II
Unit V
Advanced ARM Processors: Introduction to CORTEX Processor and its architecture
ARM Cortex-M3 Processor:

 The ARM Cortex™-M3 processor, the first of the Cortex generation of processors released by
ARM in 2006, was primarily designed to target the 32-bit microcontroller market.
 The Cortex-M3 processor provides excellent performance at low gate count and comes with
many new features previously available only in high-end processors.
 The Cortex-M3 addresses the requirements for the 32-bit embedded processor market in
the following ways:
 Greater performance efficiency: allowing more work to be done without increasing the
frequency or power requirements
 Low power consumption: enabling longer battery life, especially critical in portable
products including wireless networking applications
 Enhanced determinism: guaranteeing that critical tasks and interrupts are serviced as
quickly as possible and in a known number of cycles
 Improved code density: ensuring that code fits in even the smallest memory footprints
 Ease of use: providing easier programmability and debugging for the growing number of 8-
bit and 16-bit users migrating to 32 bits
 Lower cost solutions: reducing 32-bit-based system costs close to those of legacy 8-bit and
16-bit devices and enabling low-end, 32-bit microcontrollers to be priced at less than US$1 for
the first time
 Wide choice of development tools: from low-cost or free compilers to fullfeatured
development suites from many development tool vendors.
Cortex-M3 processor-based microcontrollers can be easily programmed using the C

language and are based on a well-established architecture, application code can be ported and
reused easily, reducing development time and testing costs. Additionally, the Cortex-M3
processor introduces a number of features and technologies that meet the specific requirements
of the microcontroller applications, such as nonmaskable interrupts for critical tasks, highly
deterministic nested vector interrupts, atomic bit manipulation, and an optional Memory
Protection Unit (MPU). These factors make the Cortex-M3 processor attractive to existing ARM
processor users as well as many new users considering use of 32-bit MCUs in their products.
Instruction Set Development
 Two different instruction sets are supported on the ARM processor: the ARM instructions
that are 32 bits and Thumb instructions that are 16 bits.
 During program execution, the processor can be dynamically switched between the ARM
state and the Thumb state to use either one of the instruction sets.
 The Thumb instruction set provides only a subset of the ARM instructions, but it can
provide higher code density. It is useful for products with tight memory requirements.
The Thumb-2 Technology and Instruction Set Architecture

The Thumb-2 technology extended the Thumb Instruction Set Architecture (ISA) into a highly
efficient and powerful instruction set that delivers significant benefits in terms of ease of use,
code size, and performance (see Figure 1.1).
Figure :The Relationship between the Thumb Instruction Set in Thumb-2 Technology and the Traditional Thumb.
 The extended instruction set in Thumb-2 is a superset of the previous 16-bit Thumb
instruction set, with additional 16-bit instructions alongside 32-bit instructions.
 It allows more complex operations to be carried out in the Thumb state, thus allowing
higher efficiency by reducing the number of states switching between ARM state and Thumb
state. Focused on small memory system devices such as microcontrollers and reducing the size
of the processor, the Cortex-M3 supports only the Thumb-2 (and traditional Thumb) instruction
set. Instead of using ARM instructions for some operations, as in traditional ARM processors, it
uses the Thumb-2 instruction set for all operations. As a result, the Cortex-M3 processor is not
backward compatible with traditional ARM processors.
 With support for both 16-bit and 32-bit instructions in the Thumb-2 instruction set, there
is no need to switch the processor between Thumb state (16-bit instructions) and ARM state (32-
bit instructions).
 For example, in ARM7 or ARM9 family processors, you might need to switch to ARM state
if you want to carry out complex calculations or a large number of conditional operations and
good performance is needed, whereas in the Cortex-M3 processor, you can mix 32-bit
instructions with 16-bit instructions without switching state, getting high code density and high
performance with no extra complexity.
 The Thumb-2 instruction set is a very important feature of the ARMv7 architecture.
Compared with the instructions supported on ARM7 family processors (ARMv4T architecture),
the Cortex-M3 processor instruction set has a large number of new features.
 For the first time, hardware divide instruction is available on an ARM processor, and a
number of multiply instructions are also available on the Cortex-M3 processor to improve
data-crunching performance. The Cortex-M3 processor also supports unaligned data accesses, a
feature previously available only in high-end processors.
Cortex-M3 Processor Applications

 Low-cost microcontrollers: The Cortex-M3 processor is ideally suited for low-cost
microcontrollers, which are commonly used in consumer products, from toys to electrical
appliances. Its lower power, high performance, and ease-of-use advantages enable
embedded developers to migrate to 32-bit systems and develop products with the ARM
architecture.
 Automotive: Another ideal application for the Cortex-M3 processor is in the automotive
industry. The Cortex-M3 processor has very high-performance efficiency and low
interrupt latency, allowing it to be used in real-time systems. The Cortex-M3 processor
supports up to 240 external vectored interrupts, with a built-in interrupt controller with
nested interrupt supports and an optional MPU, making it ideal for highly integrated and
cost-sensitive automotive applications.
 Data communications: The processor’s low power and high efficiency, coupled with
instructions in Thumb-2 for bit-field manipulation, make the Cortex-M3 ideal for many
communications applications, such as Bluetooth and ZigBee.
 Industrial control: In industrial control applications, simplicity, fast response, and
reliability are key factors. Again, the Cortex-M3 processor’s interrupt feature, low
interrupt latency, and enhanced fault-handling features make it a strong candidate in this
area.
 Consumer products: In many consumer products, a high-performance microprocessor
(or several of them) is used. The Cortex-M3 processor, being a small processor, is highly
efficient and low in power and supports an MPU enabling complex software to execute
while providing robust memory protection.
The Memory Map

 The Cortex-M3 has a predefined memory map. This allows the built-in peripherals, such
as the interrupt controller and the debug components, to be accessed by simple memory
access instructions.
 The predefined memory map also allows the Cortex-M3 processor to be highly optimized
for speed and ease of integration in system-on-a-chip (SoC) designs.
 Overall, the 4 GB memory space can be divided into ranges as shown in Figure 2.6.
 The Cortex-M3 design has an internal bus infrastructure optimized for this memory
usage. In addition, the design allows these regions to be used differently. For example,
data memory can still be put into the CODE region, and program code can be executed
from an external Random Access Memory (RAM) region.
The Bus Interface

There are several bus interfaces on the Cortex-M3 processor. They allow the Cortex-M3
to carry instructionfetches and data accesses at the same time. The main bus interfaces are as
follows:
• Code memory buses
• System bus
• Private peripheral bus
 The code memory region access is carried out on the code memory buses, which
physically consist of two buses, one called I-Code and other called D-Code. These are
optimized for instruction fetches for best instruction execution speed.
 The system bus is used to access memory and peripherals. This provides access to the
Static Random Access Memory (SRAM), peripherals, external RAM, external devices,
and part of the system level memory regions.
 The private peripheral bus provides access to a part of the system-level memory
dedicated to private peripherals, such as debugging components.
The MPU
 The Cortex-M3 has an optional MPU. This unit allows access rules to be set up for
privileged access and user program access.
 When an access rule is violated, a fault exception is generated, and the fault exception
handler will be able to analyze the problem and correct it, if possible.
 The MPU can be used in various ways. In common scenarios, the OS can set up the MPU
to protect data use by the OS kernel and other privileged processes to be protected from
untrusted user programs.
 The MPU can also be used to make memory regions read-only, to prevent accidental
erasing of data or to isolate memory regions between different tasks in a multitasking
system. Overall, it can help make embedded systems more robust and reliable.
Debugging Support
 The Cortex-M3 processor includes a number of debugging features, such as program
execution controls, including halting and stepping, instruction breakpoints, data
watchpoints, registers and memory accesses, profiling, and traces.
 The debugging hardware of the Cortex-M3 processor is based on the CoreSight
architecture.

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Jyothishmathi Institute of Technology & Science

Department of Electronics and Communication Engineering

ARM Cortex-M3 Processor:

Cortex-M3 processor-based microcontrollers can be easily programmed using the C

The Thumb-2 Technology and Instruction Set Architecture

Cortex-M3 Processor Applications

The Memory Map

The Bus Interface

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