SLUS600B − APRIL 2004 − REVISED NOVEMBER 2005

 
  




 


FEATURES DESCRIPTION
D Input Voltage Range: 4.75 V to 5.25 V The TPS51100 is a 3-A sink/source tracking
D VLDOIN Voltage Range: 1.2 V to 3.6 V termination regulator. It is specifically designed for
D 3-A Sink/Source Termination Regulator low-cost/low-external component count systems,
Includes Droop Compensation where space is a premium.
D Requires Only 20-µF Ceramic Output The TPS51100 maintains fast transient response
Capacitance only requiring 20-µF (2 × 10µF) of ceramic output
D Supports High-Z in S3 and Soft-Off in S5 capacitance. The TPS51100 supports remote
sensing functions and all features required to
D 1.2-V Input (VLDOIN) Helps Reduce Total
power the DDR and DDR2 VTT bus termination
Power Dissipation
according to the JEDEC specification. In addition,
D Integrated Divider Tracks !/2VDDQSNS for the TPS51100 includes integrated sleep-state
VTT and VTTREF controls placing VTT in High-Z in S3 (suspend to
D Remote Sensing (VTTSNS) RAM) and soft-off for VTT and VTTREF in S5
D ± 20-mV Accuracy for VTT and VTTREF (suspend to disk). The TPS51100 is available in
the thermally efficient 10-pin MSOP PowerPAD
D 10-mA Buffered Reference (VTTREF)
and is specified from −40°C to 85°C.
D Built-In Soft-Start, UVLO and OCL
D Thermal Shutdown
D Supports JEDEC Specifications ORDERING INFORMATION
APPLICATIONS PLASTIC MSOP POWER PAD
TA
(DGQ)(1)
D DDR, DDR2 Memory Termination −40°C to 85°C TPS51100DGQ
D SSTL−2, SSTL−18 and HSTL Termination (1) The DGQ package is also available taped and reeled. Add
an R suffix to the device type (i.e., TPS51100DGQR). See
the application section of the data sheet for PowerPAD
TPS51100DGQ drawing and layout information.

1 VDDQSNS VIN 10 5V_IN

2 VLDOIN S5 9 S5
C1
2 y 10 µF
3 VTT GND 8
C2
0.1 µF
4 PGND S3 7 S3

5 VTTSNS VTTREF 6 VTTREF

Cap Manuf Part Number

C1 TDK C2012JB0J106K
C2 TDK C1608JB1H104K

UDG−04015



 
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#-  && $##(

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SLUS600B − APRIL 2004 − REVISED NOVEMBER 2005

These devices have limited built-in ESD protection. The leads should be shorted together or the device placed in conductive foam
during storage or handling to prevent electrostatic damage to the MOS gates.

ABSOLUTE MAXIMUM RATINGS

over operating free-air temperature range unless otherwise noted(1)
TPS51100 UNIT
VIN, VLDOIN, VTTSNS, VDDQSNS, S3, S5 −0.3 to 6
Input voltage range(2)
PGND −0.3 to 0.3 V
Output voltage range(2) VTT, VTTREF −0.3 to 6
Operating ambient temperature range, TA −40 to 85
°C
Storage temperature, Tstg −55 to 150
(1) Stresses beyond those listed under “absolute maximum ratings” may cause permanent damage to the device. These are stress ratings only,
and functional operation of the device at these or any other conditions beyond those indicated under “recommended operating conditions”
is not implied. Exposure to absolute-maximum-rated conditions for extended periods may affect device reliability.
(2) All voltage values are with respect to the network ground terminal unless otherwise noted.

DISSIPATION RATING TABLE

TA < 25°C DERATING FACTOR TA = 85°C
PACKAGE
POWER RATING ABOVE TA = 25°C POWER RATING
10-pin DGQ 1.73 W 17.3 mW/°C 0.694 W

RECOMMENDED OPERATING CONDITIONS

MIN MAX UNIT
Supply voltage, VIN 4.75 5.25
S3, S5 −0.10 5.25
VLDOIN, VDDQSNS, VTT, VTTSNS −0.1 3.6 V
Voltage range
VTTREF −0.1 1.8
PGND −0.1 0.1
Operating free-air temperature, TA −40 85 °C

(TOP VIEW)
DGQ Package

VDDQSNS 1 10 VIN
VLDOIN 2 9 S5
VTT 3 8 GND
PGND 4 7 S3
VTTSNS 5 6 VTTREF

ACTUAL SIZE
3,05mm x 4,98mm
(4) For more information on the DGQ package, refer to TI Technical Brief, Literature No. SLMA002.
(5) PowerPADt heat slug must be connected to GND (pin 8) or electrically isolated from all other pins.

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SLUS600B − APRIL 2004 − REVISED NOVEMBER 2005

ELECTRICAL CHARACTERISTICS
TA = −40°C to 85°C, VVIN = 5 V, VLDOIN and VDDQSNS are connected to 2.5 V (unless otherwise noted)
PARAMETER TEST CONDITIONS MIN TYP MAX UNIT
SUPPLY CURRENT
TA = 25°C, VVIN = 5 V, no load
IVIN Supply current, VIN 0.25 0.50 1.00 mA
VS3 = VS5 = 5 V
TA = 25°C, VVIN = 5 V, no load
IVINSTB Standby currrent, VIN 25 50 80
VS3 = 0 V, VS5 = 5 V
µA
A
TA = 25°C, VVIN = 5 V, no load
IVINSDN Shutdown current, VIN 0.3 1.0
VS3 = VS5 = 0 V, VVLDOIN = VVDDQSNS = 0 V
TA = 25°C, VVIN = 5 V, no load
IVLDOIN Supply current, VLDOIN 0.7 1.2 2.0 mA
VS3 = VS5 = 5 V
TA = 25°C, VVIN = 5 V, no load
IVLDOINSTB Standby currrent, VLDOIN 6 10
VS3 = 0 V, VS5 = 5 V
µA
A
TA = 25°C, VVIN = 5 V, no load
IVLDOINSDN Shutdown current, VLDOIN 0.3 1.0
VS3 = VS5 = 0 V
INPUT CURRENT
IVDDQSNS Input current, VDDQSNS VVIN = 5 V, VS3 = VS5 = 5 V 1 3 5
µA
A
IVTTSNS Input current, VTTSNS VVIN = 5 V, VS3 = VS5 = 5 V −1.00 −0.25 1.00
VTT OUTPUT
VVLDOIN = VVDDQSNS = 2.5 V 1.25
VVTTSNS Output voltage, VTT V
VVLDOIN = VVDDQSNS = 1.8 V 0.9
VVLDOIN = VVDDQSNS = 2.5 |IV,VTT| = 0 A −20 20
Output voltage tolerance to
VVTTTOL25 VVLDOIN = VVDDQSNS = 2.5 |IV,VTT| = 1.5 A −30 30
VTTREF, VTT
VVLDOIN = VVDDQSNS = 2.5 |IV,VTT| = 3 A −40 40
mV
VVLDOIN = VVDDQSNS = 1.8 |IV,VTT| = 0 A −20 20
Output voltage tolerance to
VVTTTOL18 VVLDOIN = VVDDQSNS = 1.8 |IV,VTT| = 1 A −30 30
VTTREF, VTT
VVLDOIN = VVDDQSNS = 1.8 |IV,VTT| = 2 A −40 40

IVTTOCLSRC Source current limit, VTT

V TT + ǒ V VDDQSNS
2
Ǔ 0.95, PGOOD + High 3.0 3.8 6.0

VVTT = 0 V 1.5 2.2 3.0

A

IVTTOCLSNK Sink current limit, VTT

V TT + ǒ V VDDQSNS
2
Ǔ 1.05, PGOOD + High 3.0 3.6 6.0

VVTT = VVDDQ 1.5 2.2 3.0

IVTTLK Leakage current, VTT

V TT + ǒ V VDDQSNS
2
Ǔ + 1.25 V, T A + 25 oC
−1.0 0.5 1.0

VS3 = 0 V, VS5 = 5 V µA

IVTTSNSLK Leakage current, VTTSNS V TT + ǒV VDDQSNS

2
Ǔ + 1.25 V, T A + 25 oC −1.00 0.01 1.00

TA = 25°C, VS3 = VS5 = 0 V,

IDSCHRG Discharge current, VTT 10 17 mA
VVDDQSNS = 0 V, VVTT = 0.5 V

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SLUS600B − APRIL 2004 − REVISED NOVEMBER 2005

ELECTRICAL CHARACTERISTICS(continued)
TA = −40°C to 85°C, VVIN = 5 V, VLDOIN and VDDQSNS are connected to 2.5 V (unless otherwise noted)
PARAMETER TEST CONDITIONS MIN TYP MAX UNIT
VTTREF OUTPUT

VVTTREF Output voltage, VTTREF V TTREF + ǒV VDDQSNS

2
Ǔ V

Output voltage tolerance to

VVTTREFTOL25 VVLDOIN = VVDDQSNS = 2.5IVTTREF
V, < 10 mA −20 20
VDDQSNS/2, VTTREF
mV
Output voltage tolerance to
VVTTREFTOL18 VVLDOIN = VVDDQSNS = 1.8IVTTREF
V, < 10 mA −17 17
VDDQSNS/2, VTTREF
IVTTREFOCL Source current limit, VTTREF VVVTTREF = 0 V 10 20 30 mA
UVLO/LOGIC THRESHOLD
Wake up 3.4 3.7 4.0
VVINUV UVLO threshold voltage, VIN
Hysteresis 0.15 0.25 0.35
VIH High-level input voltage S3, S5 1.6 V
VIL Low-level input voltage S3, S5 0.3
VIHYST Hysteresis voltage S3, S5 0.2
IILEAK Logic input leakage current S2, S5, TA = 25°C −1 1 µA
THERMAL SHUTDOWN
Shutdown temperature 160
TSDN Thermal shutdown threshold °C
Hysteresis 10

TERMINAL FUNCTIONS
TERMINAL
I/O DESCRIPTION
NAME NO.
GND 8 − Signal ground. Connect to negative terminal of the output capacitor
PGND 4 − Power ground output for the VTT LDO
S3 7 I S3 signal input
S5 9 I S5 signal input
VDDQSNS 1 I VDDQ sense input
VIN 10 I 5-V power supply
VLDOIN 2 I Power supply for the VTT LDO and VTTREF output stage
VTT 3 O Power output for the VTT LDO
VTTREF 6 O VTT reference output. Connect to GND through 0.1-µF ceramic capacitor.
VTTSNS 5 I Voltage sense input for the VTT LDO. Connect to plus terminal of the output capacitor.

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SLUS600B − APRIL 2004 − REVISED NOVEMBER 2005

SIMPLIFIED BLOCK DIAGRAM

VDDQSNS 1 2 VLDOIN
+ HalfDDQ
+
6 VTTREF

GND 8

VIN 10
+ VinOK
ENREF
3.7 V/3.5 V +
VTTSNS 5 3 VTT

ENVTT
S3 7

5 V/10% ENVTT
4 PGND
+ +
ENREF PGOOD
S5 9

+
+

TPS51100 DGQ UDG−04016

−5 V/10%

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SLUS600B − APRIL 2004 − REVISED NOVEMBER 2005

DETAILED DESCRIPTION

VTT SINK/SOURCE REGULATOR

The TPS51100 is a 3-A sink/source tracking termination regulator designed specially for low-cost, low external
components system where space is at premium such as notebook PC applications. TPS51100 integrates high-
performance low−dropout linear regulator that is capable of sourcing and sinking current up to 3 A. This VTT
linear regulator employs ultimate fast response feedback loop so that small ceramic capacitors are enough to
keep tracking to the VTTREF within ±40 mV at all conditions including fast load transient. To achieve tight
regulation with minimum effect of trace resistance, a remote sensing terminal, VTTSNS, should be connected
to the positive node of VTT output capacitor(s) as a separate trace from the high current line from VTT.

VTTREF REGULATOR
The VTTREF block consists of an on-chip 1/2 divider, LPF and buffer. This regulator can source current up to
10 mA. Bypass VTTREF to GND using a 0.1-µF ceramic capacitor to ensure stable operation.
Soft-Start
The soft-start function of the VTT is achieved via a current clamp, allowing the output capacitors to be charged
with low and constant current that gives linear ramp up of the output voltage. The current limit threshold is
changed in two stages using an internal powergood signal. When VTT is outside the powergood threshold, the
current limit level is 2.2 A. When VTT rises above (VTTREF − 5%) or falls below (VTTREF + 5%) the current
limit level switches to 3.8 A. The thresholds are typically VTTREF ±5% (from outside regulation to inside) and
±10% (when it falls outside). The soft-start function is completely symmetrical and it works not only from GND
to VTTREF voltage, but also from VDDQ to VTTREF voltage. Note that the VTT output is in a high impedance
state during the S3 state (S3 = low, S5 = high) and its voltage can be up to VDDQ voltage depending on the
external condition. Note that VTT does not start under a full load condition.
S3, S5 Control and Soft-Off
The S3 and S5 terminals should be connected to SLP_S3 and SLP_S5 signals respectively. Both VTTREF and
VTT are turned on at S0 state (S3 = high, S5 = high). VTTREF is kept alive while VTT is turned off and left high
impedance in S3 state (S3 = low, S5 = high). Both VTT and VTTREF outputs are turned off and discharged to
the ground through internal MOSFETs during S4/S5 state (both S3 and S5 are low).

Table 1. S3 and S5 Control Table

STATE S3 S5 VTTREF VTT
S0 H H 1 1
S3 L H 1 0 (high−Z)
S4/S5 L L 0 (discharge) 0 (discharge)

(In case S3 is forced H and S5 to L, VTTREF is discharged and VTT is at High−Z state. This condition is NOT
recommended.)
VTT Current Protection
The LDO has a constant overcurrent limit (OCL) at 3.8 A. This trip point is reduced to 2.2 A before the output
voltage comes within ±5% of the target voltage or goes outside of ±10% of the target voltage.

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SLUS600B − APRIL 2004 − REVISED NOVEMBER 2005

DETAILED DESCRIPTION

VIN UVLO Protection

For VIN undervoltage lockout (UVLO) protection, the TPS51100 monitors VIN voltage. When the VIN voltage
is lower than UVLO threshold voltage, the VTT regulator is shut off. This is a non-latch protection.
Thermal Shutdown
TPS51100 monitors its temperature. If the temperature exceeds threshold value, typically 160°C, the VTT and
VTTREF regulators are shut off. This is also a non-latch protection.
Output Capacitor
For stable operation, total capacitance of the VTT output terminal can be equal or greater than 20-µF. Attach
two 10-µF ceramic capacitors in parallel to minimize the effect of ESR and ESL. If the ESR is greater than 2 mΩ,
insert an R-C filter between the output and the VTTSNS input to achieve loop stability. The R-C filter time
constant should be almost the same or slightly lower than the time constant of the output capacitor and its ESR.
Soft-start duration, TSS, is also a function of this output capacitance. Where ITTOCL = 2.2 A (typ), TSS can be
calculated as,

T SS + ǒ C OUT V VTT
I VTTOCL
Ǔ (1)
Input Capacitor
Depending on the trace impedance between the VLDOIN bulk power supply to the part, transient increase of
source current is supplied mostly by the charge from the VLDOIN input capacitor. Use a 10-µF (or more) ceramic
capacitor to supply this transient charge. Provide more input capacitance as more output capacitance is used
at VTT. In general, use 1/2 COUT for input.
VIN Capacitor
Add a ceramic capacitor with a value between 1.0-µF and 4.7-µF placed close to the VIN pin, to stabilize 5-V
from any parasitic impedance from the supply.
Thermal design
As the TPS51100 is a linear regulator, the VTT current flow in both source and sink directions generate power
dissipation from the device. In the source phase, the potential difference between VVLDOIN and VVTT times VTT
current becomes the power dissipation, WDSRC.

W DSRC + ǒV VLDOIN * V VTTǓ I VTT (2)

In this case, if VLDOIN is connected to an alternative power supply lower than VDDQ voltage, power loss can
be decreased.
For the sink phase, VTT voltage is applied across the internal LDO regulator, and the power dissipation, and
WDSNK, is calculated by:
W DSNK + V VTT I VTT (3)
Since the device does not sink and source the current at the same time and IVTT varies rapidly with time, actual
power dissipation need to be considered for thermal design is an average of above value over thermal relaxation
duration of the system. Another power consumption is the current used for internal control circuitry from VIN
supply and VLDOIN supply. This can be estimated as 20 mW or less at normal operational conditions. This
power needs to be effectively dissipated from the package. Maximum power dissipation allowed to the package
is calculated by,

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SLUS600B − APRIL 2004 − REVISED NOVEMBER 2005

DETAILED DESCRIPTION

ǒTJ(max) * TA(max)Ǔ
W PKG +
q JA (4)
where
D TJ(max) is 125°C
D TA(max) is the maximum ambient temperature in the system
D θJA is the thermal resistance from the silicon junction to the ambient
This thermal resistance strongly depends on the board layout. TPS51100 is assembled in a thermally enhanced
PowerPAD package that has exposed die pad underneath the body. For improved thermal performance, this
die pad needs to be attached to ground trace via thermal land on the PCB. This ground trace acts as a heat
sink/spread. The typical thermal resistance, 57.7°C/W, is achieved based on a 3 mm × 2 mm thermal land with
2 vias without air flow. It can be improved by using larger thermal land and/or increasing vias number. For
example, assuming 3 mm × 3 mm thermal land with 4 vias without air flow, it is 45.4°C/W. Further information
about PowerPAD and its recommended board layout is described in the application note (SLMA002). This
document is available at www.ti.com.

LAYOUT CONSIDERATIONS
Consider the following points before the layout of TPS51100 design begins.
D The input bypass capacitor for VLDOIN should be placed to the pin as close as possible with short and wide
connection.
D The output capacitor for VTT should be placed close to the pin with short and wide connection in order to
avoid additional ESR and/or ESL of the trace.
D VTTSNS should be connected to the positive node of VTT output capacitor(s) as a separate trace from the
high current power line and is strongly recommended to avoid additional ESR and/or ESL. If it is needed
to sense the voltage of the point of the load, it is recommended to attach the output capacitor(s) at that point.
Also, it is recommended to minimize any additional ESR and/or ESL of ground trace between GND pin and
the output capacitor(s).
D Consider adding LPF at VTTSNS in case ESR of the VTT output capacitor(s) is larger than 2 mΩ.
D VDDQSNS can be connected separately from VLDOIN. Remember that this sensing potential is the
reference voltage of VTTREF. Avoid any noise generative lines.
D Negative node of VTT output capacitor(s) and VTTREF capacitor should be tied together by avoiding
common impedance to the high current path of the VTT source/sink current.
D GND (Signal GND) pin node represents the reference potential for VTTREF and VTT outputs. Connect
GND to negative nodes of VTT capacitor(s), VTTREF capacitor and VDDQ capacitor(s) with care to avoid
additional ESR and/or ESL. GND and PGND (Power GND) should be isolated, with a single point
connection between them.
D In order to effectively remove heat from the package, prepare thermal land and solder to the package’s
thermal pad. Wide trace of the component−side copper, connected to this thermal land, will help heat
spreading. Numerous vias 0.33 mm in diameter connected from the thermal land to the internal/solder−side
ground plane(s) should be used to help dissipation.

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SLUS600B − APRIL 2004 − REVISED NOVEMBER 2005

TYPICAL CHARACTERISTICS

VIN SUPPLY CURRENT VIN SHUTDOWN CURRENT

vs vs
TEMPERATURE TEMPERATURE
1.0 2.0

0.9 1.8

IVINSDN − VIN Supply Current − µA

0.8 1.6
IVIN − VIN Supply Current − mA

0.7 1.4

0.6 1.2

0.5 1.0

0.4 0.8

0.3 0.6

0.2 0.4

0.1 0.2

0 0
−50 0 50 100 150 −50 0 50 100 150
TJ − Junction Temperature − °C TJ − Junction Temperature − °C
Figure 1 Figure 2

VIN SUPPLY CURRENT VLDOIN SUPPLY CURRENT

vs vs
VTT LOAD CURRENT TEMPERATURE
10 2.0
DDR2
9 VVTT = 1.8 V 1.9
IVLDOIN − VLDOIN Supply Current − mA

1.8
8
IVIN − VIN Supply Current − mA

1.7
7
1.6
6 1.5
1.4
5
1.3
4
1.2
3 1.1

2 1.0
0.9
1
0.8
0 0.7
−2.0 −1.5 −1.0 −0.5 0 0.5 1.0 1.5 2.0 −50 0 50 100 150
IVTT − VTT Load Current − A TJ − Junction Temperature − °C

Figure 3 Figure 4

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SLUS600B − APRIL 2004 − REVISED NOVEMBER 2005

TYPICAL CHARACTERISTICS

VLDOIN SHUTDOWN CURRENT DISCHARGE CURRENT

vs vs
TEMPERATURE TEMPERATURE
2.0 30

1.8
IVLDOIN − VLDOIN Supply Current − µA

IDSCHRG − VTT Discharge Current − mA

1.6
25
1.4

1.2

1.0 20

0.8

0.6
15
0.4

0.2

0 10
−50 0 50 100 150 −50 0 50 100 150
TJ − Junction Temperature − °C TJ − Junction Temperature − °C
Figure 5 Figure 6

VTT VOLTAGE LOAD REGULATION VTT VOLTAGE LOAD REGULATION

vs vs
VTT LOAD CURRENT VTT LOAD CURRENT
(DDR) (DDR2)
1.29 0.94

1.28 0.93

1.27 0.92
VVTT − VTT Voltage − V

VVTT − VTT Voltage − V

1.26 0.91

1.25 0.90
VVLDOIN = 2.5 V
VVLDOIN = 1.8 V
1.24 0.89

1.23 0.88
VVLDOIN = 1.2 V
VVLDOIN = 1.8 V
1.22 0.87
VVLDOIN = 1.5 V
1.21 0.86
−4 −3 −2 −1 0 1 2 3 4 −4 −3 −2 −1 0 1 2 3 4
IVTT − VTT Load Current − A IVTT − VTT Load Current − A

Figure 7 Figure 8

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SLUS600B − APRIL 2004 − REVISED NOVEMBER 2005

TYPICAL CHARACTERISTICS

VTTREF VOLTAGE LOAD REGULATION VTTREF VOLTAGE LOAD REGULATION

vs vs
VTTREF LOAD CURRENT VTTREF LOAD CURRENT
(DDR) (DDR2)
1.252 902

VVTTREF − VTTREF Voltage − mV

VVTTREF − VTTREF Voltage − V

1.251 901

1.250 900

1.249 899

1.248 898
0 2 4 6 8 10 0 2 4 6 8 10
IVTTREF − VTTREF Load Current − mA IVTTREF − VTTREF Load Current − mA
Figure 9 Figure 10

VTT VOLTAGE LOAD

TRANSIENT RESPONSE

VVLDOIN (50 mV/div)

Offset: 1.8 V

VVTT (20 mV/div)

Offset 0.9 V

VVTTREF
(20 mV/div)
Offset 0.9 V

IVTT
(2 A/div)

t − Time − 20 µs/div
Figure 11

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SLUS600B − APRIL 2004 − REVISED NOVEMBER 2005

TYPICAL CHARACTERISTICS

STARTUP WAVEFORMS STARTUP WAVEFORMS

S5 LOW−TO-HIGH S3 LOW−TO-HIGH

VS3 = 0 V
IVTT = IVTTREF = 0A VS5
(5 V/div)
VS3 VS5
(5 V/div) (5 V/div)
VS3
(5 V/div)

VTTREF
VVTTREF
(0.5 V/div)

VVTT (0.5 V/div)

VVTT
(0.5 V/div)

VS5 = 5 V
IVTT = IVTTREF = 0A

t − Time − 10 µs/div t − Time − 10 µs/div

Figure 12 Figure 13

SHUTDOWN WAVEFORMS SHUTDOWN WAVEFORMS

S3 HIGH-TO-LOW S3 AND S5 HIGH-TO-LOW

VS5
(5 V/div)
VS5
(5 V/div)
VS3 VS3
(5 V/div) (5 V/div)

VTTREF
VVTTREF (0.5 V/div)
(0.5 V/div)

VVTT VVTT
(0.5 V/div) (0.5 V/div)
VS5 = 5 V
IVTT = IVTTREF = 0A IVTT = IVTTREF = 0A

t − Time − 1 ms/div t − Time − 1 ms/div

Figure 14 Figure 15

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SLUS600B − APRIL 2004 − REVISED NOVEMBER 2005

TYPICAL CHARACTERISTICS

BODE PLOT BODE PLOT

DDR DDR
SOURCE SINK
80 180 80 180
Phase Phase
(−1 A) (1 A)
60 135 60 135
Phase
(−0.1 A)

40 90 40 90

Phase − °
Gain − dB

Phase − °
Gain − dB
20 45 20 45

Phase
Gain Gain (0.1 A)
0 0 0 0
(−0.1 A) (0.1 A)

−20 −45 −20 −45

Gain Gain
(−1 A) (1 A)
C1 = 2 y 10 µF C1 = 2 y 10 µF
−40 −90 −40 −90
10 k 100 k 1M 10 M 10 k 100 k 1M 10 M
f − Frequency − Hz f − Frequency − Hz
Figure 16 Figure 17

BODE PLOT BODE PLOT

DDR2 DDR2
SOURCE SINK
80 180 80 180
Phase
Phase
(−1 A)
(1 A)
60 135 60 135
Phase
(−0.1 A)

40 90 40 90
Phase − °
Gain − dB

20 45 20 45

Gain Phase
(−0.1 A) (0.1 A)
0 0 0 Gain 0
(0.1 A)

−20 −45 −20 −45

Gain
(−1 A) Gain
C1 = 2 y 10 µF (1 A)
C1 = 2 y 10 µF
−40 −90 −40 −90
10 k 100 k 1M 10 M 10 k 100 k 1M 10 M
f − Frequency − Hz f − Frequency − Hz

Figure 18 Figure 19

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 PACKAGE OPTION ADDENDUM
www.ti.com 27-Feb-2006

PACKAGING INFORMATION

Orderable Device Status (1) Package Package Pins Package Eco Plan (2) Lead/Ball Finish MSL Peak Temp (3)
Type Drawing Qty
TPS51100DGQ ACTIVE MSOP- DGQ 10 80 Green (RoHS & CU NIPDAU Level-1-260C-UNLIM
Power no Sb/Br)
PAD
TPS51100DGQG4 ACTIVE MSOP- DGQ 10 80 Green (RoHS & CU NIPDAU Level-1-260C-UNLIM
Power no Sb/Br)
PAD
TPS51100DGQR ACTIVE MSOP- DGQ 10 2500 Green (RoHS & CU NIPDAU Level-1-260C-UNLIM
Power no Sb/Br)
PAD
TPS51100DGQRG4 ACTIVE MSOP- DGQ 10 2500 Green (RoHS & CU NIPDAU Level-1-260C-UNLIM
Power no Sb/Br)
PAD
(1)
The marketing status values are defined as follows:
ACTIVE: Product device recommended for new designs.
LIFEBUY: TI has announced that the device will be discontinued, and a lifetime-buy period is in effect.
NRND: Not recommended for new designs. Device is in production to support existing customers, but TI does not recommend using this part in
a new design.
PREVIEW: Device has been announced but is not in production. Samples may or may not be available.
OBSOLETE: TI has discontinued the production of the device.

(2)
Eco Plan - The planned eco-friendly classification: Pb-Free (RoHS), Pb-Free (RoHS Exempt), or Green (RoHS & no Sb/Br) - please check
http://www.ti.com/productcontent for the latest availability information and additional product content details.
TBD: The Pb-Free/Green conversion plan has not been defined.
Pb-Free (RoHS): TI's terms "Lead-Free" or "Pb-Free" mean semiconductor products that are compatible with the current RoHS requirements
for all 6 substances, including the requirement that lead not exceed 0.1% by weight in homogeneous materials. Where designed to be soldered
at high temperatures, TI Pb-Free products are suitable for use in specified lead-free processes.
Pb-Free (RoHS Exempt): This component has a RoHS exemption for either 1) lead-based flip-chip solder bumps used between the die and
package, or 2) lead-based die adhesive used between the die and leadframe. The component is otherwise considered Pb-Free (RoHS
compatible) as defined above.
Green (RoHS & no Sb/Br): TI defines "Green" to mean Pb-Free (RoHS compatible), and free of Bromine (Br) and Antimony (Sb) based flame
retardants (Br or Sb do not exceed 0.1% by weight in homogeneous material)

(3)
MSL, Peak Temp. -- The Moisture Sensitivity Level rating according to the JEDEC industry standard classifications, and peak solder
temperature.

Important Information and Disclaimer:The information provided on this page represents TI's knowledge and belief as of the date that it is
provided. TI bases its knowledge and belief on information provided by third parties, and makes no representation or warranty as to the
accuracy of such information. Efforts are underway to better integrate information from third parties. TI has taken and continues to take
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incoming materials and chemicals. TI and TI suppliers consider certain information to be proprietary, and thus CAS numbers and other limited
information may not be available for release.

In no event shall TI's liability arising out of such information exceed the total purchase price of the TI part(s) at issue in this document sold by TI
to Customer on an annual basis.

Addendum-Page 1
 PACKAGE MATERIALS INFORMATION
www.ti.com 13-Oct-2007

TAPE AND REEL BOX INFORMATION

Device Package Pins Site Reel Reel A0 (mm) B0 (mm) K0 (mm) P1 W Pin1
Diameter Width (mm) (mm) Quadrant
(mm) (mm)
TPS51100DGQR DGQ 10 SITE 60 330 12 5.3 3.4 1.4 8 12 Q1

Pack Materials-Page 1
 PACKAGE MATERIALS INFORMATION
www.ti.com 13-Oct-2007

Device Package Pins Site Length (mm) Width (mm) Height (mm)
TPS51100DGQR DGQ 10 SITE 60 346.0 346.0 29.0

Pack Materials-Page 2
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