ASSIGNMENT PREPARED BY: SHIMOGA YALAL

ASIC:

ASIC means Application Specific Integrated Circuit. It is a device that is created for a
specific purpose or functionality. They contain only one functionality in them and through
the lifetime of the chip, it can perform only that function. For example, CPU in your phone
is an ASIC. It is meant to function as a CPU for its whole life. Its logic function cannot be
changed to anything else because its digital circuitry is made up of permanently connected
gates and flip-flops on silicon. The difference in case of ASIC is that the resultant circuit is
permanently drawn into silicon whereas in FPGA the circuit is made by connecting a
number of configurable blocks.

ASIC DESIGN FLOW:

SPECIFICATION FLOORPLAN

ARCHITECTURAL DESIGN PLACEMENT

RTL DESIGN CLOCK TREE SYNTHESIS

RTL VERIFICATION ROUTING

SYNTHESIS SIGNOFF & FABRICATION

GATE LEVEL SIMULATION POST SILICON VALIDATION

DESIGN FOR TEST CHIP

FRONTEND BACKEND

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1. SPECIFICATION: The specification for the product is collected from the market
or customer requirements. The specification also consists of what all features
the product should consist of etc. These are generally collected by marketing
people.

2. ARCHITECTURAL DESIGN: The architectural design consists of what all blocks

the design should consist of and how they are connected in the design. They
come up with a block diagram which includes all the above based on the
specification. This architecture team will estimate the block area, how much
power is required and cost for the design.

3. RTL DESIGN: The RTL design is developed using HDL. It is developed based on
the architecture design. It is written in Verilog or VHDL. This code describes
how the data is transferred between different components in the design.

4. RTL VERIFICATION: Verifying the developed design is done in this stage. Test
cases will be developed to check the functionality of the design and if found
any bug in the design, it is intimated to designer to modify it and release the
new RTL. Verification itself takes 60 percent of total lifecycle time of chip
development. This stage is very important as the design is tested for its
functionality. Any bugs found post routing is difficult to correct and also post
fabrication we cannot correct the design. So this is very important part of a
chip development cycle.

5. SYNTHESIS: It is a process of converting the RTL code into gate level netlist. Up
to RTL verification the design is technology independent. In synthesis process
the design is converted into technology dependent. It is a 3 stage process:
a. Translation: RTL code is converted to Boolean expressions.
b. Optimization: Boolean expression is optimized by SOP and POS
optimization methods
c. Mapping: In this the Boolean expression is converted into gates based
on the technology and generates a gate level netlist. The inputs for
synthesis are RTL code, .SDC and .LIB files. After the synthesis the
generated outputs are gate level netlist and .SDC files.

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6. GATE LEVEL SIMULATIONS: Gate level simulation is used to boost the
confidence regarding implementation of a design and can help verify dynamic
circuit behavior, which cannot be verified accurately by static methods. It is
run after RTL code is simulated and synthesized into a gate-level netlist. Gate
level simulation overcomes the limitations of static-timing analysis and is
increasing being used due to low power issues, complex timing checks at 40nm
and below, design for test (DFT) insertion at gate level and low power
considerations. For DFT, scan chains are inserted after the gate-level netlist is
created; gate level simulation is often used to determine whether scan chains
are correct

7. DESIGN FOR TESTABILITY: Design for testability (DFT) is a technique which

facilitates a design to become testable after production. In this stage we put
extra logic along with the design logic during implementation process which
helps post production process. The DFT will make the testing easy at post
production process. At this stage an ATPG (automatic test pattern generator)
file will generate.

8. FLOORPLAN: The floorplan is the process of determining the macro placement,

power grid generation and I/O placement. It is the process of placing
blocks/macros in the chip/core area there by determining routing areas
between them. It determines the size of the die and creates wire tracks for
placement of standard cells. It creates power straps and specifies pg
connection. It also determines the I/O, pin/pad placement information.

9. PLACEMENT: Placement is the process of automatically assigning correct

position to standard cells on the chip with no overlapping. By global placement
outside of standard cells will be placed inside roughly. By the detailed
placement the standard cells will place in site rows (legalize placement).In
placement stage we check the congestion value by GRC map.

10. CLOCK TREE SYNTHESIS (CTS): In this stage we built the clock tree by using
inverters and buffers. In the chip clock signal is essential to the flip flops, to
give the clock signal from clock source we built the clock tree. It is the process
of balancing the clock skew and minimizing insertion delay in order to meet
timing and power.

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11. ROUTING: Before the routing stage the connection between the macros,
standard cells, clock, i/o port are logical connections. In this stage we connect
all the cells physically with the metal straps. Routing is divided as two parts 1)
Global routing 2) Detailed routing. The global routing will tell for which signal
which metal layer is used. Before the detailed routing all are the logical
connections. In detailed routing the physical connections are done.

12. SIGNOFF & FABRICATION: After the routing the physical layout of chip is
completed. In signoff stage all the tests are done to check the quality and
performance of the layout before tapeout. After this the design is converted
into GDS II file. By the GDS II file information we fabricate the chip. The total
design is converted into chip by the manufacturing process.

13. POST SILICON VALIDATION: Post-silicon validation is used to detect and fix
bugs in integrated circuits and systems after manufacture. Post-silicon
validation involves operating one or more manufactured chips in actual
application environments to validate correct behaviours over specified
operating conditions. The objective is to ensure that no bugs escape to the
field. If there is any fault in the design then we modifies the design by repeating
the steps. If there are no faults then chip will go to packaging.

14. CHIP: Finally we get the required chip which will be manufactured in bulk. If
we use this process to produce only 1 chip, it costs a lot more than the actual
chip cost after production. If we produce the chips in bulk, we can save the
silicon wafer for producing more chips with single wafer and the cost of the
production for each chip will be less than the cost for which it has been sold.

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  MOORE’S LAW: Moore’s law is the observation that the number of transistors
in a dense integrated circuit doubles about every two years.

 This has been continuously driving the VLSI industry and the results of this law
are the latest technological nodes (i.e. 28nm, 14nm, 12nm, 10nm, 7nm, 5nm).
The technology node depends on the length of the gate channel. So, if the
length of the gate channel is 10nm we call it as 10nm technology node.

ASIC Design Flow varying from one technology to another (14nm to 7nm):

1. RTL – As technology changes, this process remains same.

2. DESIGN VERIFICATION – As technology changes, this process remains same.

3. SYNTHESIS – Synthesis step translates a RTL code to gate level netlist using
logical synthesis tool and physical libraries. Whenever there is a change in
technology node all the libraries gets updated due to which new netlist needs
to be generated using synthesis tool and libraries.

4. FLOOR PLANNING – In this step blueprint of chip is generated with logical IPs
and major blocks into physical layout of the chip. It involves block placement,
pin placement, physical portioning and power optimization. With the
technology update like updating from 14nm to 7nm, all the floor planning
should be redone with new pin placement, signal delays and block placement
according to the new chip size.

5. CLOCK TREE SYNTHESIS – In this step, clock tree is built to achieve defined
timing, area and power requirements. It helps in providing the clock
connection to the clock pin of a sequential element in the required time and
area, with low power consumption. With technology update all the buffer
insertions should be re-planned to achieve new delays in CTS.

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 6. ROUTING –
Global Routing: Calculates estimated values for each net by the delays of
fan-out of wire. Global routing is mainly divided into line routing and maze
routing.

Detailed Routing: In detailed routing, the actual delays of wire is calculated

by various optimization methods like timing optimization, clock tree
synthesis, etc.

As we are moving towards a lower technology node like moving from 14nm
to 7nm, engineers face complex design challenges with the need for
implanting millions of gates in a small area. In order to make this ASIC
design routable, placement density range needs to be followed for better
QoR. Placement density analysis is an important parameter to get better
outcomes with less number of iterations.

7. FINAL VERIFICATION (PHYSICAL VERIFICATION AND TIMING) – After routing,

ASIC design layout undergoes three steps of physical verification, known as
signoff checks. This stage helps to check whether the layout working the way
it was designed to. The following checks are followed to avoid any errors just
before the tapeout:

Layout versus schematic (LVS) is a process of checking that the

geometry/layout matches the schematic/netlist.

Design rule checks (DRC) is the process of checking that the geometry in the
GDS file follows the rules given by the foundry.

Logical equivalence checks (LVC) is the process of equivalence check between

pre and post design layout.

This entire step need to be rerun while moving from one node to another as all the
backdoor flow gets updated with new libraries of new technology.

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FPGA DESIGN FLOW OVERVIEW:

FPGA means Field Programmable Gate Array. It can be “field” programmed to

work as per the intended design. It means it can work as a microprocessor or graphics
card, or even as both at once. The designs running on FPGA’s are generally created using
hardware description languages such as VHDL and Verilog. FPGA is made up of number of
Configurable Logic Blocks (CLB’s) and are connected with Programmable Interconnects.
The CLB’s are primarily made of Look-Up Tables (LUT’s), Multiplexers and Flip-Flops. They
can implement complex logic functions. Apart from CLB’s, and routing interconnects,
many FPGA’s also contain dedicated hard-silicon blocks for various functions such as Block
RAM, DSP Blocks, External Memory Controllers, PLL’s etc. These dedicated hardware
blocks are critical in competing with ASIC’s.

Design entry can be done using various techniques, such as schematics, through
Hardware Description Language or HDL, or you may even combine the two and use a best
of both worlds approach using tools that can convert HDL into schematics and vice versa
depending on your FPGA design and preference. Generally, for a design that deals more
with complex systems, it is better to opt for HDL, a quicker, language-based process that
rids you of the need to design in lower level hardware, while schematics is a good choice
for someone who wishes to design hardware because it gives more visibility to the entire
system. You can also opt to go for a state-machines based approach, but it is largely
limited and unused currently. It is suited for designers who view their design as a series of
states.

There are benefits and downsides associated with each approach. While a
schematic based technique is easier to read and comprehend, it tends to only work with
relatively smaller projects. HDL based approaches, on the other hand, tend to be fast and
easy to implement, and today is most popular design entry for FPGA designs.

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FPGA engineering process usually involves the following stages:

1. ARCHITECTURE DESIGN: This stage involves analysis of the project

requirements, problem decomposition and functional simulation (if
applicable). The output of this stage is a document which describes the future
device architecture, structural blocks, their functions and interfaces.

2. HDL DESIGN ENTRY: The device is described in a formal hardware description

language (HDL). The most common HDLs are VHDL and Verilog.

3. TEST ENVIRONMENT DESIGN: This stage involves writing of test environments

and behavioural models (when applicable). They are later used to ensure that
the HDL description of a device is correct.

4. BEHAVIOURAL SIMULATION: This is an important stage that checks HDL

correctness by comparing outputs of the HDL model and the behavioural
model (being put in the same conditions).

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 5. SYNTHESIS: This stage involves conversion of an HDL description to a so-called
netlist which is basically a formally written digital circuit schematic. Synthesis
is performed by a special software called synthesizer. For an HDL code that is
correctly written and simulated, synthesis shouldn't be any problem. However,
synthesis can reveal some problems and potential errors that can't be found
using behavioral simulation, so, an FPGA engineer should pay attention to
warnings produced by the synthesizer.

6. IMPLEMENTATION: A synthesizer-generated netlist is mapped onto particular

device's internal structure. The main phase of the implementation stage is
place and route or layout, which allocates FPGA resources (such as logic cells
and connection wires). Then these configuration data are written to a special
file by a program called bit stream generator.

7. TIMING ANALYSIS: During the timing analysis special software checks whether
the implemented design satisfies timing constraints (such as clock frequency)
specified by the user.

Difference between ASIC and FPGA:

S.
ASIC FPGA
No.
1 ASIC’s can’t be reconfigured with FPGA’s can be reconfigured with
different design. They contain only one different designs.
design in them for the whole life time.
2 It is suited for bulk production. It is not suited for bulk production.
3 It is energy efficient and consumes less It consumes more power than ASIC.
power than FPGA.
4 Higher frequencies can be achieved on Limited in operating frequency on a
the same node. particular node.
5 It is built only after validating the design It is used to prototype and validate a
for permanent use of that design and design.
silicon

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