Proceedings of the 2016 IEEE Students’ Technology Symposium

Analysis and Design of Low Power Nonlinear PFD

architectures for a Fast Locking PLL
Abdul Majeed K.K, Binsu J Kailath
Department of Electronics
Indian Institute of Information Technology Design and Manufacturing (IIITDM) Kancheepuram, Chennai, India
edm12d001@ iiitdm.ac.in, bkailath@iiitdm.ac.in

Abstract— Two novel nonlinear phase frequency detectors UP

Vdd D Q Vavg Blind zone
(NL-PFD1 and NL-PFD2) designed with the objective of FF1
Clk Vdd
achieving higher gain, eliminating blind zone, reducing dead zone Rst
and area are proposed in this paper. Using pass transistor logic CLKref
Dead zone
in realizing D-flip-flop has resulted in higher gain, area reduction -2π 2π
and higher maximum frequency for NL-PFD2. Reset delay and CLKvco φ (rad)
dead zone are also found to be reduced using simple structure. Rst
Clk DN
The necessity of reset action is eliminated in both the NL-PFDs as FF2
-Vdd
D Q
UP and DN signals are never allowed to reach logic high Vdd
simultaneously and hence, blind zone is completely eliminated in Fig.1(a) Fig.1(b)
both the cases. Nonlinear Phase-Voltage characteristics of PFD Fig. 1 (a) Logical schematic of conventional linear PFD (b) Transfer
has been modeled using Fourier series and time response of PLL characteristics of conventional linear PFD
using state space technique and both have been validated by approximation in the analysis of PLL introduces considerable
simulation in MATLAB and circuit simulation in Cadence. PLL
amount of error when PLL is modeled in s-domain [6]. Hence
built with the NL-PFDs are found to provide a lock time of 1.753
µs and reference spur of -56.7 dBc with 180 nm CMOS process
PLL model has been developed using differential equations
while power dissipation in NL-PFD2 is observed to be only and state space model [6, 7] as discussed in section V followed
0.27µW. by summary and conclusion in section VI and VII respectively.

Keywords— Phase Locked Loop, Nonlinear phase frequency

II. CONCEPTUAL DESIGN OF PROPOSED NL-PFDS
detector, Dead zone, Blind zone, Lock time, Reference spur, The logical schematic of conventional linear PFD (L-PFD)
and its -V characteristics are shown in Fig. 1(a) and (b)
I. INTRODUCTION
respectively. L-PFD has a gain (KPL) of for entire
High-speed, low power, phase locked loops operating in range of phase error from 0 to 2π. L-PFD suffers from non-
gigahertz frequency range have become particularly critical in zero dead zone and blind zone which results in lower loop
mobile wireless communications, portable wireless terminals bandwidth and larger locking time. NL-PFD has similar -V
as well as highly integrated multichannel fiber optics receivers.
characteristics as that of L-PFD when magnitude of  is less
Phase frequency detector (PFD) is, one of the important
than or equal to π whereas a constant output equal to ±V dd is
building blocks in the PLL system, which plays a significant
role in defining its lock-in time. As linear PFDs (L-PFD) obtained for  greater than π.
contribute dead zone, blind zone, lower gain and larger lock Logical schematic of proposed NL-PFD1 and NL-PFD2 are
time [1-2], nonlinear PFDs (NL-PFD) have been proposed as a given in Fig. 2 (a) and (b) wherein CLKref the input signal,
popular alternative in recent years [3-4]. Even though NL- CLKvco the output of divide by N counter, UP and DN the
PFDs offer higher gain, complex circuits with higher reset output signals of PFD, and Tstart the initializing signal used to
delay and non-zero dead zone raise serious design constraints. Vdd UP
Vdd UP
D Qb
The output phase jitter due to external noise should be reduced CLKref FF1 D
FF1
Qb
Clk CLKref
by narrowing the loop bandwidth whereas the loop bandwidth Rst
Clk
Q
Rst
should be made as wide as possible for quicker lock-in process
[5]. N1 N1
Tstart Tstart
To mitigate the above said design constraints, two
nonlinear PFD architectures are proposed in this paper which N2 N2
CLKvco CLKvco
together with charge pump provide higher gain during transient Rst Rst
condition of the lock-in process and lower gain under steady Clk
FF2 DN
Clk Q
DN
FF2
state condition is proposed in this paper. Conceptual designs of D Qb D Qb
both the NL-PFDs are presented in section II while circuit level Vdd Vdd
architecture is discussed in section III. Circuit simulation (a) (b)
results are provided in section IV. Due to the sampling nature Fig. 2 (a) Logical diagram of proposed NL-PFD1 (b) Logical diagram of
and nonlinear characteristics of NL-PFD, continuous time proposed NL-PFD2.

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Vdd CLKref and CLKvco are at logic zero, both P1 and P3 would be
CLKref “on” pulling the nodes a and b up to logic high, which would
P1 P2 UP make N4 and N8 “on”, pulling the nodes c and d down to
a e
logic zero. During the condition when │Δ│< π, two cases
N1
INV1 wherein CLKref leading CLKvco and CLKvco leading CLKref
N2
c V need to be analyzed. The latter case in the following
dd
N3 N4 discussion is given in parentheses. At the rising edge of
Tstart N9
P5
CLKref (CLKvco), N2(N6) would turn on, which would pull the
gnd node e(f) down to logic zero as N4 (N8) would continue in the
Reset signal N10 “on” condition and node a(b) is still at logic high. This would
N11 make the UP(DN) signal go to logic high, and it would
P3 N12 remain at high until the rising edge of CLK vco (CLKref). At the
gnd DN
b P4 rising edge of CLKvco (CLKref), N6(N2) would turn “on”
N5 f
INV2 which would pull the voltage at node f(e) down to zero as
N6
CLKvco
d N8(N4) would continue in the “on” condition and node b(a) is
N7 N8 still at logic high. This would make the DN (UP) signal also to
go to logic high. At the same time, as both the nodes e and f
gnd are at logic low, reset signal would be at logic high making
Fig. 3 Transistor level circuits of Proposed NL-PFD1 both N1 and N5 “on”. Hence the potentials at nodes e and f
ensure UP and DN initially at zero are also marked. The main would be pulled to logic high making both UP and DN signals
difference between these designs is that the D flip-flop in NL- to logic low.
PFD2 is built with pass transistor logic while that used in NL- Similarly, when │Δ│> π also, the two cases wherein
PFD1 uses conventional structure. In order to reduce the delay
CLKref leading CLKvco and CLKvco leading CLKref need to be
caused by the logic gate, reset signal is derived from the Q
output of the other D-F/F in NL-PFD2. analyzed. The latter case in the following discussion also is
given in parentheses. When CLKref (CLKvco) is leading CLKvco
III. CIRCUIT LEVEL IMPLEMENTATION OF PROPOSED NL-PFDS (CLKref), UP (DN) would be made to go high and DN(UP) to
zero and this status would continue until the rising edge of
A. Circuit Level Implementation of NL-PFD1 CLKvco (CLKref). At the rising edge of CLKvco (CLKref), DN
Transistor level implementation of NL-PFD1 is shown in (UP) also would become one. However, even though the reset
Fig.3. Whenever the potential at any or both of the nodes e signal is high, potential at node a (b), would not be pulled
and f is at logic high, reset signal would be at logic low down to zero as N3 (N7) is “off” because CLKref (CLKvco) has
making both N1 and N5 turn “off”. Whenever potential at already become logic low.
both nodes e and f are at logic low which happens when both On the contrary, the high reset signal would cause the
UP and DN are at logic high, reset signal would be at logic potential at node b(a) to be pulled down to logic zero as both
high making both N1 and N5 turn “on”. This would pull the N5 and N7 (N1 and N3) are “on”. This would ensure UP
voltages at nodes a and b down to zero, which in turn would (DN) to continue at logic one and DN (UP) at zero. This status
make P2 and P4 “on” making the potentials at nodes e and f to (UP (DN) =1, DN (UP)=0) would continue until the phase
logic high. difference between CLKref (CLKvco) and CLKvco (CLKref)
The circuit is initialized with Tstart. Initially, when both become less than π.
CLKref B. Circuit Level Implementation of NL-PFD2
Vdd Reset delay contributed by the combination of three NMOS
INV1 INV2 UP transistors and its dependence on CLKref and CLKvco has been
p
found to be limiting the maximum operating frequency in NL-
P1 N5
PFD1. Any reduction in the number of transistors used would
N1 DN
2
Tstart 0
N2 N7 2 UP
0
N3 CLKREF CLKVCO
Voltage(V)

2
N8 0
CLKVCO
gnd 2
Vdd N4 DN
0
CLKREF
N6 2
P2
0
q 2 TSTART
CLKvco INV3 INV4
0
0 Time(ns) 150
Fig. 4 Transistor level circuits of Proposed NL-PFD2 Fig. 5 Transient response of NL-PFDs (both are found to be overlapping)

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leading CLKvco (CLKref), at the rising edge of CLKref (CLKvco),

Proposed NL-PFDs Blind Zone UP(DN) would become logic one. Even when CLKref (CLKvco)
150µ 1.8
Conventional L-PFD makes a high to low transition which happens before CLKvco
(CLKref) makes the low to high transition, UP (DN) would
75µ 0.9 remain at high until the rising edge of CLK vco (CLKref). At the
rising edge of CLKvco (CLKref), DN (UP) also become logic
Current (A)

Voltage (V)
  one. At this instant, as both UP and DN are at logic one, the

0 0.0 potentials at both the nodes p and q would be pulled down to
  logic zero. However, only DN (UP) signal would be forced to
 (rad) logic zero but UP (DN) would remain at logic one as N5 (N6)
-75µ Dead Zone -0.9 is off. This status would continue until the phase difference
between CLKref (CLKvco) and CLKvco (CLKref) become less
than π.
-150µ -1.8
IV. RESULTS OF DESIGNED NL-PFDS
-10n 0 -5n 5n 10n
Time delay (s) A. Transient Analysis
Fig. 6 Transfer characteristics NL-PFDs obtained from simulation of The transient analysis of NL-PFD1 and NL-PFD2 are
equation (1) in MATLAB and from circuit simulation in Cadence (both are
found to be overlapping)
presented in Fig. 5 wherein both the circuits provide exactly
also result in reduction in area requirement and power similar characteristics. CLKref is a symmetrical square wave
consumption. In view of this NL-PFD2 has been implemented with a time period of 10 ns and CLK vco has a time period of 11
by eliminating logic gates causing delay from the reset path ns with a duty cycle of 45%. It can be observed that for an
and using pass-transistor logic. Even though pass transistor initial duration of 50 ns when the phase difference between
logic normally causes delay; here its effect is very minimal as CLKref and CLKvco is less than π, the pulse width of UP signal
the reset path is devoid of other delay elements. is increasing as the phase difference Δ is increasing. After 50
Transistor level implementation of NL-PFD2 is shown in ns, when the phase difference is greater than π with CLKref
Fig.4. After initializing the circuit with Tstart, when both leading CLKvco, the UP signal is held at high until the phase
CLKref and CLKvco are at logic zero, both P1 and P2 would be difference become less than π which happens after about five
turned “on”, pulling the nodes p and q up to logic high. As in cycles of CLKref and CLKvco. Similar characteristics have been
NL-PFD1, the two cases wherein CLKref leading CLKvco and obtained for DN signal when CLKvco is leading CLKref.
CLKvco leading CLKref need to be analyzed. The latter case is B. Phase-Voltage ( Characteristics
given in parentheses in the following discussion. Considering
The output voltage as a function of input phase difference
the case when │ΔΦ│< π and CLKref (CLKvco)is leading
for both the NL-PFDs are presented in Fig. 6 and can be
CLKvco (CLKref), at the rising edge of CLKref (CLKVCO), UP
(DN) signal goes to logic one. UP (DN) would remain at high expressed as
until the rising edge of CLKvco (CLKref) whereas at the rising
The function representing both linear and non-linear
edge of CLKvco (CLKref), DN (UP) signal become logic one.
operating regions is determined using Fourier series as:
At this instant as both UP and DN are at logic one, the
potentials at both the nodes p and q would be pulled down to (1)
logic zero through N1, N2, N3 and N4, N2, N3 respectively.
Hence both UP and DN signals would be forced to logic zero. Equation (1) has been plotted in MATLAB as  is varied
Considering the case when │ΔΦ│> π and CLKref (CLKvco) is from -2π to 2π, with n varying from 1 to 200 and is given in
3.0 Fig. 6. The  -I characteristics of both the NL-PFDs have also
Proposed NL-PFD1
been determined from circuit simulation by introducing a
Proposed NL-PFD2
2.4 delay between CLKvco and CLKref and are also plotted in Fig.
Max. Ope. Fre. (GHz)

Conventional PFD
6 with time delay varying from -10 ns to 10 ns corresponding
to phase difference of -2π to 2π. The results from circuit
1.8
simulation in Cadence and simulation of equation (1) in
MATLAB are found to be exactly matching with each other.
1.2
C. Maximum Operating Frequency and Area of NL-
PFDs
0.6
Maximum operating frequency [8] as a function of supply
voltage for conventional L-PFD and NL-PFDs are plotted in
0.0 Fig. 7. Both NL-PFDs are implemented using GPDK090
1.5 2.0 2.5
Supply Voltage(V) library of 180 nm technologies and the layout areas are found
Fig.7 Maximum Operating Frequency as a function of supply voltage of NL- to be much less than that in the latest reported works, a
PFDs and conventional L-PFD comparison of which is presented in Table I.

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15.75 µm 15.1 µm
e<0

CLKref tp

T- T-

15.91 µm

14.53 µm
tp
CLKvco

e>0
Fig. 10 Definition of the variable tp and T-
(5)
(a) (b)
Fig. 8 Layout of Proposed (a) NL-PFD1 (b) NL-PFD2 The state matrices A, B, C and D for the two sets of equations
The chip layout of NL-PFD1 and NL-PFD2 are presented in given above could be expressed as a single matrix for each, by
Fig. 8 (a) and (b) respectively. Final placement of NL-PFD1 combining equations for the first and second loops and hence
requires 15.75 µm in width and 15.91 µm in length giving a
chip area of 250.58 µm2 while NL-PFD2 requires 15.10 µm in
width and 14.53 µm in length giving a chip area of 209.40
µm2.
Loop gain for this model is found to be:
V. STATE SPACE ANALYSIS OF PLL WITH NL PFD (6)
Due to the sampling nature and nonlinear characteristics of
Where
NL-PFD, continuous time approximation in the analysis of
PLL introduces a considerable amount of error when PLL is
modeled in s-domain [6]. Hence model for the PLL is given in (7)
Fig. 9 is developed using differential equations and state space
model [6, 7] as discussed below.
Input phase error and the voltage across the capacitors in Final solution is obtained by following the standard
the loop filter are identified as the state variables. The input procedure given by
phase error is represented by its time equivalent parameter , (8)
whose limits depend up on the actual time delay or and the final solution of this state equation for the PLL is
advancement between the input signals as shown in Fig.10 and determined as
defined below. For

(2)
XVcnT σIp t22+ bRC (9)
Differential equations corresponding to the input phase
error and voltages across the capacitors at nodes Vcnt and Vc σ (10)
(marked in Fig. 9) could be expressed for both the loops as: σ
(3) (11)
(4) 0.9
PLL Transient Analysis

0.8
Vdd
Voltage (V)

KPD Kvco
CLKref UP Icp
Voltage Fout
Vcnt 0.7
Nonlinear Controlled
CLKvco PFD Oscillator ts=1.753 s
DN R
Vc 𝑪 0.6
𝒃 𝟏
Icp C
0.5
500.0n 1.0µ
1.5µ 2.0µ 2.5µ
Time (s)
Divided by N counter
Fig. 11. Time responses of Control voltage (Vcnt) obtained from state
Fig. 9 Block diagram of PLL equation and circuit simulation

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Two cases are considered wherein the phase error is positive TABLE I
when the value of is +1, and if the phase error is negative PERFORMANCE COMPARISON OF NONLINEAR PFDS
then the value of is -1. Quantity
NL- NL- [3] [4]
PFD1 PFD2
For
Power consumption(µW) 43 0.27 37 62
No. of Transistors 21 18 22 38
(12) Maximum Operating 1.33 2.15 2 1.25
Frequency ( GHz)
(13) Blind zone (ps) free free free free
(14) Area (µm2 ) 250 209 -- --
TABLE II
Where PERFORMANCE COMPARISON OF PLL
and This [5] [9] [10] [11]
Quantity
work
Complete characteristics of the charge pump PLL with
Fref(MHz) 20 14 64 48 50
nonlinear PFD can be defined by the exact equations given by N 128 32 64 48 44
equations (8) to (14). The validity of this model has been Loop Bandwidth (MHz)
verified by plotting equations (10) and (13) in MATLAB and Non Linear 2.25 0.12 0.4 0.5 5
comparing the characteristics with that obtained from circuit Linear 0.9 0.04 0.05 0.5 5
simulation in Cadence and are presented in Fig. 11. It can be Output Frequency (GHz) 2.56 0.448 2.4 2.3 2.2
Lock Time (µs) 1.753 18 20 21m 4
observed that good matching between the graphs has been Reference Spur (dBc) -56.7 -- -54 -55 -41
obtained for both the node voltages Vcnt(t).
in increase in gain of the PFD resulting in lock time of the
VI. PLL IMPLIMENTATION AND MEASUREMENT RESULT PLL. Using pass transistor logic in realizing D-flip-flop has
resulted in a higher gain, area reduction, and higher maximum
In order to compare the performance of proposed NL-
frequency for NL-PFD2. Moreover reset delay and dead zone
PFD with that of reported PFD, a PLL has been designed and
are also reduced using a simple logic for NL-PFD2. PLL has
implemented using 180 nm technology in Cadence using
been built with the proposed components and modeled using
second order loop filter (R1=1 KΩ, C1=277 pF and C2=25 pF),
state space technique and excellent matching of characteristics
CMOS delay-cell based VCO with KVCO = 20 GradV-1,
have been obtained when the results from MATLAB
Charge pump with Icp=150 µA, Divide by 128 (N) counter and
simulations and Circuit simulations from Cadence are
Fref = 20 MHz to obtain a PLL with a frequency of 2.56 GHz.
compared.
The lock time has been determined by circuit simulation as
1.753 µs (Marked with a dotted line in Fig. 11) and reference REFERENCES
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Fig. 12 Output Spectrum of PLL using NL-PFD2

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