OMAP543x ES2.0 DM Operating Condition Addendum Public Version 0.

OMAPTM

OMAP543x Multimedia Device

Engineering Samples ES2.0
Texas Instruments OMAPTM Family of Products

Data Manual Operating Condition Addendum

Version 0.6

Public Version

Literature Number: SWPU329

May 13

OMAP is a trademark of Texas Instruments

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All other trademarks are the property of their Public Version

respective owners.
 OMAP543x ES2.0 DM Operating Condition Addendum Public Version 0.6

HISTORY

Version Date Notes

0.6 20-May-13 1

Note:
1. Creation.

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 OMAP543x ES2.0 DM Operating Condition Addendum Public Version 0.6

WARNING: EXPORT NOTICE

Recipient agrees that it will not knowingly export or re-export, directly or indirectly, any product or
technical data (as defined by the U.S, EU and other Export Administration Regulations) including
software, or any controlled product restricted by other applicable national regulations, received from
Disclosing party under this Agreement, or any direct product of such technology, to any destination to
which such export or re-export is restricted or prohibited by U.S or other applicable laws, without
obtaining prior authorisation from U.S. Department of Commerce and other competent Government
authorities to the extent required by those laws. This provision shall survive termination or expiration of
this Agreement.
According to our best knowledge of the state and end-use of this product or technology, and in
compliance with the export control regulations of dual-use goods in force in the origin and exporting
countries, this technology is classified as follows:

-US ECCN: 3E991

-EU ECCN: 3E991

and may require export or re-export license for shipping it in compliance with certain countries
regulations.

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 OMAP543x ES2.0 DM Operating Condition Addendum Public Version 0.6

TABLE OF CONTENTS

OMAP543X MULTIMEDIA DEVICE ........................................................................................................1

1 INTRODUCTION .............................................................................................................................5
1.1 DEVICE SUPPORT NOMENCLATURE ............................................................................................6
1.2 OMAP543X MIPI® DISCLAIMER ................................................................................................6
1.3 TRADEMARKS ............................................................................................................................7
1.4 COMMUNITY RESOURCES ..........................................................................................................8
2 RECOMMENDED OPERATION......................................................................................................9
2.1 MICRO PROCESSOR UNIT (MPU) ...............................................................................................9
2.2 MULTIMEDIA (MM) AND 3D GRAPHIC ACCELERATOR (GPU) .................................................... 11
2.2.1 MultiMedia (MM) .............................................................................................................. 11
2.2.2 3D Graphic Accelerator (GPU) ........................................................................................ 13
2.3 CORE ................................................................................................................................... 14
3 OPP DEPENDENCIES ................................................................................................................. 16
IMPORTANT NOTICE ........................................................................................................................... 17

OMAP is a trademark of Texas Instruments

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All other trademarks are the property of their Public Version

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 OMAP543x ES2.0 DM Operating Condition Addendum Public Version 0.6

1 INTRODUCTION
The aim of this document is to describe the operating conditions of the all OMAP543x ES2.0 devices.

This document contains the description of each OPP (Operating Performance Point) for processors
clocks and device core clocks.

Table 1-1 describes the supported operating performance point (OPP) on MPU for each OMAP543x
devices.

Table 1-1. OMAP543x vdd_mpu Operating Points (1)

OMAP543x Devices OPP_LOW_MPU OPP_NOM_MPU OPP_HIGH_MPU OPP_SPEEDBIN_MPU

OMAP5430-SB √ √ √ √

OMAP5430 √ √ √

OMAP5432-SB √ √ √ √

OMAP5432 √ √ √

(1) This table is specific to vdd_mpu with AVS feature enabled.

Table 1-2 describes the supported operating performance point (OPP) on MM for each OMAP543x
devices.

Table 1-2. OMAP543x vdd_mm Operating Points (1)

OMAP543x
OPP_LOW_MM OPP_NOM_MM OPP_OD_MM
Devices
OMAP5430-SB √ √ √

OMAP5430 √ √ √

OMAP5432-SB √ √ √

OMAP5432 √ √ √

(1) This table is specific to vdd_mm with AVS feature enabled.

Table 1-3 describes the supported operating performance point (OPP) on CORE for each OMAP543x
devices.

Table 1-3. OMAP543x vdd_core Operating Points (1)

OMAP543x
OPP_NOM_CORE
Devices
OMAP5430-SB √

OMAP5430 √

OMAP5432-SB √

OMAP5432 √

(1) This table is specific to vdd_core with AVS feature enabled.

OMAP is a trademark of Texas Instruments

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All other trademarks are the property of their Public Version

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 OMAP543x ES2.0 DM Operating Condition Addendum Public Version 0.6

1.1 Device Support Nomenclature

This device is currently in development. Experimental / Prototype devices are shipped against the
following disclaimer:

“This product is still in development and is intended for internal evaluation purposes.”
Notwithstanding any provision to the contrary, TI makes no warranty expressed, implied, or statutory,
including any implied warranty of merchantability of fitness for a specific purpose, for experimental /
prototype devices.

1.2 OMAP543x MIPI® Disclaimer

The material contained herein is not a license, either expressly or impliedly, to any IPR owned or
controlled by any of the authors or developers of this material or MIPI. The material contained herein is
provided on an “AS IS” basis and to the maximum extent permitted by applicable law, this material
is provided AS IS AND WITH ALL FAULTS, and the authors and developers of this material and MIPI
hereby disclaim all other warranties and conditions, either express, implied or statutory, including, but
not limited to, any (if any) implied warranties, duties or conditions of merchantability, of fitness for a
particular purpose, of accuracy or completeness of responses, of results, of workmanlike effort, of lack
of viruses, and of lack of negligence.

ALSO, THERE IS NO WARRANTY OF CONDITION OF TITLE, QUIET ENJOYMENT, QUIET

POSSESSION, CORRESPONDENCE TO DESCRIPTION OR NON-INFRINGEMENT WITH
REGARD TO THIS MATERIAL OR THE CONTENTS OF THIS DOCUMENT. IN NO EVENT WILL
ANY AUTHOR OR DEVELOPER OF THIS MATERIAL OR THE CONTENTS OF THIS DOCUMENT
OR MIPI BE LIABLE TO ANY OTHER PARTY FOR THE COST OF PROCURING SUBSTITUTE
GOODS OR SERVICES, LOST PROFITS, LOSS OF USE, LOSS OF DATA, OR ANY INCIDENTAL,
CONSEQUENTIAL, DIRECT, INDIRECT, OR SPECIAL DAMAGES WHETHER UNDER CONTRACT,
TORT, WARRANTY, OR OTHERWISE, ARISING IN ANY WAY OUT OF THIS OR ANY OTHER
AGREEMENT, SPECIFICATION OR DOCUMENT RELATING TO THIS MATERIAL, WHETHER OR
NOT SUCH PARTY HAD ADVANCE NOTICE OF THE POSSIBILITY OF SUCH DAMAGES.

Without limiting the generality of this Disclaimer stated above, the user of the contents of this
Document is further notified that MIPI: (a) does not evaluate, test or verify the accuracy, soundness or
credibility of the contents of this Document; (b) does not monitor or enforce compliance with the
contents of this Document; and (c) does not certify, test, or in any manner investigate products or
services or any claims of compliance with the contents of this Document.

The use or implementation of the contents of this Document may involve or require the use of
intellectual property rights ("IPR") including (but not limited to) patents, patent applications, or
copyrights owned by one or more parties, whether or not Members of MIPI. MIPI does not make any
search or investigation for IPR, nor does MIPI require or request the disclosure of any IPR or claims of
IPR as respects the contents of this Document or otherwise. Questions pertaining to this document, or
the terms or conditions of its provision, should be addressed to:

MIPI Alliance, Inc. c/o IEEE-ISTO 445 Hoes Lane Piscataway, NJ 08854 Attn: Board Secretary 252
Read This First SWPU231M–July 2010–Revised November 2010 Copyright ©

OMAP is a trademark of Texas Instruments

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All other trademarks are the property of their Public Version

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 OMAP543x ES2.0 DM Operating Condition Addendum Public Version 0.6

1.3 Trademarks

OMAP, TMS320DMC64x, C64x, ICECrusher, ICEPick and SmartReflex are trademarks of Texas
Instruments Incorporated. PicoDLP is a registered trademark of Texas Instruments Incorporated.

ARM, Jazelle, and Thumb are registered trademarks of ARM Limited.

ETM, ETB, ARM9, CoreSight, ISA, Cortex, and Neon are trademarks of ARM Limited.

Java is a trademark of Sun Microsystems, Inc.

Bluetooth is a registered trademark of Bluetooth SIG, Inc. and is licensed to Texas Instruments.

HDQ is a trademark of Benchmarq.

1-Wire is a registered trademark of Dallas Semiconductor.

Windows, WinMobile, and Direct3D are trademarks of Microsoft Corporation in the United States and
other countries.

USSE and POWERVR are trademarks or registered trademarks of Imagination Technologies Ltd.

Mentor Graphics is a registered trademark of Mentor Graphics Corporation or its affiliated companies
in the United States and other countries.

OpenGL is a trademark of Silicon Graphics, Inc.

OpenVG and OpenMAX are trademarks of Khronous Group, Inc.

Arteris is a trademark of Arteris, Inc.

RealVideo is a registered trademark of RealNetworks, Inc.

SD is a registered trademark of Toshiba Corporation.

eSD is a trademark of SD Association.

MMC and eMMC are trademarks of MultiMediaCard Association.

SonicsMX, Sonics3220 are trademarks or registered trademarks of Sonics, Inc.

JTAG is a registered trademark of JTAG Technologies, Inc.

Linux is a registered trademark of Linus Torvalds.

On2 is a registered trademark of On2 Technologies.

Symbian and all Symbian-based trademarks and logos are trademarks of Symbian Software Limited.

Synopsys is a registered trademark of Synopsys, Inc.

I2S is a trademark of Phillips Electronics.

2
I C is a trademark of Phillips Semiconductor Corp.

OMAP is a trademark of Texas Instruments

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All other trademarks are the property of their Public Version

respective owners.
 OMAP543x ES2.0 DM Operating Condition Addendum Public Version 0.6

MIPI is registered trademark of the Mobile Industry Processor Interface (MIPI) Alliance.

Flex-OneNAND and OneNAND are trademarks of SAMSUNG Electronics, Corporation.

Palm OS is a registered trademark of Palm Inc.

All other trademarks are the property of their respective owners.

1.4 Community Resources

The following links connect to TI community resources. Linked contents are provided "AS IS" by the
respective contributors. They do not constitute TI specifications and do not necessarily reflect TI's
views; see TI's Terms of Use.
TI Embedded Processors WikiTexas Instruments Embedded Processors Wiki.
Established to help developers get started with Embedded Processors from Texas Instruments and to
foster innovation and growth of general knowledge about the hardware and software surrounding
these devices.

OMAP is a trademark of Texas Instruments

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All other trademarks are the property of their Public Version

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 OMAP543x ES2.0 DM Operating Condition Addendum Public Version 0.6

2 RECOMMENDED OPERATION

NOTE
All clocks frequencies mentioned in this document assume a system clock of 19.2MHz.

2.1 Micro Processor Unit (MPU)

CAUTION
The OPP voltage and frequency values may change following the silicon characterization result.

Table 2-1 shows the recommended vdd_mpu voltages ranges (MPU voltage at ball level) with AVS
disabled.
(1) (2) (3)
Table 2-1: MPU Voltages with AVS disabled

RETENTION OPP_BOOT_MPU

MIN MIN INITIAL SAFE MAX

Vdd_mpu (V) 0.65 1.0 1.05 1.1

(1) Initial Safe voltage value documented in this table corresponds to the initial voltage to be applied at power IC
level. Whereas, minimum and maximum voltage values correspond to the possible voltage at OMAP ball level.
(2) These vdd_mpu voltage ranges are defined with AVS feature disabled for Retention and OPP_BOOT_MPU
operating points.
(3) Minimum OPP voltage values defined in this table include any voltage transient.

Table 2-2 shows the recommended vdd_mpu voltages ranges (MPU voltage at ball level) during
operation.

(1)
Table 2-2: MPU Voltages during Operation

OPP_LOW_MPU (2) OPP_NOM_MPU OPP_HIGH_MPU OPP_SPEEDBIN_MPU (3)

INITIAL INITIAL INITIAL INITIAL

MIN MAX MIN MAX MIN MAX MIN MAX
SAFE SAFE SAFE SAFE

Vdd_mpu (V) 0.83 0.88 0.92 0.85 1.06 1.1 1.05 1.25 1.31 1.05 1.25 1.31

(1) Initial Safe voltage value documented in this table corresponds to the initial voltage to be applied at power IC
level. Whereas, minimum and maximum voltage values correspond to the possible voltage at OMAP ball level.
(2) For all OPPs (except OPP_LOW where AVS is not supported), AVS has to be enabled to avoid impact on device
reliability and lifetime POH (Power-On-Hours).
(3) OPP_SPEEDBIN_MPU operating point provides a higher guaranteed frequency in OPP_HIGH_MPU mode by
performing binning during production test for the MPU. This operating point will only be available with some
orderable part codes. For more information, please, contact your T.I. representatives.

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All other trademarks are the property of their Public Version

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 OMAP543x ES2.0 DM Operating Condition Addendum Public Version 0.6

Table 2-3 describes the standard processors clocks speed characteristics vs vdd_mpu (MPU voltage
at ball level).
(2) (3)
Table 2-3: MPU Clocks AC Performances
OPP_LOW_MPU OPP_NOM_MPU OPP_HIGH_MPU OPP_SPEEDBIN_MPU (1)
Max Max Max Max
Description Source Clock Freq. Ratio Freq. Ratio Freq. Ratio Freq. Ratio
(MHz) (MHz) (MHz) (MHz)

DPLL_MPU Locked
- 998 - 2200 - 1500 - 1699.2 -
Frequency
2* 2*
M2 = 1
DPLL_MPU (M2 = 1) (M2 = 1) M2 = 1
MPU_GCLK (DCC
Locked Frequency 499.2 (DCC 1000 (DCC 1500 1699.2 (DCC
(CLKOUT_M2) enabled) (4)
disabled) disabled) (4) enabled)
(4) (4)

(1) OPP_SPEEDBIN_MPU operating point provides a higher guaranteed frequency in OPP_HIGH_MPU mode by
performing binning during production test for the MPU. This operating point will only be available with some orderable
part codes. For more information, please, contact your T.I. representatives.
(2) The DPLL ratios are configurable by software programming. For more information regarding the recommended DPLL
ratios, including M2 above, see the DPLL_MPU Preferred Settings section of the OMAP543x TRM.
(3) The DPLL ratios documented in this table are recommended ratios. Other values may apply.
(4) For more information on the Duty Cycle Correction feature, see the PRCM chapter of the OMAP543x TRM.

NOTE

The programmable divider for the asynchronous bridge to Audio Back-end (ABE) must be set to:
- MPU_GCLK / 16 when MPU_GCLK clock is running at OPP_HIGH_MPU or OPP_SPEEDBIN_MPU.
- MPU_GCLK / 8 when MPU_GCLK clock is running at OPP_NOM_MPU or OPP_LOW_MPU.

The programmable divider for the asynchronous bridge to L3 must be set to:
- MPU_GCLK / 8 when MPU_GCLK clock is running at OPP_HIGH_MPU or OPP_SPEEDBIN_MPU.
- MPU_GCLK / 4 when MPU_GCLK clock is running at OPP_LOW_MPU or OPP_NOM_MPU.

For more information on the programmable dividers for the asynchronous bridges, see the
CM_MPU_MPU_CLKCTRL register, CLKSEL_ABE_DIV_MODE and CLKSEL_EMIF_DIV_MODE
bits, in the OMAP543x TRM.

Please make sure to set the corresponding register bits (increasing the divider value) before
increasing the MPU_GCLK clock frequency (by sequence to a higher OPP).
Please make sure to decrease the MPU_GCLK clock frequency (by sequence to a lower OPP) before
setting the corresponding register bits (decreasing the divider value).

CAUTION
During MPU DVFS sequencing to a higher OPP, please make sure to increase the voltage prior to the
clocks frequencies.
During MPU DVFS sequencing to a lower OPP, please make sure to decrease the clocks frequencies
prior to the voltage.
Not respecting this MPU DVFS sequencing may lead to internal timing violations.

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 OMAP543x ES2.0 DM Operating Condition Addendum Public Version 0.6

2.2 MultiMedia (MM) and 3D Graphic Accelerator (GPU)

CAUTION
The OPP voltage and frequency values may change following the silicon characterization result.

2.2.1 MultiMedia (MM)

Table 2-4 shows the recommended vdd_mm voltages ranges (MultiMedia voltage at ball level) with
AVS disabled.

(1) (2) (3)

Table 2-4: MultiMedia Voltages with AVS disabled

RETENTION OPP_BOOT_MM

MIN MIN INITIAL SAFE MAX

Vdd_mm (V) 0.65 1.0 1.05 1.1

(1) Initial Safe voltage value documented in this table corresponds to the initial voltage to be applied at power IC
level. Whereas, minimum and maximum voltage values correspond to the possible voltage at OMAP ball level.
(2) These vdd_mm voltage ranges are defined with AVS feature disabled for Retention and OPP_BOOT_MM
operating points.
(3) Minimum OPP voltage values defined in this table include any voltage transient.

Table 2-5 shows the recommended vdd_mm voltages ranges (MultiMedia voltage at ball level) during
operation.
(1)
Table 2-5: MultiMedia Voltages during operation

OPP_LOW_MM (2) OPP_NOM_MM OPP_OD_MM

INITIAL INITIAL INITIAL
MIN SAFE MAX MIN SAFE MAX MIN SAFE MAX

Vdd_mm (V) 0.83 0.88 0.92 0.82 1.025 1.07 0.93 1.12 1.17

(1) Initial Safe voltage value documented in this table corresponds to the initial voltage to be applied at power IC
level. Whereas, minimum and maximum voltage values correspond to the possible voltage at OMAP ball level.
(2) For all OPPs (except OPP_LOW where AVS is not supported), AVS has to be enabled to avoid impact on device
reliability and lifetime POH (Power-On-Hours).

OMAP is a trademark of Texas Instruments

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All other trademarks are the property of their Public Version

respective owners.
 OMAP543x ES2.0 DM Operating Condition Addendum Public Version 0.6

Table 2-6 describes the standard processors clocks speed characteristics vs vdd_mm (MultiMedia
voltage at ball level).
(1) (2)
Table 2-6: MultiMedia Clocks AC Performances

OPP_LOW_MM OPP_NOM_MM OPP_OD_MM

Max Max Max
Freq. Freq. Freq.
Description Source Clock (MHz) Ratio (MHz) Ratio (MHz) Ratio
DPLL_IVA Locked
2330 - 2330 - 1062.4 -
Frequency -
IVA_GCLK DPLL_IVA
Locked 194.1 H12 = 12 388.3 H12 = 6 531.2 H12 = 2
(CLKOUTX2_H12) Frequency
DSP_GCLK DPLL_IVA
Locked 233 H11 = 10 466 H11 = 5 531.2 H11 = 2
(CLKOUTX2_H11) Frequency

(1) The DPLL ratios are configurable by software programming. For more information regarding the recommended
DPLL ratios, including H11, H12 above, see the DPLL_IVA Preferred Settings section of the OMAP543x TRM.
(2) The DPLL ratios documented in this table are recommended ratios. Other values may apply.

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 OMAP543x ES2.0 DM Operating Condition Addendum Public Version 0.6

2.2.2 3D Graphic Accelerator (GPU)

Table 2-7 shows the standard graphic accelerator (GPU) clocks speed characteristics vs vdd_mm
(MultiMedia voltage at ball level).
(1) (3)
Table 2-7: Graphic Accelerator (GPU) Clocks

OPP_LOW_MM OPP_NOM_MM OPP_OD_MM (2)

Max Max Max
Freq. Freq. Freq.
Description Source Clock (MHz) Ratio (MHz) Ratio (MHz) Ratio
Configuration 1 - From CORE DPLL – Locked Frequency @2127.36 MHz Maximum
DPLL_CORE Locked Frequency - 2127.36 - 2127.36 - 2127.36 -
(4)
CORE_GPU_CLK DPLL_CORE Locked Frequency (4) H14 = 2.5 H14 = 2
212.7 H14 = 5 425.47 (4) 531.84
(CLKOUTX2_H14)
GPU_CORE_GCLK CORE_GPU_GCLK 212.7 1 425.47 1 531.84 1
Configuration 2 - From PER DPLL – Locked Frequency @768 MHz Maximum
DPLL_PER Locked Frequency - 768 - 768 -
PER_GPU_CLK DPLL_PER Locked Frequency
192 H14 = 4 384 H14 = 2
(CLKOUTX2_H14)
GPU_HYD_GCLK PER_GPU_CLK 192 1 384 1

(1) The DPLL ratios are configurable by software programming. For more information regarding the recommended DPLL
ratios, including H14 above, see the DPLL_CORE Preferred Settings or, DPLL_PER Preferred Settings section of the
OMAP543x TRM.
(2) The DPLL CORE is in the CORE domain that supports up to OPP_NOM_CORE operating point compared to the 3D
GPU graphic accelerator (GPU) which is in the MultiMedia (MM) domain which supports up to the OPP_OD_MM
operating point. Hence, based on the CORE_GPU_CLK output clocks of DPLL_CORE, the 3D graphic accelerator
clock (GPU_CORE_GCLK) can supports up to OPP_HIGH_MM @600MHz based on the DPLL CORE in
OPP_NOM_CORE operating point.
(3) The DPLL ratios documented in this table are recommended ratios. Other values may apply.
(4) For DPLL CORE, an additional division by 2 is performed after the HS divider.

CAUTION
During MM / GPU DVFS sequencing to a higher OPP, please make sure to increase the voltage prior
to the clocks frequencies.
During MM / GPU DVFS sequencing to a lower OPP, please make sure to decrease the clocks
frequencies prior to the voltage.
Not respecting this MM / GPU DVFS sequencing may lead to internal timing violations.

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 OMAP543x ES2.0 DM Operating Condition Addendum Public Version 0.6

2.3 CORE

CAUTION
The OPP voltage and frequency values may change following the silicon characterization result.

Table 2-8 shows the recommended vdd_core voltages ranges (Core voltage at ball level) with AVS
disabled.

(1) (2) (3)

Table 2-8: Core Voltages with AVS disabled

RETENTION OPP_BOOT_CORE

MIN MIN INITIAL SAFE MAX

Vdd_core (V) 0.81 1.0 1.05 1.1

(1) Initial Safe voltage value documented in this table corresponds to the initial voltage to be applied at power IC
level. Whereas, minimum and maximum voltage values correspond to the possible voltage at OMAP ball level.
(2) These vdd_core voltage ranges are defined with AVS feature disabled for Retention and OPP_BOOT_CORE
operating points.
(3) Minimum OPP voltage values defined in this table include any voltage transient.

Table 2-9 shows the recommended vdd_core voltages ranges (Core voltage at ball level) during
operation.

(1)
Table 2-9: Core Voltages during operation

OPP_NOM_CORE

MIN INITIAL SAFE MAX

Vdd_core (V) 0.83 1.04 1.09

(1) Initial Safe voltage value documented in this table corresponds to the initial voltage to be applied at power IC
level. Whereas, minimum and maximum voltage values correspond to the possible voltage at OMAP ball level.
(2) For all OPPs (except OPP_LOW where AVS is not supported), AVS has to be enabled to avoid impact on device
reliability and lifetime POH (Power-On-Hours).

OMAP is a trademark of Texas Instruments

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All other trademarks are the property of their Public Version

respective owners.
 OMAP543x ES2.0 DM Operating Condition Addendum Public Version 0.6

Table 2-10 shows the standard DPLL CORE clocks speed characteristics vs vdd_core (Core voltage
at ball level).

(1) (2)
Table 2-10: Core Clocks AC Performances – From DPLL CORE

OPP_NOM_CORE

Description Source Clock Max Freq. Ratio

(MHz)
DPLL_CORE Locked
- 2127.36 -
Frequency

CORE_DLL_GCLK DPLL_CORE Locked 265.92

H11 = 8
(CLKOUTX2_H11) Frequency

CORE_X2_CLK DPLL_CORE Locked 531.84

H12 = 4
(CLKOUTX2_H12) Frequency

L3MAIN2_L3_GICLK CORE_X2_CLK 265.92 2

L3MAIN2_L4_GICLK L3MAIN2_L3_GICLK 132.96 2

EMIF_PHY_GCLK DPLL_CORE Locked 531.84 2 * (M2 =

(CLKOUT_M2) Frequency 2)

EMIF_FCLK (DDRPHY divider) EMIF_PHY_GCLK 265.92 2

GPMC_CLK L3MAIN2_L3_GICLK 265.92 2

(1) The DPLL ratios are configurable by software programming. For more information regarding the recommended DPLL
ratios, including M2, H11, H12 above, see the DPLL_CORE Preferred Settings section of the OMAP543x TRM.
(2) The DPLL ratios documented in this table are recommended ratios. Other values may apply.

OMAP is a trademark of Texas Instruments

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All other trademarks are the property of their Public Version

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 OMAP543x ES2.0 DM Operating Condition Addendum Public Version 0.6

3 OPP DEPENDENCIES
CAUTION
The OPP dependencies apply only when both voltage domains are in ON state. That is:
- Any module in the domain may be powered, clocked and active
- SMPS is in active mode, delivering the voltage corresponding to current OPP
For more information on the Voltage Domain definitions, see the Power, Reset and Clock
Management / Voltage Management Functional Description section in the OMAP543x TRM

Table 3-1 shows the acceptable OPP dependencies between MPU, CORE and MultiMedia voltage
domains.

Table 3-1. OPP Dependencies between MPU, CORE and MultiMedia

vdd_mpu vdd_core vdd_mm

OPP_LOW_MPU OPP_NOM_CORE OPP_NOM_MM

OPP_NOM_MPU OPP_NOM_CORE OPP_LOW_MM
OPP_NOM_MPU OPP_NOM_CORE OPP_NOM_MM
OPP_HIGH_MPU OPP_NOM_CORE OPP_NOM_MM
OPP_NOM_MPU OPP_NOM_CORE OPP_OD_MM
OPP_HIGH_MPU OPP_NOM_CORE OPP_OD_MM
OPP_SPEEDBIN_MPU OPP_NOM_CORE OPP_OD_MM
OPP_SPEEDBIN_MPU OPP_NOM_CORE OPP_NOM_MM
OPP_LOW_MPU OPP_NOM_CORE OPP_LOW_MM
OPP_HIGH_MPU OPP_NOM_CORE OPP_LOW_MM
OPP_SPEEDBIN_MPU OPP_NOM_CORE OPP_LOW_MM
OPP_LOW_MPU OPP_NOM_CORE OPP_OD_MM

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 OMAP543x ES2.0 DM Operating Condition Addendum Public Version 0.6

IMPORTANT NOTICE

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enhancements, improvements, and other changes to its products and services at any time and to discontinue any
product or service without notice. Customers should obtain the latest relevant information before placing orders
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Data Converters dataconverter.ti.com Computers and Peripherals www.ti.com/computers
DLP® Products www.dlp.com Consumer Electronics www.ti.com/consumer-apps
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Microcontrollers microcontroller.ti.com Video and Imaging www.ti.com/video
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