April 2015

This Issue: surface finishes

Featured Content
For years, hot air solder leveling was the predominant surface finish in the PCB industry. But now,
there’s a veritable alphabet soup of available surface finishes, and each has its own advantages
and disadvantages. This month, we focus on the latest in PCB surface finishes, with articles from
George Milad and Rick Nichols, as well as columns and articles from our regular contributors.

10 Looking Below
the Surface —
IPC Plating
Sub-committee
4-14: Surface
Finish Specifications
by George Milad

18 The Future of Nickel in Nickel/Palladium/Gold Final Finishes

by Rick Nichols

4 The PCB Design Magazine • April 2015

 RF/Microwave Materials &
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www.isola-group.com/RF
 april 2015 The optimum
28 TM
volume 4 magazine

number 4 dedicated to

34 thepcbdesignmagazine.com pcb design

Contents

Articles Video Interview

46 Hunter’s Two Newest CID Recipients 45 Altium Talks 3D Flex
Discuss Certification Packaging Design
by Kelly Dack

52 Effective
Decoupling
Radius
by Kirk Fabbri Shorts
16 Removing Risk
to Unleash the
Full Potential of
Nanomaterials

Columns 35 Breakthrough in Thermoelectric

8 Moore’s Law Turns 50 Materials
by Andy Shaughnessy
61 Driverless Cars to Renovate
30 Learning the Curve Automotive Industry
by Barry Olney

36 RF Power Capabilities of
High-Frequency PCBs News Highlights
by John Coonrod 40 PCB007

50 Mil/Aero007

62 PCBDesign007

42 The Utility Belt Extras

by Tim Haag 64 Events Calendar

65 Advertiser Index
& Masthead

6 The PCB Design Magazine • April 2015

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 column

the shaughnessy report

Moore’s Law Turns 50

by Andy Shaughnessy
I-Connect007

Let’s all pause to wish Moore’s Law a very get; it is one of the predominant driving forces in
happy 50th birthday, even as the vultures begin the electronics industry. In 1975, Moore amend-
to circle overhead. ed his prediction from one year to approximate-
Fifty years ago, Dr. Moore was director of ly every two years. (Interestingly, Moore didn’t
R&D at Fairchild Semiconductor, and Electron- come up with the term Moore’s Law; that honor
ics Magazine asked him to make some predic- belongs to Caltech’s Carver Mead.)
tions about the future of the semiconductor Moore went on to be a co-founder and CEO
industry. On April 19, 1965, the magazine pub- of Intel Corporation. He’s had a great life; he
lished his earthshaking article outlining what and his wife created the Gordon and Betty
became known as Moore’s Law. Moore Foundation with a $5 billion endow-
In the article, titled “Cramming More Com- ment. In 2001, the couple donated $600 mil-
ponents onto Integrated Circuits,” Moore pos- lion to Caltech, the biggest single gift ever given
ited that the number of components in a dense to a college, and in 2007 they gave $200 million
integrated circuit had doubled every year, and to Caltech and the University of California to
would continue at that rate for at least 10 years. fund the Thirty Meter Telescope, to be built on
Before he knew it, electronics companies around Mauna Kae in Hawaii.
the globe were using Moore’s Law for their tech- But all this time, Moore knew his law would
nology roadmaps. It has become more than a tar- hit a manufacturing wall. He once said, “It can’t

8 The PCB Design Magazine • April 2015

 the shaughnessy report

Moore’s law turns 50 continues

continue forever. The nature of exponentials is sistors, the most that Big Blue has ever fit onto
that you push them out and eventually disaster one chip. Sure, the human brain has 100 billion
happens.” neurons, but that’s a good first step.
Now, as Moore’s Law celebrates the big But my favorite is quantum computing,
Five-O, technologists are predicting that the which is still in the early experimental stages.
law will expire in the next decade. Chip com- Quantum computation encodes data into quan-
panies are spending billions trying to identify tum bits (qubits), which can exist in “superpo-
the next material, or a new way to make chips. sitions,” or more than one state at once. This
means that a qubit can represent a one and a
What’s After Silicon? zero at the same time, which is pretty cool.
A handful of new technologies show prom- All of these are in their infancy, and years
ise. Silicon nanophotonics involves replacing from being commercially available. The big
the electrons on an IC with light particles, and trick will be to create materials and processes
we know that light can transmit data through that fit into the manufacturing flow of today,
fiberoptic cables. Why not use light to move as seamlessly as possible. Good luck with that.
data on a chip? Talk about energy-efficient. In the end, the electronics industry will
Sure, nanophotonics are years away, but there’s have to make some adjustments when Moore’s
plenty of ongoing research in photonics. Law reaches the end of its life. But it won’t be
IBM is investing in carbon nanotubes (CNT), the end of the world that some of the chip com-
and plans to have a CNT chip commercially panies imagine it to be. So, let’s sing a round of
available by 2020. CNTs have been around for “Happy Birthday” to Moore’s Law and hold off
over a decade. They exhibit amazing thermal calling hospice just yet. PCBDESIGN
conductivity, but creating them has been pro-
hibitively expensive. Let’s see how IBM brings Andy Shaughnessy is manag-
down the price point on CNT technology. ing editor of The PCB Design
IBM is also working with synaptic comput- Magazine. He has been cover-
ing. Last year, the company revealed TrueNorth, ing PCB design for 15 years.
the world’s first neurosynaptic computer chip, He can be reached by clicking
which is designed to operate much like the hu- here.
man brain. TrueNorth features 5.4 billion tran-

April 2015 • The PCB Design Magazine 9

 feature

Looking Below
the Surface

IPC Plating Sub-committee 4-14:

Surface Finish Specifications
by George Milad no consensus is readily arrived at, the commit-
Uyemura tee undergoes its own testing in what is com-
Co-chair, IPC Plating Sub-Committee 4-14 monly referred to as a round-robin (RR) study.
In a RR investigation, an agreed upon test vehi-
cle (TV) is designed and manufactured. TVs are
This article was previously published in the
then sent around to the different suppliers who
February 2015 edition of The PCB Magazine.
deposit the agreed upon thicknesses to be inves-
tigated. The TVs are collected and the deposit
IPC specifications are reference documents thicknesses are verified and documented. The
to be called out by designers and OEMs. Design- TVs are then coded. The TVs are sent around
ers may take exception with one or more items again to the different testing sites that test for
in the specification to ensure that the product the desired attribute like soldering, contacting
meets the requirements of its intended use. The and wire bonding capabilities of different finish
acronym AAUBUS (as agreed upon between user thicknesses. The data is then collected, sorted
and supplier) is part of any specification. out and documented. At this point, a new at-
Specifications are consensus documents. They tempt at consensus is made and upon arrival,
are agreed upon by a panel of interested industry the thickness specification is set.
participants composed of suppliers, manufactur- A draft is prepared after consensus is com-
ers, assembly houses (CMs) and end users. The plete. The draft is then posted for peer review.
IPC Plating Sub-committee 4-14 is no exception. Any IPC member can review the document and
When there is consensus, the committee suggest technical or editorial changes. All com-
documents it in a specification. In cases where ments are then reviewed and all issues resolved

10 The PCB Design Magazine • April 2015

 feature

IPC Surface Finish Specs Update continues

before the final draft is issued. At this time the The ENIG surface finish is solderable, aluminum
IPC takes on the task of publishing the docu- wire bondable, and an excellent contacting sur-
ment in its final format. face, with a minimum shelf life of 12 months
The IPC Plating Sub-committee 4-14 has under standard storage conditions. The immer-
been active since 2001. It is co-chaired by my- sion gold layer protects the underlying nickel

“
self and Gerard O’Brien of ST and S Group. The from oxidation/passivation over its intended
IPC liaison is Tom Newton. The shelf life. Thickness specifications
sub-committee has an exten- are set to ensure the ability of
sive member list composed of the finish to meet the above
OEMs, contract assemblers, ENIG is a coplanar surface criteria.
board manufacturers, chemi- The ENIG IPC-4552 Spec-
cal suppliers, as well as labs finish composed of a ification was issued in 2002,
and consultants. nickel layer capped with and at the time of setting the
The committee operates specification for ENIG, no
a thin layer of gold. The
through one-hour, bi-weekly lead-free (LF) solder was in
conference calls. Calls are ENIG surface finish is use. For thickness, IPC-4552
held every other Wednesday solderable, aluminum stated:
at 11:00 a.m., EST, and every-
one is welcome to participate. wire bondable, and an • The EN thickness shall
A notification e-mail is sent excellent contacting be 3–6 µm [118.1 to 236.2
out before each conference surface, with a minimum µin] The IG minimum thick-
call. All decisions pertaining ness shall be 0.05 [1.97 µin],
to initiation and follow up on shelf life of 12 months at four sigma (standard devia-
round-robin studies, evalua- under standard storage tion) below the mean; typical
tion of results, draft review, values for IG of 0.075 to 0.125
conditions.

”
etc., are made during these µm [2.955 to 4.925 µin]
calls, by those in attendance.
The call minutes are document- Although no upper limit
ed and circulated. was set, the specification had a
Since its inception, the IPC Plating Sub- statement for suggested typical values for IG of
committee 4-14 has issued the following: 0.075 to 0.125 µm [2.955 to 4.925 µin]. These
values were erroneously interpreted to be the
• IPC-4552 ENIG Specification 2002 specification.
• IPC-4553 Immersion Silver specification The ENIG specification was amended in
2005 2012:
• IPC-4554 Immersion Tin Specification
2007 • The lower limit for thickness was reduced
• IPC-4553A Revised Immersion Silver 2009 from 0.05 µm to 0.04 µm (1.6 µin) with the fol-
• IPC-4554 Amended Tin Specification 2011 lowing restrictions:
• IPC-4552 Amended ENIG Specification – Limited time from manufacturing to
2012 assembly
• IPC-4556 ENEPIG Specification 2013 – Demonstrate the consistency of the
plating process
Following is a discussion of each of the – Ability to measure low gold thickness
above:
Presently, the ENIG 4552 is in revision and
Electroless Nickel/Immersion Gold (ENIG) should be out in 2015 (Revision A). The objec-
IPC-4552, 2002 tive of the revision is to set new lower and upper
ENIG is a coplanar surface finish composed thickness limits for the immersion gold, to de-
of a nickel layer capped with a thin layer of gold. termine if the restrictions in the amended ENIG

12 The PCB Design Magazine • April 2015

 feature

IPC Surface Finish Specs Update continues

spec could be lifted, to limit the typical pad size The initial IPC-4553 Immersion Silver Speci-
to be measured and to make the specification fication specified two thicknesses and stated the
applicable to LF solder and LF conditioning. following for thickness of deposit:
This entails an extensive RR study, presently in
progress. • Thin Silver: 0.05 µm(2µin) minimum at -2σ
The intent is that the revised IPC-4552 Rev from process mean as measured on a pad of area
A would also include the following Additional 2.25² µm (3600² mils). Typical value 0.07 µm
Documents: (3µin) to 0.1 2µm (5µin)
• Thick Silver: 0.12 µm (5µin) minimum at -4σ
• Test method (TM) for stripping immersion from process mean as measured on a pad of area
gold during failure analysis 2.25² µm (3600² mils). Typical value of 0.2 µm
• Test method for determining the phos (8µin) to 0.3 µm (12µin).
content of electroless nickel
• A corrosion chart setting acceptability In 2009, the immersion silver specification
criteria for nickel corrosion (black pad) was revised. At this time the lower thickness

“
supplier has discontinued his product and the
Immersion Silver (IAg) industry was left with a common
IPC-4553 A, 2009 thickness from multiple suppli-
IAg is a thin, immersion ers. This revised specification
silver deposit over copper. It In 2009, the immersion only had one thickness speci-
is a multifunctional copla- silver specification was fied (eliminating reference to
nar surface finish, applicable thin and thick). The revised
to soldering. It may also be revised. At this time the specification now includes an
applicable for some press-fit lower thickness supplier upper thickness limit. Typi-
connections and as a contact
surface. It has the potential
has discontinued his product cal values were recommended
within the specified limits.
to be suitable for aluminum and the industry was left The pad size for taking the
wire bonding. The immer- with a common thickness thickness measurement was
sion silver protects the un- also specified.
derlying copper from oxida- from multiple suppliers.
tion over its intended shelf This revised specification The IPC-4553 Rev A Im-
life. Exposure to moisture only had one thickness mersion Silver Specification
and air contaminants, such stated the following for thick-
as sulfur and chlorine, may specified (eliminating ness of deposit:
negatively impact the useful reference to thin and thick).

”
life of the deposit. The im- • The immersion silver
pact can range from a slight thickness shall be 0.12 µin [5
discoloration of the deposit to µin] minimum to 0.4 µm [16
the pads turning completely black. μin] maximum at ± 4σ from process
Proper packaging is a requirement to achieve a mean. Typical value between 0.2 µm [8 µin] to
12-month shelf life. 0.3 µm [12 µin] as measured on a pad of area
2.25 mm² or 1.5 mm X 1.5 mm [approximately
The Immersion Silver IPC-4553 Specification 0.0036 in² or 0.060 in X 0.060 in] or equivalent.
In 2005, there were two distinct types of
commercialized immersion silver with differ- Immersion Tin (ISn)
ent thickness recommendations, referred to by IPC-4554, 2007; amended 2012
the committee as “thin” and “thick.” Each re- The immersion tin (ISn) is a metallic finish
quired its own thickness specification. This cre- deposited by a chemical displacement reaction
ated much confusion as the terms were poorly that is applied directly to the basis metal of the
defined. printed board, which is copper. The immersion

14 The PCB Design Magazine • April 2015

 feature

IPC Surface Finish Specs Update continues

tin is primarily used as a solderable surface for and to gold, aluminum and copper wire bonding.
attachment of components. It may also be used It is also suitable as the mating surface for soft
when press-fit connections are employed and membrane and steel dome contacts. Additional
for zero insertion force (ZIF) edge connectors. applications include use in low insertion force
The immersion tin finish protects the underly- (LIF) and zero insertion force (ZIF) edge connec-
ing copper from oxidation over the intended tors and for press-fit applications. The electroless

“
shelf life (storage of greater than six palladium layer forms a diffusion bar-
months) of this finish. rier that impedes nickel diffusion
to the gold surface. The immer-
Immersion Tin IPC-4554 sion gold protects the palla-
Specification
ENEPIG is a coplanar dium layer from reacting with
For immersion tin, the tertiary layered surface contaminants prior to pro-
committee specified a lower finish plated over copper cessing that might otherwise
limit for thickness. The rela- affect joining processes, such
tively thick value of 1 micron as the basis metal. ENEPIG as wire bonding and solder-
(40µin) was chosen to ensure consists of an electroless ing. ENEPIG has a minimum
that enough virgin tin would
be available at the surface
nickel base layer over which shelf life of 12 months under
standard storage conditions.
for soldering after extended is plated an electroless Thickness specifications are
storage. It is well understood palladium barrier layer set to ensure the ability of the
that tin forms an interme- finish to meet all the attribut-
tallic (IMC) layer with the followed by a deposit of a ed functionality.
underlying copper, and that thin immersion gold as the
this layer continues to grow final outer layer. The ENEPIG IPC-4556

”
in thickness over time. Specification
The immersion tin thick- This is the last specification
ness will be: issued by the committee. The
document produced is very com-
• µm (40 µin) minimum at -4σ from process prehensive and includes a wealth of information
mean as measured on a pad of area 2.25² µm from the RR studies that were conducted.
(3600² mils) or equivalent. Typical value of 1.15 The Appendix contains a documentation
µm ( (46 µin) to 1.3 µm (52µin). of these studies, each authored by the princi-
  pal who conducted the testing. It also includes
The Immersion Tin Specification IPC-4554 a section on the proper methods of equipment
was amended in 2011. The amendment ad- setup for a reliable measurement of very thin
dressed solderability testing and specified the layers of metal deposits.
allowed stress testing conditions for the deposit The thickness specification for ENEPIG
and the type of fluxes to be used for both tin/ states:
lead and LF testing.
• Nickel: 3 to 6 µm [118.1 to 236.2 µin] at ± 4
Electroless Nickel/Electroless Palladium/ sigma (standard deviations) from the mean.
Immersion Gold (ENEPIG) • Palladium: 0.05 to 0.15 µm [2 to 12 µin] at ±
IPC-4556, 2013 4 sigma (standard deviations) from the mean.
ENEPIG is a coplanar tertiary layered surface • Gold: minimum 0.025 µm [1.2 µin] at - 4
finish plated over copper as the basis metal. EN- sigma (standard deviations) below the mean. No
EPIG consists of an electroless nickel base layer upper limit was set for IG.
over which is plated an electroless palladium
barrier layer followed by a deposit of a thin im- All measurements to be taken on a nominal
mersion gold as the final outer layer. It is a multi- pad size of 1.5 mm x 1.5 mm [0.060 in x 0.060
functional surface finish, applicable to soldering in] or equivalent area.

April 2015 • The PCB Design Magazine 15

 feature

IPC Surface Finish Specs Update continues

Organic Solderabilty Preservative (OSP) mally robust coatings have significantly higher
IPC Specification (NONE) decomposition temperatures than the peak as-
OSPs are organic coatings that form a com- sembly reflow temperature. They require con-
plex organo-metallic complex with the copper tact with appropriate flux and/or molten solder
surface of the PWB. This complex preserves the to penetrate the coating. They have longer shelf
solderability of the copper surface through as- life, survive multiple reflow cycles and are more
sembly. lead-free assembly compatible.
A wide variety of OSPs have evolved with After more than one year of struggling
the increasing complexity of the PWB. Initial- with a specification for OSP, no consensus was
ly, all that was required was a single thermal reached, and no specification was set forth.
excursion for soldering leads into component This was due to the wide assortment of organic
holes, Then came surface mount that required products that were used for solderability pres-
at least two thermal excursions (one per side); ervation for the various applications, each with
add on top of that the need to hand solder an its own thickness recommended values.
occasional rework. The biggest relevant evo-
lution is lead-free assembly. LF assembly tem- Acknowledgement
perature at 260°C is approximately 35°C higher To date, all committee activities have been
than eutectic soldering (225°C). The manufac- voluntary and acknowledgement is in order for
turers of OSP have developed new OSPs to meet the members and equally important for their
the market demands. These have a greater abil- respective companies that allow for the time in-
ity to withstand increasing number of thermal vested by their employees. PCBDESIGN
excursions and higher temperature, as needed
for LF.
George Milad is the national
OSP products include benzotriazoles, imid-
accounts manager of technology
azoles, benzimidiazoles and phenyl benzimid-
at Uyemura International
azoles. Some of the newer OSPs have additives
Corporation. He may be reached
occasionally referred to as “oxygen scavengers.”
by clicking here.
These additives can stretch the performance
window of the specific OSP. The more ther-

Removing Risk to Unleash the industrial competitiveness, and are already used in
hundreds of products.
Full Potential of Nanomaterials In order to fully capitalise on this potential mar-
ket however, the safety of nanomaterials must be
beyond reproach. As these nanomaterials are of-
The EU-funded NANOREG project is developing ten unique and have never been on the market
the next generation of reliable and comparable ex- before, assessments must be done on a case-by-
perimental data on the environmental, health and case basis using globally recognised and approved
safety aspects of nanomaterials. NANOREG, which methods.
began in March 2013, has already successfully es- Regular meetings have also been set up with
tablished the basic conditions for its R&D work and policy makers in partner countries, along with glob-
will now move on to deliver on its key objectives. al standardisation institutions in countries like the
Nanomaterials are chemical sub- US, Canada, Australia, Japan and
stances or materials that are manu- Russia. The long term objective of
factured at an incredibly small scale NANOREG is to ensure that the in-
(down to 10 000 times smaller than novative and economic potential of
the diameter of a human hair). Ex- nanomaterials is not put at risk sim-
perts believe they have the potential ply because health and safety issues
to contribute significantly to Europe’s have not been fully addressed.

16 The PCB Design Magazine • April 2015

 feature

The Future of
Nickel in Nickel/
Palladium/
Gold Final Finishes
by Rick Nichols time reliability by protecting the base copper.
Atotech Deutschland GmbH • Electroless nickel/immersion gold (ENIG)—
the workhorse
This article was previously published in the • Electroless nickel/electroless palladium
February 2015 edition of The PCB Magazine. (pure palladium and phosphor containing
palladium)/immersion gold (ENEPIG)—
Final finishes can be subdivided into metal- the all-purpose solution
lic and organic finishes. For the purpose of this
article, the focus will be on the metallic finishes The next-generation surface finishes need
using the combinations of nickel (Ni) and/or to be biased towards satisfying lifetime require-
palladium (Pd) and/or gold (Au). Variations on ments in combination with enhanced technical
this theme are used extensively in the electron- performance.
ics market of today. The Ni/Pd/Au mutations
are the inevitable result of technical require- • Electroless palladium/autocatalytic gold
ment changes coupled with true and perceived (EPAG)—fine-line, high-frequency, solder
acceptance within the industry. One such opti- and bonding application
mization is the phosphorus contents in the Ni
and Pd layers. This subtlety will not be focused This broad segregation implies the inclusion
on in this article as the impact on the key topics or exclusion of Ni. This Ni protection layer (4–7
is negligible. µm) has a physical impact on line and space
This subgroup of metallic final finishes can capability whilst simultaneously having a nega-
also be further divided by their application bias. tive impact on high-frequency applications.
Traditional ENIG processes are biased towards The symbiotic relationship between tech-
using a protection layer to ensure extended life- nology influences and the resultant require-

18 The PCB Design Magazine • April 2015

 feature

The Future of Nickel in Nickel/Palladium/Gold Final Finishes continues

ments for the final finish is the driving force Despite being vital, solderability satisfies
for this article. It is also the intention of this only part of the surface finish requirements.
article to highlight the superiority of the direct The surface finish must also provide adequate
palladium processes in achieving the expected protection of the underlying copper circuitry
requirements of the future. from the time of substrate fabrication until
packaging and assembly (copper corrosion on
Generic Technical Requirements fine-line technology has the potential to impact
Regardless of the surface finish, there exist significantly on signal integrity). The surface
perceived and accepted minimum requirements finish should not add to solder joint reliability
for total functionality. The established stan- concerns by contributing to the formation of
dards will inevitably be augmented and many undesirable intermetallic compounds (IMCs) or
technology sectors will adopt their own perfor- adversely affecting their growth. In other words,
mance criteria and expectations as the future the bondability must be ensured.
era of high-frequency and fine-line applications Whilst negating all responsibility for look-
become more necessary. It is also apparent that ing into the future, some trends can be pre-
the new requirements will also include more dicted as a result of integration trends. Circuit
economic wire bonding materials. features continue to shrink and maintaining

Figure 1: The generic capabilities of Ni, Pd and Au final finishes. Note: Electroless palladium/immersion gold
(EPIG) has not been included due to the process’s copper corrosion and poor wire bonding attributes.

20 The PCB Design Magazine • April 2015

 feature

The Future of Nickel in Nickel/Palladium/Gold Final Finishes continues

signal integrity becomes even more challeng- line technology hinting at 5/5 and even 2/2 the
ing. This has a direct impact on assembly, and final finish can no longer afford µm scale pro-
in response future surface finishes need to tection layers such as Ni at 4–7 µm.
accommodate newer adaptations of thermo- A further pitfall of the Ni inclusive technol-
compression bonding as the established solder ogies is their susceptibility to Ni spread and re-
technologies are also at the edge of their capa- sultant shorting, even at an abnormally low Ni
bilities. thickness (the low Ni is required to achieve the
line and space criteria).
Topics and Considerations for
Future Final Finishes High-Frequency Capabilities
The widespread use of smartphones and tab-
Fine-line Technology lets to support daily employment and leisure
The concept of fine-line technology already activities is tangible evidence of the future ap-
has to factor in the impact of etching to arrive petite for high data flow capabilities which ne-
at the required line and space. For example, to cessitates by virtue high-frequency capabilities.
achieve 10 µm line and space the circuit will be Based on history, it is clear that this insatiable
designed at 12 µm line and 9 µm space. After appetite will continue to expand.
such painstaking front-end design, final finish- At very high frequencies surface finishes
es are faced with the challenge of maintaining with a nickel layer become critical. It is known
this integrity as far as possible. With future fine- that nickel plated on copper will cause an ad-

Figure 2: The impact of established Ni containing finishes on line and space.

22 The PCB Design Magazine • April 2015

 feature

The Future of Nickel in Nickel/Palladium/Gold Final Finishes continues

ditional loss to signal propagation due to the so electromagnetic fields (eddy currents) caused
called “skin effect.” Initially proposed by Horace by alternating current will orientate the high-
Lamb in 1883 for spherical conductors, it was est current density flow to the outside of the
then applied to conductors of any shape by Oli- conductor. This is referred to as the skin effect.
ver Heaviside in 1885 (Wikipedia). In laymen’s In turn, different conductor properties (electri-
terms, the theory promulgates that induced cal and magnetic) in conjunction with differ-

Figure 3: The potential for spreading when using a Ni inclusive finish.

Figure 4: The impact of frequency on skin depth (δ) with reference to process application.

April 2015 • The PCB Design Magazine 23

 feature

The Future of Nickel in Nickel/Palladium/Gold Final Finishes continues

ent frequencies will exhibit different skin

depths (δ). With a given conductor prop-
erty the skin-depth decreases exponen-
tially with the increase of frequency.
The inclusion of Ni at 4–7 µm en-
sures that the primary signal will pass
through the outer Ni skin. Not only is
nickel a poorer conductor than copper,
the effective area for the signal to pass
through is greatly reduced. This is rather
like placing your thumb over the end of
a hose pipe, the resultant water flow is
reduced and the directional flow is great-
ly disturbed.
The skin effect is one of the reasons
why the electronics industry needs to en-
tertain the notion of nickel-free surface Figure 5: How the Ni morphology is influenced by the
finishes. layer thickness.

ENIG
Thousands of words have already been writ- Ni layer to conform to dimensions dictated by
ten about the workhorse, ENIG, and many pan- EPAG, dramatic quality issues are encountered.
els have been processed successfully using it. Early indications of this can be found by ex-
This is an established process that fulfils the re- amining the intermetallic compound (IMC) by
quirements of many existing and past applica- SEM. Whilst the IMC created using EPAG has
tions but falls short of the requirements prom- no detrimental impact to the solder joint, the
ised in the future. As such this process will not IMC created using EN (low thickness) EPIG dis-
feature further in this article unless to make a plays evidence of demarcation lines.
comparison. Demarcation lines are cosmetically alarm-
ing and create concerns for the end-user. This
ENEPIG with Thin Ni is not an acceptable situation. The impact of
Although in terms of words and produc- demarcation lines, in terms of quality, can be
tion, the above is equally true for the “the all- demonstrated using a drop test. The drop test
purpose solution” (ENEPIG) process, this is the is a simulation of a handheld device being
most promising of the Ni inclusive processes. dropped.
In addition to performing well generically According to the drop test, the performance
there a frequent question is raised within the of the EPAG system is superior to that of the thin
industry: Ni ENEPIG process. In addition to the poor drop
test performance, the thin Ni layer becomes su-
Why can’t this process fulfil future re- perfluous as a protection layer due to the low
quirements by employing a thin Ni layer? thickness and resultant poor morphology.

Ni is employed as a barrier layer due to its Silver Wire Bonding

dense crystal formations. The surface morphol- Wire bonding is a field that is evolving like
ogy, in turn is created by thicker Ni plating. This any other. Bonding speed, wire hardness and
is the background for the IPC (4552 – ENIG and cost are all in the mix. Some 3D packaging
4556 – ENEPIG), minimum thickness require- philosophies mean that wire bonding is here
ment of 3µm. to stay unless it is replaced completely by flip-
Higher Ni thicknesses positively influence chip derived bonding technology. Reduction
the integrity of solder joints. By reducing the in cost without yield and capacity loss is a ma-

24 The PCB Design Magazine • April 2015

 feature

The Future of Nickel in Nickel/Palladium/Gold Final Finishes continues

Figure 6: The impact of low Ni on demarcation lines.

jor driver in this field. Pure copper wire bond- EPAG exhibits a wide working window with
ing is one candidate for cost reduction, but this good performance indicators for silver wire
can result in other complications like compo- bonding. Well known OEMs are also champion-
nent and equipment damage due to the forces ing this direction for wire bonding. The results
and energy required. Gold, on the other hand, for Cu wire bonding are also acceptable.
is the preferred and established medium, but
recent exploration into silver wire bonding is A Look into the Future
proving potentially viable. The high potential The roadmaps, available in the public do-
for silver as a technical replacement for gold main, according to the following OEMs, IPC,
is the comparable softness of the metals. Fig- iNEMI, ITRS and Jisso, predict fine-line technol-
ure 1 demonstrates that ENEPIG and EPAG are ogy. This, by definition, has a knock on impact
both able to deliver confidence in silver wire to pitch miniaturization. This applies equally to
bondability. Additional to the technical simi- organic and inorganic substrates.
larities, silver also complies, in some way, to As part of flip-chip bonding technology, the
cost saving. tried and tested reflow bonding is limited with

April 2015 • The PCB Design Magazine 25

 feature

The Future of Nickel in Nickel/Palladium/Gold Final Finishes continues

Figure 7: The performance comparison of the low Ni ENEPIG compared to the EPAG process.

signal integrity. The reflow process requires the

application of solder. Aside from this procedure
being already at the application limit, the utili-
zation of solder does not lie within the remit of
controlled Z-axis expansion and is also a com-
paratively poor conductor compared to copper
or other more noble metals. Here we have es-
tablished that not only will the I/Os increase in
density (decrease in pitch), but the pillar height
(standoff height) will also become paramount
to future developments. To this end Atotech is
cooperating with Georgia Institute of Technol-
ogy to assess the viability of using EPAG as the
pillar and pad finish for thermo-compression
bonding.
Figure 8: Performance of EPAG for AG wire There exists a prior art to thermo-compres-
bonding. sion bonding (TCB). These can be characterized
in Figure 9.
Although the prior art technologies are
regard to in/out (I/Os) density. With the value proven, there are some viable benefits in using
of real estate becoming so important, the space EPAG as the copper interconnect. Not only can
utilized by reflow bonding techniques is becom- the key performance indicators or benefits can
ing an obstacle. When discussing real estate, it be compared to direct Cu-Cu bonding, but can
is common to solve the issue with an expan- be improved upon.
sion in the Z-axis. In the property market this is
fine, but in the portable electronics market this Conclusion
direction is also becoming crucial. The Z-axis Although ENIG and ENEPIG still have a
constraints are high-speed signal transfer and place in a supplier’s portfolio, the future is look-

26 The PCB Design Magazine • April 2015

 feature

The Future of Nickel in Nickel/Palladium/Gold Final Finishes continues

Figure 9: The characteristics of prior art TCB compared to EPAG. (The highlights are in green.)

Figure 10: This demonstrates initial results achieved at the Georgia Institute of Technology (TCB at
190C – 3s – 365MPa with perfect electrical yield [1-2Ω]).

ing bright for the EPAG process. Hinged on the

Rick Nichols is global product
discussions above it is apparent that Ni presents
manager, selective finishing,
some difficulties when considering its suitabil-
at Atotech Deutschland GmbH.
ity within the scope of future requirements. The
He may be reached by
target of this article is to highlight the superior-
clicking here.
ity of the EPAG process in ascertaining the goals
of the future. PCBDESIGN

28 The PCB Design Magazine • April 2015

 coulmn

beyond design

Learning the Curve

by Barry Olney
In-Circuit Design Pty Ltd

Currently, power integrity is just entering price. The majority of high-end tools require a
the mainstream market phase of the technol- PhD to drive. However, the mainstream market
ogy adoption life cycle. The early market is demands tools that are intuitive and can be used
dominated by innovators and visionaries who by any member of the development team from
will pay top dollar for new technology, allow- EEs to PCB designers to achieve quick results.
ing complex and expensive competitive tools to Inadequate power delivery can exhibit in-
thrive. However, the mainstream market waits termittent signal integrity issues. These include
for the technology to be proven before jumping high crosstalk and excessive emission of elec-
in. Power distribution network (PDN) planning tromagnetic radiation, degrading performance
was previously overlooked during the design and reliability of the product. The PDN must
process, but it is now becoming an essential accommodate variances of current transients
part of PCB design. But what about the learning with as little change in power supply voltages
curve? The mainstream market demands out- as possible. So the goal of PDN planning is to
of-the-box, ready-to-use tools. design a stable power source for all the required
The mainstream market, representing more power supplies. As with stackup planning, the
than 65% of the total EDA software market, PDN design is required before a single IC is
wants established technology at an affordable placed on the board.

Figure 1: Technology adoption life cycle (Geoffrey A. Moore’s Crossing the Chasm).

30 The PCB Design Magazine • April 2015

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 beyond design

Learning the Curve continues

Figure 2: PDN with optimized decoupling.

Also, the same PDN connections (planes) mum bandwidth. For a 400MHz fundamental
that are used to transport high-transient cur- frequency, the maximum bandwidth is 2GHz
rents are used to carry the return currents for to take in the 5th harmonic. But I am frequently
critical signal transmission lines. If high-fre- asked one question: Does it have to be low all
quency switching noise exists on the planes, the way up to 2GHz?
coupling may occur, resulting in ground In Figure 2, you will notice the ringing in
bounce, bit failure or timing errors. Many fail- the top right corner of the plot. This is the plane
ures to pass electromagnetic compliancy (EMC) resonance. As the frequency approaches half
are due to excessive noise on the PDN coupling wavelength, the planes (power and ground) act
into external cables and radiating emissions. as an unterminated transmission line and start
If you are not familiar with a PDN plot (AC to resonate. This resonance is not a problem
impedance vs. frequency), it can be awfully unless it falls on the fundamental frequency or
daunting at first. Figure 2 shows the ICD PDN one of the odd harmonics. A Fourier series ex-
Planner with a typically 400MHz fundamental pansion of a square wave is made up of a sum
frequency and with an optimized capacitor se- of odd harmonics. If the waveform has an even
lection. Please refer to my previous series PDN mark-to-space ratio then the even harmonics
Planning and Capacitor Selection to understand cancel.
the effects of bypass and decoupling capacitors Figure 3 illustrates the typical electromag-
on the PDN, as this column will focus on the netic (EM) radiation spectrum analyzer plot for
plane resonance. a 400MHz DDR2 data signal. The fundamen-
The AC impedance (thick red curve) should tal frequency generally has little radiation, but
be below the target impedance up to the maxi- then increases up to the 5th harmonic and re-

32 The PCB Design Magazine • April 2015

 beyond design

Learning the Curve continues

Figure 3: EM radiation from a DDR2 data signal @ 400MHz.

duces again with the higher harmonics. But I 2.8GHz peaks. However, above 1GHz, there are
have seen cases where even the 11th harmonic— a number of ways to reduce the AC impedance:
4.4GHz in this instance—can create problems.
So what does this EM radiation have to do 1. On-die capacitance. Capacitors are placed
with the PDN analysis? If the AC impedance is on the IC itself by the manufacturer and gen-
high at the fundamental frequency or at any of erally cannot be changed. However, in some
the odd harmonics, then the board will radiate. cases, the capacitors are on the top of the IC. It
In Figure 4, I have superimposed the EM radia- may be possible to piggyback parallel capacitors
tion on the PDN plot. Look at where both the to increase their effect.
radiation and plane resonance peak. If these co- 2. Reduce the loop inductance of the de-
incide, then you will have excessive radiation at coupling capacitors. This can be achieved by
that particular frequency. In this case, the fun- moving the decaps to the top side of the board
damental 400MHz has a very low impedance so that the fanout vias have less distance to
so it will not be an issue. But, the 7th harmonic travel to the power and ground planes in the
is high and the 5th is borderline. Fortunately, substrate. The loop inductance can also be re-
the amplitude diminishes as the frequency de- duced by using multiple vias per land and spac-
creases. ing them close to each other to reduce the loop
I have pointed out a possible issue on the area. But this reduced inductance has minimal
5th and 7th harmonics in Figure 4, so how do we effect above 1GHz.
fix it? Decoupling capacitors are only effective 3. Select a material with lower dielectric
below 1GHz, so no matter how many are add- constant. This will push the plane resonance to
ed, to the PDN, they will not reduce the 2 and a higher frequency.

April 2015 • The PCB Design Magazine 33

 beyond design

Learning the Curve continues

Figure 4: EM radiation overlapped on the PDN plane resonance.

4. Increase the planar capacitance. This is ing the plane area however, will also reduce the
where the tight integration between the ICD overall attenuation by increasing the character-
Stackup Planner and PDN Planner comes into istic impedance. Also, keep the area as square as
play. You can add, say, 3M embedded capaci- possible. If you create a thin rectangular shape,
tance materials between the planes and then then the plane resonances will increase due to
import this stackup back into the PDN Planner. the different standing wave ratios of the X and
This material typically has 20nF/in2 capacitance Y directions being uneven, thus creating more
and significantly reduces the AC impedance parallel resonance peaks.
above 1GHz. Ultra-thin laminates are very ex-
pensive, but another option is to put two plane The optimization of the PDN is a trial-and-
pairs, of twice the dielectric thickness, in paral- error process that needs to be done in conjunc-
lel to achieve the same effect at a lower cost. tion with the stackup materials to fully exploit
5. Modify the plane area (capacitance). Ob- all avenues. Suppressing the plane resonance
viously, a DDR2 1.8V plane will not cover the peaks at the odd harmonics, to provide a low
entire area of the board. By reducing this area impedance profile at higher frequencies, also
to as small as possible (2-square inches) the helps to minimize electromagnetic emissions.
self-resonance of the plane will be moved up in
frequency, reducing the AC impedance at the Points to Remember
higher frequency and shifting the peaks. Reduc- • The mainstream market waits for the tech-

34 The PCB Design Magazine • April 2015

 beyond design

Learning the Curve continues

nology to be proven before jumping in. • Above 1GHz, there are a number of ways
• This market, representing more than 65% to reduce the AC impedance. The most effective
of the total EDA software market, wants estab- being increasing planar capacitance and modi-
lished technology at an affordable price. fying the plane area. PCBDESIGN
• Inadequate power delivery can exhibit in-
termittent signal integrity issues. References:
• The PDN must accommodate variances of 1. Barry Olney’s Beyond Design columns:
current transients with as little change in power PDN Planning and Capacitor Selection, Part 1
supply voltages as possible. & Part 2; Power Distribution Network Planning
• The AC impedance should be below the 2. Geoffrey Moore: Crossing the Chasm
target impedance up to the maximum band- For information on the ICD Stackup and
width (5th harmonic). PDN Planner, click here.
• As the frequency approaches half wave-
length, the planes act as an unterminated
transmission line and start to resonate. This
resonance is not a problem unless it falls on the Barry Olney is managing direc-
fundamental frequency or one of the odd har- tor of In-Circuit Design Pty Ltd
monics. (ICD), Australia. The company
• The fundamental frequency generally has developed the ICD Stackup
little radiation but then increases up to the 5th Planner and ICD PDN Plan-
harmonic and reduces again with the higher ner software, is a PCB Design
harmonics. Service Bureau and specializes in board level
• If the AC impedance is high at the funda- simulation. To read past columns, or to contact
mental frequency or at any of the odd harmon- Olney, click here.
ics, the board will radiate.

Breakthrough in the heat coming out. Since the 1960s there have
been incremental advancements in alloy technol-

Thermoelectric Materials ogy used in Peltier devices.

TE alloys are special because the metals have
an incredibly high melting point. Instead of melt-
French physicist Jean Charles Athanase Peltier ing the metals to fuse them, they are combined
discovered a key concept necessary for thermo- through a process called sintering which uses heat
electric (TE) temperature control in 1834. His find- and/or pressure to join the small, metallic granules.
ings were so significant that TE devices are now The applications for such a material are abun-
commonly referred to as Peltier devices. Since his dant. As new fabrication techniques are devel-
work, there have been steady advancements in oped, Peltier cooling devices may be used in
materials and design. Despite the technological place of traditional compression refrigeration
sophistication Peltier devices, they are still less en- systems. More importantly, as electrical vehicles
ergy efficient than traditional compressor/evapo- and personal electronic devices become more
ration cooling. ubiquitous in our daily lives, it is becoming in-
In the 1960s, Peltier devices were primarily creasingly necessary to have more efficient sys-
made from Bismuth-Tel- tems for localized electri-
luride (Bi2Te3) or Anti- cal power generation and
mony-Telluride (Sb2Te3) effective cooling mecha-
alloys and had a peak ef- nisms. This new thermo-
ficiency (zT) of 1.1, mean- electric alloy paves the
ing the electricity going in way for the future of mod-
was only slightly less than ern TE devices.

April 2015 • The PCB Design Magazine 35

 coulmn

Lightning Speed Laminates

RF Power Capabilities of
High-Frequency PCBs
by John Coonrod
Rogers Corporation

I often hear this question: “How much RF ity of a PCB, MOT is used as the maximum tem-
power can be applied to a high-frequency PCB?” perature of which a circuit can be exposed over
My answer sometimes surprises engineers. I long periods of time.
tell them that they can put as much RF power For example, a circuit with a heat rise of
into the PCB as they want, with the assump- +70°C above an ambient of +25°C must en-
tion that the PCB does not exceed its maximum dure a temperature of +95°C indefinitely. The
operating temperature (MOT). MOT refers to RF power which creates this heat rise is accept-
the maximum temperature to which a circuit able if the circuit has a MOT rating of +105°C.
can be exposed without degradation of critical But if the circuit’s heat rise is greater than +80°C
properties. The actual RF power limit of a PCB above ambient, the applied RF power level that
is based on the MOT of the circuit, and that is created the heat rise would not be acceptable.
dependent on the circuit material, the PCB con- When considering circuit heating due to ap-
struction and fabrication process. plied RF power, modeling the heat rise of high-
The relative thermal index (RTI) is a rating frequency PCBs can be difficult. Many variables
given to UL-rated circuit materials for the maxi- influence heat rise, and they must be taken into
mum temperature to which the raw material account. Insertion loss is the total RF loss of a
can be exposed indefinitely without degrada- high-frequency PCB and is equal to the sum-
tion in material properties. But when the raw mation of conductor loss, dielectric loss, radia-
material is made into a circuit, MOT is the rat- tion loss and leakage loss. Insertion loss is the
ing that is most applicable to the power-han- cause of the heat generated when RF power is
dling capability of a circuit. The MOT is always applied. A circuit with a high level of insertion
less than a circuit material’s RTI. When review- loss will generate more heat than a circuit with
ing the maximum RF power-handling capabil- lower insertion loss, when considering the same

36 The PCB Design Magazine • April 2015

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RF Power Capabilities of High-Frequency PCBs continues

amount of applied RF power. Insertion loss can which can be designed so the circuit will have
also be difficult to model, because there are sub- minimal insertion loss. This means the circuit
components that make up insertion loss. Typi- will generate less heat when RF power is applied
cally, the major contributors to insertion loss and a designer may assume that higher power
are dielectric loss and conductor loss. levels could be applied. However, many PTFE
Dielectric loss is related to the dissipation materials have very low thermal conductivity
factor (Df) and the tangent delta (tanδ) of the and even though there is less heat generated,

“
material. A material with higher Df the heat cannot efficiently get out
causes higher dielectric loss, which of the circuit, so the circuit may
in turn can cause higher insertion heat more than expected.
loss and high temperature rise Another tradeoff to consid-
with applied RF power. Con- One major consideration er is the thickness of the cir-
ductor loss is far more compli- for understanding RF cuit. As an example, a double-
cated than dielectric loss, with power capabilities of a sided circuit, which is a simple
several components making up microstrip circuit bonded to a
conductor loss. In general, a cir- high-frequency PCB is heat sink, will stay cooler if
cuit using copper with a rough to understand the the circuit is thin, as opposed
surface will have more conduc- to thick, when using the same
tor losses than a circuit using
impact of insertion loss. materials and same applied RF
smooth copper. Additionally, Generally, a circuit power. The thinner circuit has
there is a circuit thickness rela- material and design will a shorter heat flow path from
tionship, and a thinner circuit where the heat is generated at
will be more prone to conduc- be chosen to minimize the signal conductor, through
tor loss variables than a thicker insertion loss, but there the dielectric and to the
circuit. The thicker circuit is ground plane below which is
are tradeoffs and other
more dominated by dielectric attached to the heat sink.

”
loss. issues to consider. There are several addition-
One major consideration for al tradeoffs to consider, but a
understanding RF power capabili- quick summary would show
ties of a high-frequency PCB is to that the optimum circuit would
understand the impact of insertion loss. Gener- use a material with low dielectric loss and
ally, a circuit material and design will be chosen smooth copper, which gives low insertion loss
to minimize insertion loss, but there are trad- and generates less heat. Additionally, the opti-
eoffs and other issues to consider. mum material would have high thermal con-
All circuit materials exhibit a property ductivity and would be relatively thin.
known as thermal conductivity: the measure of A few high-frequency materials meet these
the ability to pass heat energy through that ma- criteria. When working with RF and microwave
terial. An extremely good thermal conductor is designs, consulting your materials provider can
copper, which has a thermal conductivity value save you time and money. These companies
of 400 W/m/K. However, most substrates used have plenty of information about thermal con-
for high-frequency PCBs have thermal conduc- ductivity, insertion loss, heat flow, overall ther-
tivity values that are considered a thermal in- mal management, and much more. PCBDESIGN
sulator or a very poor thermal conductor. Most
high-frequency circuit materials have thermal
conductivity values in the range of 0.2–0.4 John Coonrod is a senior market
W/m/K. A value of 0.5 W/m/K or higher is con- development engineer for
sidered good for thermal conductivity for a PCB Rogers Corporation. To read
dielectric material. past columns, or to reach
Now, let’s consider at quick tradeoff. There Coonrod, click here.
are some extremely low-loss PTFE materials

38 The PCB Design Magazine • April 2015

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PCB007
News Highlights
How 3D Printing will Impact Schmoll Keeping an Eye on the Future—
PCB Fabrication and on LDI
In the near future, we will enter an era where elec- In this interview, Thomas Kunz, who has been at
tronic devices are printed, rather than assembled. the helm of Schmoll Maschinen as president since
They will be fabricated layer-by-layer as a single 1993, discusses the company’s lengthy history in
object, rather than assembled from separate me- mechanical engineering (more than 70 years!),
chanical, electrical, and optical parts. This article current global scope, and what he sees as a steady
describes the implications that 3D printing will progression in directions that make the most sense
have on PCB manufacturing. to customers, which include laser direct imaging.​

Material Witness: Low-Flow Prepregs— IPC Volunteers Recognized at APEX

Defining the Beast! IPC presented Committee Leadership, Distin-
The term “low flow” should make sense to both guished Committee Service and Special Recogni-
suppliers and users of the products. A low-flow tion awards at IPC APEX EXPO® at the San Diego
prepreg flows sufficiently to wet out and adhere Convention Center in February. The awards were
to bonding surfaces and to fill innerlayer copper presented to individuals who made significant
details, but does not flow so much as to fill in cut- contributions to IPC and the industry by lending
out areas in a heat sink or run unevenly out of the their time and expertise through IPC committee
interface between rigid and flexible elements of a service.
rigid-flex PWB.
IPC Opens Latest Statistical Programs
Raising a Unified Voice for an IPC’s global statistical programs for the laminate,
Advanced Manufacturing Economy solder, process consumables and assembly equip-
The electronics manufacturing industry is an im- ment industries are now open to new participants
portant sector in the global economy, and John for 2015. The deadline for IPC members to sign
Hasselmann, VP of Government Relations at IPC, is up is April 15. Participation is free to IPC-member
an advocate for policies that will help our industry, companies as a benefit of membership.
as well as the prosperity and welfare of billions of
people. Shennan Circuit Gets Top Supplier Award
“Having a network of strong-performing suppli-
Reliability and Harmonization of Global ers that share our commitment to delivering ex-
Standards at Forefront of EIPC Efforts ceptional quality and cost-effective solutions is
At IPC APEX EXPO 2015, I-Connect007 Technical essential to meeting our customers’ needs,” said
Editor Pete Starkey caught up with EIPC’s Michael Wayne Flory, vice president, material & supply for
Weinhold and Alun Morgan, who were happy to Rockwell Collins. “Shennan has been a strong-
discuss both recent and ongoing focuses for EIPC, performing supplier since we started working with
namely, reliability. Also touched on was the impor- the company nearly ten years ago.”
tance of the alignment of global standardization
processes, especially for Asia.​ HDI Leads Rigid PCB Growth in 2014
High-density interconnect was still a main engine
FlexTech Honors Flex Electronics Firms of growth in rigid PCB field in 2014, and is ex-
FlexTech Alliance awarded Thin Film Electronics, pected to maintain the momentum in 2015. As
Vitex Systems and Pacific Northwest National Lab- mobile phone screens become larger, PCBs for
oratories (PNNL), and California Polytechnic Insti- mobile phones have to react accordingly. To en-
tute’s Graphic Communication Department with sure light weight and thinness of mobile phones,
the 7th annual FLEXI Awards for Innovation, R&D, the demand for more advanced anylayer HDI in-
and Leadership in Education awards, respectively. creases tremendously.

40 The PCB Design Magazine • April 2015

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 coulmn

Tim’s Takeaways

The Utility Belt

by Tim Haag
Intercept Technology

Back in school, I had planned on a career The utility belt is a great thing to have. Bat-
in music, specifically playing jazz clarinet or man would be long dead without his, and Tim
saxophone. But that didn’t happen. Instead, I “The Tool Man” Taylor would be useless with-
enjoyed a long career as a circuit board designer out his. But for a circuit board designer, a utility
that eventually lead to my current career as a belt is equally important.
customer support and training manager. All of us at one time or another will have
Even though a career in music was never re- questions about the CAD system we use, and
alized, many of the lessons learned during my one essential tool to have in your utility belt is
musical training have helped me in this career. a list of people you can go to for help. At the top
One of those lessons came from a grizzled old of this list should be your CAD system’s friendly
saxophone teacher who taught improvisational customer support staff (like me), so make sure
jazz. He drilled us on the basics of music: scales, that your company has current and up-to-date
chords, arpeggios, etc. access to your CAD system’s technical support.
As he said, “You always want to have some- I couldn’t begin to tell you the many times
thing in your pocket to pull from on those that I have helped customers with a simple an-
nights when you just aren’t feeling as creative swer to a perplexing question. Just the other
as usual.” He was talking about having some day I had a customer who was really stuck. He
basic jazz patterns to fall back on while impro- obviously knew our software well, but he was
vising, but the same general concept can be ap- missing that one piece of information that he
plied in our industry: Make sure you have some needed to break through the log-jam. I was able
good basic tools in your utility belt to help you
out when you need them.

Figure 1: What’s in your toolbelt?

42 The PCB Design Magazine • April 2015

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 tim’s takeaways

the utility belt continues

to answer his question and with that he resolved industry resources and design periodicals like
his problem. I really didn’t do anything too spe- this one is another great tool to have at your
cial for him, but my simple answer opened up fingertips.
for him a whole new direction that he could Here’s another good tool to have in your belt:
take, and that got him unstuck. preparation. This may sound pretty basic, but I
In the same vein, another important tool feel that it is perhaps the most important tool
in your utility belt is a solid understanding of of all for a PCB designer. When I was designing
your CAD application. Knowing what you are and starting a new project, I took the time to go

“
doing when you hit the keyboard can save you through the entire design and familiarize my-
lots of time and frustration, and will self thoroughly with it. I researched
make you much more efficient at the parts that I was going to use,
your job. Read the help manu- I looked at the floor-planning
als, seek out other users as It’s also important to have that the engineer was expect-
mentors, spend time with the ing, and I prepped the design
online tutorials, and even sign resources to help you with database with as much up-
up for training if needed. And design questions. Perhaps front information that I pos-
as you come up to speed on
your design tools, be flexible
you’re stuck trying to lay siblyI have could.
seen many other de-
and adapt to the process that out a circuit with unusual signers just jump in and start
your specific CAD application requirements, or you are throwing things on the screen
is designed for. Let me tell you while I was still going through
from personal experience, it’s unfamiliar with a new type all the data. Sometimes those
extremely unproductive to be- of technology. It is always designers would pull way
rate the support staff because a good idea to have lot of ahead of my work and they
you were expecting the “View looked very impressive. But as
All” menu command to be in a different people available time went by, those other de-
different location than where that you can go to for help. signers would then start to re-

”
it actually is. Using the excuse work their board because they
“Well, that’s the way my old had made a mistake with library
CAD system worked!” isn’t very parts, or their rushed placement
helpful. Instead, get well acquaint- did not allow enough room for criti-
ed with your system and become the super user cal routing, or any one of a number of different
that others will look up to for help. reasons. I’m not saying that I’m the “be all, end
It’s also important to have resources to help all” of how to design, but I do know that my
you with design questions. Perhaps you’re stuck rate of re-work was much lower than other de-
trying to lay out a circuit with unusual require- signers because I made sure that I was prepared
ments, or you are unfamiliar with a new type for the job, up front.
of technology. It is always a good idea to have Part of being prepared is also being alert so
lot of different people available that you can go you don’t do something that you’ll regret later.
to for help. Just recently I was trying to come When I was a kid we had a very underpowered
up with a way to help a customer with a library lawn mower, and grass would always get backed
process problem. The answer was right in front up inside it. I would have to shut the mower off
of me, but I was so focused on doing it a cer- and pull the packed grass out of the exit chute
tain way that I never considered a different ap- every 25 yards or so. This got so annoying that
proach. A quick conversation with a co-worker after a while I would just dig the grass out with
turned on the light of inspiration for me that I my hand while the mower was still running.
needed to help this customer. You can see this one coming can’t you? Yep.
Staying current on design blogs, forums, One day I stuck my hand in too far and one
application FAQs and other Q&A websites is of my fingers found the spinning blade. For-
also very helpful. And keeping up with different tunately the mower was so weak that all it did

44 The PCB Design Magazine • April 2015

 tim’s takeaways

the utility belt continues

was jam my finger and split my fingernail. But before the design leaves their department. This
I had gotten careless in my haste. As carpenters is a new and different way of doing things for a
say, “Measure twice and cut once.” Perhaps we lot of designers and unfortunately many avoid
could modify that advice to make it analogous it. But it’s there for a reason: to help eliminate
to the PCB design community and then stick errors, reduce board spins, save cost, and ulti-
that in the utility belt as well. mately create a better design.
And here’s my last thought for handy tools We probably won’t ever get called upon to
to have in your utility belt: “If your CAD system save Gotham City from the Joker, and hopeful-
can do it, make sure that you use it.” Too often I ly none of us will ever try to enhance a riding
have seen designers omitting helpful features or lawnmower with a jet engine as Tim “The Tool
doing something manually when their CAD sys- Man” Taylor did, but a utility belt fully stocked
tem already has these automated routines avail- with tools to help us with PCB design is a great
able. These functions are put into the tools to thing to have, and may ultimately make the
help you, so you should use them. For example, difference when we are really stuck.
on the layout system that I support, Intercept’s As Tim Taylor would say, “Aaaaaaaarooohhh!”
Pantheon, we not only have regular DRCs avail- PCBDESIGN
able but also ERCs and MRCs (electrical rules
checking and manufacturing rules checking). Tim Haag is customer support
These checks give the designer the ability to and training manager for
verify their design in the same way that fabrica- Intercept Technology.
tion and manufacturing vendors do. With this
ability the designer has the opportunity to find
problems specific to the manufacturing process

Video Interview

Altium Talks 3D Flex Packaging Design

by Real Time with...
IPC APEX EXPO 2015

During IPC APEX EXPO,

Ben Jordan, senior manager or
product marketing for Altium,
met with Guest Editor Kelly
Dack to discuss Altium’s focus
on design tools for rigid-flex.
He explains how Altium’s tools Click
eliminate the need to create
paper dolls by modeling rigid- realtimewith.com
flex in full 3D, and much more. To View

April 2015 • The PCB Design Magazine 45

 article

Figure 1: Kelly Dack speaks with

new CID recipients Zev Gross and
Jeff Davidson, from left to right.

Hunter’s Two Newest CID

Recipients Discuss Certification
I-Connect007 Guest Editor Kelly Dack spent Dack: Now, not many people get an opportunity
time at Hunter Technology’s Silicon Valley to tell the world about this experience. What was it
plant. He had the opportunity to sit down with like going through the certification process?
two recent CID recipients, Jeff Davidson and
Zev Gross, who completed Dack’s CID training Davidson: Well, there was a lot of information
program. The two also discuss the benefits of in the book, but I thought it was pretty straight-
achieving certification and their plans to take forward. And the materials are sent to us before-
the CID+ advanced course. hand.

Kelly Dack: Thank you for the opportunity to visit Dack: Zev, what was it like for you? As one of our
Hunter Technology. And congratulations to you more vocal students in the class, you seemed to
both for achieving IPC’s Certified Interconnect De- have a take on every concept that we discussed,
sign certification. I enjoyed having you both in my and it blended right in with where we were going.
class. As an instructor, it was helpful to have your com-
mentary in the class.
Jeff Davidson: Thank you.
Gross: First of all, the feeling is great to have
Zev Gross: Thank you, Kelly. certification in our field, which is typically un-

46 The PCB Design Magazine • April 2015

 article

Hunter’s Two Newest CID Recipients Discuss Certification continues

common. Thank you for teaching us. The com- Dack: There is also an advanced CID+ class. Do
mentary stems from the fact that I come from you both plan to take the advanced certification?
a lot of different environments, both here and
abroad, which give me a take on many of the Davidson: Absolutely, I do.
issues that we were learning about.
Gross: Yes, I do as well. We want to get more
Dack: What was the purpose of obtaining your familiar and in-depth with our field and termi-
CID certification? Was it based on credibility, or the nology, which are more standardized than what
challenge, or what? we typically do. It’s nice to have it on paper.
There are many benefits for us as designers.
Davidson: I think having that certificate is a
sign of credibility, especially with IPC being the Dack: In the CID+ program, many more concepts
industry standard. are built on from the basic course. You’ll be going
into the high-speed areas and much more, so look
Dack: Here’s the way it might be explained for forward to that. Along with the class, it was part
some: We just walked through your plant, and I of the prerequisite to sign up and check out the
noticed that, at every step of the way in the PCB IPC Designer Council, which seems to be revving up
assembly process, things are checked and mea- across the country. Have you done that?
sured and verified. Isn’t the CID program a way of
measuring the capability or the learning and the Gross: Yes, we both have signed up with the
knowledge of the designer? Silicon Valley chapter. We’re looking forward to
seeing both of our names on the CID Certified
Davidson: Yes, absolutely. Our designs have got section.
to be able to go through all those steps and they
must pass all their measurements and verifica- Dack: And attending your first meeting, hopefully
tions, so it’s nice to make sure that we’re doing soon.
it correctly, so that the people down the line
can do it correctly. Gross: Yes, definitely.

Dack: Well, I’d like to

again congratulate you
both and thank you so
much for having me to
your plant. Your design
area is top notch. In fact,
I made a promise that I
wouldn’t keep you too
long because you’ve got
a customer waiting back
there and he is fully ex-
pecting high-quality CID
design right now, isn’t
he?

Davidson: Exactly Thank

you, Kelly.

Gross: Thanks, Kelly.

PCBDESIGN
Figure 2: Kelly Dack speaking with Zev Gross.

48 The PCB Design Magazine • April 2015

Mil/Aero007
News Highlights
Sanmina’s Costa Mesa Facility in the Western territory of the United States. Mr.
Earns AS9100C Kallbrier will report to Robert Nurmi, Park’s VP of
Sanmina’s PCB facility in Costa Mesa, California, sales—Americas.
has received AS9100C certification, allowing the
company to manufacture PCBs for aerospace and Isola Qualifies FTG to Use
defense electronics equipment. I-Speed Materials
Bradley C. Bourne, president and CEO of FTG,
Shennan Circuit Gets Top Supplier Award stated, “We are pleased to have Isola recognize
“Having a network of strong-performing suppliers FTG for our outstanding manufacturing capabili-
that share our commitment to delivering excep- ties using I-Speed materials. We look forward to
tional quality and cost-effective solutions is essen- continuing with the certification program in quali-
tial to meeting our customers’ needs,” said Wayne fying additional Isola materials.”
Flory, vice president, material & supply for Rock-
well Collins. Companies See Significant Benefit
in Nadcap Accreditation
Ventec Increases Focus on More than one in five companies pursues Nadcap
Aerospace Market accreditation to improve quality, according to a
Ventec Europe continues its investment in the es- recent poll conducted by the Performance Review
tablishment and maintenance of meticulous aero- Institute (PRI). Of those that responded, 21% cited
space-standard cleanliness in the pre-preg handling “improving quality” as a key driver behind their
areas of their state-of-the-art distribution center in decision to obtain Nadcap accreditation, with
Warwickshire, United Kingdom. 19% indicating that they pursued Nadcap accred-
itation in order to attract new business.
Electrochemicals Celebrates 50 Years
of Service UAV Market Hurt by Cut in
Leo Linehan, VP & GM Electronic Chemicals states, Defense Budgets
“This is an exciting time in the electronics industry The global economic slowdown has reduced the
as we see significant technological advances, min- defense budgets of most leading spenders in the
iaturization, and the need for enhanced reliability. world, including the US, France, Germany and the
OM Group is committed to meeting these needs.” UK. Cuts to military expenditures have led to the
cancellation and indefinite delays of various UAV
Automation Drives Military Ground projects and a detrimental impact on the growth
Robot Market Growth of the UAV industry.
ReportsnReports.com adds Military Ground Robot
Mobile Platform Systems to Engage Terrorists: Mar-
ket Shares, Strategies, and Forecasts, Worldwide,
2015 to 2021 industry research report that says the
new military is dependent on flexibility and early
response.

Park Electrochemical Adds New

Technical Sales Engineer
Park Electrochemical Corp. announced the ap-
pointment of Mike Kallbrier as a technical sales
engineer of Park Electrochemical Corp. In this po-
sition, Mr. Kallbrier will be responsible for sales
of Park’s aerospace and electronics product lines

50 The PCB Design Magazine • April 2015

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 article

Effective Decoupling Radius

by Kirk Fabbri components could be written about separately,

KSPT Engineering Consulting but it is the PCB that will be focused on; specifi-
cally the effective decoupling radius.[2]
When a device is active, it will require current.
Power distribution networks (PDN) are be- The type of device (process size), load on the I/O
coming an important topic. Many engineers are drivers, and how the device is operated, all have
finding that properly designing the power sup- an effect on the current required, among oth-
plies and providing adequate decoupling for de- ers. When the device demands current, it flows
vices is a challenge, especially since devices are through the complex impedance of the PDN and
switching faster and dimensions are shrinking. causes a ripple voltage to appear. This transient
Engineers often focus on discrete decoupling current is drawn from a variety of sources includ-
capacitors placed local to switching devices in ing the local on-die decoupling capacitance, the
hopes of providing the required capacitance for PCB, the discrete capacitors, and finally the VRM.
these high current demands. One of the more [1]
The edge rate of this switching current is ex-
overlooked items of the power distribution sys- tremely important when trying to calculate how
tem is the PCB, and how it contributes to the effective the PDN will be in suppressing the ripple
power distribution system’s ability to decouple voltage. The switching edge can be dissected into
the switching devices. The following experi- a variety of harmonic sine waves at decreasing
ment will outline a basic principle that should amplitude described by a Fourier series equation.
be in mind when designing a stack-up and PDN. It is here that we discover the importance of the
PCB, and its role in the PDN.
Basic PDN Model The simplest way to represent a PCB is a dis-
A basic PDN includes the voltage regula- tributed RLC network. Capacitance is formed
tor model (VRM), the discrete decoupling ca- by the copper layers and the dielectric between
pacitors, the PCB, and any on-die capacitance them. Inductance is formed by the loop area be-
formed on the IC or device. Each one of these tween the layers, and the resistance is formed by

52 The PCB Design Magazine • April 2015

April 29–30 October 13
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Discussion with international experts on
May 13–14 regulatory issues
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 article

Effective Decoupling Radius continues

the cross sectional area and length of the cop- According to Ott[2], the effective radius in
per planes. From equation 1 below, capacitance which capacitance can be utilized is calculated
can be calculated where C = capacitance in pF, by the equation below, where r = radius in inch-
eo = permittivity of free space (0.225pF/inch), es, t = rise/fall time of switching edge (ns), and
er = dielectric constant, A = area (in2), and S = er = dielectric constant. By looking at this equa-
spacing between the planes (inches)[3]. Here we tion, we can conclude that the effective area (r)
see that the best way to increase the capacitance decreases when either the switching edge be-
is by decreasing the spacing between the planes comes faster (t decreases), or the dielectric con-
or increasing the area of the metal layers. stant of the medium increases.

(1) (2)

Figure 1: The baseline stack-up for Experiment 1. Power plane pairs are spaced 3 mils apart.

54 The PCB Design Magazine • April 2015

 article

Effective Decoupling Radius continues

Experiment 1: PCB Area Larger than

Required Effective Area.
This first experiment will outline a situation (3)
where the available power plane area is larger
than the effective radius calculated in Equation
2. Shown in Figure 1 is the stack-up used for Using this effective area, we can calculate
this experiment. It is an eight-layer board with the effective capacitance as 2.13nF, shown in
a top/bottom layer, three ground planes, and equation 4 below. In this example, the capaci-
three planes at different supply voltages (1.5, tance is calculated based on a single VCC1_5
1.8, and 3.3V). The dielectric thicknesses be- and GND plane pair (layers 2 and 3) neglecting
tween the power/ground planes are 3 mils (0.75 the holes from the stitching vias.
mm), which is a fairly popular size. Shown in Figure 3 are the results of this
Shown in Figure 2 is a simple PCB created in baseline simulation. The peak noise voltage is
Mentor Graphics HyperLynx with an area of 16 in2 found to be 91.4 mV located at the current sink.
(4 x 4 inches), where U1.1 represents the VRM and
U2.1 represents the current sink. The current sink
is setup to draw 250mA with rise/fall times equal (4)
to 250ps. In this baseline case, both the current
sink and VRM are connected to layer 2 (VCC1_5),
and referenced to all three GND layers. The small
yellow circles represent stitching vias used to con- Experiment 2: Further Increasing
nect all GND layers together. Shown in equation the PCB Area
3 below is the calculation of the effective radius Oftentimes, simply increasing the PCB area
yielding an area of 6.60 in2, which is considerably is thought to have a positive effect on the noise
smaller than the total PCB area (16 in2). voltage since the capacitance is also being in-

Figure 2: The example PCB with one current sink Figure 3: Showing the results of the baseline
(U2.1) and one VRM (U1.1). The small yellow simulation connecting the VRM and current sink
circles represent stitching vias used to connect to layer 2 (VCC1_5). Peak noise voltage is 91.4
the different ground layers together. mV at the current sink.

April 2015 • The PCB Design Magazine 55

 article

Effective Decoupling Radius continues

creased. After running the simulation on this First, let’s increase the dielectric constant of
experiment, we will see that this isn’t necessar- the material. What if we were to increase it by
ily the case, as it depends on whether or not the something much larger, say 20? After altering
plane area is already larger than the effective ra- the stack-up to represent a dielectric constant
dius calculated in Equation 3 above. of 20 on all layers (besides the solder mask on
The PCB size is now made 64 in2 (8 in x 8 in) the top/bottom layers), the simulation was run
with all other factors remaining the same. The re- and resulted in a peak noise voltage of 72.3mV.
sults of the simulation are shown in Figure 4 be- At first glance, simply looking at Equation 1 for
low with a noise voltage equal to 87.1mV. It’s fairly capacitance indicates that we might expect to
easy to see that the additional capacitance of the see a larger difference in noise voltage when us-
plane isn’t significantly improving the noise volt- ing a higher dielectric constant. To answer this
age, as its contributions are outside of the effective question, the new effective radius using a di-
area based on the rise/fall times of the current sink. electric constant of 20 is calculated to be 0.67
in, as shown in Equation 5. This radius results
Experiment 3: Increasing the Dielectric in an effective area of only 1.41 in2, which by
Constant, Changing the Layer Spacing comparison, is much smaller than 6.60 in2 as it
In Experiment 2, we found that increasing was in the original experiment.
the power plane size outside of the effective area/
radius had little to no effect on the noise volt-
age created at the current sink. What if we were (5)
to increase the capacitance of the power plane
by either increasing the dielectric constant or by
decreasing the spacing between layers? Either or
both of these factors would certainly increase What we see happening here is very interest-
the capacitance of the plane pair as well. ing. In this case we wanted to increase the total
capacitance of the plane pairs in attempt to fur-
ther suppress the noise voltage. By increasing
the dielectric constant, we effectively shrink the
effective radius, and thus the area that the cur-
rent sink can effectively use. The effective ca-
pacitance from the original dielectric constant
(4.3) is approximately 2.13nF, whereas the new
capacitance formed by increasing the dielectric
constant to 20 is calculated as 2.13nF also! Run-
ning the simulation on this setup yields a noise
voltage of 72.3mV, which is improved slightly
over 87.1mV. The results of the simulation are
shown in Figure 5.
It is important to note that there are more
complex interactions at work here than just
the capacitance of the plane. Modal resonanc-
es, spreading inductance, etc., also play a part,
which are accurately captured by the field solver.

Experiment 4: Decreasing the Spacing

Figure 4: Showing the results of experiment 2 between the Planes
above. The area of the PCB (64 in2) is now much In this experiment, we will decrease the
larger than the calculated effective area (6.60 spacing between the planes to something very
in2), yet the noise voltage (87.1 mV) is almost un- small—1 mil. Although these materials are
affected from the previous simulation (91.4mV). available, they are very expensive and possibly

56 The PCB Design Magazine • April 2015

 article

Effective Decoupling Radius continues

Figure 5: Results of the simulation for Experiment Figure 6: Results of the simulation for Experiment
3. The dielectric constant was increased to 20 for 4. The dielectric constant is 4.3, with the spacing
all layers. The noise voltage at the current sink between layers 2 and 3 = 1 mil. The peak noise
has only dropped 14.8mV from the same setup voltage is found to be 31.2mV, substantially im-
with a normal dielectric constant of 4.3. proved over the 87.1mV found in Experiment 2.

unavailable depending on the fabricator used. cused on what could be done when using a sin-
In this experiment, it is done to see if there are gle power plane pair as the main source of PCB
drastic effects on the results of the noise volt- capacitance. We have shown that increasing
age. Additionally, the dielectric constants are the size of the PCB outside of the effective area
set back to their original values of 4.3, and the has little effect on the noise voltage. Likewise,
board is made large (64 in2). The capacitance of we have witnessed that increasing the dielec-
this setup is calculated as 6.39nF, and the results tric constant also has little effect on the noise
of the simulation are shown in Figure 6. Notice voltage as it offsets the added capacitance by
that the noise voltage is substantially improved shrinking the effective radius. What if we were
over the previous cases, and even more so than to use two separate plane pair structures, both
the high dielectric case. at a physical size that is similar to the size of the
What if we set the board size back to 16 effective radius?
in2 (4in x 4 in) as it was in experiment 1? Af- Running this experiment requires a change
ter running this simulation, the noise voltage to the way the current sink and VRM are set-
was found to be 32.8mV, consistent with what up in the simulation. The stack-up is altered
we thought might happen based on our previ- so that layers 6 and 7 are also connected to
ous experiments and intuition. The addition- VCC1_5. Now we will have two cavities form-
al capacitance formed by increasing the board ing capacitance, both within the effective ra-
by 4x the original size has made almost no dius of the current sink. In a simplistic man-
difference in the total noise voltage because it or, the capacitance should double, but there
is outside of the calculated effective area. is also inductance associated with not only
each plane pair cavity, but also between the
Experiment 5: Increasing the Number two cavities. Additionally, we must stitch the
of Power Planes planes together with vias for both the GND
In the previous experiments, we have fo- layers and the newly created VCC1_5 plane on

58 The PCB Design Magazine • April 2015

 article

Effective Decoupling Radius continues

layer 6. The dielectric constant is set back to

4.3 and the spacing is set to 3 mils between
plane pairs. Figure 7 shows the results of the
simulation having a peak noise voltage of only
39.1mV at the current sink.
What happens if we shrink the spacing
between the power planes to 1 mil? From our
previous experiments we can take an educated
guess that the capacitance should increase and
it should improve our noise voltage. Running
this scenario concludes this and shows a peak
noise voltage of only 15.4mV!
You may ask when a scenario like this is
appropriate. Consider a memory system such
as DDR2. Often the manufacturer will specify
that byte lanes be routed on different layers
for crosstalk, timing, trace impedance, and
other constraints. In a system like this you will
likely be forced to use multiple split planes for Figure 7: Showing the results of Experiment 5.
your PDN to accommodate other devices as Layer 6 is now connected to layer 2 by stitching
well. In a system like DDR2, it makes sense for vias to increase the effective capacitance con-
all of your signals to use either GND or a 1.8V nected to the current sink. Both layers 2 and 6
power plane as a reference (return) plane since are sized so that they are similar to the calculated
this is the nominal power loop where the cur- effective area. The peak noise voltage is only
rent is drawn from. Using a reference plane 39.1mV.
that is not in the nominal current loop (say
3.3V) may not be a good choice. In this situa-
tion, the plane that is 3.3V could be split and what if the area of the PCB is smaller, or much
connected to 1.8V in the area where the DDR2 smaller than the calculated effective area? What
nets are routed. This way the signals are refer- are the best solutions in this case?
encing a power plane (or GND) that is in the For this experiment, we will use the same
nominal power loop and providing additional current sink properties yielding an effective ra-
capacitance for the switching currents. One dius of 1.45 in and an area of 6.60 in2. However,
still needs to calculate the effective radius of the board area will be considerably smaller—2
the memory system by simulating/calculating in2 (1.41 x 1.41 in). The stack-up has been set
the edge rates of the system. From here, the back to 3 mil spacing, dielectric constant of
designer can grasp an idea of how large the 4.3, with the current sink and VRM connected
plane area needs to be. Obviously, the place- to just layer 2 as previously. Figure 8 shows the
ment/routing area of the memory system need results of the simulation. Here we see the peak
to be considered as well when deciding where noise voltage is worse at the edges of the board
to place splits. Always extend the plane so that (129.4mV) versus at the current sink (106mV).
signals aren’t routed over splits whenever pos- The board geometry is also playing a role as
sible, even if the plane area is larger than the there are modal resonances occurring different-
calculated effective area dictates. ly than with the larger board.
We can conclude that both decreasing the
Experiment 6: Board Area is Smaller dielectric spacing between the layers and using
than the Effective Area additional planes will decrease our noise volt-
Our previous experiments only looked at the age by increasing the capacitance of the system.
board when it was either similar or much larger What about increasing the dielectric constant
than the effective area of the current sink. So to something higher?

April 2015 • The PCB Design Magazine 59

 article

Effective Decoupling Radius continues

Calculating the capacitance for both cases

yields 645pF for the standard dielectric con-
stant of 4.3 and 2.12nF for the high dielectric
case. Running the simulation with the dielec-
tric constant = 14 for all power plane layers is
shown in Figure 9. Right away we notice that
the noise voltage at the current sink hasn’t
changed much (delta of ~12mV), but the noise
voltage at the plane edges has decreased by
66mV. In this case local decoupling of the cur-
rent sink should also help suppress the noise
voltage.
As a final thought, we could decrease the
spacing and add additional plane pairs to in-
crease the capacitance of the PCB. Simply chang-
ing the plane pair spacing to be 1 mil yields a
noise voltage of only 22mV at the edges and
33.5mV at the current sink. Adding in an ad-
Figure 8: Results of Experiment 6. The total board ditional layer and leaving the spacing at 3 mils
area is considerably smaller than the effective yields a noise voltage of 39.3mV at the current
area. The peak noise voltage is 129.4mV located sink and 23mV at the edges of the PCB. The best
at the edges whereas the voltage at the current scenario for this experiment is to change the
sink is approximately 106mV. power plane spacing to 1 mil as well as add an
additional layer when using the high dielectric
material. In this case the noise voltage simulates
Recalling the earlier experiment, increasing as only 15.5mV at the current sink and 8.5mV
the dielectric constant negatively affected the at the PCB edges.
available capacitance by shrinking the effective
radius, and thus the area. This still very much Conclusions
holds true, but if the plane area is smaller than Designing a stack-up and PDN can be a
the effective area, then it isn’t being fully uti- difficult task as there are many factors to con-
lized by the current sink. In this case, decreas- sider for proper performance. Often times me-
ing the effective area by increasing the dielectric chanical, thermal, and cost constraints impact
constant will increase the available capacitance the number of layers, the materials, and the
and should lower the noise voltage. amount of time that can be spent analyzing
One has to calculate how much the dielec- the design. It is also important to note that
tric constant can be increased, as to fully utilize real designs have many complex current sinks,
the available plane area, but not so much as to with many different dynamic characteristics.
shrink the effective area below the PCB plane A traditional method of estimating these cur-
area. In our case, the plane area is 2 in2, which rents is to simulate the I/O of a device(s) and
gives a capacitance of 645pF when the dielectric look at the driver I/O current spectrum to bet-
constant is 4.3 and the spacing is 3 mils. Since ter understand the switching activity of these
the area is 2 in2, the radius (r) must equal 0.797 devices1. From this frequency spectrum, one
in. Solving Equation 2 for the dielectric constant can gain a better understanding of the load
using this radius yields ~ 14, which tells us we dynamics, and how to gauge the effective ra-
can increase the dielectric constant all the way dius. With all simulations, it isn’t an exact sci-
up to 14, shrinking the effective area to match ence. Sometimes, the most important thing
the current sink. By doing this we can fully uti- you can find out is what scenarios yield the
lize the plane area in a way that maximizes the greatest impact given the amount of informa-
capacitance and lowers the noise voltage. tion available.

60 The PCB Design Magazine • April 2015

 article

Effective Decoupling Radius continues

• In the case where the PCB is larger than

the calculated effective area, further increases in
plane area outside of the effective radius/area
also have minimal impact on performance.
• In the case where the PCB is smaller than
the calculated effective area; increasing the ca-
pacitance by using higher dielectric constant
materials can improve noise voltage perfor-
mance. However, similar, if not better results
are achieved by decreasing the spacing or add-
ing additional plane pairs.
• Decreasing the plane pair spacing not only
increases the capacitance but also decreases the
inductance of the structure.
• The PCB is only one part of a PDN. The
VRM, discrete decoupling capacitors, chip pack-
age, and on-die capacitance are also very im-
portant in achieving the desired performance.
Figure 9: Showing the results of Experiment 6 PCBDESIGN
when adjusting the dielectric constant higher.
The peak noise voltage has decreased near the References
corners to 66mV, but only to 93.2mV at the 1. Right the First Time, A Practical Hand-
current sink. book on High-Speed PCB and System Design,
Volume 2, by Lee W. Ritchey.
2. Electromagnetic Compatibility Engineer-
Important Points to Remember ing, by Henry W. Ott.
• The dynamic characteristics of the cur- 3. Signal Integrity: Simplified, by Eric Boga-
rent sink or load determine the effective area tin.
in which the capacitance of the PCB can be uti-
lized.
• In the case where the PCB is much larger Kirk Fabbri is owner of KSPT
than the calculated effective area, high dielectric Engineering Consulting LLC
materials are of minimal impact in noise volt- and Electrical Engineer for
age suppression. Better performance is achieved L-3 Communications—Avionics
by increasing capacitance either by minimizing Systems. He can be reached at
power plane spacing, or by increasing the num- kirk.fabbri@L-3com.com.
ber of plane pairs attached to the current sink.

Driverless Cars to Renovate and steering wheel if one wants to drive it manually.
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Automotive Industry panies are trying to create their own adaptations of
driverless cars, satisfying the predictions that they
will be a reality on the roads possibly by the end of
The most recent Mercedes automatic car looks this decade.
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F 015 “Luxury in Motion” showcased at the Consumer as self-parking preview and adaptive cruise control
Electronics Show, is totally self-driving but has a brake show what a fully automatic car can do.

April 2015 • The PCB Design Magazine 61

Top
Ten
Recent Highlights
from PCBDesign007
1 PCB Designer and Instructor
Kelly Dack Joins EPTAC 3

Intercept Technology
Launches New Website
Kelly Dack, one of the electronic industry’s most Intercept customers can also make special use of
consummate printed circuit board designers, in- a new, authorized access section devoted spe-
dustry supporters and interviewer of the trendset- cifically for them. The new section includes the
ters in the market, has joined EPTAC Corporation latest software releases, a continually updated
to support the growth efforts of EPTAC’s IPC De- Knowledge Base complete with all documenta-
signer Group, led by Gary Ferrari. tion across products and services, an Intercept
User Forum and an easy to use customer request
page. 
2

Mentor Graphics Debuts
Xpedition Package
Integrator Flow
4

Zuken Expands E3.series
Reseller Network in N.A.
The new Package Integrator flow allows design
teams to realize faster and more efficient physi- Zuken has expanded its E³.series reseller network
cal path finding and seamless tool integration for in North America with the addition of CAM Logic.
rapid prototyping, right to the production flow. CAM Logic is a leading provider of PLM solutions
This solution ensures that ICs, packages and PCBs and 3D engineering software and services.
are optimized with each other to reduce package
substrate and PCB costs.

62 The PCB Design Magazine • April 2015

5

Azitech to Host Seminar
with Rick Hartley May 5-6 8

Pulsonix Continues Global
Growth with the
Appointment of 3D Tronic
This two-day seminar in Copenhagen, Denmark,
will feature Richard Hartley. The signal integrity This announcement continues Pulsonix EDA
guru will focus on issues PCB designers and en- software’s goal of global expansion. 3D Tronic
gineers need to know about to prevent problems boasts a wealth of experience in the EDA indus-
with noise, EMI, and signal integrity. Moreover, at- try and this experience will act as a bi-directional
tendees will learn how to deal with crosstalk and synergy for both customers and the EDA tool
grounding problems in high speed digital and alike.
mixed signal designs.

6 Zuken Offers PCB Reference 9

DesignCon 2015 Names Best
Paper Awards Winners
Design for Intel IoT Devices
DesignCon has announced the winners of the Best
Intel and Zuken are engaged in a technical partner- Paper Awards from its 2015 program. The awards
ship working to address convenience improvements were divided into four categories: Modeling &
for designs in Zuken PCB design environments that Simulation, High-Speed Signal Design, Power In-
use Intel platforms. This delivery of PCB reference tegrity & Signal Integrity, and Test & Measure-
designs forms just one part of these efforts. ment.

7

Mentor Offering Training
in Atlanta, Tampa in April
J

Mentor Graphics Launches
New HyperLynx SI/PI

The agenda will include a description of the “elec- Mentor Graphics Corporation has released the
trical signoff” problem, and an overview of the newest version of the HyperLynx Signal Integrity/
HyperLynx tools that address the signoff require- Power Integrity (SI/PI) tool for high-speed PCB de-
ments. Several short demos will show how easy- signs. HyperLynx addresses high-speed systems
to-use and effective the HyperLynx virtual proto- design problems throughout the design flow,
typing tools can be. The training will take place in starting at the earliest architectural stages through
Atlanta on April 14 and Tampa on April 16.  post-layout verification.

PCBDesign007.com for the latest circuit design

news and information —anywhere, anytime.

April 2015 • The PCB Design Magazine 63

 calendar

Events Internet of Things Applications

For the IPC Calendar of Events, click here. Europe 2015
April 28–29, 2015
Berlin, Germany
For the SMTA Calendar of Events, click here.
Wearable Technology Europe
For a complete listing, check out April 28–29, 2015
The PCB Design Magazine’s event calendar. Berlin, Germany

SMT Processes Certification

April 28–30, 2015
South East Asia Technical Training Kokomo, Indiana, USA
Conference on Electronics Assembly
Technologies 2015 IMPACT 2015: IPC ON CAPITOL HILL
April 14–16, 2015 (IPC Members-only)
Penang, Malaysia April 29–30, 2015
Washington, DC, USA
SMTA Atlanta and Designers Roundtable
April 15, 2015 Michigan Expo & Tech Forum
Duluth, Georgia, USA May 5, 2015
Livonia, Michigan, USA
NEPCON China 2015
April 21–23, 2015 Oregon Expo & Tech Forum
Shanghai, China May 5, 2015
Beaverton, Oregon, USA
Printed Electronics Europe 2015
April 28–29, 2015 Puget Sound Expo & Tech Forum
Berlin, Germany May 7, 2015
Bellevue, Washington, USA
Graphene and 2D Materials Europe
April 28–29, 2015 Wisconsin Expo & Tech Forum
Berlin, Germany May 12, 2015
Milwaukee, Wisconsin, USA

IPC Technical Education

May 13–14, 2015
Fort Worth, TX, USA

International Conference on Soldering

& Reliability 2015
May 19–21, 2015
Markham, Ontario, Canada

Toronto SMTA Expo & Tech Forum

May 21, 2015
Markham, Ontario, Canada

64 The PCB Design Magazine • April 2015

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A d v er t i s er I n de x Coming Soon to
Candor Industries............................................ 39 The PCB Design
Dibble Leaders................................................ 49 Magazine:
Downstream Technologies.............................. 21
Dymax............................................................ 37
Eagle Electronics............................................... 7 May:
EMA/EDA Design Automation......................... 11
Controlled
In-Circuit Design Pty Ltd................................... 3
Intercept......................................................... 47 Impedance
IPC.................................................................. 53
Isola.................................................................. 5 June:
Mentor............................................................ 29
IPC Standards
Miraco............................................................ 43
Multilayer Technology..................................... 27
Update
Prototron........................................................ 19
Pulsonix.......................................................... 17 July:
The PCB List................................................ 2, 57 Supply Chain
Rogers............................................................. 41
Management
Sunstone Circuits............................................ 13
US Circuit....................................................... 31
Ventec............................................................ 51

April 2015 • The PCB Design Magazine 65