EXP NO: 1 DATE:

VERIFICATION OF LOGIC GATES

AIM:
To study and verify the truth table of logic gates.

COMPONENTS REQUIRED:

• Bread board trainer kit.

• Connecting patch chords.
• IC 7400, IC 7402, IC 7404, IC 7408, IC 7432, IC 7486, IC 74266.

THEORY:
Logic gates are the basic components in digital electronics. They are used to create digital
circuits and even complex integrated circuits. For example, complex integrated circuit may bring
already a complete circuit ready to be used - microprocessors and microcontrollers are the best
example - but inside them they were projected using several logic gates.
A gate is a digital electronic circuit having only one output but one or more inputs. The
output or a signal will appear at the output of the gate only for certain input-signal combinations.
There are many types of logic gates; such as AND, OR and NOT, which are usually called the three
basic gates. Other popular gates are the NAND and the NOR gates; which are simply combinations
of an AND or an OR gate with a NOT gate inserted just before the output signal. Other gates include
the XOR "Exclusive-OR" and the XNOR "Exclusive NOR" gates. All the logic gates used in the
exercises below are known as TTL (transistor-to-transistor) logic. These have the convenient
property that the output of any gate can be used directly as input to another gate. All these TTL
circuits are operated from a 5 V power supply, and the binary digits 0 and 1 are represented by low
and high voltages on the gate terminals.
Boolean algebra is a system of mathematical logic. It differs from both ordinary algebra and
the binary number system. Boolean algebra is formulated by a defined set of elements, together with
two binary operators ‘+’ and ‘.’ and unary operator ‘-‘.
LOGIC GATES:

AND gate:
INPUTS OUTPUT
A B X=A.B
0 0 0
0 1 0
1 0 0
1 1 1
Figure: 2 input AND Gate

The AND gate is an electronic circuit that gives a high output (1) only if all its inputs are
high. A dot (.) is used to show the AND operation i.e. A.B. Bear in mind that this dot is sometimes
omitted i.e. AB.

OR gate:

INPUTS OUTPUT
A B X=A+B
0 0 0
0 1 1
1 0 1
Figure: 2 input OR Gate 1 1 1

The OR gate is an electronic circuit that gives a high output (1) if one or more of its inputs
are high. A plus (+) is used to show the OR operation.

NOT gate :

OUTPUT
INPUT
A X=AI
0 0
0 1
Figure: NOT Gate
 The NOT gate is an electronic circuit that produces an inverted version of the input at its
output. It is also known as an inverter. If the input variable is A, the inverted output is known as NOT
A.
This is also shown as A', or A with a bar over the top, as shown at the outputs. The diagrams
below show two ways that the NAND logic gate can be configured to produce a NOT gate. It cannot
also be done using NOR logic gates in the same way.
A Logic Gate which can infer any of the gate among Logic Gates. NAND and NOR Gates
are called Universal Gates because all the other gates can be created by using these gates.

Universal Gates:

NAND gate
INPUTS OUTPUT
A B
X=
0 0 1
0 1 1
1 0 1
1 1 0
Figure: NAND Gate

This is a NOT-AND gate which is equal to an AND gate followed by a NOT gate. The
outputs of all NAND gates are high if any of the inputs are low. The symbol is an AND gate with a
small circle on the output. The small circle represents
INPUTS OUTPUT
inversion. A B X=
NOR gate 0 0 1
0 1 0
1 0 0
1 1 0

Figure: NOR Gate

This is a NOT-OR gate which is equal to an OR gate followed by a NOT gate. The outputs of
all NOR gates are low if any of the inputs are high. The symbol is an OR gate with a small circle on
the output. The small circle represents inversion.
EX-OR gate

INPUTS OUTPUT
A B
0 0 0
0 1 1

Figure: EX-OR Gate 1 0 1

1 1 0

The ex-or gate output is both inputs are equal then the output of the ex-or gate is low (0),
otherwise the ex-or gate output is high (1).

EX-OR gate
INPUTS OUTPUT
A B

0 0 1
0 1 0
1 0 0
1 1 1
Figure: EX-NOR Gate

The ex-nor gate output is both inputs are equal then the output of the ex-nor gate is high (1),
otherwise the ex-or gate output is low (0).
Pin diagrams of all the logic gates are:

XNOR GATE 74266

PROCEDURE:
1. Plug the chips into the breadboard. Point all the chips in the same direction with pin 1 at the
upper left corner. (Pin 1 is often identified by a dot or a notch next to it on the chip package).
2. Connect +5V and GND pins of each chip to the power and ground bus strips on the
breadboard.
3. Make the connections as per the circuit diagram.
4. Switch on VCC and apply various combinations of input according to truth table.
5. Note down the output readings for logic gates for different combinations of inputs.

RESULT:
All the truth tables of logic gates are verified by using IC’s

VIVA QUESTIONS:

1. What is a logic gate?

2. What are basic gates?

3. Which of the logical operations is represented by the sign ‘+’?

4. What is a truth table?

5. What is the maximum number of outputs a logic gate can have?

EXP NO: 2 DATE:

REALIZATION OF BOOLEAN EXPRESSIONS

AIM:
To design a simple combinational circuit with four variables and obtain minimal SOP
expression and verify the truth table

COMPONENTS REQUIRED:

• Bread board trainer kit.

• Connecting patch chords.
• IC 7408, IC 7432, IC 7404.
THEORY:
Simplification of Boolean functions is mainly used to reduce the gate count of a design. Less
number of gates means less power consumption, sometimes the circuit works faster and also when
number of gates is reduced, cost also comes down. There are many ways to simplify a logic design.
Sum of Products:
A sum of products expression consists of several product terms logically added. A product
term is a logical product of several variables. The variables may or may not be complemented. The
following are the examples of sum of products expressions.
1. XY+X'Y+XY'
2. AB+ABC+BC'
1. Simplify the following function using Boolean algebra rules
Z=∑(0,1,2,3,6,7,8,10)
Z= Á B́ Ć D́+ Á B́ Ć D+ Á B́ C D́+ Á B́ CD+ Á BC D́+ Á BCD+ A B́ Ć D́+ A B́ C D́
Z= Á B́ D́ ( Ć+C ) + Á B́ D ( Ć +C ) + Á BC ( D́+ D ) + A B́ D́ ( Ć+C)
Z= Á B́ D́+ Á B́ D+ Á BC + A B́ D́
Z= Á B́ ( D́+ D)+ Á BC + A B́ D́
Z= Á B́+ Á BC + A B́ D́
Z=B́ ( Á + A D́)+ Á BC
Z=B́ ( Á + D́)+ Á BC
Z= Á B́+ B́ D́+ Á BC
Z= Á ( B́+ BC )+ B́ D́
Z= Á ( B́+C)+ B́ D́
Z= Á B́+ Á C + B́ D́
Z= Á B́+ Á C + B́ D́
LOGIC DIAGRAM

TRUTH TABLE
Pin diagrams of 7404, 7408, 7432 ICs:

PROCEDURE:

1. Plug the chips into the breadboard. Point all the chips in the same direction with pin 1 at
the upper-left corner. (Pin 1 is often identified by a dot or a notch next to it on the chip
package).

2. Connect +5V and GND pins of each chip to the power and ground bus strips on the
breadboard.

3. Make the connections as per the circuit diagram.

4. Switch on VCC and apply various combinations of input according to truth table.

5. Note down the output readings for Boolean expression for different combinations of
inputs.

RESULT:
The Four variable Boolean expression are simplified and verified truth table using digital
IC’s.
Viva Questions:

1. What is a Boolean algebra?

2. What are the basic operations in Boolean algebra?

3. State De-Morgan’s Laws.

4. What is the use of De-Morgan’s theorem?

5. Why to reduce Boolean expressions before realizations?

EXP NO: 3 DATE:
3 TO 8 LINE DECODER
AIM:
To Verification of functional table of 3 to 8 line Decoder /De-multiplexer
.
COMPONENTS REQUIRED:
• Bread board trainer kit.
• Connecting patch chords.
• IC 74138.

THEORY:

A decoder is a multi-input, multi-output logic circuit which converts coded inputs into
coded outputs, where the input and output codes are different.
The encoded information is presented as n inputs producing 2n possible outputs. The 2n
output values are from 0 through 2n -1

74LS138 3 to 8 Decoder

The LS138 is a high speed 1-of-8 Decoder/Demultiplexer fabricated with the low power Schottky
barrier diode process. The decoder accepts three binary weighted inputs (A0, A1, A2) and when enabled
provides eight mutually exclusive active LOW Outputs (O0–O7). The LS138 features three Enable
inputs, two active LOW (E1, E2) and one active HIGH (E3). All outputs will be HIGH unless E1 and E2
are LOW and E3 is HIGH. This multiple enable function allows easy parallel expansion of the device to a
1-of-32 (5 lines to 32 lines) decoder with just four LS138s and one inverter. The LS138 can be used as an
8-output demultiplexer by using one of the active LOW Enable inputs as the data input and the other
Enable inputs as strobes. The Enable inputs which are not used must be permanently tied to their
appropriate active HIGH or active LOW state.
PIN DIAGRAM FOR 74138 IC

LOGIC SYMBOL

LOGIC DIAGRAM

TRUTH TABLE
PROCEDURE

1. Make the connections as per the circuit diagram.

2. Connect +5V and GND pins of each chip to the power and ground bus strips on the
breadboard.
3. Switch on VCC and apply various combinations of input according to truth table and
verify the Truth Table.

RESULT:
A combinational logic circuit of 3 to 8 line Decoder /De-multiplexer is designed and
verified the truth table.
VIVA QUESTIONS:

1. What is a Decoder?

2. How many types of decoders are there? Name them.

3. What are the applications of decoders?

EXP NO: 4 DATE:

 8*1 MULTIPLEXER
AIM:
To Verification of 4 variable logic function using 8 to 1 multiplexer
.
COMPONENTS REQUIRED:
• Bread board trainer kit.
• Connecting patch chords.
• IC 74151.
THEORY:
In digital systems, many times it is necessary to select single data line from several data-
input lines, and the data from the selected data line should be available on the output. It is a
digital switch. It allows digital information from several sources to be routed onto a single output
line.
The basic multiplexer has several data-input lines and a single output line. The selection
of particular input line is controlled by a set of selection lines. Since multiplexer selects one of
the input and routes it to output, it is also known as “data selector” .
Normally , there are 2n input lines and n selection lines whose bit combinations determine
which input is selected. Therefore, multiplexer is “many into one” and it provides the digital
equivalent of an analog selector switch.
74151 8 TO 1 MULTIPLEXER
The LS151 is a logical implementation of a single pole, 8-position switch with the switch
position controlled by the state of three Select inputs, S0, S1, S2. Both assertion and negation
outputs are provided. The Enable input (E) is active LOW. When it is not activated, the negation
output is HIGH and the assertion output is LOW regardless of all other inputs. The logic function
provided at the output is:

The LS151 provides the ability, in one package, to select from eight sources of
data or control information. By proper manipulation of the inputs, the LS151 can provide any
logic function of four variables and its negation.

LOGIC DIAGRAM
. TRUTH TABLE

PIN DIAGRAM
4 variable logic function using 8 to 1 multiplexer

PROCEDURE
 1. Make the connections as per the circuit diagram.
2. Connect +5V and GND pins of each chip to the power and ground bus strips on the
breadboard.
3. Switch on VCC and apply various combinations of input according to truth table and
verify the Truth Table.

RESULT:

A combinational circuit of 4 variable logic function using 8 to 1 Multiplexer (MUX) is

designed and verified.

VIVA QUESTIONS:

1. What is a multiplexer (MUX)?

2. How many types of multiplexing are there? Name them.

3. Why a multiplexer is called a data selector?

4. What are the applications of multiplexer?

EXP NO: 5 DATE:

 FULL ADDER

AIM:
To Design full adder circuit and verify its functional table.

COMPONENTS REQUIRED:

• Bread board trainer kit.

• Connecting patch chords.
• IC 7408, IC 7432, IC 7486.
THEORY:

Full-Adder: The half-adder does not take the carry bit from its previous stage into account. This
carry bit from its previous stage is called carry-in bit. A combinational logic circuit that adds two
data bits, A and B, and a carry-in bit, Cin , is called a full-adder.
The Boolean functions describing the full-adder are:
S = (A⊕ B) ⊕ Cin
C = AB+BCin +ACin
TRUTH TABLE
LOGIC DIAGRAM

PIN DIAGRAMS OF IC7408, IC7432, IC7486

PROCEDURE
1. Make the connections as per the circuit diagram for the half adder circuit, on the trainer
kit.
2. Switch on the VCC power supply and apply the various combinations of the inputs
according to the respective truth tables.
3. Note down the output readings for the half adder circuit for the corresponding
combination of inputs.
4. Verify that the outputs are according to the expected results.

RESULT:
A full adder circuit designed and verified its functional table by using various logic gate
ICs.

VIVA QUESTIONS:

1. What is a half-adder?

2. What is a full-adder?

3. What is a ripple-carry adder?

4. Distinguish between a half-adder and a full-adder.

EXP NO: 6 DATE:
FLIP-FLOPS

AIM:
To Verify the various flip-flops of functional tables of
(i) J K Edge triggered Flip –Flop
(ii) J K Master Slave Flip – Flop
(iii) D Flip -Flop.

COMPONENTS REQUIRED:

• Bread board trainer kit.

• Connecting patch chords.
• IC 7474, IC 7476
THEORY:

"Flip-flop" is the common name given to two-state devices which offer basic memory for
sequential logic operations. Flip-flops are heavily used for digital data storage and transfer and
are commonly used in banks called "register" for the storage of binary numerical data.

D FLIP-FLOP

1. The operations of a D flip-flop are much simpler.

2. It has only one input addition to the clock. It is very useful when a single data bit (0 or 1) is
to be stored.
3. If there is a HIGH on the D input when a clock pulse is applied, the flip-flop SETs and stores
a 1.
4. If there is a LOW on the D input when a clock pulse is applied, the flip-flop RESETs and
stores a 0.
5. To implement D flip-flop we require NAND gates and NOR gates.
LOGIC DIAGRAM
Graphical symbol

PIN DIAGRAM FOR 7474 IC

TRUTH TABLE

JK FLIP FLOP
 The J-K flip-flop works very similar to S-R flip-flop.

The only difference is that this flip-flop has NO invalid state.

LOGIC DIAGRAM

GRAPHICAL SYMBOL

TRUTH TABLE

J K Master Slave Flip – Flop

 The master slave flipflop was developed to make the synchronous operation more
predictable, i.e., to avoid the problems to logic race in clocked flipflops. A master-slave flipflop
is called a pulse triggered flipflop because the length of the time required for its output to change
state equals the width of one clock pulse.
Master-slave flip flop is designed using two separate flip flops. Out of these, one acts as
the master and the other as a slave. The control inputs are applied to the master flipflop and
maintained constant set up. There are three basic types of master slave flipflops- SR, D and JK is
most commonly availablr in IC form.
The Master-Slave Flip-Flop is basically two gated SR flip-flops connected together in a
series configuration with the slave having an inverted clock pulse. The outputs from Q and Q
from the “Slave” flip-flop are fed back to the inputs of the “Master” with the outputs of the
“Master” flip flop being connected to the two inputs of the “Slave” flip flop. The input signals J
and K are connected to the gated “master” SR flip flop which “locks” the input condition while
the clock (Clk) input is “HIGH” at logic level “1”. As the clock input of the “slave” flip flop is
the inverse (complement) of the “master” clock input, the “slave” SR flip flop does not toggle.
The outputs from the “master” flip flop are only “seen” by the gated “slave” flip flop when the
clock input goes “LOW” to logic level “0”. Then, the circuit accepts input data when the clock
signal is “HIGH”, and passes the data to the output on the falling-edge of the clock signal. In
other words, the Master-Slave JK Flip flop is a “Synchronous” device as it only passes data
with the timing of the clock signal.
LOGIC DIAGRAM

TRUTH TABLE
PIN DIAGRAM FOR 7476 IC

PROCEDURE

1. Make the connections as per the circuit diagram.

2. Connect +5V and GND pins of each chip to the power and ground bus strips on the
breadboard.
3. Switch on VCC and apply proper inputs of Flip-Flops.
4. Check the output on logic section.
5. Change the input and verify the truth tables

RESULT:
 Verified the truth tables of different flip flops like. (i) J K Edge triggered Flip –Flop (ii) J K
Master Slave Flip – Flop (iii) D Flip -Flop .

VIVA QUESTIONS:

1. Distinguish between combinational and sequential switching circuits.

2. What is a flip-flop?

3. What are the applications of flipflop?

4. what is meant by clocked flipflop?

5. What do you mean by toggling?

6. What is meant by race around condition in flipflops?

7. What is a master-slave flip-flop?

8. What do mean by clock slew?

9. What do mean by time race?

EXP NO: 7 DATE:

 4-BIT RING COUNTER
AIM:
To Design a four bit ring counter using D Flip – Flops / JK Flip Flop and verify output

COMPONENTS REQUIRED:

• Bread board trainer kit.

• Connecting patch chords.
• IC 7474, IC 7476

THEORY:
A digital counter is a set of flip-flops whose states change in response to pulses applied at
the input to the counter. The FFs are interconnected such that their combined state at any time is
the binary equivalent of the total number of pulses that have occurred upto that time. A counter is
used to count pulses. Shift register counters are obtained from serial-in, serial-out shift register
by providing feedback from the output of the last FF to input of the FF. These devices are called
counters. The most widely used shift register counter is the Ring Counter as well as Twisted
Ring Counter (Johnson Counter).
Ring counter is a basic register with direct feedback such that the contents of the register
simply circulate around the register when the clock is running. Here the last output that is QD in
a shift register is connected back to the serial input.
Pin Diagram of IC7474:

D-Flipflop:

Circuit Diagrams:
Logic Diagram of a 4 – bit ring counter using D-flip-flops:

TRUTH TABLE

PROCEDURE

1. Make the connections as per the circuit diagram.

2. Switch on the power supply.
3. Apply clock pulses for ring counter and note the outputs after each clock pulse.
4. Change the inputs for parity bit generator and verify the truth tables.
RESULT:

4- Bit Ring counter are designed and their truth table are verified using D-Flipflop.
VIVA QUESTIONS:

1. What is a ring counter?

2. What are the advantages of a ring counter?

3. What are shift register counters?

EXP NO: 8 DATE:

4-BIT JOHNSON COUNTER
AIM:
To Design a four bit Johnson’s counter using D Flip-Flops / JK Flip Flops and verify output

COMPONENTS REQUIRED:

• Bread board trainer kit.

• Connecting patch chords.
• IC 7474, IC 7404, IC 7476

THEORY:
A digital counter is a set of flip-flops whose states change in response to pulses applied at
the input to the counter. The FFs are interconnected such that their combined state at any time is
the binary equivalent of the total number of pulses that have occurred upto that time. A counter is
used to count pulses. Shift register counters are obtained from serial-in, serial-out shift register
by providing feedback from the output of the last FF to input of the FF. These devices are called
counters. The most widely used shift register counter is the Ring Counter as well as Twisted
Ring Counter (Johnson Counter).
Ring counter is a basic register with direct feedback such that the contents of the register
simply circulate around the register when the clock is running. Here the last output that is QD bar
is connected back to the serial input.
Pin Diagram of IC7474:

D-Flipflop:

Circuit Diagrams:
Logic Diagram of a 4 – bit Johnson counter using D-flip-flops:
TRUTH TABLE

PROCEDURE

1. Make the connections as per the circuit diagram.

2. Switch on the power supply.
3. Apply clock pulses for johnson counter and note the outputs after each clock pulse.
4. Change the inputs for parity bit generator and verify the truth tables.
RESULT:

4- Bit Johnson counter are designed and their truth table are verified using D-Flipflop.
VIVA QUESTIONS:

1. What is a twisted ring counter?

2. What are the advantages of a twisted ring counter?

3. What are shift register counters?

EXP NO: 9 DATE:

4-BIT UNIVERSAL SHIFT REGISTER
AIM:

To verify the operation of 4-bit Universal Shift Register for different Modes of operation.

COMPONENTS REQUIRED:

• Bread board trainer kit.

• Connecting patch chords.
• IC 74194
THEORY:
A register capable of shifting in one direction only is a unidirectional shift register. A
register capable of shifting in both directions is a bidirectional shift register. If the register has
both shifts (right shift and left shift) and parallel load capabilities, it is referred to as universal
shift register.
It consists of four flip-flops and four multiplexers. The four multiplexers have two
common selection inputs S1 and S0 and they select appropriate input for D flip-flop. The register
operation depending on the selection inputs of multiplexers.
When S1 S0 = 00, input 0 is selected and the present value of the register is applied to the
D inputs of the flip-flops. This results no change in the register value.
When S1 S0 =01, input 1 is selected and circuit connections are such that it operates as a
right shift register.
When S1 S0 =10, input 2 is selected and circuit connections are such that it operates as a
left shift register.
When S1 S0 =11, input 3 is selected the binary information on the parallel input lines is
transferred into the register simultaneously and it is a parallel load operation.

CIRCUIT DIAGRAM:
4 BIT UNIVERSAL SHIFT REGISTER
PIN DIAGRAM

TRUTH TABLE

PROCEDURE

1. Make the connections as per the circuit diagram.

 2. Switch on the power supply.
3. Apply selected lines and clock pulses for universal shift register and note the outputs after
each selected lines.

RESULT:

4-bit Universal Shift Register operation is verified for different Modes of operation.

EXP NO: 10 DATE:

MOD-8 RIPPLE COUNTER
AIM:
 To draw the circuit diagram of MOD-8 ripple counter and construct a circuit using T-Flip-
Flops and Test it with a low frequency clock and Sketch the output waveforms.

COMPONENTS REQUIRED:

• Bread board trainer kit.

• Connecting patch chords.
• IC 7476
THEORY
A group of flip-flops connected together forms a register. A register storing and shifting data
which is in the form of 1s and / or 0s, entered from an external source. It has no specific sequence of
states except in certain very specialized applications. A counter is a register capable of counting the
number of clock pulses arriving at its clock input. Count represents the number of clock pulses
arrived. On arrival of each clock pulse, the counter is incremented by one. In case down counter, it is
decremented by one.
The n-bit binary counter has n flip-flops and it has 2n distinct states of outputs. For example
2–bit counter has 2 flip flops and it has 22 distinct states: 00, 01, 10 and 11. If 3-bit counter has 3
flip-flops and it has 23 distinct states: 000, 001, 010, 011, 100, 101, 110 and 111. The maximum
count that the binary counter can count 2n - 1.
For example, in 2–bit binary counter, the maximum count is 22 -1 = 4-1 =3 (11 in binary).
After reaching the maximum count the counter resets to 0 on arrival of the next clock pulse and it
starts counting again.
RIPPLE COUNTER
A binary asynchronous / ripple counter consists of a series connection of complementing flip-
flops, with the output each flip-flop connected to the clock input of the next higher order flip-flop.
The total number of counts or stable states a counter can indicate is called modulus. The mod
8 counter goes through states 0 to 7.
The flip-flop holding the least significant bit receives the incoming clock pulses. A
complementing flip-flops can be obtained from a JK flip-flop. With J and K inputs tied together or a
from T flip-flop

CIRCUIT DIAGRAM FOR MOD 8 RIPPLE COUNTER

TRUTH TABLE

OUTPUT WAVEFORM

PROCEDURE

1. Make the connections as per the circuit diagram.

2. Switch on the power supply.
3. Apply clock pulses for mod-8 counter and note the outputs after each clock pulse.

RESULT:
Mod-8 ripple counter using T-Flipflop are designed and truth table is verified.

VIVA QUESTIONS:
 1. What is a counter?

2. What do you mean by state of the counter?

3. A mod-5 Asynchronous counter how many flipflops are required?

4. The minimum number of flipflops required for mod-12 ripple counter?

EXP NO: 11 DATE:

MOD-8 SNCHRONOUS COUNTER
AIM:
 To Design MOD – 8 synchronous counter using T Flip-Flop and verify the result and Sketch
the output waveforms

COMPONENTS REQUIRED:

• Bread board trainer kit.

• Connecting patch chords.
• IC 7476, IC 7408
THEORY
A group of flip-flops connected together forms a register. A register storing and shifting data
which is in the form of 1s and / or 0s, entered from an external source. It has no specific sequence of
states except in certain very specialized applications. A counter is a register capable of counting the
number of clock pulses arriving at its clock input. Count represents the number of clock pulses
arrived. On arrival of each clock pulse, the counter is incremented by one. In case down counter, it is
decremented by one.
The n-bit binary counter has n flip-flops and it has 2n distinct states of outputs. For example
2–bit counter has 2 flip flops and it has 22 distinct states: 00, 01, 10 and 11. If 3-bit counter has 3
flip-flops and it has 23 distinct states: 000, 001, 010, 011, 100, 101, 110 and 111. The maximum
count that the binary counter can count 2n - 1.
For example, in 2–bit binary counter, the maximum count is 22 -1 = 4-1 =3 (11 in binary).
After reaching the maximum count the counter resets to 0 on arrival of the next clock pulse and it
starts counting again.
SNCHRONOUS COUNTER
When counter is clocked such that each flip-flop in the counter is triggered at the same time,
the counter is called synchronous counter.
Here clock signal is connected in parallel to clock inputs of each flip-flop. But the Qa output
of first stage is used to drive the T input of the second stage
The flip-flop holding the least significant bit receives the incoming clock pulses. A
complementing flip-flops can be obtained from a JK flip-flop. With J and K inputs tied together or a
from T flip-flop.

CIRCUIT DIAGRAM FOR MOD 8 RIPPLE COUNTER

TRUTH TABLE

OUTPUT WAVEFORM

PROCEDURE

1. Make the connections as per the circuit diagram.

2. Switch on the power supply.
3. Apply clock pulses for mod-8 counter and note the outputs after each clock pulse.

RESULT:
Mod-8 synchronous counter using T-Flipflop are designed and truth table is verified.
VIVA QUESTIONS:
 1. What is a synchronous counter?

2. What do you mean by state of the counter?

3. A mod-5 synchronous counter how many flip-flops are required?

4. The minimum number of flip-flops required for mod-10 synchronous counter?

EXP NO: 12 DATE:

 1-BIT COMPARATOR
AIM:

To draw the circuit diagram of a single bit comparator and test the output

COMPONENTS REQUIRED:

• Bread board trainer kit.

• Connecting patch chords.
• IC 7404, IC 7408, IC 74266
THEORY
A comparator is a special combinational circuit designed primarily to compare the
relative magnitude of two binary numbers. It receives a two n-bit numbers A and B as inputs and
the outputs are A>B, A=B and A<B. depending upon the relative magnitudes of the two number,
one of the outputs will be high.

1-BIT COMPARATOR
TRUTH TABLE

LOGIC DIAGRAM
PIN DIAGRAMS OF IC 7404, IC 7408, IC74266

PROCEDURE
 1. Make the connections as per the circuit diagram.
2. Connect +5V and GND pins of each chip to the power and ground bus strips on the
breadboard.
3. Switch on VCC and apply proper inputs of comparator.
4. Check the output on logic section.
5. Change the input and verify the truth tables

RESULT:

1-bit comparator are designed and verified the truth table.