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LM3241
SNOSB38C – JANUARY 2009 – REVISED NOVEMBER 2017

LM3241 6-MHz, 750-mA Miniature, Adjustable, Step-Down DC-DC Converter for RF Power
Amplifiers
1 Features 3 Description
•
1 6-MHz (typ.) PWM Switching Frequency The LM3241 is a DC-DC converter optimized for
powering RF power amplifiers (PAs) from a single
• Operates from a Single Li-Ion Cell (2.7 V to 5.5 V) Lithium-Ion cell. The device can also be used in many
• Adjustable Output Voltage (0.6 V to 3.4 V) other applications. The device steps down an input
• 750-mA Maximum Load Capability voltage from 2.7 V to 5.5 V to an adjustable output
• High Efficiency (95% typ. at 3.9 VIN, 3.3 VOUT at voltage from 0.6 V to 3.4 V. The output voltage is set
using a VCON analog input for controlling power
500 mA)
levels and efficiency of the RF PA.
• Automatic Eco-mode™ and PWM Mode Change
The LM3241 offers three modes of operation. In
• 6-Bump DSBGA Package PWM mode the device operates at a fixed frequency
• Current Overload Protection of 6 MHz (typical) which minimizes RF interference
• Thermal Overload Protection when driving medium-to-heavy loads. At light-load
• Soft Start Function conditions, the device enters into Eco-mode
automatically and operates with reduced switching
• CIN and COUT are 0402 (1005) Case Size and 6.3 frequency. In Eco-mode, the quiescent current is
V of Rated-Voltage Ceramic Capacitor reduced and extends the battery life. Shutdown mode
• Small Chip Inductor in 0805 (2012) Case Size turns the device off and reduces battery consumption
to 0.1 µA (typical).
2 Applications The LM3241 is available in a 6-bump lead-free
• Battery-Powered 3G and 4G Power Amplifiers DSBGA package. A high-switching frequency (6
MHz) allows use of tiny surface-mount components.
• Hand-Held Radios
Only three small external surface-mount components,
• RF PC Cards an inductor and two ceramic capacitors are required.
• Battery-Powered RF Devices
Device Information(1)
PART NUMBER PACKAGE BODY SIZE (NOM)
LM3241 DSBGA (6) 1.50 mm × 1.30 mm
(1) For all available packages, see the orderable addendum at
the end of the data sheet.

Typical Application
VIN
2.7 V to 5.5 V

VOUT
VIN 0.47 µH 0.6 V to 3.4 V
SW
10 F EN VOUT = 2.5 × VCON
LM3241 FB
VCON
4.7 F
GND

Copyright © 2017, Texas Instruments Incorporated

An IMPORTANT NOTICE at the end of this data sheet addresses availability, warranty, changes, use in safety-critical applications,
intellectual property matters and other important disclaimers. PRODUCTION DATA.
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Table of Contents
1 Features .................................................................. 1 7.4 Device Functional Modes........................................ 15
2 Applications ........................................................... 1 8 Application and Implementation ........................ 16
3 Description ............................................................. 1 8.1 Application Information............................................ 16
4 Revision History..................................................... 2 8.2 Typical Application ................................................. 16
5 Pin Configuration and Functions ......................... 3 9 Power Supply Recommendations...................... 19
6 Specifications......................................................... 4 10 Layout................................................................... 19
6.1 Absolute Maximum Ratings ...................................... 4 10.1 Layout Guidelines ................................................. 19
6.2 ESD Ratings.............................................................. 4 10.2 Layout Example .................................................... 21
6.3 Recommended Operating Conditions....................... 4 11 Device and Documentation Support ................. 22
6.4 Thermal Information .................................................. 4 11.1 Documentation Support ........................................ 22
6.5 Electrical Characteristics........................................... 5 11.2 Receiving Notification of Documentation Updates 22
6.6 System Characteristics ............................................. 6 11.3 Community Resources.......................................... 22
6.7 Typical Characteristics .............................................. 7 11.4 Trademarks ........................................................... 22
7 Detailed Description ............................................ 12 11.5 Electrostatic Discharge Caution ............................ 22
7.1 Overview ................................................................. 12 11.6 Glossary ................................................................ 22
7.2 Functional Block Diagram ....................................... 13 12 Mechanical, Packaging, and Orderable
7.3 Feature Description................................................. 13 Information ........................................................... 22

4 Revision History
NOTE: Page numbers for previous revisions may differ from page numbers in the current version.

Changes from Revision B (April 2013) to Revision C Page

• Added the Device Information table, ESD Ratings table, Feature Description section, Device Functional Modes
section, Application and Implementation section, Power Supply Recommendations section, Layout section, Device
and Documentation Support section, and Mechanical, Packaging, and Orderable Information section ............................... 1
• Deleted the maximum lead temperature parameter from the Absolute Maximum Ratings table........................................... 4
• Changed the minimum TJ and TA from –30°C to –40°C in the Recommended Operating Conditions table ......................... 4
• Added the Thermal Information table ..................................................................................................................................... 4
• Added maximum values for VOUT step rise and fall times under –40°C to 85°C TA range in the System
Characteristics table ............................................................................................................................................................... 6
• Added maximum value for turnon time under –40°C to 85°C TA range in the System Characteristics table ........................ 6

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5 Pin Configuration and Functions

YZR Package With 0.5 mm Pitch

6-Pin DSBGA
Top View
1 2

A EN VIN

B VCON SW

C FB GND

Not to scale

Pin Functions
PIN
TYPE DESCRIPTION
NO. NAME
Enable Input. Set this digital input high for normal operation. For shutdown, set low. Do not
A1 EN I
leave EN pin floating.
A2 VIN PWR Power supply input. Connect to the input filter capacitor (see Figure 29).
Voltage Control Analog input. VCON controls VOUT in PWM mode. Do not leave VCON pin
B1 VCON I
floating. VOUT = 2.5 × VCON.
Switching Node connection to the internal PFET switch and NFET synchronous rectifier.
B2 SW PWR Connect to an inductor with a saturation current rating that exceeds the maximum Switch
Peak Current Limit specification of the LM3241.
C1 FB I Feedback Analog Input. Connect to the output at the output inductor.
C2 GND — Ground

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6 Specifications
6.1 Absolute Maximum Ratings
(1) (2)
See and .
MIN MAX UNIT
VIN to GND –0.2 6
Pin voltage V
EN, FB, VCON, SW (GND − 0.2) (VIN + 0.2) (3)
Continuous power dissipation (4) Internally limited
Junction temperature, TJ-MAX 150 °C
Storage temperature, Tstg –65 150 °C

(1) Stresses beyond those listed under Absolute Maximum Ratings may cause permanent damage to the device. These are stress ratings
only, which do not imply functional operation of the device at these or any other conditions beyond those indicated under Recommended
Operating Conditions. Exposure to absolute-maximum-rated conditions for extended periods may affect device reliability.
(2) All voltages are with respect to the potential at the GND pins.
(3) All pins are limited to the 6-V maximum stated for the VIN supply.
(4) Internal thermal shutdown circuitry protects the device from permanent damage. Thermal shutdown engages at TJ = 150°C (typ.) and
disengages at TJ = 125°C (typical).

6.2 ESD Ratings

VALUE UNIT
(1) (2)
Electrostatic Human-body model (HBM), per ANSI/ESDA/JEDEC JS-001 2000
V(ESD) V
discharge Charged-device model (CDM), per JEDEC specification JESD22-C101 (3) 1250

(1) JEDEC document JEP155 states that 500-V HBM allows safe manufacturing with a standard ESD control process.
(2) The human body model is a 100-pF capacitor discharged through a 1.5-kΩ resistor into each pin. (MIL-STD-883 3015.7).
(3) JEDEC document JEP157 states that 250-V CDM allows safe manufacturing with a standard ESD control process.

6.3 Recommended Operating Conditions

(1)
See .
MIN NOM MAX UNIT
Input voltage 2.7 5.5 V
Recommended load current 0 750 mA
TJ Junction temperature –40 125 °C
TA Ambient temperature (2) –40 85 °C

(1) All voltages are with respect to the potential at the GND pins.
(2) In applications where high power dissipation and/or poor package thermal resistance is present, the maximum ambient temperature may
have to be de-rated. Maximum ambient temperature (TA-MAX) is dependent on the maximum operating junction temperature (TJ-MAX-OP =
125°C), the maximum power dissipation of the device in the application (PD-MAX), and the junction-to ambient thermal resistance of the
part/package in the application (RθJA), as given by the following equation: TA-MAX = TJ-MAX-OP – (RθJA × PD-MAX).

6.4 Thermal Information

LM3241
THERMAL METRIC (1) YZR (DSBGA) UNIT
6 PINS
RθJA Junction-to-ambient thermal resistance 117 °C/W
RθJC(top) Junction-to-case (top) thermal resistance 1 °C/W
RθJB Junction-to-board thermal resistance 32.5 °C/W
ψJT Junction-to-top characterization parameter 0.2 °C/W
ψJB Junction-to-board characterization parameter 32.6 °C/W
RθJC(bot) Junction-to-case (bottom) thermal resistance — °C/W

(1) For more information about traditional and new thermal metrics, see the Semiconductor and IC Package Thermal Metrics application
report.

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6.5 Electrical Characteristics

All voltages are with respect to the potential at the GND pins. Minimum (MIN) and maximum (MAX) limits are specified by
design, test, or statistical analysis. For performance over the input voltage range and closed-loop results, see the curves in
the Typical Characteristics section.
PARAMETER TEST CONDITIONS MIN TYP MAX UNIT
PWM mode, VCON = 0.24 V 0.6
Feedback voltage at
VFB,MIN PWM mode, open loop conditions at VIN = 3.6 V, V
minimum setting 0.58 0.62
VCON = 0.24 V
PWM mode, VCON = 1.36 V, VIN = 3.9 V 3.4
Feedback voltage at
VFB,MAX PWM mode, open loop conditions at VIN = 3.6 V, V
maximum setting 3.332 3.468
VCON = 1.36 V, VIN = 3.9 V
EN = SW = VCON = 0 V (1) 0.1
ISHDN Shutdown supply current open loop conditions at VIN = 3.6 V, µA
2
EN = SW = VCON = 0 V (1)
PWM mode, No switching (2), VCON = 0 V,
620
FB = 1 V
IQ_PWM PWM mode quiescent current µA
PWM mode, open loop conditions at VIN = 3.6 V,
750
No switching (2), VCON = 0 V, FB = 1 V
Eco-mode, No switching (2),
45
VCON = 0.8 V, FB = 2.05 V
IQ_ECO Eco-mode quiescent current µA
Eco-mode, open loop conditions at VIN = 3.6 V,
60
No switching (2), VCON = 0.8 V, FB = 2.05 V
VIN = VGS = 3.6 V, ISW = 200 mA 160
RDSON (P) Pin-pin resistance for PFET Open loop conditions at VIN = 3.6 V, mΩ
250
VIN = VGS = 3.6 V, ISW = 200 mA
VIN = VGS = 3.6 V, ISW = −200 mA 110
RDSON (N) Pin-pin resistance for NFET Open loop conditions at VIN = 3.6 V, mΩ
200
VIN = VGS = 3.6 V, ISW = −200 mA
PFET switch peak current 1450
ILIM mA
limit (3) Open loop conditions at VIN = 3.6 V 1300 1600
6
FOSC Internal oscillator frequency MHz
Open loop conditions at VIN = 3.6 V 5.7 6.3
VIH EN Logic high input threshold Open loop conditions at VIN = 3.6 V 1.2 V
VIL EN Logic low input threshold Open loop conditions at VIN = 3.6 V 0.4 V
Gain VCON to VOUT gain 0.24 V ≤ VCON ≤ 1.36 V 2.5 V/V
ICON VCON pin leakage current Open-loop mode, VCON = 1 V ±1 µA

(1) Shutdown current includes leakage current of PFET.

(2) IQ specified here is when the part is not switching under test mode conditions. For operating quiescent current at no load, see the curves
in the Typical Characteristics section.
(3) Current limit is built-in, fixed, and not adjustable.

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6.6 System Characteristics

The following spec table entries are specified by design providing the component values in Figure 29 are used. These
parameters are not verified by production testing. Minimum (MIN) and maximum (MAX) values apply over the full operating
ambient temperature range (–40°C ≤ TA ≤ 85°C) and over the VIN range of 2.7 V to 5.5 V unless otherwise specified. L = 0.47
µH, DCR = 50 mΩ, CIN = 10 µF, 6.3 V, 0603 (1608), COUT = 4.7 µF, 6.3 V, 0603 (1608).
PARAMETER TEST CONDITIONS MIN TYP MAX UNIT
VIN = 3.6 V, VCON = 0.24 V to 1.36 V,
VCON TR = 1 µs, RLOAD = 10 Ω, 25
VOUT step rise time from 0.6 V to 3.4 V –30°C ≤ TA ≤ 85°C
(to reach 3.26 V)
VIN = 3.6 V, VCON = 0.24 V to 1.36 V,
30
VCON TR = 1 µs, RLOAD = 10 Ω
TCON TR µs
VIN = 3.6 V, VCON = 1.36 V to 0.24 V,
VCON TF = 1 µs, RLOAD = 10 Ω, 25
VOUT step fall time from 3.4 V to 0.6 V –30°C ≤ TA ≤ 85°C
(to reach 0.74 V)
VIN = 3.6 V, VCON = 1.36 V to 0.24 V,
30
VCON TF = 1 µs, RLOAD = 10 Ω
D Maximum Duty cycle 100%
IOUT Maximum output current capability 2.7 V ≤ VIN ≤ 5.5 V, 0.24 V ≤ VCON ≤ 1.36 V 750 mA
CCON VCON input capacitance VCON = 1 V, Test frequency = 100 KHz 5 10 pF
–3% 3%
Linearity Linearity in control range 0.24 V to 1.36 V Monotronic in nature (1)
–50 +50 mV
EN = Low-to-High, VIN = 4.2 V, VOUT = 3.4 V,
Turnon time (time for output to reach 50
IOUT = < 1 mA, COUT = 4.7 µF, –30°C ≤ TA ≤ 85°C
TON 95% final value after Enable low-to-high µs
transition) EN = Low-to-High, VIN = 4.2 V, VOUT = 3.4 V,
55
IOUT = < 1 mA, COUT = 4.7 µF
VIN = 3.6 V, VOUT = 0.8 V, IOUT = 10 mA,
75%
Eco-mode
VIN = 3.6 V, VOUT = 1.8 V, IOUT = 200 mA,
η Efficiency 90%
PWM mode
VIN = 3.9 V, VOUT = 3.3 V, IOUT = 500 mA,
95%
PWM mode
VIN = 3.6 V to 4.2 V, TR = TF = 10 µs,
LINE TR Line transient response 50
IOUT = 100 mA, VOUT = 0.8 V
mVpk
VIN = 3.1 V/3.6 V/4.5 V, VOUT = 0.8 V,
LOAD TR Load transient response 50
IOUT = 50 mA to 150 mA, TR = TF = 0.1 µs

(1) Linearity limits are ±3% or ±50 mV whichever is larger.

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6.7 Typical Characteristics

VIN = EN = 3.6 V and TA = 25°C, unless otherwise noted.

SW = VCON = EN = 0 V No switching FB = 1 V VCON = 0 V

Figure 1. Shutdown Current vs Temperature Figure 2. Quiescent Current vs Supply Voltage

Closed loop Switching No load VOUT = 2 V IOUT = 200 mA

Figure 3. Eco-mode Supply Current vs Output Voltage Figure 4. Switching Frequency vs Temperature
2.006 3.46
3.45
2.004
TA = -30°C 3.44
VIN = 3.9V
OUTPUT VOLTAGE (V)

OUTPUT VOLTAGE (V)

TA = +25°C 3.43
2.002
3.42
VIN = 3.6V
2.000 3.41
3.40
1.998
3.39
TA = +85°C VIN = 4.2V
3.38
1.996
3.37
1.994 3.36
2.5 3.0 3.5 4.0 4.5 5.0 5.5 6.0 0 100 200 300 400 500 600 700 800

SUPPLY VOLTAGE (V) OUTPUT CURRENT (mA)

VOUT = 2 V RLOAD = 10 Ω VOUT = 3.4 V

Figure 5. Output Voltage vs Supply Voltage Figure 6. Output Voltage vs Output Current

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Typical Characteristics (continued)

VIN = EN = 3.6 V and TA = 25°C, unless otherwise noted.
0.63 2.03

0.62 2.02
OUTPUT VOLTAGE (V)

OUTPUT VOLTAGE (V)

ECO to PWM
ECO to PWM
0.61 2.01

0.60 2.00

PWM to ECO PWM to ECO

0.59 1.99

0.58 1.98
0 25 50 75 100 125 150 0 25 50 75 100 125 150

OUTPUT CURRENT (mA) OUTPUT CURRENT (mA)

VOUT = 0.6 V VOUT = 2 V

Figure 7. Output Voltage vs Output Current Figure 8. Output Voltage vs Output Current

Figure 9. ECO-PWM Mode Threshold Current vs Output Figure 10. PWM-Eco-Mode Threshold Current vs Output
voltage voltage
100
VIN = 3.6V
VIN = 3.0V
95
EFFICIENCY (%)

90

85

VIN = 4.2V
80

75

70
0 100 200 300 400 500 600 700 800

OUTPUT CURRENT(mA)
VOUT = 2 V VOUT = 2 V

Figure 11. Closed-loop Current Limit vs Temperature Figure 12. Efficiency vs Output Current

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Typical Characteristics (continued)

VIN = EN = 3.6 V and TA = 25°C, unless otherwise noted.
100 100
VIN = 3.6V
VIN = 3.0V
95 95
VIN = 3.6V
90
EFFICIENCY (%)

EFFICIENCY (%)
90
VIN = 4.2V 85
85 VIN = 3.9V
80
80
75 VIN = 4.2V

75 70

70 65
0 100 200 300 400 500 600 700 800 0.5 1.0 1.5 2.0 2.5 3.0 3.5

OUTPUT CURRENT(mA) OUTPUT VOLTAGE (V)

VOUT = 3.3 V RLOAD = 10 Ω

Figure 13. Efficiency vs Output Current Figure 14. Efficiency vs Output Voltage

Figure 15. PFET RDSON vs Supply Voltage Figure 16. NFET RDSON vs Supply Voltage

RLOAD = 10 Ω 100% Duty Cycle

Figure 17. Low VCON Voltage vs Output Voltage Figure 18. VIN-VOUT vs Output Current

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Typical Characteristics (continued)

VIN = EN = 3.6 V and TA = 25°C, unless otherwise noted.

VOUT = 2 V IOUT = 200 mA

Figure 19. EN High Threshold vs Supply Voltage Figure 20. Output Voltage Ripple in PWM Mode

VOUT = 2 V IOUT = 50 mA VIN = 3.6 V/4.2 V VOUT = 0.8 V RLOAD = 8 Ω

Figure 21. Output Voltage Ripple in Eco-Mode Figure 22. Line Transient Response

VOUT = 2.5 V IOUT = 10 mA/250 mA VOUT = 0.6 V IOUT = 10 mA/60 mA

Figure 23. Load Transient Response Figure 24. Load Transient Response

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Typical Characteristics (continued)

VIN = EN = 3.6 V and TA = 25°C, unless otherwise noted.

VIN = 4.2 V VOUT = 3.4 V RLOAD = 3.6 kΩ VIN = 4.2 V VOUT = 3.4 V RLOAD = 10 kΩ

Figure 25. Startup Figure 26. Shutdown

VOUT = 2 V RLOAD = 10 Ω

Figure 27. Timed Current Limit

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7 Detailed Description

7.1 Overview
The LM3241 is a simple, step-down DC-DC converter optimized for powering RF power amplifiers (PAs) in
mobile phones, portable communicators, and similar battery-powered RF devices. The device is designed to
allow the RF PA to operate at maximum efficiency over a wide range of power levels from a single Li-Ion battery
cell. The design is based on a voltage-mode buck architecture, with synchronous rectification for high efficiency.
The device is designed for a maximum load capability of 750 mA in PWM mode. Maximum load range may vary
from this depending on input voltage, output voltage, and the inductor chosen.
Three modes of operation are available depending on the current required: pulse width modulation (PWM), Eco-
mode (economy mode), and shutdown. The LM3241 operates in PWM mode at higher load-current conditions.
Lighter loads cause the device to automatically switch into Eco-mode. Shutdown mode turns off the device and
reduces battery consumption to 0.1 µA (typical).
Precision of the DC PWM-mode output voltage is ±2% for 3.4 VOUT. Efficiency is around 95% (typical) for a 500-
mA load with a 3.3-V output and 3.9-V input. The output voltage is dynamically programmable from 0.6 V to 3.4
V by adjusting the voltage on the control pin (VCON) without the need for external feedback resistors. This
feature ensures longer battery life by being able to change the PA supply voltage dynamically depending on its
transmitting power.
Additional features include current overload protection and thermal overload shutdown.
The LM3241 is constructed using a chip-scale, 6-bump DSBGA package. This package offers the smallest
possible size for space-critical applications, such as cell phones, where board area is an important design
consideration. Use of a high switching frequency (6 MHz, typical) reduces the size of external components. As
shown in Figure 29, only three external power components are required for implementation. Use of a DSBGA
package requires special design considerations for implementation (for more information see the DSBGA
Package Assembly and Use section.) The fine-bump pitch of the package requires careful board design and
precision assembly equipment. Use of this package is best suited for opaque-case applications, where its edges
are not subject to high-intensity ambient red or infrared light. Also, the system controller should set EN low during
power-up and other low supply voltage conditions (see the Shutdown Mode section).

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7.2 Functional Block Diagram

EN VIN

ECO
COMPARATOR

OLP

Ref1

OVERVOLTAGE
DETECTOR
VCON

DELAY

PWM
COMPARATOR CONTROL LOGIC DRIVER
ERROR
AMP
FB SW

RAMP
GENERATOR
NCP

EN Ref2

OSCILLATOR
Ref3
LIGHT-LOAD
OUTPUT SHORT THERMAL CHECK COMP
PROTECTION SHUTDOWN

GND
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7.3 Feature Description

7.3.1 Circuit Operation
Referring to Figure 29 and the Functional Block Diagram, the LM3241 operates as follows. During the first part of
each switching cycle, the control block in the LM3241 turns on the internal, top-side PFET switch. This allows
current to flow from the input through the inductor to the output filter capacitor and load. The inductor limits the
current to a ramp with a slope of around (VIN – VOUT) / L, by storing energy in a magnetic field. During the second
part of each cycle, the controller turns the PFET switch off, blocking current flow from the input, and then turns
the bottom-side NFET synchronous rectifier on. In response, the magnetic field of the inductor collapses,
generating a voltage that forces current from ground through the synchronous rectifier to the output filter
capacitor and load. As the stored energy is transferred back into the circuit and depleted, the inductor current
ramps down with a slope around VOUT / L. The output filter capacitor stores charge when the inductor current is
high, and releases it when low, smoothing the voltage across the load.
The output voltage is regulated by modulating the PFET switch-on time to control the average current sent to the
load. The effect is identical to sending a duty-cycle modulated rectangular wave formed by the switch and
synchronous rectifier at SW to a low-pass filter formed by the inductor and output filter capacitor. The output
voltage is equal to the average voltage at the SW pin.

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Feature Description (continued)

7.3.2 Internal Synchronization Rectification
While in PWM mode, the LM3241 uses an internal NFET as a synchronous rectifier to reduce rectifier forward
voltage drop and associated power loss. Synchronous rectification provides a significant improvement in
efficiency whenever the output voltage is relatively low compared to the voltage drop across an ordinary rectifier
diode.
With medium and heavy loads, the NFET synchronous rectifier is turned on during the inductor current-down
slope in the second part of each cycle. The synchronous rectifier is turned off prior to the next cycle. The NFET
is designed to conduct through its intrinsic body diode during transient intervals before it turns on, eliminating the
need for an external diode.

7.3.3 Current Limiting

The current limit feature allows the LM3241 to protect itself and external components during overload conditions.
In PWM mode, the cycle-by-cycle current limit is 1450 mA (typical). If an excessive load pulls the output voltage
down to less than 0.3 V (typical), the NFET synchronous rectifier is disabled, and the current limit is reduced to
530 mA (typical). Moreover, when the output voltage becomes less than 0.15 V (typical), the switching frequency
decreases to 3 MHz, thereby preventing excess current and thermal stress.

7.3.4 Dynamically Adjustable Output Voltage

The LM3241 features dynamically adjustable output voltage to eliminate the need for external feedback resistors.
The output voltage can be set from 0.6 V to 3.4 V by changing the voltage on the analog VCON pin. This feature
is useful in PA applications where peak power is needed only when the handset is far away from the base station
or when data is being transmitted. In other instances the transmitting power can be reduced. Therefore the
supply voltage to the PA can be reduced, promoting longer battery life. For more information, see the Setting the
Output Voltage in the Application and Implementation section. The LM3241 moves into Pulse Skipping mode
when the duty cycle is over approximately 92% or less than approximately 15%, and the output voltage ripple
increases slightly.

7.3.5 Thermal Overload Protection

The LM3241 has a thermal overload protection function that operates to protect itself from short-term misuse and
overload conditions. When the junction temperature exceeds around 150°C, the device inhibits operation. Both
the PFET and the NFET are turned off. When the temperature drops below 125°C, normal operation resumes.
Prolonged operation in thermal overload conditions may damage the device and is considered bad practice.

7.3.6 Soft Start

The LM3241 has a soft-start circuit that limits in-rush current during startup. During startup the switch current limit
is increased in steps. Soft start is activated if EN goes from low to high after VIN reaches 2.7 V.

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7.4 Device Functional Modes

7.4.1 PWM Mode Operation
While in PWM mode operation, the converter operates as a voltage-mode controller with input voltage feed
forward. This operation allows the converter to achieve excellent load and line regulation. The DC gain of the
power stage is proportional to the input voltage. To eliminate this dependence, feed forward inversely
proportional to the input voltage is introduced. While in PWM mode, the output voltage is regulated by switching
at a constant frequency and then modulating the energy per cycle to control power to the load. At the beginning
of each clock cycle the PFET switch is turned on and the inductor current ramps up until the comparator trips
and the control logic turns off the switch. The current-limit comparator can also turn off the switch in case the
current limit of the PFET is exceeded. Then the NFET switch is turned on and the inductor current ramps down.
The next cycle is initiated by the clock turning off the NFET and turning on the PFET.

7.4.2 Eco-mode™ Operation

At very light loads (50 mA to 100 mA), the LM3241 enters Eco-mode operation with reduced switching frequency
and supply current to maintain high efficiency. During Eco-mode operation, the LM3241 positions the output
voltage slightly higher (+7 mV typical) than the normal output voltage during PWM mode operation, allowing
additional headroom for voltage drop during a load transient from light to heavy load.

Eco-modeΠat Light Load

High ECO Threshold

Load current increases

Target Output Voltage

Low ECO Threshold

PWM Mode at Heavy Load

Figure 28. Operation in Eco-mode and Transfer to PWM Mode

7.4.3 Shutdown Mode

Setting the EN digital pin low (<0.4 V) places the LM3241 in shutdown mode (0.1 µA typical). During shutdown,
the PFET switch, the NFET synchronous rectifier, reference voltage source, control and bias circuitry of the
LM3241 are turned off. Setting the EN pin high (>1.2 V) enables normal operation. The EN pin should be set low
to turn off the LM3241 during power-up and undervoltage conditions when the power supply is less than the 2.7-
V minimum operating voltage. The LM3241 has an undervoltage-lockout (UVLO) comparator to turn off the
power device in the case the input voltage or battery voltage is too low. The typical UVLO threshold is around 2.0
V for lock and 2.1 V for release.

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8 Application and Implementation

NOTE
Information in the following applications sections is not part of the TI component
specification, and TI does not warrant its accuracy or completeness. TI’s customers are
responsible for determining suitability of components for their purposes. Customers should
validate and test their design implementation to confirm system functionality.

8.1 Application Information

The LM3241 is a synchronous step-down converter in which output voltage is adjusted by a controlled voltage.
The following section discusses the design of the external components to complete the power supply design for
several input and output voltage options by using typical applications as a reference.

8.2 Typical Application

VIN
2.7 V to 5.5 V

C1 L1 VOUT
10 F VIN 0.47 µH 0.8 V
EN SW
EN VOUT = 2.5 × VCON
VCON LM3241
0.32 V FB
VCON C2
4.7 F
GND

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Figure 29. LM3241 Typical Application Schematic

8.2.1 Design Requirements

For this design example, use the parameters listed in Table 1.

Table 1. Design Parameters

DESIGN PARAMETER EXAMPLE VALUE
Input voltage 2.7 V to 5.5 V
Output voltage 0.8 V
Maximum current 750 mA

8.2.2 Detailed Design Procedure

Table 2 lists the component descriptions for Figure 29.

Table 2. List of Components

REFERENCE DESCRIPTION MANUFACTURER
C1 10 μF, Ceramic capacitor, 6.3 V, X5R, size 0603, GRM188R60J106ME47D Murata
C2 4.7 μF, Ceramic capacitor, 6.3 V, X5R, size 0603, GRM188R71H472KA01D Murata
L1 0.47 μH, Fixed Inductor, 1.6 A, size 0806, LQM2MPNR47NG0L Murata

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8.2.2.1 Setting the Output Voltage

The LM3241 features a pin-controlled adjustable output voltage to eliminate the need for external feedback
resistors. The output voltage can be programmed for an output voltage from 0.6 V to 3.4 V by setting the voltage
on the VCON pin, as shown in Equation 1.
VOUT = 2.5 × VCON (1)
When the VCON voltage is between 0.24 V and 1.36 V, the output voltage follows proportionally by 2.5 times of
VCON.
If the VCON voltage is less than 0.24 V (VOUT = 0.6 V), the output voltage may be regulated (for details see
Figure 17). Figure 17 exhibits the characteristics of a typical part, and the performance cannot be ensured as a
part-to-part variation could occur for output voltages less than 0.6 V. For VOUT lower than 0.6 V, the converter
could suffer from larger output ripple voltage and higher current limit operation.

8.2.2.2 Inductor Selection

Two main considerations must be considered when choosing an inductor: the inductor should not saturate, and
the inductor current ripple should be small enough to achieve the desired output voltage ripple. Different
manufacturers follow different saturation current rating specifications, so attention must be given to details.
Saturation current ratings are typically specified at 25°C so ratings over the ambient temperature of application
should be requested from manufacturer.
The minimum value of inductance to ensure good performance is 0.3 µH at bias current (ILIM, typical) over the
ambient temperature range. Shielded inductors radiate less noise and should be preferred. Two methods are
avaialble to choose the inductor saturation current rating.

8.2.2.2.1 Method 1
The saturation current should be greater than the sum of the maximum load current and the worst case average
to peak inductor current. Use Equation 2 to find the saturation current (ISAT).
ISAT > IOUT_MAX + IRIPPLE
where
• IOUT_MAX is the maximum load current (750 mA).
• IRIPPLE is the average-to-peak inductor current. Use Equation 3 to calculate the IRIPPLE value. (2)
§ VIN VOUT · § VOUT · § 1 ·
IRIPPLE ¨ ¸u¨ ¸u¨ ¸
© 2 u L ¹ © VIN ¹ © f ¹
where
• VIN is the maximum input voltage in application.
• VOUT is the output voltage
• L is the minimum inductor value including worst-case tolerances (30% drop can be considered for Method 1)
• f is the minimum switching frequency (5.7 MHz) (3)

8.2.2.2.2 Method 2
A more conservative and recommended approach is to choose an inductor that can support the maximum
current limit of 1600 mA.
The resistance of the inductor should be less than approximately 0.1 Ω for good efficiency. Table 3 lists
recommended inductors and suppliers.

Table 3. Recommended Inductors

Model Size (W x L x H) (mm) Vendor
MIPSZ2012D0R5 2.0 x 1.2 x 1.0 FDK
LQM21PNR54MG0 2.0 x 1.25 x 0.9 Murata
LQM2MPNR47NG0 2.0 x 1.6 x 0.9 Murata

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8.2.2.3 Capacitor Selection

The LM3241 is designed for use with ceramic capacitors for its input and output filters. Use a 10-µF ceramic
capacitor for the input and a 4.7-µF ceramic capacitor for the output. The capacitors should maintain at least
50% capacitance at DC bias and temperature conditions. Ceramic capacitors type such as X5R, X7R, and B are
recommended for both filters. These types provide an optimal balance between small size, cost, reliability, and
performance for cell phones and similar applications. Table 4 lists some recommended part numbers and
suppliers. DC bias characteristics of the capacitors must be considered when selecting the voltage rating and
case size of the capacitor. For CIN, use of an 0805 (2012) size may also be considered if room is available on the
system board.

Table 4. Recommended Capacitors

Capacitance, Voltage Rating, Case Size Model Vendor
4.7 µF, 6.3 V, 0603 C1608X5R0J475M TDK
4.7 µF, 6.3 V, 0402 C1005X5R0J475M TDK
4.7 µF, 6.3 V, 0402 CL05A475MQ5NRNC Samsung
10 µF, 6.3 V, 0603 C1608X5R0J106M TDK
10 µF, 6.3 V, 0402 CL05A106MQ5NUNC Samsung

The input filter capacitor supplies AC current drawn by the PFET switch of the LM3241 in the first part of each
cycle and reduces the voltage ripple imposed on the input power source. The output filter capacitor absorbs the
AC inductor current, helps maintain a steady output voltage during transient load changes, and reduces output
voltage ripple. These capacitors must be selected with sufficient capacitance and sufficiently low equivalent
series resistance (ESR) to perform these functions. The ESR of the filter capacitors is generally a major factor in
voltage ripple.

8.2.3 Application Curves

100

95

90 VIN = 4.2V
EFFICIENCY (%)

VIN = 3.6V
85 VIN = 3.0V

80

75

70

65

60
0 50 100 150 200 250
VOUT = 0.6 V/3.4 V RLOAD = 10 Ω
OUTPUT CURRENT(mA)
VOUT = 0.8 V Figure 31. VCON Transient Response

Figure 30. Efficiency vs Output Current

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9 Power Supply Recommendations

The device is designed to operate from an input voltage supply range from 2.7 V to 5.5 V. Ensure that the input
power supply has a sufficient current rating for the application.

10 Layout

10.1 Layout Guidelines

10.1.1 DSBGA Package Assembly and Use
Use of the DSBGA package requires specialized board layout, precision mounting and careful reflow techniques,
as detailed in the AN-1112 DSBGA Wafer Level Chip Scale Package application report. For best results in
assembly, alignment ordinals on the PC board should be used to facilitate placement of the device. The pad style
used with DSBGA package must be the non-solder mask defined (NSMD) type. This pad type means that the
solder-mask opening is larger than the pad size which prevents a lip that otherwise forms if the solder-mask and
pad overlap when holding the device off the surface of the board causing interference with mounting. For specific
instructions on how to do this, refer to the AN-1112 DSBGA Wafer Level Chip Scale Package application report.
The 6-bump package used for LM3241 has 300 micron solder balls and requires 10.82 mil pads for mounting on
the circuit board. The trace to each pad should enter the pad with a 90° angle to prevent debris from being
caught in deep corners. Initially, the trace to each pad should be 7 mil wide, for a section approximately 7 mil
long, as a thermal relief. Then each trace should neck up or down to its optimal width. The important criterion is
symmetry which ensures the solder bumps on the LM3241 reflow evenly and that the device solders level to the
board. In particular, special attention must be paid to the pads for bumps A2 and C2. Because the VIN and GND
pins are typically connected to large copper planes, inadequate thermal relief can result in late or inadequate
reflow of these bumps.
The DSBGA package is optimized for the smallest possible size in applications with red or infrared opaque
cases. Because the DSBGA package lacks the plastic encapsulation characteristic of larger devices, it is
vulnerable to light. Backside metallization and/or epoxy coating, along with front-side shading by the printed
circuit board, reduce this sensitivity. However, the package has exposed die edges. In particular, DSBGA
devices are sensitive to light in the red and infrared range shining on the exposed die edges of the package.
TI recommends connecting a 10-nF capacitor between the VCON pin and ground for non-standard ESD events
or environments and manufacturing processes. This capacitor prevents unexpected output voltage drift.

10.1.2 Board Layout Considerations

Printed-circuit board (PCB) layout is an important part of DC-DC converter design. Poor board layout can disrupt
the performance of a DC-DC converter and surrounding circuitry by contributing to EMI, ground bounce, and
resistive voltage loss in the traces. These factors can send erroneous signals to the DC-DC converter device,
resulting in poor regulation or instability. Poor layout can also result in reflow problems leading to poor solder
joints between the DSBGA package and board pads—poor solder joints can result in erratic or degraded
performance. Good layout for the LM3241 can be implemented by following a few simple design rules, as shown
in Figure 33.
1. Place the LM3241 on 10.82 mil pads. As a thermal relief, connect each pad with a 7mil wide, approximately
7mil long trace, and then incrementally increase each trace to its optimal width. The VIN and GND traces are
especially recommended to be as wide as possible. The important criterion is symmetry to ensure the solder
bumps reflow evenly (refer to the AN-1112 DSBGA Wafer Level Chip Scale Package application report).
2. Place the LM3241, inductor, and filter capacitors close together and make the traces short. The traces
between these components carry relatively high switching current and act as antennae. Following this rule
reduces radiated noise. Special care must be given to place the input filter capacitor very close to the
VIN and GND pads.
3. Arrange the components so that the switching current loops curl in the same direction. During the first half of
each cycle, current flows from the input filter capacitor, through the LM3241 and inductor to the output filter
capacitor and back through ground, forming a current loop. In the second half of each cycle, current is pulled
up from ground, through the LM3241 by the inductor, to the output filter capacitor and then back through
ground, forming a second current loop. Routing these loops so the current curls in the same direction
prevents magnetic field reversal between the two half-cycles and reduces radiated noise.

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Layout Guidelines (continued)

4. Connect the ground pads of the LM3241 and filter capacitors together using generous component-side
copper fill as a pseudo-ground plane. Then connect this to the ground-plane (if one is used) with several
vias. This connection reduces ground-plane noise by preventing the switching currents from circulating
through the ground plane. It also reduces ground bounce at the LM3241 by giving it a low impedance ground
connection.
5. Use side traces between the power components and for power connections to the DC-DC converter circuit
which reduces voltage errors caused by resistive losses across the traces.
6. Route noise sensitive traces such as the voltage feedback path away from noisy traces between the power
components. The output voltage feedback point should be taken approximately 1.5 nH away from the output
capacitor. The feedback trace also should be routed opposite to noise components. The voltage feedback
trace must remain close to the LM3241 circuit and should be routed directly from FB to VOUT at the
inductor and should be routed opposite to noise components. This trace placement allows fast
feedback and reduces EMI radiated onto the voltage feedback trace of the DC-DC converter (see Figure 32).

VIN

VOUT

FB trace on another layer to be

protected from noise.

Figure 32. Feedback Trace

7. Place noise-sensitive circuitry, such as radio IF blocks, away from the DC-DC converter, CMOS digital
blocks, and other noisy circuitry. Interference with noise-sensitive circuitry in the system can be reduce
through distance.
In mobile phones, for example, a common practice is to place the DC-DC converter on one corner of the board,
arrange the CMOS digital circuitry around it (because this also generates noise), and then place sensitive
preamplifiers and IF stages on the diagonally opposing corner. Often, the sensitive circuitry is shielded with a
metal pan and power to it is post-regulated to reduce conducted noise, using low-dropout linear regulators.

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10.2 Layout Example

Figure 33. LM3241 Board Layout

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11 Device and Documentation Support

11.1 Documentation Support

11.1.1 Related Documentation
For related documentation see the following:
Texas Instruments, AN-1112 DSBGA Wafer Level Chip Scale Package application report

11.2 Receiving Notification of Documentation Updates

To receive notification of documentation updates, navigate to the device product folder on ti.com. In the upper
right corner, click on Alert me to register and receive a weekly digest of any product information that has
changed. For change details, review the revision history included in any revised document.

11.3 Community Resources

The following links connect to TI community resources. Linked contents are provided "AS IS" by the respective
contributors. They do not constitute TI specifications and do not necessarily reflect TI's views; see TI's Terms of
Use.
TI E2E™ Online Community TI's Engineer-to-Engineer (E2E) Community. Created to foster collaboration
among engineers. At e2e.ti.com, you can ask questions, share knowledge, explore ideas and help
solve problems with fellow engineers.
Design Support TI's Design Support Quickly find helpful E2E forums along with design support tools and
contact information for technical support.

11.4 Trademarks
Eco-mode, E2E are trademarks of Texas Instruments.
All other trademarks are the property of their respective owners.
11.5 Electrostatic Discharge Caution
This integrated circuit can be damaged by ESD. Texas Instruments recommends that all integrated circuits be handled with
appropriate precautions. Failure to observe proper handling and installation procedures can cause damage.
ESD damage can range from subtle performance degradation to complete device failure. Precision integrated circuits may be more
susceptible to damage because very small parametric changes could cause the device not to meet its published specifications.

11.6 Glossary
SLYZ022 — TI Glossary.
This glossary lists and explains terms, acronyms, and definitions.

12 Mechanical, Packaging, and Orderable Information

The following pages include mechanical, packaging, and orderable information. This information is the most
current data available for the designated devices. This data is subject to change without notice and revision of
this document. For browser-based versions of this data sheet, refer to the left-hand navigation.

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 PACKAGE OPTION ADDENDUM

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PACKAGING INFORMATION

Orderable Device Status Package Type Package Pins Package Eco Plan Lead/Ball Finish MSL Peak Temp Op Temp (°C) Device Marking Samples
(1) Drawing Qty (2) (6) (3) (4/5)

LM3241TLE/NOPB ACTIVE DSBGA YZR 6 250 Green (RoHS SNAGCU Level-1-260C-UNLIM -40 to 85 H
& no Sb/Br)
LM3241TLX/NOPB ACTIVE DSBGA YZR 6 3000 Green (RoHS SNAGCU Level-1-260C-UNLIM -40 to 85 H
& no Sb/Br)

(1)
The marketing status values are defined as follows:
ACTIVE: Product device recommended for new designs.
LIFEBUY: TI has announced that the device will be discontinued, and a lifetime-buy period is in effect.
NRND: Not recommended for new designs. Device is in production to support existing customers, but TI does not recommend using this part in a new design.
PREVIEW: Device has been announced but is not in production. Samples may or may not be available.
OBSOLETE: TI has discontinued the production of the device.

(2)
RoHS: TI defines "RoHS" to mean semiconductor products that are compliant with the current EU RoHS requirements for all 10 RoHS substances, including the requirement that RoHS substance
do not exceed 0.1% by weight in homogeneous materials. Where designed to be soldered at high temperatures, "RoHS" products are suitable for use in specified lead-free processes. TI may
reference these types of products as "Pb-Free".
RoHS Exempt: TI defines "RoHS Exempt" to mean products that contain lead but are compliant with EU RoHS pursuant to a specific EU RoHS exemption.
Green: TI defines "Green" to mean the content of Chlorine (Cl) and Bromine (Br) based flame retardants meet JS709B low halogen requirements of <=1000ppm threshold. Antimony trioxide based
flame retardants must also meet the <=1000ppm threshold requirement.

(3)
MSL, Peak Temp. - The Moisture Sensitivity Level rating according to the JEDEC industry standard classifications, and peak solder temperature.

(4)
There may be additional marking, which relates to the logo, the lot trace code information, or the environmental category on the device.

(5)
Multiple Device Markings will be inside parentheses. Only one Device Marking contained in parentheses and separated by a "~" will appear on a device. If a line is indented then it is a continuation
of the previous line and the two combined represent the entire Device Marking for that device.

(6)
Lead/Ball Finish - Orderable Devices may have multiple material finish options. Finish options are separated by a vertical ruled line. Lead/Ball Finish values may wrap to two lines if the finish
value exceeds the maximum column width.

Important Information and Disclaimer:The information provided on this page represents TI's knowledge and belief as of the date that it is provided. TI bases its knowledge and belief on information
provided by third parties, and makes no representation or warranty as to the accuracy of such information. Efforts are underway to better integrate information from third parties. TI has taken and
continues to take reasonable steps to provide representative and accurate information but may not have conducted destructive testing or chemical analysis on incoming materials and chemicals.
TI and TI suppliers consider certain information to be proprietary, and thus CAS numbers and other limited information may not be available for release.

In no event shall TI's liability arising out of such information exceed the total purchase price of the TI part(s) at issue in this document sold by TI to Customer on an annual basis.

Addendum-Page 1
 PACKAGE OPTION ADDENDUM

www.ti.com 25-Oct-2017

Addendum-Page 2
 PACKAGE MATERIALS INFORMATION

www.ti.com 3-Oct-2017

TAPE AND REEL INFORMATION

*All dimensions are nominal

Device Package Package Pins SPQ Reel Reel A0 B0 K0 P1 W Pin1
Type Drawing Diameter Width (mm) (mm) (mm) (mm) (mm) Quadrant
(mm) W1 (mm)
LM3241TLE/NOPB DSBGA YZR 6 250 178.0 8.4 1.24 1.7 0.76 4.0 8.0 Q1
LM3241TLX/NOPB DSBGA YZR 6 3000 178.0 8.4 1.24 1.7 0.76 4.0 8.0 Q1

Pack Materials-Page 1
 PACKAGE MATERIALS INFORMATION

www.ti.com 3-Oct-2017

*All dimensions are nominal

Device Package Type Package Drawing Pins SPQ Length (mm) Width (mm) Height (mm)
LM3241TLE/NOPB DSBGA YZR 6 250 210.0 185.0 35.0
LM3241TLX/NOPB DSBGA YZR 6 3000 210.0 185.0 35.0

Pack Materials-Page 2
 MECHANICAL DATA
YZR0006xxx

D
0.600±0.075

TLA06XXX (Rev C)

D: Max = 1.51 mm, Min = 1.45 mm

E: Max = 1.12 mm, Min = 1.06 mm

4215044/A 12/12

NOTES: A. All linear dimensions are in millimeters. Dimensioning and tolerancing per ASME Y14.5M-1994.
B. This drawing is subject to change without notice.

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