Digital Electronics MCQ
Digital Electronics MCQ
Digital Electronics MCQ
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9. The NAND latch works when both inputs are ___________
a) 1
b) 0
c) Inverted
d) Don’t cares
View Answer
Answer: a
Explanation: The NAND latch works when both inputs are 1. Since, both of the inputs
are inverted in a NAND latch.
10. The first step of analysis procedure of SR latch is to ___________
a) label inputs
b) label outputs
c) label states
d) label tables
View Answer
Answer: b
Explanation: All flip flops have at least one output labeled Q (i.e. inverted). This is so
because the flip flops have inverting gates inside them, hence in order to have both Q
and Q complement available, we have atleast one output labelled.
11. The inputs of SR latch are ___________
a) x and y
b) a and b
c) s and r
d) j and k
View Answer
12. When a high is applied to the Set line of an SR latch, then ___________
a) Q output goes high
b) Q’ output goes high
c) Q output goes low
d) Both Q and Q’ go high
View Answer
13. When both inputs of SR latches are low, the latch ___________
a) Q output goes high
b) Q’ output goes high
c) It remains in its previously set or reset state
d) it goes to its next set or reset state
View Answer
Answer: c
Explanation: When both inputs of SR latches are low, the latch remains in it’s present
state. There is no change in the output.
14. When both inputs of SR latches are high, the latch goes ___________
a) Unstable
b) Stable
c) Metastable
d) Bistable
View Answer
Answer: c
Explanation: When both gates are identical and this is “metastable”, and the device will
be in an undefined state for an indefinite period.
1. Latches constructed with NOR and NAND gates tend to remain in the latched
condition due to which configuration feature?
a) Low input voltages
b) Synchronous operation
c) Gate impedance
d) Cross coupling
View Answer
Answer: d
Explanation: Latch is a type of bistable multivibrator having two stable states. Both
inputs of a latch are directly connected to the other’s output. Such types of structure is
called cross coupling and due to which latches remain in the latched condition.
2. One example of the use of an S-R flip-flop is as ___________
a) Transition pulse generator
b) Racer
c) Switch debouncer
d) Astable oscillator
View Answer
Answer: c
Explanation: The SR flip-flop is very effective in removing the effects of switch bounce,
which is the unwanted noise caused during the switching of electronic devices.
3. The truth table for an S-R flip-flop has how many VALID entries?
a) 1
b) 2
c) 3
d) 4
View Answer
Answer: c
Explanation: The SR flip-flop actually has three inputs, Set, Reset and its current state.
The Invalid or Undefined State occurs at both S and R being at 1.
4. When both inputs of a J-K flip-flop cycle, the output will ___________
a) Be invalid
b) Change
c) Not change
d) Toggle
View Answer
Answer: c
Explanation: After one cycle the value of each input comes to the same value. Eg:
Assume J=0 and K=1. After 1 cycle, it becomes as J=0->1->0(1 cycle complete) and
K=1->0->1(1 cycle complete). The J & K flip-flop has 4 stable states: Latch, Reset, Set
and Toggle.
5. Which of the following is correct for a gated D-type flip-flop?
a) The Q output is either SET or RESET as soon as the D input goes HIGH or LOW
b) The output complement follows the input when enabled
c) Only one of the inputs can be HIGH at a time
d) The output toggles if one of the inputs is held HIGH
View Answer
Answer: a
Explanation: In D flip flop, when the clock is high then the output depends on the input
otherwise reminds previous output. In a state of clock high, when D is high the output Q
also high, if D is ‘0’ then output is also zero. Like SR flip-flop, the D-flip-flop also have an
invalid state at both inputs being 1.
6. A basic S-R flip-flop can be constructed by cross-coupling of which basic logic gates?
a) AND or OR gates
b) XOR or XNOR gates
c) NOR or NAND gates
d) AND or NOR gates
View Answer
Answer: c
Explanation: The basic S-R flip-flop can be constructed by cross coupling of NOR or
NAND gates. Cross coupling means the output of second gate is fed to the input of first
gate and vice-versa.
7. The logic circuits whose outputs at any instant of time depends only on the present
input but also on the past outputs are called
a) Combinational circuits
b) Sequential circuits
c) Latches
d) Flip-flops
View Answer
Answer: b
Explanation: In sequential circuits, the output signals are fed back to the input side. So,
The circuits whose outputs at any instant of time depends only on the present input but
also on the past outputs are called sequential circuits. Unlike sequential circuits, if output
depends only on the present state, then it’s known as combinational circuits.
8. Whose operations are more faster among the following?
a) Combinational circuits
b) Sequential circuits
c) Latches
d) Flip-flops
View Answer
Answer: a
Explanation: Combinational circuits are often faster than sequential circuits. Since, the
combinational circuits do not require memory elements whereas the sequential circuits
need memory devices to perform their operations in sequence. Latches and Flip-flops
come under sequential circuits.
9. How many types of sequential circuits are?
a) 2
b) 3
c) 4
d) 5
View Answer
Answer: a
Explanation: There are two type of sequential circuits viz., (i) synchronous or clocked
and (ii) asynchronous or unclocked. Synchronous Sequential Circuits are triggered in the
presence of a clock signal, whereas, Asynchronous Sequential Circuits function in the
absence of a clock signal.
10. The sequential circuit is also called ___________
a) Flip-flop
b) Latch
c) Strobe
d) Adder
View Answer
Answer: b
Explanation: The sequential circuit is also called a latch because both are a memory cell,
which are capable of storing one bit of information.
11. The basic latch consists of ___________
a) Two inverters
b) Two comparators
c) Two amplifiers
d) Two adders
View Answer
Answer: a
Explanation: The basic latch consists of two inverters. It is in the sense that if the output
Q = 0 then the second output Q’ = 1 and vice versa.
12. In S-R flip-flop, if Q = 0 the output is said to be ___________
a) Set
b) Reset
c) Previous state
d) Current state
View Answer
Answer: b
Explanation: In S-R flip-flop, if Q = 0 the output is said to be reset and set for Q = 1.
13. The output of latches will remain in set/reset untill ___________
a) The trigger pulse is given to change the state
b) Any pulse given to go into previous state
c) They don’t get any pulse more
d) The pulse is edge-triggered
View Answer
Answer: a
Explanation: The output of latches will remain in set/reset untill the trigger pulse is given
to change the state.
14. What is a trigger pulse?
a) A pulse that starts a cycle of operation
b) A pulse that reverses the cycle of operation
c) A pulse that prevents a cycle of operation
d) A pulse that enhances a cycle of operation
View Answer
Answer: a
Explanation: Trigger pulse is defined as a pulse that starts a cycle of operation.
15. The circuits of NOR based S-R latch classified as asynchronous sequential circuits,
why?
a) Because of inverted outputs
b) Because of triggering functionality
c) Because of cross-coupled connection
d) Because of inverted outputs & triggering functionality
View Answer
Answer: c
Explanation: The cross-coupled connections from the output of one gate to the input of
the other gate constitute a feedback path. For this reason, the circuits of NOR based S-
R latch classified as asynchronous sequential circuits. Moreover, they are referred to as
asynchronous because they function in the absence of a clock pulse.
This set of Digital Electronic/Circuits online quiz focuses on “Flip Flops – 2”.
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