Digital Electronics MCQ

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This set of Digital Electronics/Circuits Multiple Choice Questions & Answers

(MCQs) focuses on “Latches”.

1. A latch is an example of a ___________


a) Monostable multivibrator
b) Astable multivibrator
c) Bistable multivibrator
d) 555 timer
View Answer
Answer: c
Explanation: A latch is an example of a bistable multivibrator. A Bistable multivibrator is
one in which the circuit is stable in either of two states. It can be flipped from one state to
the other state and vice-versa.
2. Latch is a device with ___________
a) One stable state
b) Two stable state
c) Three stable state
d) Infinite stable states
View Answer
Answer: b
Explanation: Since, a latch works on the principal of bistable multivibrator. A Bistable
multivibrator is one in which the circuit is stable in either of two states. It can be flipped
from one state to the other state and vice-versa. So a latch has two stable states.
3. Why latches are called a memory devices?
a) It has capability to stare 8 bits of data
b) It has internal memory of 4 bit
c) It can store one bit of data
d) It can store infinite amount of data
View Answer
Answer: c
Explanation: Latches can be memory devices, and can store one bit of data for as long
as the device is powered. Once device is turned off, the memory gets refreshed.
4. Two stable states of latches are ___________
a) Astable & Monostable
b) Low input & high output
c) High output & low output
d) Low output & high input
View Answer
Answer: c
Explanation: A latch has two stable states, following the principle of Bistable
Multivibrator. There are two stable states of latches and these states are high-output and
low-output.
5. How many types of latches are ___________
a) 4
b) 3
c) 2
d) 5
View Answer
Answer: a
Explanation: There are four types of latches: SR latch, D latch, JK latch and T latch. D
latch is a modified form of SR latch whereas, T latch is an advanced form of JK latch.
6. The full form of SR is ___________
a) System rated
b) Set reset
c) Set ready
d) Set Rated
View Answer
Answer: b
Explanation: The full form of SR is set/reset. It is a type of latch having two stable states.
7. The SR latch consists of ___________
a) 1 input
b) 2 inputs
c) 3 inputs
d) 4 inputs
View Answer
Answer: b
Explanation: SR or Set-Reset latch is the simplest type of bistable multivibrator having
two stable states.
The diagram of SR latch is shown below:

8. The outputs of SR latch are ___________


a) x and y
b) a and b
c) s and r
d) q and q’
View Answer
Answer: d
Explanation: SR or Set-Reset latch is the simplest type of bistable multivibrator having
two stable states. The inputs of SR latch are s and r while outputs are q and q’. It is clear
from the diagram:

.
9. The NAND latch works when both inputs are ___________
a) 1
b) 0
c) Inverted
d) Don’t cares
View Answer
Answer: a
Explanation: The NAND latch works when both inputs are 1. Since, both of the inputs
are inverted in a NAND latch.
10. The first step of analysis procedure of SR latch is to ___________
a) label inputs
b) label outputs
c) label states
d) label tables
View Answer
Answer: b
Explanation: All flip flops have at least one output labeled Q (i.e. inverted). This is so
because the flip flops have inverting gates inside them, hence in order to have both Q
and Q complement available, we have atleast one output labelled.
11. The inputs of SR latch are ___________
a) x and y
b) a and b
c) s and r
d) j and k
View Answer
12. When a high is applied to the Set line of an SR latch, then ___________
a) Q output goes high
b) Q’ output goes high
c) Q output goes low
d) Both Q and Q’ go high
View Answer
13. When both inputs of SR latches are low, the latch ___________
a) Q output goes high
b) Q’ output goes high
c) It remains in its previously set or reset state
d) it goes to its next set or reset state
View Answer
Answer: c
Explanation: When both inputs of SR latches are low, the latch remains in it’s present
state. There is no change in the output.
14. When both inputs of SR latches are high, the latch goes ___________
a) Unstable
b) Stable
c) Metastable
d) Bistable
View Answer
Answer: c
Explanation: When both gates are identical and this is “metastable”, and the device will
be in an undefined state for an indefinite period.

This set of Digital Electronics/Circuits Multiple Choice Questions & Answers


(MCQs) focuses on “Flip Flops – 1”.

1. Latches constructed with NOR and NAND gates tend to remain in the latched
condition due to which configuration feature?
a) Low input voltages
b) Synchronous operation
c) Gate impedance
d) Cross coupling
View Answer
Answer: d
Explanation: Latch is a type of bistable multivibrator having two stable states. Both
inputs of a latch are directly connected to the other’s output. Such types of structure is
called cross coupling and due to which latches remain in the latched condition.
2. One example of the use of an S-R flip-flop is as ___________
a) Transition pulse generator
b) Racer
c) Switch debouncer
d) Astable oscillator
View Answer
Answer: c
Explanation: The SR flip-flop is very effective in removing the effects of switch bounce,
which is the unwanted noise caused during the switching of electronic devices.
3. The truth table for an S-R flip-flop has how many VALID entries?
a) 1
b) 2
c) 3
d) 4
View Answer
Answer: c
Explanation: The SR flip-flop actually has three inputs, Set, Reset and its current state.
The Invalid or Undefined State occurs at both S and R being at 1.
4. When both inputs of a J-K flip-flop cycle, the output will ___________
a) Be invalid
b) Change
c) Not change
d) Toggle
View Answer
Answer: c
Explanation: After one cycle the value of each input comes to the same value. Eg:
Assume J=0 and K=1. After 1 cycle, it becomes as J=0->1->0(1 cycle complete) and
K=1->0->1(1 cycle complete). The J & K flip-flop has 4 stable states: Latch, Reset, Set
and Toggle.
5. Which of the following is correct for a gated D-type flip-flop?
a) The Q output is either SET or RESET as soon as the D input goes HIGH or LOW
b) The output complement follows the input when enabled
c) Only one of the inputs can be HIGH at a time
d) The output toggles if one of the inputs is held HIGH
View Answer
Answer: a
Explanation: In D flip flop, when the clock is high then the output depends on the input
otherwise reminds previous output. In a state of clock high, when D is high the output Q
also high, if D is ‘0’ then output is also zero. Like SR flip-flop, the D-flip-flop also have an
invalid state at both inputs being 1.
6. A basic S-R flip-flop can be constructed by cross-coupling of which basic logic gates?
a) AND or OR gates
b) XOR or XNOR gates
c) NOR or NAND gates
d) AND or NOR gates
View Answer
Answer: c
Explanation: The basic S-R flip-flop can be constructed by cross coupling of NOR or
NAND gates. Cross coupling means the output of second gate is fed to the input of first
gate and vice-versa.
7. The logic circuits whose outputs at any instant of time depends only on the present
input but also on the past outputs are called
a) Combinational circuits
b) Sequential circuits
c) Latches
d) Flip-flops
View Answer
Answer: b
Explanation: In sequential circuits, the output signals are fed back to the input side. So,
The circuits whose outputs at any instant of time depends only on the present input but
also on the past outputs are called sequential circuits. Unlike sequential circuits, if output
depends only on the present state, then it’s known as combinational circuits.
8. Whose operations are more faster among the following?
a) Combinational circuits
b) Sequential circuits
c) Latches
d) Flip-flops
View Answer
Answer: a
Explanation: Combinational circuits are often faster than sequential circuits. Since, the
combinational circuits do not require memory elements whereas the sequential circuits
need memory devices to perform their operations in sequence. Latches and Flip-flops
come under sequential circuits.
9. How many types of sequential circuits are?
a) 2
b) 3
c) 4
d) 5
View Answer
Answer: a
Explanation: There are two type of sequential circuits viz., (i) synchronous or clocked
and (ii) asynchronous or unclocked. Synchronous Sequential Circuits are triggered in the
presence of a clock signal, whereas, Asynchronous Sequential Circuits function in the
absence of a clock signal.
10. The sequential circuit is also called ___________
a) Flip-flop
b) Latch
c) Strobe
d) Adder
View Answer
Answer: b
Explanation: The sequential circuit is also called a latch because both are a memory cell,
which are capable of storing one bit of information.
11. The basic latch consists of ___________
a) Two inverters
b) Two comparators
c) Two amplifiers
d) Two adders
View Answer
Answer: a
Explanation: The basic latch consists of two inverters. It is in the sense that if the output
Q = 0 then the second output Q’ = 1 and vice versa.
12. In S-R flip-flop, if Q = 0 the output is said to be ___________
a) Set
b) Reset
c) Previous state
d) Current state
View Answer
Answer: b
Explanation: In S-R flip-flop, if Q = 0 the output is said to be reset and set for Q = 1.
13. The output of latches will remain in set/reset untill ___________
a) The trigger pulse is given to change the state
b) Any pulse given to go into previous state
c) They don’t get any pulse more
d) The pulse is edge-triggered
View Answer
Answer: a
Explanation: The output of latches will remain in set/reset untill the trigger pulse is given
to change the state.
14. What is a trigger pulse?
a) A pulse that starts a cycle of operation
b) A pulse that reverses the cycle of operation
c) A pulse that prevents a cycle of operation
d) A pulse that enhances a cycle of operation
View Answer
Answer: a
Explanation: Trigger pulse is defined as a pulse that starts a cycle of operation.
15. The circuits of NOR based S-R latch classified as asynchronous sequential circuits,
why?
a) Because of inverted outputs
b) Because of triggering functionality
c) Because of cross-coupled connection
d) Because of inverted outputs & triggering functionality
View Answer
Answer: c
Explanation: The cross-coupled connections from the output of one gate to the input of
the other gate constitute a feedback path. For this reason, the circuits of NOR based S-
R latch classified as asynchronous sequential circuits. Moreover, they are referred to as
asynchronous because they function in the absence of a clock pulse.

This set of Digital Electronic/Circuits online quiz focuses on “Flip Flops – 2”.

1. What is an ambiguous condition in a NAND based S’-R’ latch?


a) S’=0, R’=1
b) S’=1, R’=0
c) S’=1, R’=1
d) S’=0, R’=0
View Answer
Answer: d
Explanation: In a NAND based S-R latch, If S’=0 & R’=0 then both the outputs (i.e. Q &
Q’) goes HIGH and this condition is called as ambiguous/forbidden state. This state is
also known as an Invalid state as the system goes into an unexpected situation.
2. In a NAND based S’-R’ latch, if S’=1 & R’=1 then the state of the latch is
____________
a) No change
b) Set
c) Reset
d) Forbidden
View Answer
Answer: a
Explanation: In a NAND based S’-R, latch if S’=1 & R’=1 then there is no any change in
the state. It remains in its prior state. This state is used for the storage of data.
3. A NAND based S’-R’ latch can be converted into S-R latch by placing ____________
a) A D latch at each of its input
b) An inverter at each of its input
c) It can never be converted
d) Both a D latch and an inverter at its input
View Answer
Answer: d
Explanation: A NAND based S’-R’ latch can be converted into S-R latch by placing either
a D latch or an inverter at its input as it’s operations will be complementary.
4. One major difference between a NAND based S’-R’ latch & a NOR based S-R latch is
____________
a) The inputs of NOR latch are 0 but 1 for NAND latch
b) The inputs of NOR latch are 1 but 0 for NAND latch
c) The output of NAND latch becomes set if S’=0 & R’=1 and vice versa for NOR latch
d) The output of NOR latch is 1 but 0 for NAND latch
View Answer
Answer: a
Explanation: Due to inverted input of NAND based S’-R’ latch, the inputs of NOR latch
are 0 but 1 for NAND latch.
5. The characteristic equation of S-R latch is ____________
a) Q(n+1) = (S + Q(n))R’
b) Q(n+1) = SR + Q(n)R
c) Q(n+1) = S’R + Q(n)R
d) Q(n+1) = S’R + Q'(n)R
View Answer
Answer: a
Explanation: A characteristic equation is needed when a specific gate requires a specific
output in order to satisfy the truth table. The characteristic equation of S-R latch is
Q(n+1) = (S + Q(n))R’.
6. The difference between a flip-flop & latch is ____________
a) Both are same
b) Flip-flop consist of an extra output
c) Latches has one input but flip-flop has two
d) Latch has two inputs but flip-flop has one
View Answer
Answer: c
Explanation: Flip-flop is a modified version of latch. To determine the changes in states,
an additional control input is provided to the latch.
7. How many types of flip-flops are?
a) 2
b) 3
c) 4
d) 5
View Answer
Answer: c
Explanation: There are 4 types of flip-flops, viz., S-R, J-K, D, and T. D flip-flop is an
advanced version of S-R flip-flop, while T flip-flop is an advanced version of J-K flip-flop.
8. The S-R flip flop consist of ____________
a) 4 AND gates
b) Two additional AND gates
c) An additional clock input
d) 3 AND gates
View Answer
Answer: b
Explanation: The S-R flip flop consist of two additional AND gates at the S and R inputs
of S-R latch.
9. What is one disadvantage of an S-R flip-flop?
a) It has no Enable input
b) It has a RACE condition
c) It has no clock input
d) Invalid State
View Answer
Answer: d
Explanation: The main drawback of s-r flip flop is invalid output when both the inputs are
high, which is referred to as Invalid State.
10. One example of the use of an S-R flip-flop is as ____________
a) Racer
b) Stable oscillator
c) Binary storage register
d) Transition pulse generator
View Answer
Answer: c
Explanation: S-R refers to set-reset. So, it is used to store two values 0 and 1. Hence, it
is referred to as binary storage element. It functions as memory storage during the No
Change State.
11. When is a flip-flop said to be transparent?
a) When the Q output is opposite the input
b) When the Q output follows the input
c) When you can see through the IC packaging
d) When the Q output is complementary of the input
View Answer
Answer: b
Explanation: Flip-flop have the property of responding immediately to the changes in its
inputs. This property is called transparency.
12. On a positive edge-triggered S-R flip-flop, the outputs reflect the input condition
when ________
a) The clock pulse is LOW
b) The clock pulse is HIGH
c) The clock pulse transitions from LOW to HIGH
d) The clock pulse transitions from HIGH to LOW
View Answer
Answer: c
Explanation: Edge triggered device will follow when there is transition. It is a positive
edge triggered when transition takes place from low to high, while, it is negative edge
triggered when the transition takes place from high to low.
13. What is the hold condition of a flip-flop?
a) Both S and R inputs activated
b) No active S or R input
c) Only S is active
d) Only R is active
View Answer
Answer: b
Explanation: The hold condition in a flip-flop is obtained when both of the inputs are
LOW. It is the No Change State or Memory Storage state if a flip-flop.
14. If an active-HIGH S-R latch has a 0 on the S input and a 1 on the R input and then
the R input goes to 0, the latch will be ________
a) SET
b) RESET
c) Clear
d) Invalid
View Answer
Answer: b
Explanation: If S=0, R=1, the flip flop is at reset condition. Then at S=0, R=0, there is no
change. So, it remains in reset. If S=1, R=0, the flip flop is at the set condition.
15. The circuit that is primarily responsible for certain flip-flops to be designated as edge-
triggered is the _____________
a) Edge-detection circuit
b) NOR latch
c) NAND latch
d) Pulse-steering circuit
View Answer
Answer: a
Explanation: The circuit that is primarily responsible for certain flip-flops to be designated
as edge-triggered is the edge-detection circuit

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