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ISSN : 2248-9622, Vol. 7, Issue 5, ( Part -4) May 2017, pp.60-63

RESEARCH ARTICLE OPEN ACCESS

A Review of Different Methods for Booth Multiplier

Jyoti Kalia*, Vikas Mittal**
*(Department of Electronics and Communication Engineering, MMU University, Haryana
Email: jyotikaliasharma121@gmail.com)
**(Department of Electronics and Communication Engineering, MMU University, Haryana)

ABSTRACT
In this review paper, different type of implementation of Booth multiplier has been studied. Multipliers has
great importance in digital signal processor, so designing a high-speed multiplier is the need of the hour.
Advantages of using modified booth multiplier algorithm is that the number of partial product is reduced.
Different types of addition algorithms are also discussed which are used for addition operation of multiplier.
Keyword -booth multiplier, modified booth multiplier, radix-8, fixed-width.

I. INTRODUCTION
In many digital signals processing (DSP) Integrated with the storage element, our proposed
applications computer arithmetic is extensively used. multiplier shows great efficiency in area, power and
As compare to the adders and subtractors multiplier scalability.
are more complex, so the multiplier speed usually
Honglan Jiang et al. [2] The Booth multiplier has
resolves the operating speed of a DSP system. With
been widely used for high performance signed
other considerations such as Hardware complexity,
multiplication by encoding and thereby reducing the
power dissipation of a design and delay the high
number ofpartial products. A multiplier using the
precision is often looked as a strict requirement.
radix-4(or modified Booth) algorithm is very
Some applications such as media processing,
efficient due to the ease of partial product
recognition and data mining are error-tolerant, so an
generation, whereas the radix-8 Booth multiplier is
approximate arithmetic unit can be employed. With
slow due to the complexity of generating the odd
the accumulation of partial products, the design of
multiples of the multiplicand. In this paper, this issue
an approximate multiplier is usually deals, in its
is alleviated by the application of approximate
operation which is bottleneck. To reduce the delay
designs. An approximate 2-bit adder is deliberately
and hardware overhead the truncation of the lower
designed for calculating the sum of 1× and 2× of a
part of the partial products is a simple approximation
binary number. This adder requires a small area, a
scheme; to as fixed-width multiplier design such a
low power and a short critical path delay.
scheme is referred [2]. Multipliers play an important
Subsequently, the 2-bit adder is employed to
role in today’s digital signal processing and various
implement the less significant section of a recoding
other applications. With advances in technology,
adder for generating the triple multiplicand with no
many researchers have tried and are trying to design
carry propagation. In the pursuit of a trade-off
multipliers which offer either of the following
between accuracy and power consumption, two
design targets – high speed, low power consumption,
signed 16×16-bit approximate radix-8 Booth
regularity of layout and hence less area or even
multipliers are designed using the approximate
combination of them in one multiplier thus making
recoding adder with and without the truncation of
them suitable for various high speed, low power and
many less significant bits in the partial products. The
compact VLSI implementation.
proposed approximate multipliers are faster and
II. LITRATURE SURVEY more power efficient than the accurate Booth
Tao Luo et al. [1] In this paper, present an in- multiplier; moreover, the multiplier with 15-bit
memory Booth multiplier based on racetrack truncation achieves the best overall performance in
memory to alleviate this problem. As the building terms of hardware and accuracy when compared to
block of our multiplier, a racetrack memory based other approximate Booth multiplier designs. Finally,
adder is proposed, which saves 56.3% power the approximate multipliers are applied to the design
compared with the state-of-the-art magnetic adder. of a low-pass FIR filter and they show better
performance than other approximate Booth
multipliers.

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Jyoti Kalia . Int. Journal of Engineering Research and Application www.ijera.com
ISSN : 2248-9622, Vol. 7, Issue 5, ( Part -4) May 2017, pp.60-63

Jiun-Ping Wang et al. [3] This paper presents the the multiplier circuit. The multiplier circuit is
design of high-accuracy fixed-width modified Booth designed with conventional full adder. The
multipliers. To reduce the truncation error, firstly schematics are drawn and simulated. The power
slightly modify the partial product matrix of Booth results are thus compared for the different inputs.
multiplication and then derive an effective error The result shows that average power consumed by
compensation function that makes the error the multiplier. When using booth multiplier
distribution be more symmetric to and centralized in technique is less compared to column bypass
the error equal to zero, leading the fixed-width technique and array multiplier. Booth multiplier
modified Booth multiplier to very small mean and consumes comparatively less power and hence
mean-square errors.In addition, a simple multiplier with booth recoding unit is designed for
compensation circuit mainly composed of the low power consumption.
simplified sorting network is also proposed.
Furthermore, experimental results on two real-life Hsin-Lei Lin et al. [7] This paper presents a novel
applications also demonstrate that the proposed radix-4 Booth multiplier. A conventional Booth
fixed-width multipliers can improve the average multiplier consists of the Booth encoder, the partial-
peak signal-to-noise ratio of output images by at product summation tree, and the canypropagate
least 2.0 dB and 1.1 dB, respectively. adder. Different schemes are addressed to improve
the area and circuit speed effectively. A novel
Razaidi Hussin et al. [4] in this paper, present the modified Booth encodeddecoder is proposed and the
design of an efficient multiplication unit. This summation column is compressed by the proposed
multiplier architecture is based on Radix 4 Booth MFAr. The proposed design is simulated by
multiplier. The first is to modify the Wen-Chang’s Synopsys and Apollo. It results 20% area reduction,
Modified Booth Encoder (MBE) since it is the 17%&-24% power decrease, and 15% reduction of
fastest scheme to generate a partial product. the delay time of the critical path.
However, when implementing this MBE with the
Simplified Sign Extension (SSE) method, the Hwang-Cherng Chow et al. [8] In this paper, a new
multiplication’s output is incorrect. The 2nd part is MBE (modified Booth encoding) recoder, and a new
to improve the delay in the 4:2 compressor circuits. MBE decoder are proposed in CMOS transistor
The redesigned 4:2 compressor reduced the delay of level' to improve the performance of traditional
the Carry signal. This modification has been made multipliers. The proposed pipelined Booth multiplier
by rearranging the Boolean equation of the Carry can reduce the delay time of critical path by
signal. This architecture has been designed using levelizing the complex gate in the MBE decoder. As
Quartus II. The Gajski rule has been adopted to a result, MBE decoder is never the speed bottleneck
estimate the delay and size of the circuit. The total of a pipelined booth multiplier, and the speed of the
transistor count for this new multiplier is being a MBE decoder can be improved up to 66.3 percent.
slightly bigger. This is due to the new MBE which is Finally, a low voltage, high speed pipelined glitch-
uses more transistor.However, in performance speed, free Booth multiplier architecture is presented at
this efficiency multiplier is quite good. The lGhz in TSMC 0.35um process with a power
propagation delay is reduced by about 2% – 7% consumption of only 100.52mw.
from other designers.
Justin Hensley et al. [9] This paper makes the
Chung-Yi Li et al. [5] In this paper, a following contributions. First, a novel counter flow
probabilistic estimation bias (PEB) circuit for a organization is introduced, in which the data bits’
fixed-width two’s-complement Booth multiplier is flow in one direction, and the Booth commands
proposed. The proposed PEB circuit is derived from piggyback on the acknowledgments flowing in the
theoretical computation, instead of exhaustive opposite direction. Second, the arithmetic and shifter
simulations and heuristic compensation strategies units are merged together to obtain significant
that tend to introduce curve-fitting errors and improvement in area, energy as well as speed. Third,
exponential-grown simulation time. Consequently, design performs overlapped execution of multiple
the proposed PEB circuit provides a smaller area and iterations of the Booth algorithm. Finally, the design
a lower truncation error compared with existing is quite modular, which allows scaling to arbitrary
works. Implemented in an 8 × 8 2-D discrete cosine operand widths, without gate resizing or cycle time
transform (DCT) core, the DCT core using the overheads.
proposed PEB Booth multiplier improves the peak
signal-to-noise ratio by 17 dB with only a 2% area K. J. Cho et al. [10] In this paper, an efficient fixed-
penalty compared with the direct-truncated method. width modified Booth multiplier design method is
presented. To efficiently compensate for the
A.S.Prabhu et al. [6] In this paper, booth quantization error with reduced hardware
multipliers are proposed for reducing the power of complexity, Booth encoder outputs (not the

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Jyoti Kalia . Int. Journal of Engineering Research and Application www.ijera.com
ISSN : 2248-9622, Vol. 7, Issue 5, ( Part -4) May 2017, pp.60-63

multiplier coefficients) are used for the generation of generation. Here when the multiplier bit is zero then
the compensation bias. Also, the truncated bits are a row of zeros is summed to previous partial
divided into two groups (major group and minor product. when the multiplier bit is one then the
group) depending upon their effects on the multiplicand is added once to the previous partial
quantization error. Then, different error products with a position shift towards left.
compensation methods are applied to each group.
Simulation results show that significant reduction in
the truncation error can be achieved by the proposed
method compared with the fixed width modified
Booth multiplier.

III. BOOTH MULTIPLIER

It is a powerful algorithm for signed-number
multiplication, which treats both positive and
negative numbers uniformly. For the standard add-
shift operation, each multiplier bit generates one
multiple of the multiplicand to be added to the
partial product. If the multiplier is very large, then
many multiplicands must be added. In this case, the
delay of multiplier is determined mainly by the
number of additions to be performed. If there is a
way to reduce the number of the additions, the
performance will get better. Booth multiplication is a
technique that allows for smaller, faster
multiplication circuits, by recoding the numbers that
are multiplied. It is the standard technique used in
chip design, and provides significant improvements
over the "long multiplication" technique.

IV. MODIFIED BOOTH MULTIPLIER Fig.1: Modified Booth Multiplier Architecture

There are several Multiplier Architectures which has V. CONCLUSION
come into existence over recent years. Multiplier is
one of the key hardware blocks in Digital Signal This paper presents the design of review of different
Processors(DSP)and microprocessors. Multiplication methods with high-accuracy fixed-width modified
operations are so considerable in-order to slow down Booth multipliers. To reduce the truncation error,
the system operations. In this present years, firstly slightly modify the partial product matrix of
multiplier architectures are developed by Booth multiplication and then derive an effective
considering minimal operational speed, area and error compensation function that makes the error
power. An efficient Multiplier can improve the distribution be more symmetric to and centralized in
performance of Digital Signal Processors in case of the error equal to zero, leading the fixed-width
filtering, spectral analysis. The above multiplier modified Booth multiplier to very small mean and
architecture can be divided into two stages. In the mean-square errors.
first stage the Partial Products are formed by the
Booth encoder and Partial Product Generator(PPG). REFERENCES
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ISSN : 2248-9622, Vol. 7, Issue 5, ( Part -4) May 2017, pp.60-63

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