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    Hef4025b PDF

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    GoodLookingPirate
    This document provides data sheets for the HEF4025B triple 3-input NOR gate integrated circuit from Philips Semiconductors. It includes descriptions of the IC, its pinning diagram, logic diagram, and family specifications. It also provides typical and maximum values for the IC's propagation delays, output transition times, and dynamic power dissipation as functions of supply voltage and load capacitance.

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    Hef4025b PDF

    Uploaded by

    GoodLookingPirate
    21 views3 pages
    This document provides data sheets for the HEF4025B triple 3-input NOR gate integrated circuit from Philips Semiconductors. It includes descriptions of the IC, its pinning diagram, logic diagram, and family specifications. It also provides typical and maximum values for the IC's propagation delays, output transition times, and dynamic power dissipation as functions of supply voltage and load capacitance.

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    This document provides data sheets for the HEF4025B triple 3-input NOR gate integrated circuit from Philips Semiconductors. It includes descriptions of the IC, its pinning diagram, logic diagram, and family specifications. It also provides typical and maximum values for the IC's propagation delays, output transition times, and dynamic power dissipation as functions of supply voltage and load capacitance.

    Copyright:

    © All Rights Reserved
    Download as PDF, TXT or read online from Scribd
    Download as pdf or txt
    21 views3 pages

    Hef4025b PDF

    Uploaded by

    GoodLookingPirate
    This document provides data sheets for the HEF4025B triple 3-input NOR gate integrated circuit from Philips Semiconductors. It includes descriptions of the IC, its pinning diagram, logic diagram, and family specifications. It also provides typical and maximum values for the IC's propagation delays, output transition times, and dynamic power dissipation as functions of supply voltage and load capacitance.

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    © All Rights Reserved
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    You are on page 1of 3

    INTEGRATED CIRCUITS

    DATA SHEET
    For a complete data sheet, please also download:

    • The IC04 LOCMOS HE4000B Logic


    Family Specifications HEF, HEC
    • The IC04 LOCMOS HE4000B Logic
    Package Outlines/Information HEF, HEC

    HEF4025B
    gates
    Triple 3-input NOR gate
    Product specification January 1995
    File under Integrated Circuits, IC04
    Philips Semiconductors Product specification

    HEF4025B
    Triple 3-input NOR gate
    gates

    DESCRIPTION
    The HEF4025B provides the positive triple 3-input NOR
    function. The outputs are fully buffered for highest noise
    immunity and pattern insensitivity of output impedance.

    Fig.2 Pinning diagram.

    HEF4025BP(N): 14-lead DIL; plastic


    (SOT27-1)
    HEF4025BD(F): 14-lead DIL; ceramic (cerdip)
    (SOT73)
    HEF4025BT(D): 14-lead SO; plastic
    Fig.1 Functional diagram.
    (SOT108-1)
    ( ): Package Designator North America

    Fig.3 Logic diagram (one gate).

    FAMILY DATA, IDD LIMITS category GATES


    See Family Specifications

    January 1995 2
    Philips Semiconductors Product specification

    HEF4025B
    Triple 3-input NOR gate
    gates

    AC CHARACTERISTICS
    VSS = 0 V; Tamb = 25 °C; CL = 50 pF; input transition times ≤ 20 ns

    VDD TYPICAL EXTRAPOLATION


    SYMBOL TYP. MAX.
    V FORMULA
    Propagation delays
    In → On 5 70 135 ns 43 ns + (0,55 ns/pF) CL
    HIGH to LOW 10 tPHL 25 55 ns 14 ns + (0,23 ns/pF) CL
    15 20 40 ns 12 ns + (0,16 ns/pF) CL
    5 60 120 ns 33 ns + (0,55 ns/pF) CL
    LOW to HIGH 10 tPLH 25 50 ns 14 ns + (0,23 ns/pF) CL
    15 15 35 ns 7 ns + (0,16 ns/pF) CL
    Output transition times 5 60 120 ns 10 ns + (1,0 ns/pF) CL
    HIGH to LOW 10 tTHL 30 60 ns 9 ns + (0,42 ns/pF) CL
    15 20 40 ns 6 ns + (0,28 ns/pF) CL
    5 60 120 ns 10 ns + (1,0 ns/pF) CL
    LOW to HIGH 10 tTLH 30 60 ns 9 ns + (0,42 ns/pF) CL
    15 20 40 ns 6 ns + (0,28 ns/pF) CL

    VDD
    TYPICAL FORMULA FOR P (µW)
    V
    Dynamic power 5 900 fi + ∑ (foCL) × VDD 2 where
    dissipation per 10 4000 fi + ∑ (foCL) × VDD 2 fi = input freq. (MHz)
    package (P) 15 10 900 fi + ∑ (foCL) × VDD 2 fo = output freq. (MHz)
    CL = load capacitance (pF)
    ∑ (foCL) = sum of outputs
    VDD = supply voltage (V)

    January 1995 3

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