8086 MIN AND MAX MODE

C O U R S E C O O R D I N AT O R D E E PA L I G H O R PA D E

COURSE CODE BM 502 MICROCONTROLLER AND BIOELECTRONICS

MEMORY BANKING

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COURSE CODE BM 502 2

8086 MEMORY BANKING

࡮ࡴࡱ A0
0 0 2byte D0-D15
0 1 MSB ,ODD ,D8-D15
1 0 LSB,EVEN, D0-D7
1 1 IDLE

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COURSE CODE BM 502 3

PIN CONFIGURATION

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8282 LATCH and 8286 TRANSRECEIVER

Latches are single bit storage elements which are
widely used in computing as well as data storage.

The 8282 is 8-bit latch, hence total three 8282
latches are required for 20-bit address.

If OE (Output Enable) is connected to GND, the chip is
selected. STB (Strobe) is connected to the pin ALE
(Address Latch Enable) of the processor and takes over
the address data from the multiplexed address-
/databus.

A Transceiver can be used to provide bidirectional,
input or output control, of either digital or analogue
devices to a common shared data bus.

8286 is 8bit bidirectional Bus transreceiver , hence
total two are required for 16bit data bus of 8086

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COURSE CODE BM 502 5

8282 LATCH and 8286 TRANSRECEIVER

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COURSE CODE BM 502 6

8086 INTERFACING

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PIN CONFIGURATION

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PIN CONFIGURATION

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CLOCK : MACHINE : INSTRUCTION CYLES
Clock cycle:
The clock cycle is the amount of time between two pulses of an oscillator. It is a single increment of the
central processing unit (CPU) clock during which the smallest unit of processor activity is carried out.
Generally speaking, the higher number of pulses per second, the faster the computer processor will be
able to process information. The clock speed is measured in Hz, typically either megahertz (MHz) or
gigahertz (GHz). For example, a 4GHz processor performs 4,000,000,000 clock cycles per second.
Machine cycle:
It is the time required to complete one operation of accessing memory/ I/o, either Memory write,
Memory Read, I/o read or I/O write, opcode fetch
Instruction Cycle:
Instruction cycle is the time required to complete the execution of an instruction . It consist of fetch and
Execute Cycle.
CLOCK : MACHINE : INSTRUCTION CYLES
CLOCK : MACHINE : INSTRUCTION CYLES

COURSE CODE BM 502 12

8086 BUS OPERATION

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8086 BUS OPERATION

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DIRECT MEMORY ACCESS

DMA stands for Direct Memory Access. It is
designed by Intel to transfer data at the fastest
rate. It allows the device to transfer the data
directly to/from memory without any interference
of the CPU.

Using a DMA controller, the device requests the
CPU to hold its data, address and control bus, so
the device is free to transfer data directly to/from
the memory. The DMA data transfer is initiated
only after receiving HLDA signal from the CPU.

DMA can save processing time and is a more
efficient way to move data from the computer's
memory to other devices.

For example, a sound card may need to access
data stored in the computer's RAM, but since it
can process the data itself, it may use DMA to
bypass the CPU.

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COURSE CODE BM 502 15

PIN CONFIGURATION
Pins Pin no Signal Description
VCC 40 DC supply +5v
GND 1 & 20 Ground
CLK 19 Clock signal Provides the basic
timing signals for the
8086 and bus controls .
AD0-AD15 2 - 16 Address/Data bus During the first clock
Low order cycle, it carries 16-bit
address bus. address and after that it
carries 16-bit data.
AD0-AD7 low order byte
data

AD8-AD15 higher order byte

data.
PIN CONFIGURATION
Pins Pin no Signal Description QS0 QS1 STATUS
A16-A19/ 35-38 Address(High During the first clock cycle, it 0 0 No operation.
S3-S6 order address carries 4-bit address and During the last clock cycle, nothing
bus. )/ status later it carries status signals.
was taken from the queue.
bus
QS1 and QS0 24 and Queue status 0 1 First Byte. The byte taken from the
25 queue was the first
byte of the instruction..
SEGMENT
S4 S3 1 0 Empty the queue.
ACCESSED
The queue has been reinitialized
0 0 Extra as a result of the execution of a
0 1 Stack
transfer instruction.

1 0 Code 1 1 Subsequent Byte. The byte taken

from the queue was a subsequent
1 1 Data
byte of the instruction.
PIN CONFIGURATION
Pins Pin no Signal Description
It indicates what mode the
MN/ࡹࢄ Minimum/ processor is to operate in; when it
33
Maximum is high, it works in the minimum
mode and vice-versa.
A high on the HOLD pin indicates
that another master is required to
HOLD 31
take over the S/M This is an active
high(1).
HOLD This signal acknowledges the
HLDA 30 acknowledgement HOLD signal.

It is the It is an active high signal. When it

acknowledgement is high, it indicates that the device
from the addressed is ready to transfer data. When it
READY 22 memory or I/O is low, it indicates wait state.
device that it will
complete the data
transfer.
PIN CONFIGURATION
Pins Pin no Signal Description
Read signal It is an output signal. It is active
RD 32
when low.
Write It is used to write the data into
the memory or the output device
ܹܴ 29
depending on the status of M/IO
signal.
Data Transmit/ High - data is transmitted out
DT/ܴത 27 Receive and vice-a-versa.

Data Enable It is used to enable Trans receiver

‫ܰܧܦ‬ 8286. The trans receiver is a
26
device used to separate data from
the address/data bus.
Memory and Low – Memory Operation
M/‫ܱܫ‬ I/O operations High – I/O operation
28
PIN CONFIGURATION
Pins Pin no Signal Description

S7/࡮ࡴࡱ 34 Bus Indicate the transfer of data using data bus

High D8-D15. This signal is low during the first
Enable clock cycle, thereafter it is active. BHE can
be used in conjunction with AD0 to select
the memory

ࡸࡻ࡯ࡷ 29 When signal is active ,It indicates that

other processors are not allowed to gain
control of the system bus). The LOCK signal
will be active until the completion of the
next instruction. It is activated using LOCK
prefix on any instruction and is available at
pin 29

ࡾࡽ/ࡳࢀ૙ 31 Reques used by the other processors requesting

t/Grant the CPU to release the system bus. When
ࡾࡽ/ࡳࢀ૚ 30 . the signal is received by CPU, then it sends
acknowledgment. RQ/GT0 has a higher
priority than RQ/GT1.
PIN CONFIGURATION
Pins Pin no Signal Description
INTA 24 Interrupt When the microprocessor receives this signal, it acknowledges the interrupt.
Acknowledgement
INTR 18 Interrupt Request This is triggered input. This is sampled during the last clock cycles of each
instruction for determining the availability of the request. If any interrupt request
is found pending, the processor enters the interrupt acknowledge cycle. This can
be internally masked after resulting the interrupt enable flag. This signal is active
high(1) and has been synchronized internally.

ࢀࡱࡿࢀ 23 This examined by a ‘WAIT’ instruction. If the TEST pin is low(0), execution will
continue, else the processor remains in an idle state. The input is internally
synchronized during each of the clock cycle on leading edge of the clock.

NMI 17 Non-Maskable It is an edge triggered input, which causes an interrupt request to the
Interrupt microprocessor.
PIN CONFIGURATION
Pins Pin no Description
RESET 21 Reset causes the processor to immediately terminate its present activity.
To be recognized, the signal must be active high for at least four clock cycles,
except after power-on which requires a 50 Micro Sec. pulse.
It causes the 8086 to initialize registers DS, SS, ES, IP and flags to all zeros. It
also initializes CS to FFFF H.
Reset active Status Upon removal of the RESET signal from the RESET pin, the 8086 will fetch its
CS FFFFH next instruction from the 20 bit physical address FFFF0H.
The reset signal to 8086 can be generated by the 8284. (Clock generation
DS 0000H
chip).
ES 0000H
To guarantee reset from power-up, the reset input must remain below 1.5
SS 0000H volts for 50 Micro sec. after Vcc has reached the minimum supply voltage of
IP 0000H 4.5V.
PIN CONFIGURATION
Pins Pin no Signal Description
S0, S1, S2 26,27,28 Status used by the Bus Controller 8288 to
generate memory & I/O control signals.

S2 S1 S0 Status
0 0 0 Interrupt acknowledgement
0 0 1 I/O Read
0 1 0 I/O Write
0 1 1 Halt
1 0 0 Opcode fetch
1 0 1 Memory read
1 1 0 Memory write
1 1 1 Passive (no bus activity)
THANK YOU

COURSE CODE BM502 24