What Is Callback?: Systemverilog&Uvm Interview Questions
What Is Callback?: Systemverilog&Uvm Interview Questions
What Is Callback?: Systemverilog&Uvm Interview Questions
1. What is callback?
Callback is mechanism of changing to behavior of a verification component such as driver or
generator or monitor without actually changing to code of the component. It's used for
functional coverage, inject errors and output transaction in a scoreboard.
class abc_transactor;
virtual task pre_send();
endtask
virtual task post_send();
endtask
task xyz();
this.pre_send();
this.post_send();
endtask : xyz
endclass : abc_transactor
(3.2)wr_monitor,
//Need to declare the callback first
wif_wr_data_callbacks wr_data_cbs;
`vmm_callback(wif_wr_data_callbacks, post_tx(pkt));
(3.3)mvc_scoreboard,
//Need to declare and define the function
function mvc_scoreboard::save_expected_packet(data_to_sb wr_pkt);
(3.4)in UVM,
class uvm_callbacks #(
type T = uvm_object,
type CB = uvm_callback
) extends uvm_typed_callbacks#(T)
Now we are done with the bothering about the objects to be created. The next problem that
we need to solve is to write the toy factory class itself. For simplicity, let's consider the case
where we will want to pass 1 to get an instance of tank class and 2 for getting an instance of
bus class from the factory. Now the factory class will look like this.
class TOY_factory;
Toy my_toy
// Common methods
function toy get_toy(int type);
if(type == 1)
this.my_toy = new TOY_Tank();
if(type == 2)
this.my_toy = new TOY_Bus();
return this.my_toy;
endfunction
endclass
Note that we are using virtual function for bringing polymorphism in action and save us from
having an individual instance of the toy type in the factory class.
3. Explain the difference between data types logic and reg and wire
Wire:-
1. Wires are used for connecting different elements
2. They can be treated as a physical wire
3. They can be read or assigned
4. No values get stored in them
5. They need to be driven by either continuous assign statement or from a port of a module
Reg:-
1. Contrary to their name, regs doesn't necessarily corresponds to physical registers
2. They represents data storage elements in Verilog/SystemVerilog
3. They retain their value till next value is assigned to them (not through assign statement)
4. They can be synthesized to FF, latch or combinational circuit (They might not be
synthesizable !!!)
Logic:-
1. Reg/Wire data type give X if multiple driver try to drive them with different value. logic
data cannot be driven by multiple structural drivers, In this case, the variable needs to be a
net-type such as wire/tri
2. SystemVerilog improves the classic reg data type so that it can be driven by continuous
assignments, gates, and modules, in addition to being a variable
5. What are the ways to avoid race condition between testbench and RTL using
SystemVerilog?
Likewise, initial blocks within program blocks are scheduled in the Reactive region; in
contrast, initial blocks in modules are scheduled in the Active region. In addition, design
signals driven from within the program must be assigned using non-blocking assignments and
are updated in the re-NBA region. Thus, even signals driven with no delay are propagated
into the design as one event. With this behavior, correct cycle semantics can be modeled
without races, thereby making program-based testbenches compatible with clocked assertions
and formal tools.
Programs that read design values exclusively through clocking blocks with #0 input skews are
insensitive to read-write races. It is important to understand that simply sampling input
signals (or setting nonzero skews on clocking block inputs) does not eliminate the potential
for races. Proper input sampling only addresses a single clocking block. With multiple clocks,
the arbitrary order in which overlapping or simultaneous clocks are processed is still a
potential source for races. The program construct addresses this issue by scheduling its
execution in the Reactive region, after all design events have been processed, including clocks
driven by non-blocking assignments.
6. What are the types of coverage available in SV ?
(1. Code Coverage: Here you are measuring how many lines of code have been executed (line
coverage), which paths through the code and expressions have been executed (path coverage),
which single bit variables have had the values 0 or 1 (toggle coverage), and which states and
transitions in a state machine have been visited (FSM coverage). Code coverage measures
how thoroughly your tests exercised the “implementation” of the design specification, and not
the verification plan.
(2. Functional Coverage: Functional coverage is tied to the design intent and is sometimes
called “specification coverage,” while code coverage measures the design implementation.
(3. Assertion coverage: We can measure how often these assertions are triggered during a test
by using assertion coverage. A cover property observes sequences of signals, whereas a cover
group (described below) samples data values and transactions during the simulation
(2 pre_randomize
(3 post_randomize
import ABC::Color;
import ABC::*; // Import everything inside the package
25. Without using randomize method or rand, generate an array of unique values?
int UniqVal[10];
foreach(UniqVal[i])
UniqVal[i] = i;
UniqVal.shuffle();
The second benefit of ref arguments is that a task can modify a variable and is
instantly seen by the calling function. This is useful when you have several threads
executing concurrently and want a simple way to pass information. See Chap. 7 for
more details on using fork-join.
28. What is the difference between bit[7:0] sig_1; and byte sig_2;
byte is signed whereas bit [7:0] is unsigned.
Modports are part of Interface. Modports are used for specifing the direction of the signals
with respect to various modules the interface connects to.
interface my_intf;
wire x, y, z;
modport master (input x, y, output z);
modport slave (output x, y, input z);
endinterface
covergroup cg;
cover_point_y : coverpoint y {
option.auto_bin_max = 4 ; }
endgroup
cg cg_inst = new();
initial
foreach(values[i])
begin
y = values[i];
cg_inst.sample(); //gather coverage
end
endprogram
45. How to add a new process without disturbing the random number generator state?
constraint_mode()
46. What is the need of alias in SV?
The Verilog has one-way assign statement is a unidirectional assignment and can contain
delay and strength change. To have bidirectional short-circuit connection SystemVerilog has
added alias statement
module byte_rip (inout wire [31:0] W, inout wire [7:0] LSB, MSB);
alias W[7:0] = LSB;
alias W[31:24] = MSB;
endmodule
47. How can I model a bi-directional net with assignments influencing both source and
destination?
The assign statement constitutes a continuous assignment. The changes on the RHS of the
statement immediately reflect on the LHS net. However, any changes on the LHS don't get
reflected on the RHS. System Verilog has introduced a keyword alias, which can be used only
on nets to have a two-way assignment. For example, in the following code, any changes to the
rhs is reflected to the lhs , and vice versa.
module test ();
wire rhs, lhs;
alias lhs=rhs;
endmodule
48. What is the need to implement explicitly a copy() method inside a transaction , when we
can simple assign one object to other ?
If you assign one object to other then both the handles will point to the same object. This
will not copy the transaction. By defining copy(), we can use the deep copy but not the
shallow copy.
my_struct_s st = '{
32'haaaa_aaaad,
8'hbb,
16'hcccc,
32'hdddd_dddd
};
$display("str = %x %x %x %x ", st.a, st.b, st.c, st.d);
end
Union
Unlike structures, the components of a union all refer to the same location in memory. In this
way, a union can be used at various times to hold different types of objects, without the need
to create a separate object for each new type.
typedef union { int i; real f; } num_u;
num_u un;
un.f = 0.0; // set value in floating point format
Unions are useful when you frequently need to read and write a register in several different
formats. But class is more oftenly used.
56. What is advantage of program block over clock block w.r.t race condition?
Program schedules events in the Reactive region, the clocking block construct is very useful
to automatically sample the steady-state values of previous time steps or clock cycles.
Programs that read design values exclusively through clocking blocks with #0 input skews are
insensitive to read-write races, for single clock.
63. What data structure is used to store data in your environment and why ?
Mailbox or queue. Because especially for the scoreboard, for each cycle, we have to collect
data and drop these data from the driver and monitor respectively. Therefore, queue or
mailbox would be more convenient than array.
64. Explain how the timescale unit and precision are taken when a module does not have any
time scalar declaration in RTL?
In SV
timeunit 100ps;
timeprecision 10fs;
is as same as `timescale 100ps/10fs in Verilog
If a timeunit is not specified in the module, program, package, or interface definition, then the
time unit shall be determined using the following rules of precedence:
a) If the module or interface definition is nested, then the time unit shall be inherited from the
enclosing module or interface (programs and packages cannot be nested).
b) Else, if a `timescale directive has been previously specified (within the compilation unit),
then the time unit shall be set to the units of the last `timescale directive.
c) Else, if the compilation-unit scope specifies a time unit (outside all other declarations), then
the time unit shall be set to the time units of the compilation unit.
d) Else, the default time unit shall be used.
67. How to make sure that a function argument passed has ref is not changed by the function?
const ref
68. What is the difference between initial block and final block?
(1. the most obvious one: Initial blocks get executed at the beginning of the simulation, final
block at the end of simulation
(2. Final block has to be executed in zero time, which implies it can't have any delay, wait, or
non-blocking assignments.
(3. Final block can be used to display statistical/general information regarding the status of
the execution
Ans: Code specified in program blocks and pass/fail code from property expressions are
scheduled in reactive scheduler.
Ans: In an always block which is used to model combinational logic. forgetting an else leads
to an unintended latch. To avoid this mistake, SystemVerilog adds specialized
Ans: There are two terminologies associated with the arrays in systemverilog. Packed and
unpacked arrays. When the dimensions of arrays are declared before the object name is
referred to as packed arrays. The unpacked array term is used to refer when the dimensions
are declared after the object name. The memory allocation of both packed and unpacked
arrays also differs.
E.g.: int [7:0] c1; //packed array
reg r[7:0] //unpacked array
Ans: Assertions are mainly used to check the behavior of the design whether it is working
correctly or not. They are useful in providing the functional coverage information .i.e. how
good the test is and whether the design meets all the requirements for testing. There are
mainly two types of assertions in systemverilog. They are: immediate assertions and
concurrent assertions.
78. What is the difference between code coverage and functional coverage?
Ans: Functional coverage: Functional coverage determines how much functionality of the
design has been exercised. Functional assertions are used to check whether each and every
corner of the design is explored and functions properly. Code coverage: This will give
information about how many lines are executed, how many times each expression is executed.
It describes the level up to which the code has been tested.
79. If the functional coverage is more that code coverage, what does it means?
Ans: code: High functional: High - You are most likely done
code: High functional: Low - Still need to run more simulation or improve test bench
code: Low functional: High - Probably missing functional coverage points
code: Low functional: Low - Still need to run more simulation or improve test bench
80. How we can have #delay which is independent of time scale in system verilog?
Ans: Random constraints, user defined constraints, inline constraints, if-else constraints and
global constraints.
Ans: If the given expression is true, all the constraints in the first constraint block should be
satisfied, otherwise all of the constraints in the else constraint block will be satisfied.
Ans: Mailbox is similar to a queue, which allows only atomic operations. They can be
bounded/unbounded. Get/put/peek task is used to suspend a bounded mailbox. That's why
mailbox is used more for communication between threads. Queues are large structures.
Inserting data in queues is very difficult.
84. What is the significance of super keyword?
Ans: The super keyword is used from the derived class to refer to the members of the base
class. If we want to access members of base class that are overridden by the derived class,
super keyword is used. Super keyword cannot be accessed directly.
Ans: Skews are numbers that are indicated before the input and output ports. A skew number
indicated before an input defines that the input is sampled before the clocking event occurs, ie
a posedge or negedge occurs. A skew number in the output indicates that the output is
synchronized and then sent to the clocking blocks. A skew must be a constant expression. It
can also be specified as a parameter.
Ans: The main purpose of dividing the time slots in systemverilog is to provide interaction
between the design and the testbench.
Ans: In systemverilog we can create a static variable inside the class. But this variable has a
limited scope. The variable declared static is shared among the other variables in the class. A
static variable is usually instantiated inside the declaration.
88. In simulation environment under what condition the simulation should end?
Ans: Objects in systemverilog can be declared as public and private. Public declarations are
accessible from outside that object, i.e. they are accessible by the users. By default
declarations in systemverilog are public
Ans: In order to make the declarations private, local attribute is used. Once the data is
declared as local, it can be accessed on in the particular class.
Ans. Chandle is a data type used to store pointers passed from DPI. Size of the chandle is
machine dependent. Initialized value of the chandle is null. It can be used to pass arguments
to functions or tasks.
94. What are the features added in systemverilog for function and task?
Ans: Begin and end not required. Function can have any number of input, output and inouts
including none. Return can be used in task. Function return can have void return type.
Ans: Captures result from a random stimulation. Encapsulates the coverage specification.
Ex: enum { red, green, blue } color;
bit [3:0] pixel;
covergroupg1 @ (posedgeclk);
coverpoint color;
coverpoint pixel;
AxC: cross color, pixel;
endgroup
Ans : Creating the real time environment for the (DUT ) to check its performance in real time.
The verification plan closely tied with the hardware specification and contains a description
of what features need to be verified.
Contains:
Directed testing
Random testing
Assertion
Hardware and software co-verification
Use of verification IP
101. Explain how messages are handled?
Ans: The parameter value can be changed during execution but not in the case of define
construct/macros.
Ans: Associative arrays basically used for very large memories. They have feature of string
indexing. They executes at compile time.
Value is assigned to dynamic array at run time. New constructor is used to initialize the size
of dynamic array.
Ans: Immediate assertion is basically a statement that something must be true, similar to if
statement.
If assert evaluates to X, Z or 0, then the assertion fails and the simulator writes an error
message.
my_assert:assert(condition1 & condition2)
$display("Passed..");
else
$error("Failed..");
107. What are Assertion severity system level task? What happens if we won't specify these
tasks?
Ans : When we set property and if we won't specify failure case of the property, then by
default language dictates simulator should give error as $error severity level.
$fatal - Run time fatal (quit Simulation)
$error - Run time error.
$warning ? Run time warning
$info ? Means this assertion carries no specific severity.
Ans: The variables used in a concurrent assertion are sampled in the Pre-poned region of a
time slot and the assertions are evaluated during the Observe region. Both these regions occur
immediately before a clock edge.
Ans : This operator specifies that an expression will match the number of times specified not
necessarily on continuous clock cycles.
Ex: x [->4:7]
x has been true 4, 5, 6 or 7 times, not necessarily on consecutive clocks.
Ans : local
Ans : Sometimes we use loop that spawns threads and we don't save variable values before
the next iteration. We should use the automatic variables inside a fork join statement to save
the copy of a variable. Key word automatic create a copy of variable in each loop, cuz the
stock/fifo storage mechanism.
example,
Sample 3.22 Specifying automatic storage in program blocks
program automatic test;
task wait_for_mem(input [31:0] addr, expect_data,
output success);
while (bus.addr !== addr)
@(bus.addr);
success = (bus.data == expect_data);
endtask
...
endprogram
You can call this task multiple times concurrently, as the addr and expect_data arguments are
stored separately for each call. Without the automatic modifier, if you called wait_for_mem a
second time while the first was still waiting, the second call would overwrite the two
arguments.
Packed array:
For some data types, you may want both to access the entire value and also to divide it into
smaller elements. A SystemVerilog packed array is treated as both an array and a single
value. It is stored as a contiguous set of bits with no unused space, unlike an unpacked array.
The packed bit and array dimensions are specified as part of the type, before the variable
name.
bit [3:0] [7:0] bytes; // 4 bytes packed into 32-bits
bytes = 32'hCafe_Dada;
With a single subscript, you get a word of data, barray[2]. With two subscripts, you
get a byte of data, barray[0][3]. With three subscripts, you can access a single bit,
barray[0][1][6].
120. Queue
Like a linked list, you can add or remove elements anywhere in a queue, without the
performance hit of a dynamic array that has to allocate a new array and copy the entire
contents. Like an array, you can directly access any element with an index, without linked
list’s overhead of stepping through the preceding elements.
int j, q2[$] = {3,4}, q[$] = {0,2,5};// Queue literals do not use '
bit [4:0] ack_que[$];
initial begin
q.insert(1, j); // {0,1,2,5} Insert 1 before 2
q.insert(3, q2); // {0,1,2,3,4,5} Insert queue in q1
q.delete(1); // {0,2,3,4,5} Delete elem. #1
// These operations are fast
q.push_back(8); // {0,2,3,4,8} Insert at back
j = q.pop_front; // {2,3,4,8} j = 0
j = q[$]; //j=8
foreach (q[i])
$display(q[i]); // Print entire queue
q.delete(); // {} Delete entire queue
end
(3Global Variable
-Defined under $root (outside any module)
-Must be static
-Accessible from anywhere
-Task and function can be global
(4 Local Variable
-Default to static. Can be automatic
-Accessible at where they are defined and below
-Accessible through hierarchical path
initial begin
parent p;
child c;
c = new();
p = c;
c.display_c(); //result: Child Child
p.display_c(); //result:Parent Child
end
Comments: (1.without virtual function declared in the parent class, although the "p" points to
the handle of "c", it's not allowed to call the function in the child class. With virtual, p can
access to the child class's method. (2 if several child classes define the "display_c()" by the
same name, it is called polymorphism.
(2
virtual class parent;
pure virtual task display_c();
endclass
initial begin
parent p[2];
p[0] = new(); //illegal
child1 c1 = new();
child2 c2 = new();
p[0] = c1;
p[1] = c2;
foreach(p[i]) begin
p[i].display_c();
end
Comments: Assigning virtual class's handle to child object is also a way of polymorphsim.
129. 1) What if design engineer and verification engineer do the same mistake in Test bench
BFM (Bus Functional Model) and RTL (DUT)? How can you able to detect errors?
Answer:
1. Code reviews & protocol checkers
2. IP gets verified in multiple environmentslike block level test bench, out of box
testbench (connecting DUT back to back) , fullfledged testbench using proven BFM, SoC
level testbench using processor and all that etc... This all environments SHOULD be executed
by different persons and so you should be able to catch that bug in one of this testbench.
3. Customer will catch the problem (worst case)
2) If you got a failure from the customer, how do you debug this? How do you prevent it to
happen again?
Answer:
1. first, try to reproduce the problem in your own environment. Try to get customer's
vector, so you can inject the same vector to create the problem in house.
2. If you confirm the problem and fix them, you should put the new assertion or test to
catch the problem again. Add this new test in the future test plan, so the problem will not happen again.
In pass by reference functions and tasks directly access the specified variables passed as
arguments.Its like passing pointer of the variable.
1. $range = 100000000;
$random_number = int(rand($range));
+ntb_random_seed = $random_number; ##doesn’t apply to Verilog $random
2. +ntb_random_seed_automatic
132. How to call the task which is defined in parent object into derived class ?
Answer:
The super keyword is used from within a derived class to refer to members of the parent
class. It is necessary to use super to access members of a parent class when those
members are overridden by the derived class
133. What is the difference between function overloading and function overriding?
A. Overloading is a method that allows defining multiple member functions with the
same name but different signatures. The compiler will pick the correct function based on
the signature. Overriding is a method that allows the derived class to redefine the
behavior of member functions which the derived class inherits from a base class. The
signatures of both base class member function and derived class member function are the
same; however, the implementation and, therefore, the behavior will differ
134. What's the difference between data type logic, reg and wire?
$display //will give you compile error (dynamic type cannot be used at LHS of non-
blocking assignment, as here is automatic type), you cannot use $strobe in program, it
will crushed.
static int a = 1;
a = 2;
a<=3;
137. Class can have module(to force the signals through hierarchy), module can also have
class instant. (refer to 150)
Program cannot have module, interface, or other program; module can include program
Program can instant class, cannot instant other program, class cannot instant program
Program is the link between test-bench (class) and design (module)
a = new;
a.a_m = 40;
b = new a; //function new will not copy
b.a_m = 50; //a and b point to different handle but share the same a_m.
//a_m will be 50
a = new;
b = a; //b and a point to the same handle
a = new; //b point to the first handle, a point to the second one
Class B extends A;
Constraint key_con {a ==5;} //overwrite should use the same name
…
endclass
…
A a = new;
Assert(!a.randomize(with {a == 7})) //will give you compile error
Build_phase
141. In uvm
In driver, how do you do pipelining?
Answer:
In systemverilog, you are using mailbox
In UVM, you should explicitly build queues to do pipelining.
Reference
1. http://www.asic-world.com/
2. http://www.testbench.in/
3. SystemVerilog for Verification: A Guide to Learning the Testbench Language
Features by Chris Spear
scenarios.
2. FSM for number divisible by 3 .
3. UVM subscriber, sequences, TLM ports and FIFO.
4. write code for random number generation for given
distribution and ranges.
5. byte addressing in an integer memory system.
6. . constrain for non-overlapping segment-addresses
generation.
7. Explain any testbench architecture you have worked on.
8. Lots of simple questions to test SystemVerilog and OOP
concepts.
What is the difference between new () and new []?
- A new() is used for constructing object whereas new[] is used to declare a dynamic array.
- A constructor function does not have a return type. When you use a constructor, the left
hand side of the assignment determines the return type.
Myths and misconception surrounding constructors are abound. We will try to disspell some
of them here.
"I must have a constructor for each class that I define."
It is not illegal not to have a constructor for each class, though having one will be a
good practice for your peace of mind.
Although it is customary to name a constructor as 'new', any other name is fine too.
Triangle t = my_new();
On the contrary, it is always a good idea to make your constructor flexible by passing
arguments to it. For example, we can customize our own new() defined
within Triangle as:
Refer https://pcisig.com/faq?field_category_value%5B%5D=pci_express_3.0&keys=
For PCIe question answers
The PLL generates the PCLK used in synchronizing the parallel PHY/MAC Interface based
on the CLK input. The PCLK frequency is 125 MHz for 16-bit implementations and 250
MHz for 8-bit implementations. The PLL will produce a 250 MHz clock used as an input to
the 8B/10B encoder and decoder and the elastic buffer. The PLL will produce a 2.5 GHz clock
that is used as an input to the SERDES and the clock recovery circuitry.
How does the PCIe 3.0 8GT/s "double" the PCIe 2.0 5GT/s bit rate?
- The PCIe 2.0 bit rate is specified at 5GT/s, but with the 20 percent performance overhead
of the 8b/10b encoding scheme, the delivered bandwidth is actually 4Gbps. PCIe 3.0
removes the requirement for 8b/10b encoding and uses a more efficient 128b/130b
encoding scheme instead. By removing this overhead, the interconnect bandwidth can be
doubled to 8Gbps with the implementation of the PCIe 3.0 specification. This bandwidth
is the same as an interconnect running at 10GT/s with the 8b/10b encoding overhead. In
this way, the PCIe 3.0 specifications deliver the same effective bandwidth, but without the
prohibitive penalties associated with 10GT/s signaling, such as PHY design complexity
and increased silicon die size and power. The following table summarizes the bit rate and
approximate bandwidths for the various generations of the PCIe architecture: PCIe
architecture Raw bit rate Interconnect bandwidth Bandwidth per lane per direction Total
bandwidth for x16 link
- When CS is low and R / W are high, the memory chip drives the data bus with the data
from the location indicated by the address bus. This allows the microprocessor to load
data out of memory into registers.
- A virtual sequence does not itself interact with a sequencer, it can be started without a
sequencer.
- Virtual sequences are typically used to coordinate the behavior of multiple agents (though
strictly speaking a sequence that coordinates multiple agents need not be a virtual
sequence.
- In the 1st approach, Virtual Sequence will contain itself the handles of the Agent’s
Sequencers on which the Sub-Sequences are to be executed.
- In the 2nd approach, Virtual Sequence will run on a Virtual Sequencer which is of type
uvm_sequencer. In this approach, Virtual Sequencer will contain the target Agent
Sequencer’s handle.
http://www.learnuvmverification.com/index.php/2016/02/23/how-virtual-sequence-works-
part-1/
Write (method) — a method that is called through an analysis port and implemented within a
component that has an analysis imp. The implementation of the method write typically
performs checking or functional coverage collection.
PVIP questions
How to off copy and compare or methods in uvm?
- Using uvm_field_* macros define transaction required methods. So use UVM_NOPACK
for excluding atomic creation of packing and unpacking method.
- `uvm_field_int(length, UVM_ALL_ON|UVM_NOPACK)
The `uvm_field_* macros are invoked inside of the `uvm_*_utils_begin and `uvm_*_utils_end
(`uvm_object_utils_begin or `uvm_component_utils_begin) macro blocks to form “automatic”
implementations of the core data methods: copy, compare, pack, unpack, record, print, and sprint.
`uvm_field_int(ARG,FLAG)
ARG is an integral property of the class, and FLAG is a bitwise OR of one or more flag settings as
described in Field Macros above.
UVM_ALL_ON Set all operations on (default).
- Packs the integral value (less than or equal to 64 bits) into the pack array. The size is
the number of bits to pack, usually obtained by $bits.
- packer.pack_field_int(da,$bits(da));
Mobiveil questions
Different ways to start sequence.
Difference between `uvm_do and `uvm_do_on_with
- `uvm_do we simply pass the sequence or item whereas in `uvm_do_on_with we need to
pass sequence, sequencer and constraints.
Handshake mechanism between sequencer and driver
How to get response from driver
Is it possible to connect sequencer and driver with analysis ports and scoreboard and monitor
with seq_item_port/export ?
- No. The seq_item_port is used exclusively for the sequencer/driver. The methods
contained within the seq_item_port are usable only by sequences and not meant for any
other use.
- The seq_item_port is a specific type of port which allows bi-directional communication
between the sequencer and driver. There are several additional methods provided by it
which enable sequences to function.
Types of responses in AXI
Initial blocks get executed at the beginning of the simulation, final block gets
executed at the end of simulation
Final block has to be executed in zero time, which implies it can’t have any delay,
wait, or non-blocking assignments. Initial block doesn’t have any such restrictions of
execution in zero time (and can have delay, wait and non-blocking statements)Final block can
be used to display statistical/general information regarding the status of the execution like this
Program
1.final begin
2.$display(“Simulation Passed”);
3.$display(“Final value of xyz = %h”,xyz);
4.$display(“Bye :: So long, and Thanks for all the fishes”);
5.end
Build Phase
– Generate configuration : Randomize the configuration of the DUT and surrounding
environment
– Build environment : Allocate and connect the testbench components based on the
configuration.
A testbench component is one that only exists in the testbench, as opposed to physical
components in the design that are built with RTL.
– Reset the DUT
– Configure the DUT : Based on the generated configuration from the first step, load the DUT
command registers
Run Phase
– Start environment : Run the testbench components such as BFMs and stimulus generators
– Run the test : Start the test and then wait for it to complete. It is easy to tell when a directed
test has completed, but doing so can be complex for a random test. You can use the testbench
layers as a guide. Starting from the top, wait for layer to drain all the inputs from the previous
layer (if any), wait for the current layer to become idle, and wait for the next lower layer.
You should use time-out checkers to make sure the DUT or testbench does not lock up.
Wrap-up Phase
– Sweep : After the lowest layer completes, you need to wait for the final transactions to drain
out of the DUT.
– Report : Once DUT is idle, sweep the testbench for lost data. Sometimes the scoreboard
holds the transactions which never came out, perhaps because they were dropped by the
DUT. Armed with this information, you can create the final report on whether the test passed
or failed. If it failed, be sure to delete any functional coverage results, as they may not be
correct.
23. What is the Difference between SystemVerilog packed and unpacked array?
Dimension declared before the object in packed array and in unpacked it is assigned after
the object
A packed array is represented in a memory as a contiguous set of bits.
Alias is system verilog coding technique to model bi-directional mapping for 'inout' ports or
wires in a module. In particular, alias mapping is direct connection of one inout port to other.
In other way, its a short-circuit of wires.
Associative arrays are better to model large arrays as memory is allocated only when an entry
is written into the array. Dynamic arrays on the other hand need memory to be allocated and
initialized before using.
For example: If you want a memory array of 64KB to be modelled using dynamic array, you
would first need to allocate 64K entries and use the array for read/write. Associative arrays
doesn’t need allocation and initialization of memory upfront and can be allocated and
initialized just when an entry of the 64K array needs to be referenced. However, associative
arrays are also slowest as they internally implement search for elements in the array using a
hash.
28. How to avoid race round condition between DUT and test bench in SystemVerilog
verification?
Program block or clocking block can avoid the race condition between DUT and
testbench
Program block act as a separation between DUT and Testbench and it schedules all the
Testbench activity in the Reactive region thereby synchronising the events which avoids the
race condition.
vI provide mechanism of seprating abstact model and test program from actual signals that
make of the design .it allow the same sub program to operate in different portion of the design
With inheritance we are able to force a subclass to offer the same properties like their
superclasses. Consequently, objects of a subclass behave like objects of their superclasses.
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