IEICE Electronics Express, Vol.9, No.

15, 1249–1253

Simple odd number

frequency divider with 50%
duty cycle
Sangjin Byun1a) , Chung Hwan Son1 , and Jae Joon Kim2
1
Div. Electronics and Electrical Engineering, Dongguk University - Seoul
26 Pil-dong 3-ga, Jung-gu, Seoul 100–715, South Korea
2
Ulsan National Institute of Science and Technology
50 UNIST-gil Eonyang-eup, Ulju-gun, Ulsan 689–798, South Korea
a) sjbyun@dongguk.edu

Abstract: A simple odd number frequency divider with 50% duty

cycle is presented. The odd number frequency divider consists of a
general odd number counter and the proposed duty cycle trimming
circuit. The duty cycle trimming circuit can output 50% duty cycle
with only additional six transistors. A prototype divide-by-5 circuit
with 50% duty cycle was implemented for a 500-Mb/s ∼ 5.6-Gb/s 1:10
CDR/DEMUX IC in a 0.13 µm 1P8M CMOS process.
Keywords: odd number frequency divider, duty cycle
Classification: Integrated circuits

References

[1] Universal Serial Bus 3.0 Specification, Revision 1.0, Nov. 2008. [Online]
Available: http://www.usb.org
[2] Y. Moon, S.-H. Lee, and D. Shim, “A Divide-by-16.5 Circuit for 10-Gb
Ethernet Transceiver in 0.13 µm CMOS,” IEEE J. Solid-State Circuits,
vol. 40, no. 5, pp. 1175–1179, May 2005.
[3] C.-C. Meng, T.-H. Wu, J.-S. Syu, S.-W. Yu, K.-C. Tsung, and Y.-H. Teng,
“2.4/5.7-GHz CMOS Dual-Band Low-IF Architecture Using Weaver-
Hartley Image-Rejection Techniques,” IEEE Trans. Microw. Theory
Tech., vol. 57, no. 3, pp. 552–561, March 2009.
[4] S.-C. Tseng, H.-J. Wei, J.-S. Syu, C. Meng, K.-C. Tsung, and G.-W.
Huang, “True 50% Duty-Cycle High-Speed Divider with the Modulus of
Odd Numbers,” Proc. Asia Pacific Microwave Conference, pp. 305–308,
Dec. 2009.
[5] R. Magoon and A. Molnar, “RF Local Oscillator Path for GSM Direct
Conversion Transceiver with True 50% Duty Cycle Divide by Three and
Active Third Harmonic Cancellation,” Proc. IEEE RFIC Symposium,
pp. 23–26, 2002.

1 Introduction

c IEICE 2012 Odd number frequency dividers are often used in frequency synthesizers,
DOI: 10.1587/elex.9.1249
Received June 06, 2012 clock generators, clock and data recovery (CDR) circuits, demultiplexers
Accepted July 17, 2012
Published August 08, 2012

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 IEICE Electronics Express, Vol.9, No.15, 1249–1253

(DEMUXs), etc [1, 2, 3]. For an example, a 2:10 DEMUX of a high speed
serial interface receiver may need a divide-by-5 circuit for output clock signal
generation. Although odd number frequency dividers do not have 50% duty
cycle, they are sometimes required to have exact 50% duty cycle. It is be-
cause both of rising and falling edges of the divided clock signal can be used
for efficient high speed operation. To obtain 50% duty cycle, special types
of latches or flipflops have been generally used for odd number frequency
dividers [2, 3, 4, 5]. A negative level sensitive latch was used in [2] and a cur-
rent switchable D flipflop (DFF) was used in [3, 4, 5] for dual edge triggering
operation in odd number frequency dividers. However, those special latches
and flipflops require more circuit complexity and are not appropriate when
a rail-to-rail signal swing is needed.
In this paper, we present a simple full swing odd number frequency divider
with 50% duty cycle. The presented odd number frequency divider consists of
a general odd number counter and the proposed duty cycle trimming circuit.
For the odd number counter, single edge triggered CMOS DFFs are used. The
duty cycle trimming circuit can output 50% duty cycle with only additional
six transistors: i.e. one NMOS transistor, one PMOS transistor and a pair of
cross-coupled inverters.

2 Proposed duty cycle trimming circuit

Fig. 1 shows the proposed odd number frequency divider with the division
ratio of 5. It consists of a divide-by-5 circuit and a new duty cycle trimming
circuit. The divide-by-5 circuit contains three rising-edge triggered DFFs and
one NAND gate. The duty cycle of the divider’s output clock signal, X, is not
50% but 60% because all the DFFs of the divide-by-5 circuit are triggered
by the rising edge of the input clock signal, CLKIN . So, the proposed duty
cycle trimming circuit is added after this divider. The duty cycle trimming
circuit consists of two transistors, M1 and M2, and a pair of cross-coupled
inverters, INV1 and INV2 , as shown in Fig. 1. M1 and M2 are an NMOS
transistor and a PMOS transistor, of which gate, source and drain terminals
are connected to each other. Because both gates of M1 and M2 are driven
by the same CLKIN , M1 can be turned on when CLKIN =1 and M2 can be
turned on when CLKIN =0. Between the cross-coupled inverters, INV1 and
INV2 , the transistor sizes of INV2 are designed much smaller than those of
INV1 and other transistors of M1, M2, and DFF1 ∼ DFF3 .
To explain the operation of the proposed duty cycle trimming circuit,
we derived the truth table of this duty cycle trimming circuit as shown in
Fig. 2 (a). First, let’s assume CLKIN =0 and X=0. When CLKIN =0, M1 is
turned off and M2 can be turned on. But X=0 makes the turn-on resistance
of M2 very high and the cross-coupled inverters hold their values at Y and
CLKOUT . Second, let’s assume CLKIN =0 and X=1. Now M2 is turned on
with the low turn-on resistance and Y equals X regardless of its previous

value, i.e. Y=X=1. It is because the transistor sizes of INV2 are designed
c IEICE 2012
DOI: 10.1587/elex.9.1249 much smaller than those of DFF3 . So, CLKOUT =0. Third, let’s assume
Received June 06, 2012
Accepted July 17, 2012
Published August 08, 2012

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 IEICE Electronics Express, Vol.9, No.15, 1249–1253

Fig. 1. Divide-by-5 circuit with the proposed duty cycle

trimming circuit

Fig. 2. (a) Truth table and (b) timing diagram of the pro-
posed duty cycle trimming circuit

CLKIN =1 and X=0. In this case, M2 is turned off, M1 is turned on with the
low turn-on resistance and Y becomes X, i.e. Y=X=0, due to the same rea-
son as the second case. So, CLKOUT =1. Finally, let’s assume CLKIN =1 and
X=1. Because CLKIN =1, M2 is turned off and M1 can be turned on. How-
ever, X=1 makes the turn-on resistance of M1 very high and the cross-coupled
inverters hold their values at Y and CLKOUT . By summarizing the above
discussion, the truth table of Fig. 2 (a) is obtained. Looking carefully this
truth table, we can simply say that “if CLKIN =X then CLKOUT =CLKIN ”.
Based on the obtained truth table, the timing diagram of the proposed
duty cycle trimming circuit is drawn as shown in Fig. 2 (b). In this timing di-

c IEICE 2012
DOI: 10.1587/elex.9.1249 agram, X is the divided-by-5 clock signal, of which duty cycle is not 50% but
Received June 06, 2012
Accepted July 17, 2012
Published August 08, 2012

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 IEICE Electronics Express, Vol.9, No.15, 1249–1253

Fig. 3. (a) Simulated waveforms of the proposed duty cy-

cle trimming circuit and (b) frequency response of
the corrected duty cycle of CLKOUT

60%. After duty cycle trimming, the duty cycles of Y and CLKOUT are cor-
rected as shown in Fig. 2 (b). Because the rising edge of Y is triggered by the
falling edge of CLKIN and the falling edge of Y is triggered by the falling edge
of X which is triggered by the rising edge of CLKIN , the duty cycles of Y and
CLKOUT are affected by the duty cycle of CLKIN , CLKIN -Y delay, X-Y delay
and CLK-Q delay of DFF3 as shown in Fig. 2 (b). Let’s consider those effects
carefully. First, the duty cycle of CLKIN is directly related to the duty cycle
of CLKOUT . If the input duty cycle error of CLKIN is 10%, then the corrected
output duty cycle of CLKOUT will be 10%/N, where N is the division ratio of
the odd number frequency divider. Fortunately, CLKIN comes directly from
the integrated voltage controlled oscillator (VCO) and has almost 50% duty
cycle in general. Second, CLKIN -Y delay and X-Y delay can be matched by

c IEICE 2012
DOI: 10.1587/elex.9.1249 properly choosing the sizes of M1 and M2 to have the same equivalent turn-on
Received June 06, 2012
Accepted July 17, 2012
Published August 08, 2012

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resistance. But small mismatch may exist between CLKIN -Y delay and X-Y
delay depending on the process variation. The transistor sizes of M1 and M2
were (W/L)M1 =0.5 µm/0.13 µm and (W/L)M2 =1 µm/0.13 µm, respectively.
Finally, CLK-Q delay of DFF3 may limit the accuracy of the duty cycle of
CLKOUT . However, it is relatively small for low frequency operation and
starts to show up as the CLKIN frequency increases. To compensate the
CLK-Q delay of DFF3 for high speed operation, an appropriate buffer can
be inserted to CLKIN before CLKIN drives the gates of M1 and M2. This
CLK-Q delay of DFF3 depends on the process variations. Although the tim-
ing diagram of Fig. 2 (b) shows the case of a divide-by-5 circuit, any odd
number frequency divider can be incorporated with the proposed duty cycle
trimming circuit for 50% duty cycle.

3 Simulation results and conclusion

The divide-by-5 circuit and the proposed duty cycle trimming circuit were
designed for a 500-Mb/s ∼ 5.6-Gb/s 1:10 CDR/DEMUX IC in a 0.13 µm
1P8M CMOS process. Fig. 3 (a) shows the simulated waveforms of CLKIN , X,
Y and CLKOUT of the proposed duty cycle trimming circuit. The simulated
waveforms agree well with the timing diagram shown in Fig. 2 (b). The
small ripple on the waveform of Y is generated when CLKIN =X=1 and Y=0
because of the high but not infinite turn-on resistance of M1. This ripple
can be reduced by designing INV2 with a bit larger transistors. Due to the
proposed duty cycle trimming circuit, the output duty cycle of CLKOUT is
corrected from 60% to 49.5% when the input clock frequency of 1 GHz is
applied to the proposed divide-by-5 circuit. Fig. 3 (b) shows the frequency
responses of the corrected duty cycle of the divide-by-5 circuit and the duty
cycle trimming circuit for the process variations, TT, FF, SS, FS and SF.
The duty cycle of CLKOUT deviates from 50% as the operating frequency
increases. The duty cycle of CLKOUT is within 2.7% from 50% over the
frequency range from 20 MHz to 3 GHz, which satisfies the required clock
frequency range, i.e. 250 MHz ∼ 2.8 GHz, for the 500-Mb/s ∼ 5.6-Gb/s 1:10
CDR/DEMUX IC with a half rate phase detector. The maximum frequency
range is limited not by the duty cycle trimming circuit but by the divide-by-
5 circuit, because the D-Q delay of DFFs and the propagation delay of the
NAND gate limit the maximum operating speed of the frequency divider.
In conclusion, the proposed duty cycle trimming circuit provides 50%
duty cycle for full swing odd number frequency dividers at the cost of only
additional six transistors.

Acknowledgments
This research was supported by Basic Science Research Program through
the National Research Foundation of Korea (NRF) funded by the Ministry
of Education, Science and Technology (2012-008324). The CAD tools were

c IEICE 2012 supported by IDEC.
DOI: 10.1587/elex.9.1249
Received June 06, 2012
Accepted July 17, 2012
Published August 08, 2012

1253