Real time clock module

4-bit REAL TIME CLOCK MODULE

RTC-72421/72423
• Builtin crystal unit allows adjustment-free efficient operation.
• ALE input terminal available for 8048, 8051, and 8085 series.
• 12/24H clock switchover function and automatic leap year setting.
• Interrupt masking.
• 30 second adjustment function.
• Low current consumption and features a backup function.

Actual size

Specifications (characteristics)
Absolute Max. rating Terminal connection
Item Symbol Condition Specifications Unit RTC-72421 No. 72421 No. 72423
Power source voltage VDD Ta=25˚C -0.3 to 7.0 1 STD. P 1 STD. P
18 17 16 15 14 13 12 11 10 2 CS 0 2 CS 0
Input and output voltage VI/O Ta=25˚C GND -0.3 to VDD+0.3 V ALE
3 3 NC
RTC-72421 -55 to +85 4 A0 4 ALE
Storage temperature TSTG ˚C 5 A1 5 A0
RTC-72423 -55 to +125 6 A2 6 NC
Under 260˚C within 10 sec. 7 A3 7 A1
RTC-72421 (lead part) (package should 8 RD 8 NC
be less than 150˚C) 9 GND 9 A2
Soldering condition TSOL
Twice at under 260˚C within 1 2 3 4 5 6 7 8 9 10 WR 10 A3
RTC-72423 10 sec. or under 230˚C 11 D3 11 RD
within 3 min. 12 D2 12 GND
RTC-72423 13 D1 13 WR
Operating range 24 23 22 21 20 19 18 17 16 15 14 13
14 D0 14 D3
15 CS1 15 D2
Item Symbol Condition Specifications Unit 16 (VDD) 16 D1
17 (VDD) 17 NC
Operating voltage VDD 4.5 to 5.5 V 18 VDD 18 NC
RTC-72421 -10 to 70 19 D0
Operating temperature TOPR ˚C 20 CS1
RTC-72423 -40 to 85 21 NC
22 (VDD)
Data holding voltage VDH 2.0 to 5.5 V 23 (VDD)
24 VDD
CSI data holding time tCDR Refer to the data 1 2 3 4 5 6 7 8 9 10 11 12
2.0 min. µs (VDD) and VDD are to have the same level of voltage. Do not connect it to any external terminals.
Operation restoring time tR holding timing
NC is not connected internally.

Frequency characteristics and current consumption

characteristics External dimensions (Unit: mm)
Item Symbol Condition Specifications Unit
RTC-72421
72421 A ±10
23.1 max.
Ta=25˚C 72421 B ±50
Frequency tolerance ∆f/fo
VDD=5V 72423 A ±20
6.8 max.

ppm RTC72421 A
72423 ±50
EPSON 5053C
Frequency temperature -10 to +70˚C +10/-120 7.62
(25˚C reference temperature)
characteristics
0.2 min.
4.2

VDD=5V, Ta=25˚C,
Aging fa first year ±5 max. ppm/Y
0.25
Three drops on a
hard board from 75 cm 90° to
Shock resistance S.R. or 3000G x 0.3ms x ±10 max. ppm 105°
3.3 min.

1/2 sine wave x 3 directions

IDD1 CS1=0V VDD=5V 10 max.

Current consumption Exclude input/ µA
IDD2 output current VDD=2V 5 max.

Electrical characteristics RTC-72423

Applicable
Item Symbol Condition Min. Typ. Max. Unit terminal
16.3 max.
“H” input voltage (1) VIH1 2.2 — All inputs
— V other than
“L” input voltage (1) VIL1 0.8 CS1
Input other
Input leak current (1) ILK1 ±1 than D0 to D3
V1=VDD/0V — µA
RTC72423 A
12.2 max.

Input leak current (2) ILK2 —

±10
7.9

D0 to D3
“L” output voltage (1) VOL1 IOL=2.5mA 0.4 EPSON 6150
“H” output voltage VOH IOH=-400µA 2.4 — V
“L” output voltage (2) VOL2 IOL=2.5mA 0.4
STD.P
Off leak current IOFFLK V1=VDD/0V — 10 µA
2.5

Input other
Input 10 than D0 to D3
Input capacity pF 0° to
C1 frequency 1 MHz 0.05 min. 1.0
0.2

20 — D0 to D3 10°
0.3

2.8 max.
“H” input voltage (2) VIH2 4/5 VDD
VDD=2 to 5.5V — V CS1
“L” input voltage (2) VIL2 — 1/5 VDD
65

This datasheet has been downloaded from http://www.digchip.com at this page

 Real time clock module

Register table Write mode (with ALE)

Data
Address

Register
Count
A3 A2 A1 A0 Remarks
D1 D0 Value
D3 D2
VIH (CS1) VIH (CS1)
0 0 0 0 0 S1 s8 s4 s2 s1 0 to 9 1- second digit register CS1 tSU (CS1) tSU (A-ALE) tH (ALE-A) tH (CS1)

1 0 0 0 1 S10 ∗ s40 s20 s10 0 to 5 10- second digit register A0 to A3 VIH VIH
2 0 0 1 0 MI 1 mi8 mi4 mi2 mi1 0 to 9 1- minute digit register CS0
VIL VIL

3 0 0 1 1 MI10 ∗ mi40 mi20 mi10 0 to 5 10- minute digit register tW (ALE)

4 0 1 0 0 H1 h8 h4 h2 h1 0 to 9 1- hour digit register VIH VIH VIL

ALE
0 to 2 tSU (ALE-W) tW (W) tSU (W-ALE)
5 0 1 0 1 H10 ∗ PM/AM h20 h10 or PM/AM,10- hours digit register WR
0 to 1 VIH VIL
VIL tSU (R-ALE)
6 0 1 1 0 D1 d8 d4 d2 d1 0 to 9 1- day digit register tSU (D-W) tH (W-D)
7 0 1 1 1 D10 ∗ ∗ d20 d10 0 to 3 10 -day digit register D0 to D3
VIH VIH
VIH VIL
8 1 0 0 0 MO1 mo8 mo4 mo2 mo1 0 to 9 1- month digit register
9 1 0 0 1 MO10 ∗ ∗ ∗ mo10 0 to 1 10- month digit register
A 1 0 1 0 Y1 y8 y4 y2 y1 1- year digit register
B 1 0 1 1 Y10 y80 y40 y20 y10 0 to 9 10- year digit register
C 1 1 0 0 W ∗ w4 w2 w1 0 to 6 Week register
30 sec. IRQ
D 1 1 0 1 RegD ADJ FLAG BUSY HOLD Control Register D Read mode (with ALE)
E 1 1 1 0 RegE t1 t0 ITRPT ----- Control Register E
/STND MASK
F 1 1 1 1 RegF TEST 24/12 STOP REST Control Register F VIH (CS1)
VIH (CS1)
CS1 tSU (CS1) tSU (A-ALE) tH (ALE-A)
0=“L” level,1=“H” level, REST = RESET ITRPT/ STND=INTERRUPT/STANDARD
A0 to A3 tH (CS1)
1) Bit ∗ does not exist. VIH
VIL
VIH
VIL
2) Please mask AM/PM bit with 10's of hours operations. CS0
tW (ALE)
3) Busy is read only. IRQ can only. IRQ can only be set low (“O”).
4) Data Bit PM/AM ITRPT/STND 24/12 VIH VIH VIL VIL
1 PM ITRPT 24 ALE
tSU (ALE-R) tSU (R-ALE)
0 AM STND 12
RD VIH
VIH VIL
5) TEST bit should be “O”. VIL
trnc (R)
Switching characteristics (with ALE) tPZV (R-Q) tPVZ (R-Q)
(Please connect ALE to VDD if the microprocessor does not have an ALE output.) D0 to D3 VOH
VOL
VOH
VOL

Item Symbol ConditionMin. Max. Unit

CS1 setup time tSU (CS1) 1000
Address setup time before ALE tSU (A-ALE) 50
Address hold time after ALE tH (ALE-A) 50
ALE pulse width tW (ALE) 80
ALE setup time before WRITE tSU (ALE-W) 0 ---- Data holding timing
ALE setup time before READ tSU (ALE-R) 0
VDD
ALE setup time after WRITE tSU (W-ALE) 50 4V 4V
ALE setup time after READ tSU (R-ALE) 50 ns 2 to 4V
WRITE pulse width tW (W) 120 t CDR tR
CS1
DATA delay time after READ tPZV (R-Q) CL=150pF ---- 120 VIH2 VIH2
DATA Hold time after READ tPVZ (R-Q) 0 70 VIL2 CS1 ≤ 1/5VDD VIL2
DATA setup time before WRITE tSU (D-W) 80 Data storage mode
Interface possible Interface possible
DATA hold time after WRITE tH (W-D) 10 with external
---- with the external
CS1 hold time tH (CS1) 1000 terminals terminals
CS0 or WR not occurred
READ/WRITE recovery time tREC (R/W) 200
( VDD = 5V ± 0.5V )
Block diagram

RD WR CS1 ALE CS0 A0 A1 A2 A3 D0 D1 D2 D3

DIVIDER READ • WRITE ADDRESS LATCH DATA BUS • BUFFER

OSC CONTROL

4
30ADJ

HOLD
STOP

BUSY
REST

4
64 HZ
ADDRESS DECODER
STD•P CARRY PER
SEC.
CARRY PER
MIN.
CARRY PER
HOUR
4
IRQFLAG

4 4
Week

Seconds Minutes Hours Days Months Years

Sec 1 Sec 10 Min 1 Min 10 Hou 1 Hou 10 Day 1 Day 10 Mon 1 Mon 10 Yea 1 Yea 10 Reg D Reg E Reg F

24/12
66