a High Performance,

BiFET Operational Amplifiers

AD542/AD544/AD547
FEATURES CONNECTION DIAGRAM
Ultralow Drift: 1 mV/8C (AD547L)
Low Offset Voltage: 0.25 mV (AD547L) TAB

Low Input Bias Currents: 25 pA max

8
Low Quiescent Current: 1.5 mA NULL 1 +V
7
Low Noise: 2 mV p-p
High Open Loop Gain: 110 dB INVERTING 2 6 OUTPUT
INPUT
High Slew Rate: 13 V/ms

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Fast Settling to 60.01%: 3 ms NONINVERTING 3 5 NULL
INPUT
Low Total Harmonic Distortion: 0.0025% 4

Available in Hermetic Metal Can and Die Form –V

MIL-STD-883B Versions Available NOTE: PIN 4 CONNECTED TO CASE

Dual Versions Available: AD642, AD644, AD647

PRODUCT DESCRIPTION

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The BiFET series of precision, monolithic FET-input op amps
PRODUCT HIGHLIGHTS
1. Improved bipolar and JFET processing results in the lowest

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are fabricated with the most advanced BiFET and laser trim- bias current available in a monolithic FET op amp.
ming technologies. The AD542, AD544, AD547 series offers 2. Analog Devices, unlike some manufacturers, specifies each
bias currents significantly lower than currently available BiFET device for the maximum bias current at either input in the
devices, 25 pA max, warmed up. warmed-up condition, thus assuring the user that the device
In addition, the offset voltage is laser trimmed to less than will meet its published specifications in actual use.
0.25 mV on the AD547L, which is achieved by utilizing Analog 3. Advanced laser wafer trimming techniques reduce offset volt-
Devices’ exclusive laser wafer trimming (LWT) process. When age drift to 1 µV/°C max and offset voltage to only 0.25 mV
combined with the AD547’s low offset drift (1 µV/°C), these max on the AD547L.
features offer the user performance superior to existing BiFET
op amps at low BiFET pricing. 4. Low voltage noise (2 µV p-p) and low offset voltage drift en-
hance performance as a precision op amp.
The AD542 or AD547 is recommended for any operational am-
plifier application requiring excellent dc performance at low to 5. High slew rate (13 V/µs) and fast settling time to 0.01% (3 µs)
moderate cost. Precision instrument front ends requiring accu- make the AD544 ideal for D/A, A/D, sample-hold circuits
rate amplification of millivolt level signals from megohm source and high speed integrators.
impedances will benefit from the device’s excellent combination 6. Low harmonic distortion (0.0025%) make the AD544 an
of low offset voltage and drift, low bias current and low 1/f ideal choice in audio applications.
noise. High common-mode rejection (80 dB, min on the “K”
7. Bare die are available for use in hybrid circuit applications.
and “L” grades) and high open-loop gain, even under heavy
loading, ensures better than “12-bit” linearity in high imped-
ance buffer applications.
The AD544 is recommended for any op amp applications re-
quiring excellent ac and dc performance at low cost. The
2 MHz bandwidth and low offset of the AD544 make it the first
choice as an output amplifier for current output D/A converters,
such as the AD7541, 12-bit CMOS DAC.
Devices in this series are available in four grades: the “J,” “K,”
and “L” grades are specified over the 0°C to +70°C temperature
range and the “S” grade over the –55°C to +125°C operating
temperature range. All devices are offered in the hermetically
sealed, TO-99 metal can package.

REV. B
Information furnished by Analog Devices is believed to be accurate and
reliable. However, no responsibility is assumed by Analog Devices for its
use, nor for any infringements of patents or other rights of third parties
which may result from its use. No license is granted by implication or One Technology Way, P.O. Box 9106, Norwood, MA 02062-9106, U.S.A.
otherwise under any patent or patent rights of Analog Devices. Tel: 617/329-4700 Fax: 617/326-8703
AD542/AD544/AD547–SPECIFICATIONS ( V = 615 V @ T = +258C unless otherwise noted)
S A

AD542 AD544 AD547

Parameter Min Typ Max Min Typ Max Min Typ Max Units
1
OPEN-LOOP GAIN
VOUT = ± 10 V, RL = 2 kΩ
J Grade 100 30 100 V/mV
K, L, S Grades 250 50 250 V/mV
TA = TMIN to TMAX
J Grade 100 20 100 V/mV
S Grade 100 20 100 V/mV
K, L Grades 250 40 250 V/mV
OUTPUT CHARACTERISTICS
RL = 2 kΩ
TA = TMIN to TMAX ± 10 ± 12 ± 10 ± 12 ± 10 ± 12 V

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RL = 10 kΩ
TA = TMIN to TMAX ± 12 ± 13 ± 12 ± 13 ± 12 ± 13 V
Short Circuit Current 25 25 25 mA
FREQUENCY RESPONSE
Unity Gain, Small Signal 1.0 2.0 1.0 MHz

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Full Power Response 50 200 50 kHz
Slew Rate, Unity Gain 2.0 3.0 8.0 13.0 2.0 3.0 V/µs
Total Harmonic Distortion 0.0025 %
INPUT OFFSET VOLTAGE2

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J Grade 2.0 2.0 1.0 mV
K Grade 1.0 1.0 0.5 mV
L Grade 0.5 0.5 0.25 mV
S Grade 1.0 1.0 0.5 mV
vs. Temperature3
J Grade 20 20 5 µV/°C
K Grade 10 10 2 µV/°C
L Grade 5 5 1 µV/°C
S Grade 15 15 5 µV/°C
vs. Supply, TA = TMIN to TMAX
J Grade 200 200 200 µV/V
K, L, S Grades 100 100 100 µV/V
INPUT BIAS CURRENT4
Either Input
J Grade 50 50 50 pA
K, L, S Grades 10 25 10 25 10 25 pA
Input Offset Current
J Grade 5 15 5 15 5 15 pA
K, L, S Grades 2 15 2 15 2 15 pA
INPUT IMPEDANCE
Differential 1012i6 1012i6 1012i6 ΩipF
Common Mode 1012i3 1012i3 1012i3 ΩipF
INPUT VOLTAGE5
Differential ± 20 ± 20 ± 20 V
Common Mode ± 10 ± 12 ± 10 ± 12 ± 10 ± 12 V
Common-Mode Rejection
VIN = ± 10 V
J Grade 76 76 76 dB
K, L, S Grades 80 80 80 dB

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 AD542/AD544/AD547
AD542 AD544 AD547
Parameter Min Typ Max Min Typ Max Min Typ Max Units
POWER SUPPLY
Rated Performance ± 15 ± 15 ± 15 V
Operating ±5 ± 18 ±5 ± 18 ±5 ± 18 V
Quiescent Current 1.1 1.5 1.8 2.5 1.1 1.5 mA
VOLTAGE NOISE
0.1 Hz to 10 Hz
J Grade 2.0 2.0 2.0 µV p-p
K, L, S Grades 2.0 2.0 4.0 µV p-p
10 Hz 70 35 70 nV/√Hz
100 Hz 45 22 45 nV/√Hz
1 kHz 30 18 30 nV/√Hz

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10 kHz 25 16 25 nV/√Hz
TEMPERATURE RANGE
Operating, Rated Performance
J, K, L Grades 0 to +70 0 to +70 0 to +70 °C

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S Grade –55 to +125 –55 to +125 –55 to +125 °C
Storage –65 to +150 –65 to +150 –65 to +150 °C
TRANSISTOR COUNT 29 29 29
NOTES

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1
Open-Loop Gain is specified with V OS both nulled and unnulled.
2
Input Offset Voltage specifications are guaranteed after 5 minutes of operation at T A = +25°C.
3
Input Offset Voltage Drift is specified with the offset voltage unnulled. Nulling will induce an additional 3 µV/°C/mV of nulled offset.
4
Bias Current specifications are guaranteed at either input after 5 minutes of operation at T A = +25°C. For higher temperatures, the current doubles every 10°C.
5
Defined as the maximum safe voltage between inputs, such that neither exceeds ± 10 V from ground.
Specifications subject to change without notice.
Specifications shown in boldface are tested on all production units at final electrical test. Results from those tests are used to calculate outgoing quality levels.
All min and max specifications are guaranteed, although only those shown in boldface are tested on all production units.

ORDERING GUIDE

Initial Offset Settling Time

Offset Voltage to 60.012% for Package Package
Model Voltage Drift a 10 V Step Description Option

AD542JCHIPS 2.0 mV 20 µV/°C 5 µs Bare Die

AD542JH 2.0 mV 20 µV/°C 5 µs 8-Pin Hermetic Metal Can H-08A
AD542KH 1.0 mV 10 µV/°C 5 µs 8-Pin Hermetic Metal Can H-08A
AD542LH 0.5 mV 5 µV/°C 5 µs 8-Pin Hermetic Metal Can H-08A
AD542SH 1.0 mV 15 µV/°C 5 µs 8-Pin Hermetic Metal Can H-08A
AD542SH/883B 1.0 mV 15 µV/°C 5 µs 8-Pin Hermetic Metal Can H-08A
AD544JH 2.0 mV 20 µV/°C 3 µs 8-Pin Hermetic Metal Can H-08A
AD544KH 1.0 mV 10 µV/°C 3 µs 8-Pin Hermetic Metal Can H-08A
AD544LH 0.5 mV 5 µV/°C 3 µs 8-Pin Hermetic Metal Can H-08A
AD544SH 1.0 mV 15 µV/°C 3 µs 8-Pin Hermetic Metal Can H-08A
AD544SH/883B 1.0 mV 15 µV/°C 3 µs 8-Pin Hermetic Metal Can H-08A
AD547JH 1.0 mV 5 µV/°C 5 µs 8-Pin Hermetic Metal Can H-08A
AD547KH 0.5 mV 2 µV/°C 5 µs 8-Pin Hermetic Metal Can H-08A
AD547LH 0.25 mV 1 µV/°C 5 µs 8-Pin Hermetic Metal Can H-08A
AD547SCHIPS 0.5 mV 5 µV/°C 5 µs Bare Die
AD547SH/883B 0.5 mV 5 µV/°C 5 µs 8-Pin Hermetic Metal Can H-08A

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AD542/AD544/AD547–Typical Characteristics

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Figure 2. Output Voltage Swing vs. Figure 3. Output Voltage Swing vs.
Figure 1. Input Voltage Range vs.
Supply Voltage Load Resistance
Supply Voltage

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Figure 4. Input Bias Current vs.
Supply Voltage
Figure 5. Input Bias Current vs.
Temperature CMV
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Figure 6. Input Bias Current vs.

Figure 7. Change in Offset Voltage Figure 8. Open Loop Gain vs. Figure 9. Open Loop Frequency
vs. Warm-Up Time Temperature Response

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 AD542/AD544/AD547

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Figure 10. Open Loop Voltage Figure 11. Power Supply Rejection Figure 12. Common-Mode Rejection
Gain vs. Supply Voltage vs. Frequency Ratio vs. Frequency

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Figure 13. Quiescent Current vs.
Supply Voltage
Figure 14. Large Signal Frequency
Response
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Figure 15. AD544 Output Swing and
Error vs. Settling Time

Figure 16. AD544 Total Harmonic Figure 17. Input Noise Voltage Figure 18. Total RMS Noise vs.
Distortion vs. Frequency Spectral Density Source Resistance

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AD542/AD544/AD547

a. Unity Gain Follower b. Follower with Gain = 10

Figure 19. THD Test Circuits Figure 20. Standard Null Circuit

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Figure 21a. Unity Gain Follower Figure 21b. Unity Gain Follower Figure 21c. Unity Gain Follower–
Pulse Response (Large Signal) Pulse Response (Small Signal) AD542/AD547

Figure 22a. Unity Gain Inverter Figure 22b. Unity Gain Inverter Figure 22c. Unity Gain Inverter
AD542/AD547 Pulse Response (Large Signal) Pulse Response (Small Signal)

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 AD542/AD544/AD547

Figure 23a. Unity Gain Follower Figure 23b. Unity Gain Follower Figure 23c. Unity Gain Follower
Pulse Response (Large Signal) Pulse Response (Small Signal)

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Figure 24a. Unity Gain Inverter

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Figure 24b. Unity Gain Inverter Figure 24c. Unity Gain Inverter

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Pulse Response (Large Signal) Pulse Response (Small Signal)

Figure 25. Settling Time Test Circuit Figure 27. Circuit for Driving a Large Capacitance Load
The upper trace of the oscilloscope photograph of Figure 26 The circuit in Figure 27 employs a 100 Ω isolation resistor
shows the settling characteristic of the AD544. The lower trace which enables the amplifier to drive capacitance loads exceeding
represents the input to Figure 27. The AD544 has been designed 500 pF; the resistor effectively isolates the high frequency feed-
for fast settling to 0.01%, however, feedback components, cir- back from the load and stabilizes the circuit. Low frequency
cuit layout and circuit design must be carefully considered to feedback is returned to the amplifier summing junction via the
obtain optimum settling time. low-pass filter formed by the 100 Ω series resistor and the load
capacitance, CL.

Figure 26. Settling Characteristic Detail–AD544 Figure 28. Transient Response RL = 2 kΩ

CL = 500 pF–AD544

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AD542/AD544/AD547
current-to-voltage converting amplifier. This possibility necessi-
BiFET Application Hints tates some form of input protection. Many electrometer type
devices, especially CMOS designs, can require elaborate Zener
APPLICATION NOTES protection schemes which often compromise overall perfor-
The BiFET series was designed for high performance op amp mance. The BiFET series requires input protection only if the
applications that require true dc precision. To capitalize on all source is not current-limited, and as such is similar to many
of the performance available from the BiFETs there are some JFET-input designs. The failure mode would be overheating
practical error sources that should be considered. from excess current rather than voltage breakdown. If the
source is not current-limited, all that is required is a resistor in
The bias currents of JFET input amplifiers double with every
series with the affected input terminal so that the maximum
10°C increase in chip temperature. Therefore, minimizing the
overload current is 1.0 mA (for example, 100 kΩ for a 100 volt
junction temperature of the chip will result in extending the
overload). This simple scheme will cause no significant reduc-
performance limits of the device.
tion in performance and give complete overload protection. Fig-
1. Heat dissipation due to power consumption is the main ure 30 shows proper connections.

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contributor to self-heating and can be minimized by reducing
the power supplies to the lowest level allowed by the
application.
2. The effects of output loading should be carefully considered.
Greater power dissipation increases bias currents and de-

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creases open loop gain.

GUARDING
The low input bias current (25 pA) and low noise characteristics
of the high performance BiFET op amp make it suitable for

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Figure 30. Input Protection
electrometer applications such as photo diode preamplifiers and
picoampere current-to-voltage converters. The use of guarding D/A CONVERTER APPLICATIONS
techniques in printed circuit board layout and construction is The BiFET series of operational amplifiers can be used with
critical for achieving the ultimate in low leakage performance CMOS DACs to perform both 2-quadrant and 4-quadrant
available from these amplifiers. The input guarding scheme operation. The output impedance of a CMOS DAC varies with
shown in Figure 29 will minimize leakage as much as possible; the digital word, thus changing the noise gain of the amplifier
the guard ring is connected to a low impedance potential at the circuit. The effect will cause a nonlinearity the magnitude of
same level as the inputs. High impedance signal lines should not which is dependent on the offset voltage of the amplifier. The
be extended for any unnecessary length on a printed circuit. BiFET series with trimmed offset will minimize this effect. Ad-
ditionally, the Schottky protection diodes recommended for use
with many older CMOS DACs are not required when using one
of the BiFET series amplifiers.
Figure 31a shows the AD547 and AD7541 configured for uni-
polar binary (2-quadrant multiplication) operation. With a dc
reference voltage or current (positive or negative polarity) ap-
plied at pin 17, the circuit operates as a unipolar converter.
With an ac reference voltage or current, the circuit provides
2-quadrant multiplication (digitally controlled attenuation).
Figure 29. Board Layout for Guarding Inputs

INPUT PROTECTION
The BiFET series is guaranteed for a maximum safe input
potential equal to the power supply potential. The input stage
design also allows differential input voltages of up to ± 1 volt
while maintaining the full differential input resistance of 1012 Ω.
This makes the BiFET series suitable for comparator situations
employing a direct connection to high impedance source.
Many instrumentation situations, such as flame detectors in gas
chromatographs, involve measurement of low level currents
from high-voltage sources. In such applications, a sensor fault Figure 31a. AD547 Used as DAC Output Amplifier
condition may apply a very high potential to the input of the

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 AD542/AD544/AD547
The oscilloscope photo of Figure 31b shows the output of the USING THE AD547 IN LOG AMPLIFIER APPLICATIONS
circuit of Figure 31a. The upper trace represents the reference Log amplifiers or log ratio amplifiers are useful in applications
input, and the bottom trace shows the output voltage for a requiring compression of wide-range analog input data, linear-
digital input of all ones on the DAC (Gain 1–2–n). The 47 pF ization of transducers having exponential outputs, and analog
capacitor across the feedback resistor compensates for the DAC computing, ranging from simple translation of natural relation-
output capacitance, and the 150 pF load capacitor serves to ships in log form (e.g., computing absorbance as the log-ratio of
minimize output glitches. input currents), to the use of logarithms in facilitating analog
computation of terms involving arbitrary exponents and
multi-term products and ratios.
The picoamp level input current and low offset voltage of the
AD547 make it suitable for wide dynamic range log amplifiers.
Figure 33 is a schematic of a log ratio circuit employing the
AD547 that can achieve less than 1% conformance error over 5
decades of current input, 1 nA to 100 µA. For voltage inputs,

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the dynamic range is typically 50 mV to 10 V for 1% error,
limited on the low end by the amplifiers’ input offset voltage.

Figure 31b. Voltage Output DAC Settling Characteristic

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Figure 32a illustrates the 10-bit digital-to-analog converter,
AD7533, connected for bipolar operation. Since the digital
input can accept bipolar numbers and VREF can accept a bipolar
analog input, the circuit can perform a 4-quadrant multiplying

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function.

Figure 33. Log-Ratio Amplifier

The conversion between current (or voltage) input and log out-
put is accomplished by the base emitter junctions of the dual
transistor Q1. Assuming Q1 has β > 100, which is the case for
the specified transistor, the base-emitter voltage on side 1 is to a
Figure 32a. AD544 Used as DAC Output Amplifiers
close approximation:
The photos exhibit the response to a step input at VREF. Figure
V BE A = kT/q ln I1/I S1
32b is the large signal response and Figure 32c is the small sig-
nal response. C1 phase compensation (15 pF) is required for
This circuit is arranged to take the difference of the VBE’s of
stability when using high speed amplifiers. C1 is used to cancel
Q1A and Q1B, thus producing an output voltage proportional
the pole formed by the DAC internal feedback resistance and
to the log of the ratio of the inputs:
the output capacitance of the DAC.
KkT
VOUT = – K (VBE A – V BE B) = – (ln I1 /I S1 – ln I 2 /I S2 )
q

V OUT = −K kT /q ln I1 / I 2

The scaling constant, K is set by R1 and RTC to about 16, to

produce 1 V change in output voltage per decade difference in
input signals. RTC is a special resistor with a +3500 ppm/°C
temperature coefficient, which makes K inversely proportional
Figure 32b. Large Signal Figure 32c. Small Signal to temperature, compensating for the “T” in kT/q. The log-
Response Response ratio transfer characteristic is therefore independent of
temperature.

REV. B –9–
AD542/AD544/AD547
This particular log ratio circuit is free from the dynamic prob- This log ratio amplifier can be readily adjusted for optimum
lems that plague many other log circuits. The –3 dB bandwidth accuracy by following this simple procedure. First, apply V1 =
is 50 kHz over the top 3 decades, 100 nA to 100 µA, and de- V2 = –10.00 V and adjust “Balance” for VOUT = 0.00 V. Next
creases smoothly at lower input levels. This circuit needs no ad- apply V1 = –10.00 V, V2 = –1.00 V and adjust gain for VOUT =
ditional frequency compensation for stable operation from +1.00 V. Repeat this procedure until gain and balance readings
input current sources, such as photodiodes, that may have 100 are within 2 mV of ideal values.
pF of shunt capacitance. For larger input capacitances a 20 pF
integration capacitor around each amplifier will provide a
smoother frequency response.

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Figure 34. Differentiator

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Figure 35. Low Drift Integrator and
Low Leakage Guarded Reset
Figure 36. Wien-Bridge
Oscillator–fO = 10 kHz

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Figure 37. Capacitance Figure 38. Long Interval Figure 39. Positive Peak Detector
Multiplier Timer–1,000 Seconds

–10– REV. B
 AD542/AD544/AD547
OUTLINE DIMENSIONS
Dimensions shown in inches and (mm).

TO-99 (H-08A)

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PRINTED IN U.S.A. C826c–2–11/91