Video Technical Guide: GR-AXM700U/AXM500EK/AXM870S

VIDEO TECHNICAL GUIDE
VHS VIDEO MOVIE
GR-AXM700U/AXM500EK/AXM870S
(NTSC/PAL/SECAM)
No. 86047
COPYRIGHT © 1999 VICTOR COMPANY OF JAPAN, LTD. Apri 1999
INDEX
SECTION 1 OUTLINE
1.1 GENERAL STATEMENT OF 1998 CAMCORDERS ..........................................................1-1
1.2 TABLE OF CAMCORDER MODELS (NEWLY PUT ON THE MARKET IN 1998) .................1-1
1.2.1 Table of camcorder models ............................................................................................1-1
SECTION 2 DSC CIRCUIT GR-AXM700U/AXM500EK/AXM870S

2.1 LIST OF CAMCORDER WITH A BUILT-IN DSC................................................................2-1
2.2 SIGNAL FLOW ..................................................................................................................2-2
2.3 DSC BLOCK......................................................................................................................2-3

2.3.1 DSC block diagram ........................................................................................................2-3
2.4 OUTLINE OF DSC CIRCUIT .............................................................................................2-4
2.5 CPU INTERFACE (IC8001) ...............................................................................................2-5

2.5.1 CPU interface (IC8001) pin location...............................................................................2-6
2.5.2 CPU interface (IC8001) block diagram...........................................................................2-7
2.5.3 CPU interface (IC8001) pin functions.............................................................................2-8
2.6 DSC CPU (IC8002)............................................................................................................2-11

2.6.1 DSC CPU (IC8002) pin location .....................................................................................2-11
2.6.2 DSC CPU (IC8002) block diagram.................................................................................2-12
2.6.3 DSC CPU (IC8002) pin function.....................................................................................2-13
2.6.4 DSC CPU (IC8002) pin functions ...................................................................................2-14
2.7 1M FLASH MEMORY (IC8003) .........................................................................................2-16

2.7.1 1M Flash memory (IC8003) pin location.........................................................................2-16
2.7.2 1M Flash memory (IC8003) block diagram ....................................................................2-17
2.7.3 1M Flash memory (IC8003) pin functions.......................................................................2-18
2.8 RS232C INTERFACE (IC8006) .........................................................................................2-19

2.8.1 RS232C INTERFACE (IC8006) pin location & block diagram ........................................2-19
2.8.1 RS232C Interface (IC8006) pin functions.......................................................................2-19
2.9 RESET CIRCUIT (IC8004, IC8007, IC8008, IC8009) ........................................................2-20
SECTION 3 CAMERA CIRCUIT

3.1 CCD IMAGE SENSOR .........................................................................................................3-1
3.1.1 Pixel arrangement..........................................................................................................3-1
3.1.2 CCD ratings ...................................................................................................................3-1
3.1.3 CCD block diagram & pin location..................................................................................3-2
3.1.4 CCD pin functions..........................................................................................................3-2
3.2 CDS / AGC / AD (IC5202)..................................................................................................3-3

3.2.1 CDS/AGC/AD (IC5202) block diagram & pin location.....................................................3-3
3.2.2 CDS/AGC/AD (IC5202) pin functions.............................................................................3-4
INDEX-1
3.3 TG / VIDEO DRIVER (IC5201) .............................................................................................3-5
3.3.1 TG / Video driver (IC5201) block diagram & pin location ................................................3-5
3.3.2 TG / Video driver (IC5201) pin functions ........................................................................3-6
3.4 DOWN CONVERTOR (IC5203/IC4002/IC4005)...................................................................3-7

3.4.1 Down converter (IC5203/IC4002/IC4005) block diagram & pin location .........................3-7
3.4.2 Down converter (IC5203/IC4002/IC4005) pin functions .................................................3-7
3.5 DSP (IC4001) ....................................................................................................................3-8

3.5.1 DSP (IC4001) pin location..............................................................................................3-9
3.5.2 DSP (IC4001) block diagram .........................................................................................3-10
3.5.3 DSP (IC4001) pin functions............................................................................................3-11
3.6 FILTER & AMP (IC4003) ......................................................................................................3-14

3.6.1 Filter & Amp (IC4003) block diagram & pin location .......................................................3-14
3.6.2 Filter & Amp (IC4003) pin functions ...............................................................................3-14
3.7 Y/C (IC3001) ........................................................................................................................3-15

3.7.1 Y/C (IC3001) pin location ...............................................................................................3-15
3.7.2 Y/C (IC3001) block diagram...........................................................................................3-16
3.7.3 Y/C (IC3001) pin functions .............................................................................................3-17
3.8 3 INPUT VIDEO SWITCH (IC3051) ...................................................................................3-18

3.8.1 3 input video switch (IC3051) block diagram & pin location............................................3-18
3.8.2 3 input video switch (IC3051) pin functions ....................................................................3-18
3.9 1H DELAY LINE + CCD COMB FILTER (IC3101)..............................................................3-19

3.9.1 1H delay line + CCD comb filter (IC3101) pin location ...................................................3-19
3.9.2 1H delay line + CCD comb filter (IC3101) pin functions..................................................3-19
3.10 D/A CONVERTER (IC4301).............................................................................................3-20

3.10.1 D/A converter (IC4301) block diagram & pin location ...................................................3-20
3.10.2 D/A converter (IC4301) pin functions ...........................................................................3-21
3.11 STEPPING MOTOR DRIVE (IC4501) ..............................................................................3-22

3.11.1 Stepping motor drive (IC4501) pin location...................................................................3-22
3.11.2 Stepping motor drive (IC4501) block diagram ..............................................................3-23
3.11.3 Stepping motor drive (IC4501) pin functions.................................................................3-24
SECTION 4 DECK CIRCUIT

4.1 PRE/REC (IC3501) ..............................................................................................................4-1
4.1.1 PRE/REC (IC3501) block diagram & pin location...........................................................4-1
4.1.2 PRE/REC (IC3501) pin functions ...................................................................................4-2
4.2 AUDIO PROCESS (IC2001).................................................................................................4-3

4.2.1 Audio process (IC2001) block diagram & pin location ....................................................4-3
4.2.2 Audio process (IC2001) pin functions ............................................................................4-4
4.3 CPU (IC101).........................................................................................................................4-5

4.3.1 CPU (IC101) pin location ...............................................................................................4-5
4.3.2 CPU (IC101) pin functions .............................................................................................4-6
INDEX-2
4.4 RTC (IC104).........................................................................................................................4-9
4.4.1 RTC (IC104) block diagram & pin location .....................................................................4-9
4.4.2 RTC (IC104) pin functions..............................................................................................4-9
4.5 EEPROM (IC105).................................................................................................................4-10

4.5.1 EEPROM (IC105) block diagram & pin location .............................................................4-10
4.5.2 EEPROM (IC105) pin functions .....................................................................................4-11
4.6 SYSCON SUB (IC108) .........................................................................................................4-12

4.6.1 SYSCON SUB (IC108) pin location................................................................................4-12
4.6.2 SYSCON SUB (IC108) pin functions..............................................................................4-13
4.7 OSD (IC109) ........................................................................................................................4-14

4.7.1 OSD (IC109) pin location ...............................................................................................4-14
4.7.2 OSD (IC109) block diagram ...........................................................................................4-14
4.7.3 OSD (IC109) pin functions .............................................................................................4-15
4.8 CTL AMP (IC1201)...............................................................................................................4-16

4.8.1 CTL AMP (IC1201) block diagram & pin location ...........................................................4-16
4.8.2 CTL AMP (IC1201) pin functions....................................................................................4-17
4.9 MECHA MDA (IC1601) ........................................................................................................4-18

4.9.1 MECHA MDA (IC1601) pin location ...............................................................................4-18
4.9.2 MECHA MDA (IC1601) block diagram ...........................................................................4-19
4.9.3 MECHA MDA (IC1601) pin functions .............................................................................4-20
4.10 REGULATOR (IC6001) ......................................................................................................4-22

4.10.1 REGULATOR (IC6001) block diagram & pin location ...................................................4-22
4.10.2 REGULATOR (IC6001) pin functions ...........................................................................4-23
SECTION 5 MONITOR & SPEAKER / E. VF CIRCUITS

5.1 RGB DECODER / DRIVER (IC7502)....................................................................................5-1
5.1.1 RGB decoder / driver (IC7502) block diagram & pin location .........................................5-1
5.1.2 RGB decoder / driver (IC7502) pin functions..................................................................5-2
5.2 TIMING CONTROL (IC7505) ...............................................................................................5-3

5.2.1 Timing control (IC7505) block diagram & pin location.....................................................5-3
5.2.2 Timing control (IC7505) pin function...............................................................................5-4
5.3 E. VF (IC7001) .....................................................................................................................5-5

5.3.1 E. VF (IC7001) block diagram & pin location..................................................................5-5
5.3.2 E. VF (IC7001) pin functions ..........................................................................................5-5
SECTION 6 SECAM CIRCUIT

6.1 SECAM COLOR PROCESS (IC3401)..................................................................................6-1
6.1.1 SECAM color process (IC3401) block diagram & pin location ........................................6-1
6.1.2 SECAM color process (IC3401) pin functions ................................................................6-2
6.2 SECAM COLOR (IC4751) ....................................................................................................6-3

6.2.1 SECAM color (IC4751) block diagram & pin location .....................................................6-3
6.2.2 SECAM color (IC4751) pin functions..............................................................................6-4
INDEX-3
6.3 BASEBAND DELAY LINE (IC4752)......................................................................................6-5
6.3.1 Baseband delay line (IC4752) pin location .....................................................................6-5
6.3.2 Baseband delay line (IC4752) block diagram .................................................................6-5
6.3.3 Baseband delay line (IC4752) pin functions ...................................................................6-6
6.4 SYNC SEPARATOR (IC4754) ..............................................................................................6-7

6.4.1 Sync separator (IC4754) block diagram & pin location...................................................6-7
6.4.2 Sync separator (IC4754) pin functions ...........................................................................6-7
INDEX-4
SECTION 1
OUTLINE
1.1 GENERAL STATEMENT OF 1998 CAMCORDERS
Models of JVC camcorders that were newly put on the market throughout the year of 1998 are listed in
Table 1-2-1.
As a notable feature of 1998 models, the DSC (Digital Still Camera) function is employed in some of them.
In other words, some of 1998 models are capable of "SNAP SHOT" that is a familiar function to users of
the DVC (Digital Video Camera).
By the function of the "SNAP SHOT", still pictures can be recorded on video tape, therefore, the user can
take snapshots to record momentary expressions and stop-motions of camera objects.
1.2 TABLE OF CAMCORDER MODELS (NEWLY PUT ON THE MARKET IN 1998)

1.2.1 Table of camcorder models 1/2
Color Y/C & Process VF LCD

Model Name Description
System System Type Monitor
GR-AX220 NTSC Analog Color Not used
GR-AX230U NTSC Analog B/W Not used
GR-AX230U-C NTSC Analog B/W Not used
GR-AX247UM NTSC Analog B/W Not used
GR-AX255 NTSC Analog Color Not used
GR-AX430U NTSC Analog Color Not used
GR-AX430U-C NTSC Analog Color Not used
GR-AX730U-C NTSC Analog Color Not used
GR-AX847UM NTSC Analog Color Not used
GR-AXM100U NTSC Analog B/W 3inch
GR-AXM100U-C NTSC Analog B/W 3inch
GR-AXM33UM NTSC Analog B/W 3inch
GR-AX830U NTSC Digital Color Not used
GR-AX830U-C NTSC Digital Color Not used
GR-AX930U-C NTSC Digital Color Not used
GR-AX947UM NTSC Digital Color Not used
GR-AX999UM NTSC Digital Color Not used DSC built-in
GR-AXM270U NTSC Digital B/W 3inch
GR-AXM270U-C NTSC Digital B/W 3inch
GR-AXM650U NTSC Digital Color 3inch
GR-AXM700 NTSC Digital B/W 3inch DSC built-in
GR-AXM700U NTSC Digital B/W 3inch DSC built-in
GR-AXM77UM NTSC Digital B/W 3inch
GR-AXM800U NTSC Digital Color 4inch
Table 1-2-1 Table of camcorder models 1/2

1-1
· Table of camcorder models 2/2

Model Name Description
GR-AXM900U NTSC Digital B/W 4inch DSC built-in
GR-AXM99UM NTSC Digital B/W 3inch DSC built-in
GR-AX11EG-S PAL Analog B/W Not used
GR-AX280EA PAL Analog B/W Not used
GR-AX280EE PAL Analog B/W Not used
GR-AX280EG PAL Analog B/W Not used
GR-AX280EK PAL Analog B/W Not used
GR-AX31EG-S PAL Analog Color Not used
GR-AX358EG-B PAL Analog B/W Not used
GR-AX380EG PAL Analog Color Not used
GR-AX480EE PAL Analog B/W Not used
GR-AX480EG PAL Analog B/W Not used
GR-AX480EK Analog B/W Not used
GR-AX528EG-S PAL Analog Color Not used
GR-AX558EG-B PAL Analog Color Not used
GR-AXM18EG-S PAL Analog B/W 3inch
GR-AXM23EA PAL Analog B/W 3inch
GR-AXM23EG Analog B/W 3inch
GR-AXM23EK PAL Analog B/W 3inch
GR-AXM33EG-SH PAL Analog B/W 3inch
GR-AXM33EK Analog B/W 3inch
GR-AXM368EG-B PAL Analog B/W 3inch
GR-AX680EG PAL Digital B/W Not used
GR-AX680EK PAL Digital B/W Not used
GR-AX780EE PAL Digital B/W Not used
GR-AX880EG PAL Digital B/W Not used DSC built-in
GR-AX880EK PAL Digital B/W Not used DSC built-in
GR-AX958EG-SH PAL Digital B/W Not used DSC built-in
GR-AXM38EG-S PAL Digital B/W 4inch
GR-AXM43EG PAL Digital B/W 3inch
GR-AXM500EK Digital B/W 3inch DSC built-in
GR-AXM53EA PAL Digital B/W 3inch
GR-AXM66EG-SH PAL Digital B/W 4inch
GR-AXM768EG-B PAL Digital B/W 4inch
GR-AX550S Analog B/W Not used
GR-AXM270S SECAM Analog B/W 3inch
GR-AX650S SECAM Digital B/W Not used
GR-AX850S SECAM Digital B/W Not used DSC built-in
GR-AXM670S SECAM Digital B/W 4inch
GR-AXM870S SECAM Digital B/W 3inch DSC built-in
Table 1-2-1 Table of camcorder models 2/2
1-2
SECTION 2
DSC CIRCUIT GR-AXM700U/AXM500EK/AXM870S
"DSC" is an abbreviation for "Digital Still Camera". The DSC function enables the camera to save still
pictures in the built-in memory when the camera is set in the "SNAP SHOT" mode.
The "SNAP SHOT" mode is classified into two modes of the VIDEO mode and DSC mode, which are
switchable to each other by a slide switch depending on the situation. In the VIDEO mode still pictures are
recorded both on video tape and in the built-in memory, on the other hand, in the DSC mode still pictures
are recorded in the built-in memory only. Still pictures can be recorded in either of two selective types: one
is the PINUP type to record a still picture with white edges, and the other is the FULL type to record a
picture without edge. There are two classes of resolutions provided for deciding picture quality on taking a
still picture in the commemorative photography mode. In the FINE mode 22 still pictures can be saved in
the built-in memory, while in the STANDARD mode 44 still pictures can be saved in it.
Regarding playback of still pictures in the VIDEO mode and DSC mode, the VIDEO mode plays back still
pictures in the general video playback manner, while the DSC mode plays back still pictures recorded in
the built-in memory. Since still pictures saved in the built-in memory are automatically numbered in
sequence, it is easy not only to protect or erase respective pictures but to play them back by index number
or in the slide manner. Furthermore, still pictures saved in the built-in memory can be inserted into
recording on other video tape and transferred to a personal computer. On the other hand, picture data
saved in the memory of a personal computer can be saved in the built-in memory of the DSC circuit as
desired. For communication with a personal computer to transmit and receive picture data between the
two, it is needed to use an optional software "Picture Navigator".
2.1 LIST OF CAMCORDER WITH A BUILT-IN DSC

Model Name Brand
GR-AXM700 Victor NTSC Digital B/W 3 inch
GR-AXM700U JVC NTSC Digital B/W 3 inch
GR-AXM900U JVC NTSC Digital B/W 4 inch
GR-AXM99UM JVC NTSC Digital B/W 3 inch
GR-AX999UM JVC NTSC Digital Color Not used
GR-AX880EG JVC PAL Digital B/W Not used
GR-AX880EK JVC PAL Digital B/W Not used
GR-AX958EG-SH JVC PAL Digital B/W Not used
GR-AXM500EK JVC PAL Digital B/W 3 inch
GR-AX850S JVC SECAM Digital B/W Not used
GR-AXM870S JVC SECAM Digital B/W 3 inch
Table 2-1-1 List of camcorder with a built-in DSC
2-1
2.2 SIGNAL FLOW
In the general video-recording, CCD output is supplied to the Y/C circuit after correlative double sampling
and A-D conversion by the CDS/AD circuit, every necessary compensation, image processing and D-A
conversion by the DSP (Digital Signal Processor) circuit. However, when the "commemorative
photography button" is pressed, image data for one field is transferred from the DSP circuit to the DSC
circuit.
In the general video playback, video data recorded on video tape is played back. On the other hand, still
pictures saved in the memory built-in the DSC circuit are played back in the DSC playback mode.
EE & REC
OP SIGNAL
PB SIGNAL
CCD
CDS / AGC / AD
DIGITAL
DSP DSC OUT
AV OUT
Y / C
VF
PROCESS
MONITOR
PRE / REC HEAD
Fig 2-1-1 Signal flow
2-2
2.3 DSC BLOCK
2.3.1 DSC block diagram
0 5 REAR
J505
8 7 6
5 4 3
2 1
10 9
CN32
SIN
1
DSC_GND
2
SOUT
3
0 1 MAIN1 0 8 DSC IC8006
CN19 CN81
17 MY7 11
IC4001 IC8001
18 MY6 10 RS232C
19 MY5 9 IF CN82
95 11 8
DCY7 MY4 Y7 116 97 SIN 1
20 8 2TXD TIIN 14
Y IN/OUT MY3 Y IN/OUT DSC_GND 2
21 7 2RXD RIOUT 13
103 DCY0 MY2 Y0 125 98 9 SOUT 3
22 6 X8001
23 MY1 5
DSP 24 MY0 4
22 3 2
XIN OUT GND
MC3
13 15 21 R8003 OSC
104 D C C 3 MC2 C3 132
R-Y IN/OUT 14 14 R-Y XOUT 4
B-Y IN/OUT MC1 IN/OUT
15 13 B-Y VDD DSC_3.3V
107 D C C 0 MC0 C0 135 20
16 12 SCLK
24 ADDRESS BUS
A8 - A30
DATA BUS
16
2 HD_H 137
MHD 11 17 AHD D0 - D15
3 VD_H 138
MVD 10 18 AVD
108 MCLK 139
DCLK 9 19 VCLK
136 FLD
IC8002
A8 - A30
D0 - D15
CPU
IF 18
CLKIN
90 INT2 SID 100 71 SID IC8003

91 INT3 BS 9 13 BS
92 99 69
A0 - A18
R/W R/W
DQ0 - DQ15
PORT3 DSC
BCL 101 72 BCL
BCH 102 73 BCH
CPU
DC 8 12 DC
HREQ 44 40 HREQ
HACK 43 39 HACK
IC101 29 22
CS CS 1M
42 37
FLASH
INT INT
59 MEMORY
CPU 60 94
RST
DSC_3.3V
47 FI 128 26
FI 12 16 CE CE
71 CS_CE1 117 129 28
CS_CEL 8 20 CE1 OE OE
127 SCK1 116 130 11
SCK1 25 3 SCK WE WE
125 SO1 114 131 15
SO1 26 2 SI RY/BY RY/BY
126 SI1 115 80 12
SI1 27 1 SO RST RESET
DSC_3.3V 47 BYTE
FROM
IC8004_4PIN
Fig. 2-3-1 DSC block diagram
2-3
2.4 OUTLINE OF DSC CIRCUIT
The DSC circuit is composed of the CPU IF IC to perform data communication, the DSC CPU to compress
image data, the Flash memory to save image data and the RS2232C IF to transmit/receive image data
to/from a personal computer.
In shooting, Y (luminance) data and C (color difference) data on one field output from the DSP IC are
transferred to the CPU IF IC of the DSC circuit as shown in Fig. 2-4-1. Since there are two buffers in the
CPU IF IC, the respective buffers alternately save Y data and C data for 1H and alternately transfer the
data to the DSC CPU. The DSC CPU compresses image data by the JPEG system and writes the JPEG-
compressed data in the Flash memory. In the pinup mode a picture is white-edged by the DSC CPU.
In playback, JPEG data read out of the Flash memory is decompressed by the DSC CPU IC and then
output to the DSP circuit through the CPU IF IC.
IC8001 IC8002 IC8003
CCD INTERFACE 1MByte

DSC CPU
& DMA Flash Memory
BUFFER1
REC
JPEG SAVE
PB
BUFFER2
In the period that Y In recording, image data is

data for 4 pixels compressed by JPEG 44 still pictures are
are transferred, C system. In the pinup mode, saved here in the
data for 1 pixel is still picture is white-edged standard mode, while
Two buffers in the
transferred. here before data 22 still pictures are
CPU IF IC
compression. saved in the fine
alternately operate
In playback, JPEG- mode.
at intervals of 1H.
compressed data is
decompressed here.
Fig. 2-4-1 DSC signal flow
2-4
2.5 CPU INTERFACE (IC8001)
Since the CPU IF IC has both the functions of interface and DMA (Direct Memory Access), it transfers
image data between the DSP circuit and the DSC CPU under control of the DSC CPU besides the function
to manage RS-232C serial communication.
If the DSC CPU directly communicates with the memory to transmit/receive image data, it takes a
considerable time to process a great deal of image data. Therefore, the CPU IF IC is used to speed up
image data processing.
Moreover, the CPU IF IC incorporates two buffers inside. Thanks to this merit, this IC charges data for 1H
in one buffer while it transfers data for the preceding 1H to the DSC CPU reading it out of the other buffer.
This operation avoids such a trouble as overwriting the preceding 1H data with new 1H data during data
transfer.
Regarding the signal transfer system, the DSP IC transfers Y (luminance) signal data in 8-bit width and C
(color difference) signal data in 4-bit width. Moreover, C (color difference) data is transferred in a data
distribution system that high-order 4 bits are allotted to R-Y data while low-order 4 bits are allotted to B-Y
data. As a result, the ratio among Y, R-Y and B-Y of video signal components is 4:1:1.
In recording, 1H image data charged in one buffer is transferred to the DSC CPU in the form of 16-bit wide
data, which is followed by the next 1H data. Explaining in detail, 8-bit Y data is transferred to the DSC CPU
first and C data of the rest 8 bits is transferred to the DSC CPU following the Y data. In playback, 16-bit
wide data is restored to its original form comprising 8 bits of Y data and the other 8 bits (double 4 bits) of C
data.
Y8 Y7 Y6 Y5 Y4 Y3 Y2 Y1
0 0 0 0 0 0 0 0
1 1 1 1 1 1 1 1
2 2 2 2 2 2 2 2
3 3 3 3 3 3 3 3
4 4 4 4 4 4 4 4
5 5 5 5 5 5 5 5
6 6 6 6 6 6 6 6
from to
DSP 7 7 7 7 7 7 7 7 CPU IF
4 0 4 0 4 0 4 0
5 1 5 1 5 1 5 1
6 2 6 2 6 2 6 2
7 3 7 3 7 3 7 3
B-Y B-Y R-Y R-Y B-Y B-Y R-Y R-Y
High Low High Low High Low High Low
B-Y 2 R-Y 2 B-Y 1 R-Y 1
Fig. 2-5-1 Y & C data transfer
For transferring data on one still picture, four kinds of sync signals are used as shown in Fig. 2-5-2, and a
field data is saved at the rise of FLD, AVD and AHD pulses. Then, sampling of the image data starts
several H's after the rise of AVD pulse. VCLK pulse is synchronized with one pixel.
FLD
1V
AVD
AHD
VCLK
Fig. 2-5-2 Image data transfer sync signal

2-5
2.5.1 CPU interface (IC8001) pin location
2RXD(JLIP)
1RXD(IrDA)
2TXD(JLIP)
1TXD(IrDA)
P_READY
P_WAIT
INT3(L)
INT2(L)
INT1(L)
PORT3
BCH(L)
P_CD2
P_CD1
RST(L)
R/W(L)
BCL(L)
P_VS2
P_VS1
BUSY
GND
VDD
VDD
VDD
CE2
A30
A29
A28
A27
A26
A25
A24
A23
A22
A21
A20
SID
108
107
106
105
104
103
102
101
100
92
87
85
84
83
82
79
78
77
76
75
74
99
98
97
94
93
91
90
89
88
86
81
80
73
96
95
GND 109 72 GND
D15 110 71 D7
D14 111 70 D6
D13 112 69 D5
D12 113 68 D4
SI 114 67 P_RST
SO 115 66 P_IOWR
SCK 116 65 P_IORD
CE1 117 64 P_REG
Y7 118 63 P_D15
Y6 119 62 P_D14
Y5 120 61 P_D13
Y4 121 60 P_D12
Y3 122 59 P_D11
Y2 123 58 P_D10
Y1 124 57 P_D9
Y0 125 56 P_D8
GND
VDD
CE(L)
126
127
128
IC8001 55
54
53
VDD
GND
P_D7
OE(L) 129 52 P_D6
WE(L) 130 51 P_D5
RY/BY 131 50 P_D4
C3 132 49 P_D3
C2 133 48 P_D2
C1 134 47 P_D1
C0 135 46 P_D0
FLD 136 45 TEST
AHD 137 44 HREQ(L)
AVD 138 43 HACK(L)
VCLK 139 42 INT(L)
D11 140 41 D3
D10 141 40 D2
D9 142 39 D1
D8 143 38 D0
GND 144 37 GND
10
11
12
13
14
15
16
17
18
19
20
21
22
23
24
25
26
27
28
29
30
31
32
33
34
35
36
1
2
3
4
5
6
7
8
9
XOUT
P_CE1
P_CE2
A19
A18
A17
A16
A15
A14
DC(L)
A13
A12
A11
A10
GND
VDD
VDD
VDD
SCLK
BS(L)
P_OE
P_A0
P_A1
P_A2
P_A3
P_A4
P_A5
P_A6
P_A7
P_A8
P_A9
XIN
CS(L)
A9
A8
P_WE
Fig. 2-5-3 CPU interface (IC8001) pin location
2-6
2.5.2 CPU interface (IC8001) block diagram
DMA controller CCD image interface
TEST Y7-0
C3-0
DMACSJVC CCDIF2 FLD
AVD
SCLK CLKGEN AHD
Clock VCLK
generator
Y TXD1
Interval IrDA- S
RST(L) timer UART1
SIR10
Y RXD1
ITIME1 S
IrDA
XIN serial
1/ 2 communication
XOUT
TXD2
ITIME2 UART2
RXD2
SI
TIME CSIO SO
SCK
A8-30 Clocked
serial P_A9-0
D0-15 I/O
P_D15-0
SID(L) P_CE1(L)
BS(L) Configration P_CE2(L)
RW P_OE(L)
BCL(L) P_WE(L)
CONFIG
Selector
BCH(L) P_REG(L)
P_IORD(L)
DC(L) PCMCIA P_IOWR(L)
Bus
interface P_RST
unit PCMCIA
HREQ(L) interface P_READY
HACK(L) P_CD1(L)
CS(L) P_CD2(L)
BIU Interrupt
INT(L) controller P_VS1(L)
P_VS2(L)
P_WAIT(L)
Programmable
port
ICU
CE1
PORT_J
RY_BY
PORT3
INT1
INT2
INT3
BUSY(L)
CE(L)
OE(L)
WE(L)
CE2(L)
Fig. 2-5-4 CPU interface (IC8001) block diagram
2-7
2.5.3 CPU interface (IC8001) pin functions 1/3
Pin No. Pin Name I/O REF.

1 VDD - Power supply (+3.3V)
2 A19 In/Out
3 A18 In/Out
4 A17 In/Out
Address inputs/outputs
5 A16 In/Out
6 A15 In/Out
7 A14 In/Out
8 DC (L) In/Out Data complete
9 BS (L) In Bus start
10 P_CE1 In/Out
11 P_CE2 In/Out
12 P_OE In/Out
13 P_A0 In/Out
Not used
14 P_A1 In/Out
15 P_A2 In/Out
16 P_A3 In/Out
17 P_A4 In/Out
18 GND - Ground
20 SCLK In System clock input
21 XOUT Out 1/2 periods clock output
22 XIN In External clock input
23 P_A5 In/Out
24 P_A6 In/Out
25 P_A7 In/Out
Not used
26 P_A8 In/Out
27 P_A9 In/Out
28 P_WE In/Out
29 CS (L) Out Chip select
30 A13 In/Out
31 A12 In/Out
32 A11 In/Out
33 A10 In/Out
34 A9 In/Out
35 A8 In/Out
37 GND - Ground
38 D0 In/Out
39 D1 In/Out
Data inputs/outputs
40 D2 In/Out
41 D3 In/Out
42 INT (L) Out External interrupt request output pin
43 HACK (L) In Hold acknowledge
44 HREQ (L) Out Bus right request input pin of the system bus
45 TEST In/Out Test pin
46 P_D0 In/Out
47 P_D1 In/Out Not used
48 P_D2 In/Out
Table 2-5-1 CPU interface (IC8001) pin functions 1/3

2-8
· CPU interface (IC8001) pin functions 2/3

49 P_D3 In/Out
50 P_D4 In/Out
51 P_D5 In/Out Not used
52 P_D6 In/Out
53 P_D7 In/Out
54 GND - Ground
56 P_D8 In/Out
57 P_D9 In/Out
58 P_D10 In/Out
59 P_D11 In/Out
60 P_D12 In/Out
61 P_D13 In/Out
Not used
62 P_D14 In/Out
63 P_D15 In/Out
64 P_REG In/Out
65 P_IORD In/Out
66 P_IOWR In/Out
67 P_RST In/Out
68 D4 In/Out
69 D5 In/Out
Data inputs/outputs
70 D6 In/Out
71 D7 In/Out
72 GND - Ground
74 A20 In/Out
75 A21 In/Out
76 A22 In/Out
77 A23 In/Out
78 A24 In/Out
79 A25 In/Out
80 RST (L) In System reset input pin
81 P_READY In/Out
82 P_CD1 In/Out
83 P_CD2 In/Out
84 P_VS1 In/Out
85 P_VS2 In/Out Not used
86 P_WAIT In/Out
87 CE2 Out
88 BUSY (L) In
89 INT1 (L) In
90 INT2 (L) In VD (vertical drive) interrupt input
91 INT3(L) In HD (horizontal drive) interrupt input
92 PORT3 In/Out Field index input port
94 GND - Ground
95 TXD1 (IrDA) Out RS232C TXD for IrDA
96 RXD1 (IrDA) In RS232C RXD for IrDA

2-9
· CPU interface (IC8001) pin functions 3/3

97 TXD2 (JLIP) Out RS232C TXD for PC
98 RXD2 (JLIP) In RS232C RXD for PC
99 RW (L) In/Out Outputs R/W (L) to identify whether the external bus cycle a read or a write cycle
100 SID In/Out Space identifier between user space and I/O space (L: user, H: I/O)
101 BCL (L) In/Out BCL (L) corresponds to the LSB side (D8 to D15)
102 BCH (L) In/Out BCH (L) corresponds to the MSB side (D0 to D7)
103 A26 In/Out
104 A27 In/Out
105 A28 In/Out Address inputs/outputs
106 A29 In/Out
107 A30 In/Out
109 GND - Ground
110 D15 In/Out
111 D14 In/Out
Data inputs/outputs
112 D13 In/Out
113 D12 In/Out
114 SI In Serial data input
115 SO Out Serial data output
116 SCK In/Out Serial clock input/output
117 CE1 In/Out Chip select
118 Y7 In/Out
119 Y6 In/Out
120 Y5 In/Out
121 Y4 In/Out
Digital Y signal input
122 Y3 In/Out
123 Y2 In/Out
124 Y1 In/Out
125 Y0 In/Out
126 GND - Ground
128 CE (L) Out Chip enable
129 OE (L) Out Output enable
130 WE (L) Out Write enable
131 RY_BY In Ready / Busy signal
132 C3 In/Out
133 C2 In/Out
Digital Color signal input
134 C1 In/Out
135 C0 In/Out
136 FLD In Field index input port
137 AHD In HD (horizontal drive) input
138 AVD In VD (vertical drive) input
139 VCLK In CCD image clock input
140 D11 In/Out
141 D10 In/Out
Data inputs/outputs
142 D9 In/Out
143 D8 In/Out
144 GND - Ground

2-10
2.6 DSC CPU (IC8002)
Since this IC has no operating program inside, it operates according to the program stored in the IC8003
(Flash memory).
In video-recording, the DSC CPU first saves Y and C data for 1 field that are transferred from the CPU IF
and then overwrite the saved data with frame data (white edges in the pinup mode, or no edge in the full
mode). Next, it converts (square grid conversion) the data into pixels for personal computer and then
saves the whole pixel data in the Flash memory (IC8003) after JPEG data compression.
In playback, the DSC CPU reads pixel data out of the Flash memory and decompress the data before
transferring it to the CPU IF IC. Since the data on one still picture saved in the RAM is for one field only,
the same field data is interpolated to prepare one frame data before returning the data to the DSP circuit.
Among some playback modes, the index playback and slide playback (slide show) are controlled
according to commands of the SYSCON CPU (IC101).
2.6.1 DSC CPU (IC8002) pin location

WKUP
VCC
VCC
VCC
VCC
VCC
VSS
VSS
VSS
VSS
D10
D11
D12
D13
D14
D15
NC
NC
D8
D9
100
99
98
97
96
95
94
93
92
91
90
89
88
87
86
85
84
83
82
81
VCC 1 80 VCC
A19 2 79 A30
A18 3 78 A29
A17 4 77 A28
A16 5 76 A27
VSS 6 75 VSS
A15 7 74 A26
A14 8 73 BCH(L)
VCC 9 72 BCL(L)
VCC 10 71 SID
NC 11 70 VCC
DC(L) 12 69 R/W(L)
BS(L) 13 68 VCC
VCC 14 67 VCC
VSS
PLLRC
15
16 IC8002 66
65
VSS
VSS
VSS 17 64 VCC
CLKIN 18 63 VCC
VSS 19 62 VCC
PP1 20 61 VCC
PP0 21 60 RST(L)
CS(L) 22 59 M/S(L)
A13 23 58 A25
A12 24 57 A24
VSS 25 56 VSS
A11 26 55 A23
A10 27 54 A22
A9 28 53 A21
A8 29 52 A20
VCC 30 51 VCC
31
32
33
34
35
36
37
38
39
40
41
42
43
44
45
46
47
48
49
50
VDD
VDD
VDD
VDD
VDD
VDD
VDD
VDD
VDD
VDD
VDD
VDD
VDD
VDD
VDD
VDD
VDD
VDD
VDD
VDD
Fig. 2-6-1 DSC CPU (IC8002) pin location
2-11
2.6.2 DSC CPU (IC8002) block diagram
128
128 instruction queue
cache
memory 128 bits x 2 stages
(4K bytes)
instruction
RST(L)
decorder
M/S(L)
128 bits internal bus
multiply
accumulate
register
unit
32 bits load/
PC ALU shift 32 x 16 bits
x store INT(L)
128 MUL
16
+
DRAM SBI(L)
56 bits-ACC
(1M bytes)
WKUP(L)
STBY(L)
128 32 bits
programmable PP0
data selector memory I/O port PP1
32 bits <-> 128 bits controller
128 CLKIN
PLL clock
external bus interface unit PLLCAP
generating
128 bits <-> 16 bits circuit PLLVCC
PLLVSS
23 16
BS(L)
HACK(L)
BCL(L)
DC(L)
BURST(L)
HREQ(L)
CS(L)
BCH(L)
R/W(L)
SID
ST
A8-A30
D0-D15
Fig. 2-6-2 DSC CPU (IC8002) block diagram
2-12
2.6.3 DSC CPU (IC8002) pin function
CLKIN SID
PLLCAP BCL(L)
clock
PLLVCC BCH(L)
PLLVSS BS(L)
ST
bus
R/W(L)
RST(L) control
BURST(L)
system M/S(L)
DC(L)
control WKUP(L)
IC8002 HREQ(L)
STBY(L)
DSC CPU HACK(L)
CS(L)
23
address bus A8-A30
INT(L)
interrupt input
SBI(L)
16
data bus D0-D15
PP0 programmable
PP1 I/O port
Fig. 2-6-3 DSC CPU (IC8002) pin function
2-13
2.6.4 DSC CPU (IC8002) pin functions 1/2

1 VCC - Power source (+3.3V)
2 A19 In/Out
3 A18 In/Out
Address Inputs/Outputs
4 A17 In/Out
5 A16 In/Out
6 VSS - Ground
7 A15 In/Out
8 A14 In/Out
11 STBY (L) Out An "L" level is output while in the standby mode
12 DC (L) In/Out Data complete
13 BS (L) Out Bus start
14 PLLVCC - Connects a power source for internal PLL
15 PLLVSS - Connects a ground for internal PLL
16 PLLCAP - Connects a capacitor for internal PLL
17 VSS - Ground
18 CLKIN In Clock input
19 VSS - Ground
20 PP1 In/Out
Programmable I/O port
21 PP0 In/Out
22 CS (L) In Chip select
23 A13 In/Out
24 A12 In/Out
25 VSS - Ground
26 A11 In/Out
27 A10 In/Out
28 A9 In/Out
29 A8 In/Out
31 VSS - Ground
32 D0 In/Out
33 D1 In/Out
Data Inputs/Outputs
34 D2 In/Out
35 D3 In/Out
37 INT (L) In External interrupt request input pin
38 SBI (L) In System break interrupt input pin
39 HACK (L) Out Hold acknowledge
40 HREQ (L) In Bus right request input pin of the system bus
42 VSS - Ground
43 VSS - Ground
46 D4 In/Out
47 D5 In/Out
Data Inputs/Outputs
48 D6 In/Out
49 D7 In/Out
50 VSS - Ground
Table 2-6-1 DSC CPU (IC8002) pin functions 1/2
2-14
· DSC CPU (IC8002) pin functions 2/2

52 A20 In/Out
53 A21 In/Out
54 A22 In/Out
55 A23 In/Out
56 VSS - Ground
57 A24 In/Out
58 A25 In/Out
59 M/S (L) In Sets the default operation to either system bus master ("H") or bus slave ("L")
60 RST (L) In Internally reset
65 VSS - Ground
66 VSS - Ground
69 R/W (L) In/Out Outputs R/W (L) to identify whether the external bus cycle a read or a write cycle
71 SID In/Out Space identifier between user space and I/O space (L: user / H: I/O )
72 BCL (L) In/Out BCL (L) corresponds to the LSB side (D8 to D15)
73 BCH (L) In/Out BCH (L) corresponds to the MSB side (D0 to D7)
74 A26 In/Out Address Inputs/Outputs
75 VSS - Ground
76 A27 In/Out
77 A28 In/Out
78 A29 In/Out
79 A30 In/Out
81 VSS - Ground
82 D15 In/Out
83 D14 In/Out
Data Inputs/Outputs
84 D13 In/Out
85 D12 In/Out
87 BURST (L) Out Burst
88 ST Out Bus status
90 VSS - Ground
92 VSS - Ground
94 WKUP (L) In Input pin to request return from standby mode
96 D11 In/Out
97 D10 In/Out
Data Inputs/Outputs
98 D9 In/Out
99 D8 In/Out
100 VSS - Ground
Table 2-6-1 DSC CPU (IC8002) pin functions 2/2
2-15
2.7 1M FLASH MEMORY (IC8003)
The IC8003 is an flash memory having 1 Mbyte storage capacity, and it also has the program to operate
the IC8002. Among its 1 Mbyte storage capacity, about 220 kbytes are used for the operating program for
the IC8002, about 700 kbytes are used for saving image data, and the rest of 100 kbytes are used for
saving address data.
In the image data domain, data for 22 still pictures can be saved in the fine mode or those for 44 still
pictures can be saved in the standard mode.
2.7.1 1M Flash memory (IC8003) pin location
A15 1 48 A16
A14 2 47 BYTE(L)
A13 3 46 VSS
A12 4 45 DQ15/A-1
A11 5 44 DQ7
A10 6 43 DQ14
A9 7 42 DQ6
A8 8 41 DQ18
A19 9 40 DQ5
NC 10 39 DQ12
WE(L) 11 38 DQ4
RESET(L)
NC
12
13
IC8003 37
36
VCC
DQ11
NC 14 35 DQ3
RY/BY(L) 15 34 DQ10
A18 16 33 DQ2
A17 17 32 DQ9
A7 18 31 DQ1
A6 19 30 DQ8
A5 20 29 DQ0
A4 21 28 OE(L)
A3 22 27 VSS
A2 23 26 CE(L)
A1 24 25 A0
Fig. 2-7-1 1M Flash memory (IC8003) pin location
2-16
2.7.2 1M Flash memory (IC8003) block diagram
DQ0-DQ15
RY/BY(L)
Buffer
RY/BY(L)
Vcc Erase Voltage Input/Output

Vss Generator Buffers
WE(L) State
BYTE(L) Control
RESET(L)
Command
Register Program voltage
Genarator Chip Enable STB
Data Latch
Output Enable
CE(L) Logic
OE(L)
Y-Decorder Y-Gating
STB
Low Vcc
Detector Timer for
Program/Erase Address
Latch
X-Decorder Cell Matrix
A0-A18
A-1
Fig. 2-7-2 1M Flash memory (IC8003) block diagram
2-17
2.7.3 1M Flash memory (IC8003) pin functions

1 A15 In
2 A14 In
3 A13 In
4 A12 In
5 A11 In Address Inputs
6 A10 In
7 A9 In
8 A8 In
9 A19 In
10 NC - No Internal Connection
11 WE (L) In Write Enable
12 RESET (L) In Hardware Reset Pin/Temporary Sector Unprotection
15 RY/BY (L) Out Ready/Busy Output
16 A18 In
17 A17 In
18 A7 In
19 A6 In
20 A5 In
Address Inputs
21 A4 In
22 A3 In
23 A2 In
24 A1 In
25 A0 In
26 CE (L) In Chip Enable
27 VSS - Device Ground
28 OE (L) In Output Enable
29 DQ0 In/Out
30 DQ8 In/Out
31 DQ1 In/Out
32 DQ9 In/Out
Data Inputs/Outputs
33 DQ2 In/Out
34 DQ10 In/Out
35 DQ3 In/Out
36 DQ11 In/Out
37 VCC - Device Power Supply
38 DQ4 In/Out
39 DQ12 In/Out
40 DQ5 In/Out
41 DQ13 In/Out
Data Inputs/Outputs
42 DQ6 In/Out
43 DQ14 In/Out
44 DQ7 In/Out
45 DQ15/A-1 In/Out
46 VSS - Device Ground
47 BYTE (L) In L: BYTE mode (8bits) / H: WORD mode (16bits)
48 A16 In/Out Address Inputs
Table 2-7-1 1M Flash memory (IC8003) pin functions

2-18
2.8 RS232C INTERFACE (IC8006)
Data on still pictures saved in the Flash memory are output as RS-232C format serial data from the CPU
IF IC (IC8001). Since there is a difference in operating voltage between the camcorder and the personal
computer, the IC8006 transforms the voltage into a proper voltage to be used in the personal computer
before outputting it. On the other hand, when receiving image data from a personal computer, the IC8006
transforms the voltage of the personal computer into the voltage equivalent to that for the DSC circuit.
2.8.1 RS232C INTERFACE (IC8006) pin location & block diagram
EN (L) 1 16 FORCEOFF(L)
C1+ 2 15 VCC
IC8006
V+ 3 14 GND
C1- 4 13 TIOUT
C2+ 5 12 FORCEON
C2- 6 11 TIIN
V- 7 10 INVALID(L)
R1IN 8 9 R1OUT
Fig. 2-8-1 RS232C INTERFACE (IC8006) pin location & block diagram
2.8.1 RS232C Interface (IC8006) pin functions

1 EN (L) Receiver enable control
2 C1+ Positive terminal of charge pump capacitor for voltage doubler
3 V+ 5.5 V power generated by charge pump
4 C1- Negative terminal of charge pump capacitor for voltage doubler
5 C2+ Positive terminal of inverse charge pump capacitor
6 C2- Negative terminal of inverse charge pump capacitor
7 V- -5.5 V power generated by charge pump
8 R_IN (R STN) In RS-232C receiver input
9 R_OUT (2RXD) Out RS-232C RXD for personal computer
10 INVALID (L) Out Valid signal detection output
11 T_IN (2TXD) In RS-232C TXD for personal computer
12 FORCEON Overwriting automatic circuit when FORCEON is at H level
13 T_OUT (R SOUT) Out RS-232C transmitter output
14 GND - GND
15 VCC - Power supply (+3.3 V)
16 FORCEOFF (L) Overwriting automatic circuit and FORCEON
Table 2-8-1 RS232C Interface (IC8006) pin functions
2-19
2.9 RESET CIRCUIT (IC8004, IC8007, IC8008, IC8009)
If the CPU IF IC (IC8001) and DSC CPU (IC8002) are released from resetting at the same time because
of power supply to the DSC circuit, both bus-line outputs come into collision with each other. To prevent
the respective outputs from collision, reset cancel timing of certain IC's is delayed as shown in Fig. 2-9-1.
Fig. 2-9-2 is an input/output timing chart of each IC in the period from power supply to the DSC circuit to
start of communication through the bus line between CPU IF IC and DSC CPU. Details of the reset timing
operation are explained in the following.
Timing 1: Power is supplied to the DSC circuit and every IC is turned on. However, the reset
terminals of the IC8001 and IC8002 are held at L level because outputs of the IC8004 and IC8007 are
delayed for their respective inputs. When the IC8001's pin 14 (RST[L]) is at L level, the IC8001 is in the
reset status, while the pin 44 (HREQ[L]) of IC8001 outputs L level signal to the pin 40 (HREQ[L]) of
IC8002, which accordingly keeps all bus lines in the hold status to disable outward access. At that time,
both inputs to the pin 1 and pin 2 of IC8009 are at H level, and the output level of the IC8009 is L as
shown in the truth table of Fig. 2-9-1.
Timing 2: H level signal is supplied to the reset terminals of IC8001 and IC8002, and these IC's are
accordingly released from the reset status. The input levels at the pin 1 and pin 2 of IC8009 change to L
and H respectively, however, its output level is still L.
Timing 3: As the IC8002 is disabled for any outward access, L level signal is output from the pin 39
(HACK[L]) of IC8002 to the pin 2 of IC8009. Accordingly, input levels at the pin 1 and pin 2 of IC8009
change to L respectively and its pin 4 outputs H level signal to the pin 43 (HACK[L]) of IC8001. As a
result, the IC8002 is released from the reset status and the IC8001 is informed that the bus lines come
into the hold status.
Timing 4: Simultaneously with input of H level signal to the pin 40 (HREQ[L]) of IC8002 from the
pin 44 (HREQ[L]) of IC8001, bus communication between the IC8001 and IC8002 starts.
2-20
DSC 3.3V
VCC 5 IC8001
CPU IF
IC8004
System HREQ(L) 44
Reset VDD
HACK(L) 43 Truth table
OUT 4 14 RST(L) 1pin 2pin 4pin
L L H
IC8009 L H L
VCC 5 IC8008
INVERTER H L L
IC8007 1
System 4 H H L
Reset 2
OUT 4 1 7
39 HACK(L)
2 6
HREQ(L) 40
VCC
OUT 60 RST(L)
Truth table VCC
IC8004 and IC8007 1pin 7,6pin 2pin
output Vcc delaying IC8002
its rise for 100 msec L H L DSC
or more.
H L H
Fig. 2-9-1 System reset block
2-21
Timing 2 Timing 3
Timing 1 Timing 4
IC8004,IC8007,IC8001,
IC8002,IC8008,IC8009
VCC
IC8004,IC8007
4pin OUT
1pin IN
IC8008
6,7pin OUT
2pin OUT
1pin IN
IC8009
2pin IN
4pin OUT
RST(L) IN
IC8001
HREQ(L) OUT
HACK(L) IN
RST(L) IN
IC8002
HREQ(L) IN
HACK(L) OUT
IC8001,IC8002
BUS COMMUNICATION
Fig. 2-9-2 System reset timing chart
2-22
SECTION 3
CAMERA CIRCUIT
3.1 CCD IMAGE SENSOR
The 1998 models employ the interline CCD with the electronic zoom function as the solid-state pickup
device for them. Besides the Ye, Cy and Mg filters, G-complementary mosaic filter is used. Charges stored
in the CCD are read out by the field period reading system, and the charge storage time is variable by
means of the electronic shutter function.
3.1.1 Pixel arrangement
OPTICAL BLACK
g
h NTSC PAL SECAM
inc a 2 7 3
f
4
h
1/ b 510 500 752
c 25 30 40
d 537 537 795
e 12 14 12
f 482 582 582
g 1 1 2
h 505 597 596
a b c
e
Fig. 3-1-1 pixel arrangement
3.1.2 CCD ratings
Rating
Item
GR-AXM700U GR-AXM500EK GR-AXM870S
Transfer system Interline transfer Interline transfer Interline transfer
Optical format 1/4 inch 1/4 inch 1/4 inch
510 (H) × 492 (V) 500 (H) × 582 (V) 752 (H) × 582 (V)
Effective pixels
Approx. 250000 pixels Approx. 290000 pixels Approx. 440000 pixels
537 (H) × 505 (V) 537 (H) × 597 (V) 795 (H) × 596 (V)
Overall pixels
Approx. 270000 pixels Approx. 320000 pixels Approx. 470000 pixels
Chip size 4.47mm (H) × 3.80mm (V) 4.47mm (H) × 3.80mm (V) 4.47mm (H) × 3.80mm (V)
Unit cell size 7.15µ m (H) × 5.55µ m (V) 7.3µ m (H) × 4.7µ m (V) 4.85µ m (H) × 4.65µ m (V)
Complementary color Complementary color Complementary color

Color filter system
mosaic filter (Mg, G, Cy, Ye) mosaic filter (Mg, G, Cy, Ye) mosaic filter (Mg, G, Cy, Ye)
Added functions Variable electronic shutter Variable electronic shutter Variable electronic shutter
Table 3-1-1 CCD ratings

3-1
3.1.3 CCD block diagram & pin location
VOUT
GND
NC
V1
V2
V3
V4
7 6 5 4 3 2 1
Cy Ye Cy Ye
Mg G Mg G
Vertical-Register
Cy Ye Cy Ye
G Mg G Mg
Cy Ye Cy Ye
Mg G Mg G ∗
Horizontal-Register
Photo
∗ Sensor
8 9 10 11 12 13 14
VDD
H1
H2
SUB
GND
VL
RG
Fig. 3-1-2 CCD block diagram & pin location
3.1.4 CCD pin functions
Pin No. Label In/Out REF.

1 V4 In Verticall transfer clock (4th phase) input
2 V3 In Verticall transfer clock (3rd phase) input
3 V2 In Verticall transfer clock (2nd phase) input
4 V1 In Verticall transfer clock (1st phase) input
5 NC - Not used
6 GND - GND
7 V OUT Out Video output
8 VDD - Power supply
9 GND - GND
10 SUB In Substrate (Electrical shutter pulse input)
11 VL - Transistor bias for protect
12 RG In Riset gate clock
13 H1 In Horizontal transfer clock (1st phase) input
14 H2 In Horizontal transfer clock (2nd phase) input
Table 3-1-2 CCD pin functions
3-2
3.2 CDS / AGC / AD (IC5202)
3.2.1 CDS/AGC/AD (IC5202) block diagram & pin location
CDSIN
AVDD
AVDD
AVSS
AVSS
BIAS
VRM
VRB
VRT
CIN
YIN
NC
36 35 34 33 32 31 30 29 28 27 26 25
BIAS
AVSS 37 24 NC
AVDD 38 23 CLP
NC 39 22 NC
NC 40 21 AVDD
AVDD 41 20 AVSS
AVSS 42 19 SPSIG
Gain AGC CDS
Select
CS 43 18 SPBLK
Serial Clamp
SCK 44 Interface 17 OBP
Circuit
SDATA 45 10bit ADC 16 ADCLK
DVDD 46 15 DVDD
DVSS 47 14 DVSS
Output Latch
DVSS 48 13 NC
1 2 3 4 5 6 7 8 9 10 11 12
NC
NC
D0
D1
D2
D3
D4
D5
D6
D7
D8
D9
Fig. 3-2-1 CDS/AGC/AD (IC5202) block diagram & pin location
3-3
3.2.2 CDS/AGC/AD (IC5202) pin functions

1 NC - Not used
2 D0 Out Not used
3 D1 Out
4 D2 Out
5 D3 Out
6 D4 Out
Digital output
7 D5 Out
8 D6 Out
9 D7 Out
10 D8 Out
11 D9 Out Digital output (MSB)
12 NC - Not used
13 NC - Not used
14 DVSS - Digital ground (0V)
15 DVDD - Digital power supply (+3.0V)
16 ADCLK In ADC conversion clock input
17 OBP In Optical black pulse input
18 SPBLK In Black level sampling clock input
19 SPSIG In Signal level sampling clock input
20 AVSS - Analog ground (0V)
21 AVDD - Analog power supply (+3.0V)
22 NC - Not used
23 CLP - Clamp voltage
24 NC - Not used
27 CDSIN In CDS input
28 YIN - Not used
29 CIN In Color signal input
32 VRB - Reference voltage 3
33 VRM - Reference voltage 2
34 VRT - Reference voltage 1
35 BIAS - Inside bias
36 NC - Not used
39 NC - Not used
40 NC - Not used
43 CS In Serial interface control input
44 SCK In Serial clock control input
45 SDATA In Serial data control input
46 DVDD - Digital power supply (+3.0V)
Table 3-2-1 CDS/AGC/AD (IC5202) pin functions

3-4
3.3 TG / VIDEO DRIVER (IC5201)
3.3.1 TG / Video driver (IC5201) block diagram & pin location
VGAT
VM
NC
NC
NC
NC
VH
V4
VL
V3
V1
V2
36 35 34 33 32 31 30 29 28 27 26 25
SSK 37 24 SUB
Mode Set V driver
SSI 38 Serial/ 23 VSS4
Parallel
SEN 39 SUB driver 22 H2
RST 40 H driver 21 H1
NC 41 20 VDD4
RG driver
DSGAT 42 19 VDD3
Timing Generator
XSHP/
VDD5 43 XSHD 18 RG
driver
AHD 44 HRST SW 17 NC
AVD 45 VRST 16 XSHD
CKINH 46 15 XSHP
1/2 1/3 D D
NC 47 HRST 14 VSS3
ID 48 SW 13 VDD2
1 2 3 4 5 6 7 8 9 10 11 12
NC
NC
NC
VDD1
NC
NC
CK
CCDCKL
OSCI
VSS1
VSS2
TESTEN
Fig. 3-3-1 TG / Video driver (IC5201) block diagram & pin location
3-5
3.3.2 TG / Video driver (IC5201) pin functions

1 NC - Not used
2 NC - Not used
3 VSS1 - GND
4 OSCI In Oscillation inverter input (NTSC: 1820 fH, PAL: 1816 fH)
5 NC - Not used
6 VSS2 - GND
7 CK In IC main clock input
8 TESTEN In IC test terminal control input
9 CCDCKL Out 510H master clock output; NTSC: (606+2/3) fH, PAL: (605+1/3) fH
10 VDD1 - Power supply
11 NC - Not used
12 NC - Not used
14 VSS3 - GND
15 XSHP Out CCD precharge level S/H pulse output
16 XSHD Out CCD data level S/H pulse output
17 NC - Not used
18 RG Out CCD reset gate pulse output
21 H1 Out CCD horizontal register clock output
22 H2 Out CCD horizontal register clock output
23 VSS4 - GND
24 SUB Out CCD electronic shutter pulse output
25 V2 Out CCD vertical register clock output (binary output)
26 V1 Out CCD vertical register clock output (ternary output)
27 VH - 15 V power supply
28 V3 Out CCD vertical register clock output (ternary output)
29 VL - -9 V power supply
30 VM - GND
31 V4 Out CCD vertical register clock output (binary output)
32 NC - Not used
33 NC - Not used
34 NC - Not used
35 NC - Not used
36 VGAT In Electronic zoom vertical clock dropout control signal input
37 SSK In IC's internal mode setting clock input
38 SSI In IC's internal mode setting data input
39 SEN In IC's internal mode setting strobe input
40 In IC's internal reset input terminal
41 NC - Not used
42 DSGAT In CCD drive pulse, S/H pulse generation stop control
44 AHD In Phase advanced horizontal sync signal input ahead of sync signal
45 AVD In Phase advanced vertical sync signal input ahead of sync signal
46 CKINH In CCDCKH terminal control input
47 NC - Not used
48 ID Out Vertical line discrimination signal
Table 3-3-1 TG / Video driver (IC5201) pin functions

3-6
3.4 DOWN CONVERTER (IC5203/IC4002/IC4005)
3.4.1 Down converter (IC5203/IC4002/IC4005) block diagram & pin location
CONT 1 5 VIN
GND 2
NOISE 3 Thermal 4 VOUT

Protect
Fig. 3-4-1 Down converter (IC5203/IC4002/IC4005) block diagram & pin location
3.4.2 Down converter (IC5203/IC4002/IC4005) pin functions

1 CONT In Output voltage on/off control (L: OFF, H: ON)
2 GND - GND
3 NOISE - Noise reduction capacitor connection
4 VOUT Out Rregulator output
5 VIN In Regulator input
Table 3-4-1 Down converter (IC5203/IC4002/IC4005) pin functions
3-7
3.5 DSP (IC4001)
The IC4001 is a digital signal processor (DSP) LSI that processes signals of the camcorder by only one
chip.
Functions of this IC are mentioned below.

Y/C signal processing for the line sequential color difference CCD
Arithmetic processing for the auto system (AWB, AF, AE)
Arithmetic processing for the EIS
Field memory control
3-way (NTSC/PAL/SECAM) digital color encoding
Cyclic YHNR
Shutter sound generation (D-A converter is built in)
SSG
Built-in D-A converter with sync signal adding function for 2-channel video signal
Utilizing the clock input (28.63636 MHz in NTSC, 28.375 MHz in PAL/SECAM), this IC generates internal
clocks such as clock for processing CCD input signal, that for the color encoder and the other for the SSG.
Besides those clocks, it internally generates various TV pulses because it has the SSG function.
This IC carries out Y/C signal processing for input signal from the CCD, such as gamma correction,
vertical/horizontal aperture correction, color separation, etc., and it generates 8-bit luminance signal and
8-bit bit sequential color difference signal. By its arithmetic processing for the auto systems (AWB, AF, AE),
it reads operation data according to microcomputer data. Furthermore, it is able to generate 75 % color
bar signal and blue back signal as test signals.
Following the above-mentioned operation, this IC performs data operation for camera shake correction,
field memory control, etc. Then, the luminance signal is output to the D-A converter through the cyclic
horizontal noise reducer, while the color difference signals are output to the D-A converter through the
NTSC/PAL/SECAM digital color encoder. The color encoder converts the color signal into carrier color
signal in the NTSC/PAL system or into FM (frequency-modulated) color signal just before the bell filter in
the SECAM system.
The D-A converter for the luminance signal that operates at the CCD drive frequency adds sync signal to
the luminance signal to output analog luminance signal. The D-A converter for the color signal that
operates at the frequency of 14.31818 MHz (NTSC) or 14.1875 MHz (PAL/SECAM) outputs analog color
signal.
Since this IC internally incorporates the shutter sound generator circuit and the D-A converter for shutter
sound generation, it generates shutter sound by accessing the microcomputer address.
3-8
3.5.1 DSP (IC4001) pin location
DCC0
DCC1
DCC2
DCC3
DCLK
DCY0
DCY1
DCY2
DCY3
DCY4
DCY5
DCY6
DCY7
VDD2
VDD1
VSS
VSS
VSS
NC
NC
NC
NC
NC
NC
NC
NC
NC
NC
NC
NC
NC
NC
NC
NC
NC
NC
108
107
106
105
104
103
102
101
100
98
73
97
95
99
96
94
93
92
91
90
89
88
87
86
85
84
83
82
81
80
79
78
77
76
75
74
VDD1 109 72 NC
AD8 110 71 NC
AD7 111 70 NC
AD6 112 69 NC
AD5 113 68 NC
AD4 114 67 NC
AD3 115 66 VSS
AD2 116 65 VDD1
VSS 117 64 NC
AD1 118 63 NC
AD0 119 62 NC
TCK 120 61 NC
NC 121 60 NC
NC 122 59 NC
NC 123 58 NC
NC 124 57 NC
VPD 125 56 NC
VDD2 126 55 VSS
VSS 127 54 YOUT
LHF 128 53 COUT
ID 129 52 IREF
AHD 130 51 IREFS
AVD 131 50 IREFK
NC 132 49 VREF
CPOB 133 48 VREFS
PBHD 134 47 VREFK
PBVD 135 46 NC
HBLKS 136 45 KOUT
VDD1 137 44 NC
VSS 138 43 AVDD
CBLKS 139 42 VSS
BFS 140 41 VDD2
TVSEL NTSC/PAL 141 40 DTEST
CLR 142 39 KRST
PSAVE 143 38 USEL
CLK 144 37 VDD1
10
11
12
13
14
15
16
17
18
19
20
26
27
28
29
30
31
32
33
34
35
36
21
22
23
24
25
1
2
3
4
5
6
7
8
9
MVD
OMT
VDD1
NC
NC
NC
NC
VDD2
MHD
FLD
AD10
AD11
AD12
AD13
AD14
AD15
CFMO
AD0
AD1
AD2
AD3
AD4
AD5
AD6
AD7
AD8
AD9
RE
DSTB
ALE
BUSY
VSS
HWE
LWE
VSS
VSS
Fig. 3-5-1 DSP (IC4001) pin location
3-9
3.5.2 DSP (IC4001) block diagram
DCY[7:0] FMY[7:0] TMY[7:0] TNW FMWR FMRE FMWE W A D
DCC[3:0] FMC[3:0] TMC[3:0] OMT MCLK R A E R A D W A E IE
TEST[5:0] FMREO FMWEO WADO

RAEO RADO W A E O IEO VDDI
FMY[7:0] TMY[7:0]
DCY[7:0] DCC[3:0] FMC[3:0] TMC[3:0] VDDE
CLKFMC VSS
USEL MCIF
TNW
ADR[15:0] OMT AVDD
FMWR TIIF
RE ALE MCLK AVSS
HWE LWE Micro Computer FMRE FMWE VRAM for TI
DSTB Interface RAE RAD
WAE WAD Interface VREFK
IE IREFK
LHF LHF VREFS
AFBEND AFBEND BEND P W M IREFS
BEND VREF
PWM IREF
CLKYCA CLKYCA CLKFMC CLKFMC
FYO[7:0] CLKFMC
YYO[7:0] NYO[7:0]
DNP
ADIN[8:0] Test signal generator YO[7:0] YOUT
ADIN[8:0] YCA EIS/FMC YHNR YDAC YOUT
YCO[7:0] Nega / Posi inverter NCO[3:0] FCO[3:0]
8 to 4 converter
DCTL interface JCY0069_Refine
JCY0068_Refine Hadamard NR
HDFMC
ID NHRSTD VDFMC CSYNCO
ID HDYCA DCC CFMO
VDYCA HCLR YBLK CFMO
CLK CLK
NTSC :1820fH CLK CLKYCA CLKFMC CLK14 CLK14
CLK14 C L K F M C CLKYCA CLK14
PAL :1816fH CLKSSG
SECAM:1816fH CLK14
CLKFMC FCNV FCC[7:0] CO[7:0] COUT
CLR PSAVE SSG ENC CDAC COUT
CLR PSAVE
4to8 converter NTSC/PAL/
FLD CP2 C P O B B U S Y Frequency converter SECAM
AHD AVD Color encoder
MHD MVD AHD AVD MHD MVD
CP2 BUSY NHRSTF
FLD CPOB INHE INVE
HBLKSO CBLKSO BFSO
PBHD PBVD PBHD PBVD
CLK14 R6FH
HBLKS
CBLKS HBLKS CBLKS BFS
Shutter KO[7:0] KOUT
BFS KDAC KOUT
Sound
DCLK Shutter sound R6FH
DCLK generator
NHRSTK KRST
TVSEL TVSEL0 KRST
Fig. 3-5-2 DSP (IC4001) block diagram
3-10
3.5.3 DSP (IC4001) pin functions 1/3

1 VDD1 - Power (CORE), Typ. 2.3 V
2 MHD Out Horizontal reference pulse output for microcomputer
3 MVD Out Vertical reference pulse output for microcomputer
4 FLD Out Field discrimination pulse output
5 CFMO Out Color frame pulse output
6 NC -
7 NC - Not used
8 NC -
9 VSS - GND
10 NC - Not used
11 OMT Out EIS readout data enable flag output
12 BUSY Out Busy pulse output
13 DSTB In Data strobe input
14 HWE In High-order address write enable input
15 LWE In Low-order address write enable input
16 RE In Read enable input
17 ALE In Address latch enable input
18 VDD2 - Power (I/O), Typ. 3.3 V
19 VSS - GND
20 AD0 In/Out
21 AD1 In/Out
22 AD2 In/Out
23 AD3 In/Out
24 AD4 In/Out
Microcomputer bus input/output
25 AD5 In/Out
26 AD6 In/Out
27 AD7 In/Out
28 AD8 In/Out
29 AD9 In/Out
30 VSS - GND
31 AD10 In/Out
32 AD11 In/Out
33 AD12 In/Out
Microcomputer bus input/output
34 AD13 In/Out
35 AD14 In/Out
36 AD15 In/Out
38 USEL In Microcomputer selection (H level: Test terminal)
39 KRST In Click sound reset (L: Reset)
40 DTEST In Test terminal (Lin usual)
41 VDD2 - Power (I/O) (Additional), Typ. 3.3 V
42 AVSS - GND for analog system
43 AVDD - Power (typ. 3.3 V) for analog system
44 NC - Not used
45 KOUT Out Shutter sound output
46 NC - Not used
47 VREFK In Current adjustment (for shutter sound)
48 VREFS In Current adjustment (for synchronizing)
Table 3-5-1 DSP (IC4001) pin functions 1/3

3-11
· DSP (IC4001) pin functions 2/3

49 VREF In Current adjustment reference voltage input terminal
50 IREFK Out Current adjustment (for shutter sound), 2.7 kΩ in usual
51 IREFS Out
Current adjustment (for synchronizing), 2.7 kΩ in usual
52 IREF Out
53 COUT Out Modulated color signal output
54 YOUT Out Luminance signal output
55 VSS - GND
56 NC -
57 NC -
58 NC -
59 NC -
60 NC - Not used
61 NC -
62 NC -
63 NC -
64 NC -
66 VSS - GND
67 NC -
68 NC -
69 NC -
Not used
70 NC -
71 NC -
72 NC -
74 NC -
75 NC -
76 NC -
77 NC - Not used
78 NC -
79 NC -
80 NC -
81 VSS - GND
82 NC -
83 NC -
84 NC -
85 NC -
Not used
86 NC -
87 NC -
88 NC -
89 NC -
90 VDD2 - Power (I/O), Typ. 3.3 V
91 VSS - GND
92 NC -
93 NC - Not used
94 NC -
95 DCY7 In/Out
Digital luminance signal input/output for DRAM controller connection
96 DCY6 In/Out

3-12
· DSP (IC4001) pin functions 3/3

97 DCY5 In/Out
98 DCY4 In/Out
99 DCY3 In/Out Digital luminance signal input/output for DRAM controller connection
100 DCY2 In/Out
101 DCY1 In/Out
102 VSS - GND
103 DCY0 In/Out Digital luminance signal input/output for DRAM controller connection
104 DCC3 In/Out
105 DCC2 In/Out
Digital color difference signal input/output for DRAM controller connection
106 DCC1 In/Out
107 DCC0 In/Out
108 DCLK Out Clock output for DRAM controller
110 AD8 In
111 AD7 In
112 AD6 In
113 AD5 In Digital signal input from A-D converter
114 AD4 In
115 AD3 In
116 AD2 In
117 VSS - GND
118 AD1 In
Digital signal input from A-D converter
119 AD0 In
120 TCK In Test terminal (Normal: L)
121 NC -
122 NC -
Not used
123 NC -
124 NC -
125 VPD In Test terminal (Normal: L)
126 VDDE - Power (I/O), Typ. 3.3 V
127 VSS - GND
128 LHF Out LHF signal output
129 ID In Line discrimination pulse input
130 AHD Out Horizontal reference pulse output
131 AVD Out Vertical reference pulse output
132 NC - Clamp pulse output
133 CPOB Out OB clamp pulse output
134 PBHD In Horizontal reference pulse input for PB (SECAM)
135 PBVD In Vertical reference pulse input for PB (SECAM)
136 HBLKS Out Horizontal blanking pulse output for SECAM
138 VSS - GND
139 CBLKS Out Composite blanking pulse output for SECAM
140 BFS Out Burst flag pulse output for SECAM
141 TVSEL_NTSC/PAL In TV system switching (L: NTSC, H: PAL/SECAM)
142 CLR In Clear input (L: Clear)
143 PSAVE In Power save input (L: PSAVE, H: Normal)
144 CLK In Clock input (28.63636/28.375 MHz)

3-13
3.6 FILTER & AMP (IC4003)
3.6.1 Filter & Amp (IC4003) block diagram & pin location
FSW2
YOUT
CTL2
GND
VCC
YIN
NC
FC
16 15 14 13 12 11 10 9
CLAMP VCA2 LPF
H L VCA1 BPF
-4dB
1 2 3 4 5 6 7 8
VCC
GND
NC
CIN
CTL1
COUT
CSW
FSW1
Fig. 3-6-1 Filter & Amp (IC4003) block diagram & pin location
3.6.2 Filter & Amp (IC4003) pin functions

1 VCC - Power supplyY
2 CIN In Chroma signal input
3 CSW - Chroma gain select
4 CTL1 - Chroma gain control
5 COUT Out Chroma signal output
6 FSW1 - Chroma BPF frequency select
7 GND - GND
8 NC - Not used
9 FC - LPF, BPF frquency response adjust
10 NC - Not used
11 GND - GND
12 YOUT Out Y output
13 FSW2 - Y LPF frequency select
14 CTL2 - Y gain control
15 YIN In Y signal input
16 VCC - Power supply
Table 3-6-1 Filter & Amp (IC4003) pin functions
3-14
3.7 Y/C (IC3001)
3.7.1 Y/C (IC3001) pin location
MAIN DE-EMPH COLLECTOR
MAIN DE-EMPH EMITTER

MAIN EMPH FBC FILTER/
REC LOW BAND COLOR
MAIN EMPH ALC FILTER

AUTO BALANCE FILTER
PB LOW BAND COLOR
MAIN DE-EMPH APL

AAF DET FILTER
MAIN EMPH NF
MAIN EMPH
AAF fo ADJ
BPF TRAP
REC FM
SIGNAL
SIGNAL
Y-GND
C-VCC
PB FM
64
63
62
61
60
59
58
57
56
55
54
53
52
51
50
49
COLOR KILLER
1 48 PICTURE CONTROL
DET FILTER
DISCRIMINATOR
2 47 NC ATT
FILTER
LC VCO 3 46 YNR NL-DC
REC AFC FILTER/

4 45 REC/PB SW
PB APC FILTER
CR CTL FILTER 5 44 CLAMP
2fsc 6 43 CCD DRIVE
SW30/SW25 7 42 CCD CLAMP
YNR CCD ADJ

X'TAL OSC 8 41
FILTER
fsc 9 40 VIDEO ALC ADJ
X'TAL OSC 10 39 VIDEO ALC TRAP
VIDEO AGC DET

REC APC FILTER 11 38
FILTER
SERIAL CTL DATA 12 37 COMPOSITE VIDEO
SERIAL CTL
13 36 VIDEO OUT FBC
CLOCK
BGP/DO PULSE 14 35 CAMERA Y
COLOR COMB VIDEO OUT ALC

15 34
FILTER DRIVE FILTER
ACC DET FILTER 16 33 REC FRING

17
18
19
20
21
22
23
24
25
26
27
28
29
30
31
32
CHAR MIX ON/OFF
COLOR COMB SIGNAL
VIDEO OUT FRING

EVF. COLOR B/W CTL
COMPOSITE VIDEO
EVF. VIDEO
Y-VCC
SIGNAL
VIDEO OUT DATA

2.8V REG
CAMERA COLOR
C-GND
SQUELCH
GND
REC DATA
VCC
SYNC SEP
Fig. 3-7-1 Y/C (IC3001) pin location
3-15
3.7.2 Y/C (IC3001) block diagram
Fig. 3-7-2 Y/C (IC3001) block diagram
3-16
3.7.3 Y/C (IC3001) pin functions
Pin No. REF. I/O Pin No. REF. I/O

1 COLOR KILLER DET FILTER In 33 REC FRING IN In
2 DISCRIMINATOR FILTER In 34 VIDEO OUT ALC FILTER In
3 LC VCO In 35 CAMERA Y IN In
4 REC AFC FILTER/PB APC FILTER In 36 VIDEO OUT FBC Out
5 CR CTL FILTER In 37 COMPOSITE VIDEO IN In
6 2fsc OUT Out 38 VIDEO AGC DET FILTER In
7 SW30/SW25 In 39 VIDEO ALC TRAP In
8 X'TAL OSC OUT Out 40 VIDEO ALC ADJ In
9 fsc OUT Out 41 YNR CCD ADJ FILTER In
10 X'TAL OSC IN In 42 FROM CCD CLAMP IN In
11 REC APC FILTER In 43 TO CCD DRIVE Out
12 SERIAL CTL DATA IN In 44 CLAMP IN In
13 SERIAL CTL CLOCK IN In 45 REC/PB SW OUT Out
14 BGP OUT/DO PULSE OUT Out 46 YNR NL-DC In
15 COLOR COMB FILTER DRIVE Out 47 NC ATT In
16 ACC DET FILTER In 48 PICTURE CONTROL IN In
17 COLOR COMB SIGNAL IN In 49 MAIN DE-EMPH EMITTER Out
18 EVF. COLOR B/W CTL In 50 MAIN EMPH FBC FILTER/MAIN DE-EMPH APL -
19 C-GND - 51 MAIN DE-EMPH COLLECTOR In
20 CAMERA COLOR SIGNAL IN In 52 MAIN EMPH ALC FILTER In
21 2.8V REG - 53 MAIN EMPH NF In
22 SQUELCH IN In 54 MAIN EMPH OUT Out
23 VIDEO OUT DATA IN In 55 Y-GND -
24 VIDEO OUT FRING IN In 56 AAF fo ADJ In
25 SYNC SEP OUT Out 57 AAF DET FILTER In
26 GND - 58 PB FM IN In
27 COMPOSITE VIDEO OUT Out 59 REC FM OUT Out
28 VCC - 60 PB LOW BAND COLOR SIGNAL IN In
29 EVF VIDEO OUT Out 61 AUTO BALANCE FILTER In
30 Y-VCC - 62 REC LOW BAND COLOR SIGNAL OUT Out
31 CHAR MIX ON/OFF IN In 63 C-VCC -
32 REC DATA IN In 64 BPF TRAP In
Table 3-7-1 Y/C (IC3001) pin functions
3-17
3.8 3 INPUT VIDEO SWITCH (IC3051)
This switch selects color signal to be output to the LCD monitor circuit. Color signal is muted in the special
playback mode.
3.8.1 3 input video switch (IC3051) block diagram & pin location
VIN1 1 8 GND
BUFFER
SW1 2 7 VOUT
SW1 SW2 OUTPUT SIGNAL
L L VIN1 PB COLOR
VIN2 3 6 V+
H L VIN2 REC COLOR
BIAS
L/H H VIN3 MUTE
SW2 4 5 VIN3
Fig. 3-8-1 3 input video switch (IC3051) block diagram & pin location
3.8.2 3 input video switch (IC3051) pin functions

1 VIN1 In Playback color signal input
2 SW1 In Play/REC select SW (L: PB / H: CAMERA)
3 VIN2 In Camera color signal input
4 SW2 In Color signal mute SW
5 VIN3 In Not used
6 V+ - Power supply input terminal
7 VOUT Out Monitor R-Y signal output
8 GND - GND
Table 3-8-1 3 input video switch (IC3051) pin functions
3-18
3.9 1H DELAY LINE + CCD COMB FILTER (IC3101)
This circuit functions to eliminate crosstalk components of color signal and to delay luminance signal for
1H.
3.9.1 1H delay line + CCD comb filter (IC3101) pin location
COUT
YOUT
VGG
COB
YOB
CIN
YIN
NC
16 15 14 13 12 11 10 9
1 2 3 4 5 6 7 8
VSS1
VSS2
VSS3
PLL-FIL
VDD1
VDD2
NC
CLOCK
Fig. 3-9-1 1H delay line + CCD comb filter (IC3101) pin location
3.9.2 1H delay line + CCD comb filter (IC3101) pin functions

1 VSS1 - GND
3 VSS2 - GND
5 VSS3 - Power supply
6 NC - Not used
7 CLOCK - fsc input
8 PLL_FIL - fsc (input) → Pll filter terminal for generating 4 fsc (inter clock)
9 YOUT Out Y signal output
10 YOB - YOB reference voltage ripple filter connection terminal
11 YIN In Y signal input
12 VGG - VGG reference voltage ripple filter connection terminal
13 NC - Not used
14 CIN In PB chroma signal input
15 COB - COB reference voltage ripple filter connection terminal
16 COUT Out Chroma signal output
Table 3-9-1 1H delay line + CCD comb filter (IC3101) pin functions
3-19
3.10 D/A CONVERTER (IC4301)
3.10.1 D/A converter (IC4301) block diagram & pin location
VCC
VDD
AO6
AO5
AO4
AO3
VSS
NC
16 15 14 13 12 11 10 9
D/A D/A D/A 8bit

R-2R + segment
CH6 CH5 CH4 D/A conv.
CH3
L L L
8bit Latch
(6) (6)
8bit Latch
Address L
Decoder CH2
CH1 8bit
R-2R + segment
D/A D/A conv.
D11
D10
D9
D8
D7
D6
D5
D4
D3
D2
D1
D0
Buffer
12bit OP amp.
Shift Resistor
1 2 3 4 5 6 7 8
CLK
GND
AO1
AO2
NC
NC
LD
DI
Fig. 3-10-1 D/A converter (IC4301) block diagram & pin location
3-20
3.10.2 D/A converter (IC4301) pin functions

1 NC - 12-bit register MSB bit data output
2 LD In LD terminal
3 CLK In Shift clock input
4 DI In Serial data input
5 AO1 Out
8-bit D-A output
6 AO2 Out
7 NC - Not used
8 GND - GND
9 VSS - D-A converter lower reference voltage (VrefL) input
10 NC - Not used
11 AO3 Out
12 AO4 Out
8-bit D-A output
13 AO5 Out
14 AO6 Out
15 VDD - D-A converter higher reference voltage (VrefH) input
16 VCC - Power supply terminal
Table 3-10-1 D/A converter (IC4301) pin functions
3-21
3.11 STEPPING MOTOR DRIVE (IC4501)
3.11.1 Stepping motor drive (IC4501) pin location
GND 1 38 RESET
Cosc 2 37 NC
FILa 3 36 OSCin
FILb 4 35 SCLK
FILc 5 34 SDATA
FILd 6 33 LATCH
Vref 7 32 Vsync
Vdd 8 31 NC
Vm3 9 30 B2
D2 10 29 FBb
FBd 11 28 B1
D1 12 27 Vm2
Vm4 13 26 A2
C2 14 25 FBa
FBc 15 24 A1
C1 16 23 Vm1
EXP0 17 22 NC
EXP1 18 21 EXP3
EXP2 19 20 P_GND
Fig. 3-11-1 Stepping motor drive (IC4501) pin location
3-22
3.11.2 Stepping motor drive (IC4501) block diagram
P_GND
RESET
SDATA
LATCH
OSCin
Vsync
Vsync
SCLK
EXP0
EXP1
EXP2
Cosc
Vref
38 2 32 36 7 32 35 34 33 17 18 19 20
X2
Serial/Paralle Decoder
PULSE GENERATOR EXTOUT SELECTOR
I/N EVR1 EVR2 EVR1 EVR2
SELECTOR OSC CURRENT SET CURRENT SET

α β
FILTER FILTER FILTER FILTER

Vm Vm Vm Vm
H BRIDGE H BRIDGE H BRIDGE H BRIDGE

α 1ch α 2ch β 1ch β 2ch
25 24 26 3 29 28 30 4 15 16 14 5 11 12 10 6 31 32
FBc
NC
C1
C2
D1
D2
FBa
A1
A2
FBb
B1
B2
FBd
FILc
Vsync
FILa
FILb
FILd
Fig. 3-11-2 Stepping motor drive (IC4501) block diagram
3-23
3.11.3 Stepping motor drive (IC4501) pin functions

1 GND - GND
2 Cosc - Chopping capacitor connection
3 FILa - Alpha channel 1 filter capacitor connection
4 FILb - Alpha channel 2 filter capacitor connection
5 FILc - Beta channel 1 filter capacitor connection
6 FILd - Beta channel 2 filter capacitor connection
7 Vref In Reference voltage input
8 Vdd In Control supply voltage input
9 Vm3 In Output supply voltage input
10 D2 Out Beta channel 2 output
11 FBd - Beta channel 2 sensing resistor connection
12 D1 Out Beta channel 2 output
14 C2 Out Beta channel 1 output
15 FBc - Beta channel 1 sensing resistor connection
16 C1 Out Beta channel 1 output
17 EXP0 Out
18 EXP1 Out Output monitor (open drain)
19 EXP2 Out
20 P_GND - GND
21 EXP3 Out Output monitor (open drain)
22 NC - Not used
24 A1 Out Alpha channel 1 output
25 Fba - Alpha channel 1 sensing resistor connection
26 A2 Out Alpha channel 1 output
28 B1 Out Alpha channel 2 output
29 FBb - Alpha channel 2 sensing resistor connection
30 B2 Out Alpha channel 2 output
31 NC - Not used
32 Vsync In Video sync signal input
33 LATCH In Latch signal input
34 SDATA In Serial data input
35 SCLK In Serial clock input
36 OSCin In Source oscillation input
37 NC - Not used
38 RESET In Reset signal input
Table 3-11-1 Stepping motor drive (IC4501) pin functions
3-24
SECTION 4
DECK CIRCUIT
4.1 PRE/REC (IC3501)
4.1.1 PRE/REC (IC3501) block diagram & pin location
CH2/4_GND
CH1/3_GND
REC_BIAS
REC_BIAS
RECIOUT
RECIOUT
CTSW4
CTSW1
PB_IN
PB_IN
NC
NC
36 35 34 33 32 31 30 29 28 27 26 25
DP_2/4 37 24 DP_1/3
PB Current Current PB
PB_IN 38 AMP 2/4 A M P 4 A M P 1 AMP 1/3 23 PB_IN
REC_BIAS 39 22 REC_BIAS
CTSW2 40 21 CTSW3
RECIOUT 41 20 RECIOUT
Current Current
ENV_DC_CTL 42 AMP 2 AMP 3 19 EP/SP
GND 43 18 LOGIC_GND
VCC_5V 44 ENV DET 17 FE_OUT
VCCSW 45 FE 16 FE
EP/SP Y6dB
ENV_DET_OUT 46 AMP 15 FE_ON
C0dB
ENV_LPF 47 AGC DET 14 NC

V/I LOGIC
AMP Y/C
FM_AGC_OUT 48 MIX
13 NC
AGC
AMP
1 2 3 4 5 6 7 8 9 10 11 12
PB_AMP_OUT
VCC_3.3V
REC_BIAS_FILTER
Y/C_MIX_OUT
HEAD_SW
MUTE
NC
NC
C_IN
V/I_AMP_IN
REC/PB
Y_IN
Fig. 4-1-1 PRE/REC (IC3501) block diagram & pin location
4-1
4.1.2 PRE/REC (IC3501) pin functions

1 NC - Not used
2 NC - Not used
3 REC_BIAS_FILTER - Filter terminal to moderate rise of REC amp. power
4 REC/PB - REC/PB mode switching terminal (L: REC)
5 PB_AMP_OUT Out PB amp. output terminal
6 V/I_AMP_IN In REC amp. input terminal
7 Y/C_MIX_OUT Out REC Y/C-mixed signal output terminal
8 C_IN In REC color signal input terminal
9 Y_IN In REC Y signal input terminal
10 VCC_3.3V - 3.3 V power supply terminal (3.3 V is internally generated from 5 V)
11 MUTE - REC and PB mute terminal (H: Mute)
12 HEAD_SW - CH1/CH2/CH3/CH4 switching control terminal
13 NC - Not used
14 NC - Not used
15 FE_ON - Not used (Flying erase on/off control terminal)
16 FE - Not used (Flying erase oscillation frequency control terminal)
17 FE_OUT Out Not used (Flying erase output terminal)
18 LOGIC_GND - GND
19 EP/SP - EP/SP switching terminal (L: SP)
20 RECIOUT Out CH3 REC amp. output
21 CTSW3 - Shorting switch control terminal (Switching-on control for all channels except CH3)
22 REC_BIAS - REC amp. power supply (CH3)
23 PB_IN In PB amp. input (CH3)
24 DP_1/3 - PB amp. feedback damping terminal (frequency response correction), (for CH1, 3)
25 CH1/3_GND - GND
29 RECIOUT Out REC amp. output (CH1)
30 NC - Not used
31 NC - Not used
36 CH2/4_GND - GND
37 DP2/4 - PB amp. feedback damping terminal (frequency response correction), (for CH2, 4)
42 ENV_DC_CTL - PB envelope output level control terminal
43 GND - GND
44 VCC_5V - 5V
45 VCC_SW - 5V
46 ENV_DET_OUT Out PB envelope output
47 ENV_LPF - Envelope generating LPF terminal
48 FM_AGC_OUT Out PB FM AGC output
Table 4-1-1 PRE/REC (IC3501) pin functions

4-2
4.2 AUDIO PROCESS (IC2001)
4.2.1 Audio process (IC2001) block diagram & pin location
RIPPLE FILTER
REC/EE CTRL
EP/SP CTRL
REC OUT
REC NFB
PB NFB
EQ SW
EQ SW
EQ SW
PB IN
GND
VCC
24 23 22 21 20 19 18 17 16 15 14 13
Vreg
REC
PB
BIAS
ALC VR
LINE
40dB
BUFF
BIAS ALC DET
1 2 3 4 5 6 7 8 9 10 11 12
MUTE CTRL
LINE NFB
PB OUT
PB/EE CTRL
BIAS1
BIAS2
ALC FILTER
LINE IN
LINE OUT
HEAD SW DRIVER
LINE (PB) IN
ALC LEVEL
Fig. 4-2-1 Audio process (IC2001) block diagram & pin location
4-3
4.2.2 Audio process (IC2001) pin functions

1 PB OUT Out PB audio output
2 LINE IN In Line (microphone) input
3 LINE (PB) IN In Line (PB) input
4 BIAS1 In HPF terminal for internal bias
5 LINE NFB In HPF terminal for line amp.
6 BIAS2 Out Internal bias voltage output
7 ALC FILTER - ALC attack/recovery time setting
8 ALC LEVEL - ALC attack level setting
9 MUTE CTRL In Line amp. output control
10 LINE OUT Out External audio output
11 HEAD SW DRIVER - Not used
12 PB/EE CTRL In REC/PB switching terminal
13 REC OUT Out REC audio output
14 REC/EE CTRL In REC amp. output on/off switching (H: REC)
15 REC NFB In REC EQ feedback
16 EP/SP CTRL In EP/SP switching terminal
17 EQ SW - REC EQ SP/EP switching terminal (ON: EP)
18 GND - GND
19 PB IN In PB audio input
20 EQ SW - REC EQ SP/EP switching terminal (ON: EP)
21 PB NFB In REC EQ feedback
22 RIPPLE FILTER - Ripple filter control terminal
23 EQ SW Out REC EQ SP/EP switching terminal (ON: EP)
Table 4-2-1 Audio process (IC2001) pin functions
4-4
4.3 CPU (IC101)
4.3.1 CPU (IC101) pin location
OEM_REG5CTL
START_SENS
CAMERA_SW
OP_SENSOR
VTR_PB_SW
CAP_BRAKE
PB_FM_DET
CTL_ERASE
REMOTE_IN
DEW_SENS
SUP_SENS
ZOOM_SW
TAPE_LED
DRUM_PG
DRUM_FG
EN_SENS
IR_FLICK
OFF_SW
CAP_FG
PB_CTL
PHOTO
KEY_D
KEY_C
KEY_B
KEY_A
IR_A/D
AL_3V
AL_3V
MOLE
BATT
GND
GND
NC
NC
VD
CS
108
107
106
105
104
103
102
101
100
98
73
97
95
99
96
94
93
92
91
90
89
88
87
86
85
84
83
82
81
80
79
78
77
76
75
74
AL_3V 109 72 AL_3V
GND 110 71 CS_CE1
REG_3V 111 70 CFM
ATC_INT 112 69 OMT
REC_CTL 113 68 VF_VD
SAFE_CTL 114 67 EVRLAD_B
CCD_SCS 115 66 V_CS
A_BIAS_L 116 65 NMI
BUZZER 117 64 CDS_CS
HD_L 118 63 V_PULSE
FEH_ON 119 62 B_PHASE
AL_3V 120 61 A_PHASE
GND 121 60 V_REC_L
TX 122 59 V_OVL_BCD
RXD 123 58 V_OVL_A
TRIG_SW 124 57 V_FF
SO1 125 56 AV_3V
SI1 126 55 GND
SCK1 127 54 A_FADE
V_RC_MUT 128 53 IRIS_PWN
SO2 129 52 CAP_REF
SI2 130 51 DRUM_REF
SCK2 131 50 DRUM_SAVE
SO3 132 49 MECHA_MDA_CS
SI3 133 48 IRIS_O/C
SCK3 134 47 FI
C_PWR_ON 135 46 LENS_MDA_CS
LENS_MDA_CLK 136 45 VF_LOAD
RESET (L) 137 44 OPEN_SW
X1 138 43 REV_SW
X2 139 42 MODE2
AL_3V 140 41 AL_3V
GND 141 40 AL_3V
GND 142 39 VDD
AL_3V 143 38 GND/VPP7.5V
GND 144 37 GND
10
11
12
13
14
15
16
17
18
19
20
26
27
28
29
30
31
32
33
34
35
36
21
22
23
24
25
1
2
3
4
5
6
7
8
9
LBEN (L)
MIRROR
A_MUTE
AL_3V
EEPROM_CS
UBEN (L)
BL_ON
AD15
AD14
AD13
AD12
AD11
AD10
AL_3V
R/W (L)
RTC_CS
GND
NC
LCD_CS
AD9
AD8
AD7
AD6
AD5
AD4
AD3
AD2
AD1
AD0
DSTB (L)
WAIT_L
ASTB
OSD_CS
D_PWR_ON
EJECT_SW
R_SAF_SW
Fig. 4-3-1 CPU (IC101) pin location
4-5
4.3.2 CPU (IC101) pin functions 1/3

1 AL_3V - Power supply (+3.3 V)
2 NC - Not used
3 WAIT_L In DSP bus access wait input
4 A_MUTE Out Audio mute output
5 EEPROM_CS Out Chip select for EEPROM
6 ASTB Out DSP bus access address latch enable
7 DSTB (L) Out DSP bus access data latch enable
8 R/W (L) Out DSP bus access read/write select
9 UBEN (L) Out DSP bus access high-order enable
10 LBEN (L) Out DSP bus access low-order enable
11 RTC_CS Out Chip select for real-time clock
12 LCD_CS Out Chip select for LCD
13 BL_ON Out LCD monitor backlight ON: H
14 OSD_CS Out Chip select for OSD
15 D_PWR_ON Out Deck power control signal (H: ON, L: OFF)
16 EJECT_SW In Eject switch input
17 R_SAF_SW In REC Safety switch input
18 MIRROR Out LCD monitor output inversion: H
19 GND - GND
20 AD15 In/Out Multiplexed bus bit 15 for DSP
37 GND - GND
38 GND/VPP7.5V - CPU flush ROM write voltage impression (Normally grounded)
42 MODE2 - CPU operation mode select (L: Normal, H: Flush write)
43 REV_SW In LCD monitor inversion switch input
44 OPEN_SW In LCD monitor open/shut switch input
45 VF_LOAD Out EVR load pulse inside color VF
46 LENS_MDA_CS Out Chip select for lens motor driver
47 FI In Field index input
48 IRIS_O/C Out Iris manual control signal (H: Open, L: Closed)
Table 4-3-1 CPU (IC101) pin functions 1/3

4-6
· CPU (IC101) pin functions 2/3

49 MECHA_MDA_CS Out Chip select for mechanism motor driver
50 DRUM_SAVE Out Drum start control signal
51 DRUM_REF Out Drum control signal (PWM output)
52 CAP_REF Out Capstan control signal (PWM output)
53 IRIS_PWN Out Iris control signal (PWM output)
54 A_FADE Out Audio fader control signal (PWM output)
55 GND - GND
57 V_FF Out Video flip-flop signal
58 V_OVL_A Out Video overlap signal ACH
59 V_OVL_BCD Out Video overlap signal BCDCH
60 V_REC_L Out Video recording control signal (L: Recording)
61 A_PHASE In Dial switch ACH input
62 B_PHASE In Dial switch BCH input
63 V_PULSE Out V. sync pulse in special PB
64 CDS_CS Out Chip select for camera CDS
65 NMI In Unmaskable interrupt input
66 V_CS Out Chip select for video Y/C signal
67 EVRLAD_B Out Chip select for EVF
68 VF_VD In VF V. sync input
69 OMT In ESI data read enable
70 CFM In Color frame input
71 CS_CE1 In Chip select input for DSC serial communication
73 GND - GND
75 CS Out Chip select for extension port
76 TAPE_LED Out Tape sensor LED control signal
77 REMOTE_IN In Remote control pulse input
78 SUP_SENS In Supply sensor input
79 OEM_REG5CTL Out RAE control output pull-up signal
80 VTR_PB_SW In PB power-on switch input
81 OFF_SW In Power-off switch input
82 CAMERA_SW In Camera power-on switch input
83 DRUM_FG In Drum FG signal input
84 VD In VD (vertical drive) input
85 CAP_FG In Capstan FG signal input
86 PB_CTL In Control pulse signal input
87 DRUM_PG In Drum PG signal input
88 CTL_ERASE Out Control pulse erase
89 IR_FLICK In Infrared flicker component input
90 CAP_BRAKE Out Capstan brake control signal
91 GND - GND
93 HOLE In Iris hall element voltage input
94 IR_A/D In Infrared D/C component input
95 BATT In Battery voltage input
96 DEW_SENS In Dew sensor input

4-7
· CPU (IC101) pin functions 3/3

97 PHOTO In Photo switch input
98 OP_SENSOR In Focus/zoom sensor input
99 ZOOM_SW In Zoom switch input
100 START_SENS In Tape beginning sensor input
101 EN_SENS In Tape end sensor input
102 KEY_A In Deck switch input
103 KEY_B In Light switch input
104 KEY_C In Camera switch input
105 KEY_D In Scene dial switch input
106 PB_FM_DET In PB FM signal envelope input
107 NC - Not used
108 NC - Not used
110 GND - GND
111 REG_3V - A-D converter reference voltage
112 ATC_INT In Real-time clock
113 REC_CTL Out REC control pulse output
114 SAFE_CTL Out Over-current protection circuit control signal
115 CCD_SCS Out Chip select for CCD drive timing generator
116 A_BIAS_L Out Audio bias ON: L
117 BUZZER - Buzzer output (Not used)
118 HD_L In Horizontal drive input
119 FEH_ON Out Flying erase ON: H
121 GND - GND
122 TX Out RS-232C TXD
123 RXD In RS-232C RXD
124 TRIG_SW In Trigger switch input
125 SO1 Out Serial 1 communication data output
126 SI1 In Serial 1 communication data input
127 SCK1 Out Serial 1 communication clock output
128 V_RC_MUT Out Video recording mute ON: H
135 C_PWR_ON Out Camera power control signal
136 LENS_MDA_CLK Out 4 MHz clock for lens motor driver
137 RESET (L) In CPU reset input
138 X1 In CPU clock, 16 MHz
139 X2 Out CPU clock, 16 MHz
141 GND - GND
142 GND - GND
144 GND - GND

4-8
4.4 RTC (IC104)
This is a real-time clock IC that serially transfers clock and calendar data to the CPU.
4.4.1 RTC (IC104) block diagram & pin location
CE 1 8 VDD
SCLK 2 7 OSCIN
SIO 3 6 OSCOUT
VSS 4 5 INTR
OSCIN 7 SEC MIN HOUR WEEK DAY MONTH YEAR

OSC DIV
OSCOUT 6
TIME COUNTER
OSC 2 SCLK
DETECT ADDRESS ADDRESS
VDD 8 DECODER REGISTOR
3 SIO
V O L T A GE I/O
REGULATOR CONTROL
VSS 4
INTR 5 INTERRUPT
SHIFT REGISTER 1 CE
CONTROL
Fig. 4-4-1 RTC (IC104) block diagram & pin location
4.4.2 RTC (IC104) pin functions

1 CE In Chip enable input
2 SCLK In Shift clock input
3 SIO In/Out Serial input and output
4 VSS - GND
5 INTR Out Interrupt output
6 OSCOUT Out Oscillator input
7 OSCIN In Oscillator output
Table 4-4-1 RTC (IC104) pin functions
4-9
4.5 EEPROM (IC105)
4.5.1 EEPROM (IC105) block diagram & pin location
CS 1 8 VCC
SO 2 7 HOLD
WP 3 6 SCK
VSS 4 5 SI
8 VCC
CS 1
4 VSS
SCK 6 Instruction
Decoder 2 SCLK
HOLD 7
Control Logic,
and Clock Generator
Instruction
SI 5
Register
Program
Address Enable High Voltage
Counter/ Generator and
Register Vpp Program Timer
EEPROM Array
Decoder
4096 Bits
1 of 512
(512x8)
Read/Write
Amps
Data In/Out Register Data Out

2 SO
8Bits Buffer
Non-Volatile
Status Register
Fig. 4-5-1 EEPROM (IC105) block diagram & pin location
4-10
4.5.2 EEPROM (IC105) pin functions

1 CS In Chip select input
2 SO Out Serial data output
3 WP In Write protect
4 VSS - GND
5 SI In Serial data input
6 SCK In Serial data clock
7 HOLD In Serial data hold
Table 4-5-1 EEPROM (IC105) pin functions
4-11
4.6 SYSCON SUB (IC108)
4.6.1 SYSCON SUB (IC108) pin location
V_ALL_MUTE
V_PLS_ON
REEL_LED
V_PULSE
IND_CTL
VF_CTL
A_PB
V_FF
VSS
NC
NC
NC
36 35 34 33 32 31 30 29 28 27 26 25
SH_L 37 24 TEST
LAMP_ON 38 23 D_PWR_ON
SP_L 39 22 P_SW
P_SAVE 40 21 REC_SAFE_SW
V_FF 41 20 NC
DSGAT 42 19 VDD1
VDD2 43 18 JLIP
A_FADE 44 17 REMOTE
NC 45 16 EJECT_SW
NC 46 15 PA2
NC 47 14 PAI
DSP_RST 48 13 NMI
1 2 3 4 5 6 7 8 9 10 11 12
NC
NC
CS (L)
SOUT
SCLK
V_PB_L
PA11
RESET (L)
V_PULSE
REC_SAFE
SIN
VSS
Fig. 4-6-1 SYSCON SUB (IC108) pin location
4-12
4.6.2 SYSCON SUB (IC108) pin functions

1 NC - NC
2 V_PB_L Out PB signal control terminal (L in PB)
3 V_PULSE In False V pulse in special PB (Level shift input)
4 NC - Not used
5 REC_SAFE In REC SAFE switch input for starting operation
6 VSS - GND
7 PA11 In Power switch input for starting operation
8 RESET (L) In Reset input
9 SCLK In Serial communication clock input
10 SIN In Serial communication data input
11 SOUT Out Serial communication data output
12 CS (L) In Chip select input
13 NMI Out Interrupt signal output for activating CPU
14 PA1 In Seizing signal input
15 PA2 Out Seizing signal output
16 EJECT_SW In Eject switch input
17 REMOTE - VDD1 (3.3 V)
18 JLIP In JLIP input for activation
19 VDD1 - VDD1 (3.3 V)
20 NC - Not used
21 REC_SAFE_SW In REC SAFE switch input
22 P_SW In Power switch input
23 D_PWR_ON In Power control signal input
24 TEST - GND
25 V_PLS_ON Out V. pulse input enable signal output
26 V_ALL_MUTE Out Video signal mute output
27 V_FF Out FF output (Level shift output)
28 A_PB Out Audio control signal (H in PB)
29 VF_CTL Out VF ON/OFF control signal
30 REEL_LED Out Reel sensor LED control signal
31 VSS - GND
32 IND_CTL Out OSD display control signal
33 V_PULSE Out False V. pulse in special PB (Level shift output)
34 NC - Not used
35 NC - Not used
36 NC - Not used
37 SH_L Out Shutter sound mute control signal
38 LAMP_ON Out Video light ON/OFF control signal
39 SP_L Out Tape speed control signal (L in SP)
40 P_SAVE Out Camera DSP power save control signal
41 V_FF In FF input (Level shift input)
42 DSGAT Out TG power save control signal
43 VDD2 - VDD2 (5 V)
44 A_FADE In Audio fader input (Not used)
45 NC - Not used
46 NC - Not used
47 NC - Not used
48 DSP_RST Out Camera DSP reset output
Table 4-6-1 SYSCON SUB (IC108) pin functions

4-13
4.7 OSD (IC109)
This IC serves to display on-screen characters.
4.7.1 OSD (IC109) pin location
V_BLK
BLK2
BLK1
V_G
V_R
VC2
VC1
V_B
HD
VD
20 19 18 17 16 15 14 13 12 11
1 2 3 4 5 6 7 8 9 10
VDD
CKO
SBT2
CS
OSCI
DATA
PCL
VSS
TEST
OSCO
Fig. 4-7-1 OSD (IC109) pin location
4.7.2 OSD (IC109) block diagram
9 TEST
5 VDD
DATA 3
DATA INPUT CONTROL 10 VSS
INSTRUCTION DECODER
SBT2 1 SHIFT RESISTOR SIGNAL
4 PCL
CS 2
DISPLAY POSITION WRITE-IN VIDEO RAM

CHARACTER
DISPLAY CONTROL DATA
BACKGROUND CONTROL
HORIZONTAL ADDRESS
SIZE RESISTOR
ADDRESS RESISTOR COUNTER
DATA SELECTOR
DATA RESISTOR
CHARACTER DATA
RESISTOR
INVERTER DATA
OUTPUT DATA
8bit X 256 word
3bit X 256 word
1bit X 256 word
8bit X 256 word
1bit X 256 word

COLOR DATA
BLINK DATA
6
CKO HORIZONTAL SIZE HORIZONTAL SIZE
HORIZONTAL
ADDRESS
COUNTER COUNTER
COUNTER
7
OSC0
OSC
DISPLAY POSITION
VERTICAL ADDRESS
RESISTOR
OSC1 8
CHARACTER
GENERATOR ROM
12 X 18bit X 256word
VERTICAL
H D 20
VERTICAL SIZE VERTICAL POSITION
ADDRESS
COUNTER COUNTER
COUNTER
SYNC.
PROTECT
OUTPUT CONTORLLER
V D 19
11 12 13 14
BLK1 VC1 BLK2 VC2
Fig. 4-7-2 OSD (IC109) block diagram
4-14
4.7.3 OSD (IC109) pin functions

1 SBT2 In Clock input
2 CS In Chip select input
3 DATA In Serial data input
4 PCL - Power on clear
6 CKO Out Clock output
7 OSCO Out LC oscillator output
8 OSCI In LC oscillator input
9 TEST - Test terminal
10 VSS - GND
11 BLK1 Out Blanking signal output 1
12 VC1 Out Character signal output 1
13 BLK2 Out Blanking signal output 2
14 VC2 Out Character signal output 2
15 V_BLK Out Blanking signal output
16 V_R Out
17 V_G Out Character signal output
18 V_B Out
19 VD In Vertical sync signal input
20 HD In Horizontal sync signal input
Table 4-7-1 OSD (IC109) pin functions
4-15
4.8 CTL AMP (IC1201)
4.8.1 CTL AMP (IC1201) block diagram & pin location
MONI_OUT
HysBIAS
FILTER
BIAS-
AGC
3.0V
IN-
14 13 12 11 10 9 8
DET
AGC AMP Ref
REC
AMP
P R R P R P
sw
1 2 3 4 5 6 7
RECHPB
RECIN
RECGND
CTL+
CTL OUT
GND
CTL-
Fig. 4-8-1 CTL AMP (IC1201) block diagram & pin location
4-16
4.8.2 CTL AMP (IC1201) pin functions

1 CTL_OUT Out Control pulse output
2 RECHPB In REC amp. input/PB amp input switching
3 RECIN In REC control pulse input
4 GND - GND
5 CTL+ In/Out REC: REC current at + side of CTL head, PB: Bias current of CTL pulse input
6 CTL- In/Out REC: REC current at - side of CTL head, PB: Bias current of CTL pulse input
7 RECGND - GND for REC amp. and PB amp.
8 BIAS - PB amp. bias terminal
9 IN- In PB amp. feedback input
10 MONI_OUT Out PB amp. output monitor
11 AGC In AGC time constant setting
12 HysBIAS In Hysteresis amp. center level setting
13 FILTER In High freq. noise reduction filter connection/Hysteresis amp. input
14 3.0V - Power supply
Table 4-8-1 CTL AMP (IC1201) pin functions
4-17
4.9 MECHA MDA (IC1601)
4.9.1 MECHA MDA (IC1601) pin location
D.PGSOUT
D.FGSOUT
D.PGOUT
D.FGOUT
D.FGPG+
D.COM
TEST2
D.WIN
GND1
D.PG-
DCC1
DCC2
DCC3
D.UIN
D.FG-
D.WH
D.VIN
D.UH
D.VH
DCC
62
61
78
80
79
77
76
75
74
73
72
71
70
69
68
67
66
65
64
63
GND1 1 60 TEST1
D.U 2 59 DETECT
D.VM 3 58 START
D.V 4 57 D.OSC
D.RNF 5 56 D.PCV
L.REF 6 55 D.PCI
D.W 7 54 D.ECR
L.FWD 8 53 D.EC
GND2 9 52 NC
L.GND 10 51 GND2
NC 11 50 D4
UNREG 12 49 D3
L.REV 13 48 D2
C.U 14 47 D1
NC 15 46 D0
C.RNF 16 45 DOUT
C.V 17 44 DIN
C.VM 18 43 CS
C.W 19 42 CLK
C.UH 20 41 NC
21
22
23
24
25
26
27
28
29
30
31
32
33
34
35
36
37
38
39
40
C.RCC
VCC
C.ECR
C.VH
C.HV+
C.HV-
C.PCV
C.EC
C.BRK
C.HU+
C.HU-
C.VS
C.PCI
C.FG+
C.FG-
C.HW+
C.HW-
C.WH
C.FGSOUT
C.FGOUT
Fig. 4-9-1 MECHA MDA (IC1601) pin location
4-18
4.9.2 MECHA MDA (IC1601) block diagram
DCC1
DCC2
DCC3
DCC
VCC UNREG
D.VM
UPPER/LOWER DIVISION
D.UH
DRIVE SIGNAL LOGIC

D.UIN
D.U
D.VH
D.VIN
D.V
D.WH
D.WIN
D.W
D.COM
START D.GND
D.OSC OSC
TIMING
D.FG −
D.BRK BRAKE
D.PG−
D.EC
D.ECR
TORQUE
CTL D.FGPG +
CURRENT FEED BACK
D.PG.SM
UNREG
D.FGSOUT
L.REF
D.PGSOUT
L.FWD
CS C.FR POWER CTL
C.MODE
CLK
SHIFT C.TL SAVE LOGIC
REGISTER D.PG.SM L.REV
DIN & D.BRK
L.FIN L.GND
DOUT LATCH L.RIN
PW_SAVE PW_SAVE L.FIN L.RIN
D.FG −
DRUM_FG D.FG +
C.FR DIRECTION C.VM
C.UH
UPPER/LOWER DIVISION
DRIVE SIGNAL LOGIC
C.HU+
C.U
C.HU-
C.VH
C.HV+
C.V
C.HV-
C.WH
C.HW+
C.W
C.HW-
C.GND
C.RCC
RIPPLE
CANCEL
C.EC C.EC
C.VS
C.ECR CAP_ERR
TORQUE
CTL C.MODE C.VM
C.TL
CURRENT C.MODE
LIMIT
C.BRK BRAKE
Fig. 4-9-2 MECHA MDA (IC1601) block diagram

4-19
4.9.3 MECHA MDA (IC1601) pin functions 1/2

1 GND1 - GND
2 D. U Out Drum motor output
3 D. VM In Drum VM
4 D. V Out Drum motor output
5 D. RNF - Drum GND (current detection resistance)
6 L. REF - Loading output voltage setup
7 D. W Out Drum motor output
8 L. FWD Out Loading output
9 GND2 - GND
10 L. GND - Loading GND
11 NC - Not used
12 UNREG - Loading and drum BEMF comparator unregulated power supply
13 L. REV Out Loading output
14 C. U Out Capstan motor output
15 NC - Not used
16 C. RNF - Capstan GND (current detection resistance)
17 C. V Out Capstan motor output
18 C. VM In Capstan VM
19 C. W Out Capstan motor output
20 C. UH Out
21 C. VH Out Capstan motor output (pre-drive)
22 C. WH Out
23 C. HW- In
24 C. HW+ In
25 C. HV- In
Capstan hall input
26 C. HV+ In
27 C. HU- In
28 C. HU+ In
29 C. FGSOUT Out Capstan FG schmitt output
30 C. FGOUT Out Capstan FG amp. output
31 C. FG- In
Capstan FG input
32 C. FG+ In
33 VCC - BIP control VCC
34 C. VS - Capstan motor power supply control
35 C. PCV - Capstan output saturation prevention circuit phase compenstion (upper side)
36 C. PCI - Capstan output saturation prevention circuit phase compensation (lower side)
37 C. ECR In Capstan torque command reference input
38 C. EC In Capstan torque command control input
39 C. RCC - Capstan ripple cancel variation (resistor connection)
40 C. BRK In Capstan brake input (H: braking)
Table 4-9-1 MECHA MDA (IC1601) pin functions 1/2
4-20
· MECHA MDA (IC1601) pin functions 2/2

41 NC - Not used
42 CLK In I/O clock signal input
43 CS In I/O select signal input
44 DIN In I/O serial data input
45 DOUT Out I/O serial output
46 D0 In Rotary encoder switch A input
47 D1 In Rotary encoder switch B input
48 D2 In Rotary encoder switch C input
49 D3 In Cassette switch input
50 D4 In Take-up reel sensor input
51 GND2 - GND
52 NC - Not used
53 D. EC In Drum torque command control input
54 D. ECR In Drum torque command reference input
55 D. PCI - Drum output saturation prevention circuit phase compensation (lower side)
56 D. PCV - Drum output saturation prevention circuit phase compensation (upper side)
57 D. OSC - Drum start signal oscillation
58 START - Drum start mode time setting
59 DETECT - Drum detection mode time setting
60 TEST1 -
Not used
61 TEST2 -
62 D. PGSOUT Out Drum PG schmitt output
63 D. PGOUT Out Drum PG amp. output
64 D. PG- In Drum PG input
65 D. FGPG+ In Drum FG/PB common input
66 D. FG- In Drum FG input
67 D. FGOUT Out Drum FG amp. input
68 D. FGSOUT Out Drum FG schmitt output
69 GND1 - GND
70 D. UIN In
71 D. VIN In Drum BEMF comparator input
72 D. WIN In
73 D. COM - Drum motor midpoint
74 DCC3 -
75 DCC2 - Drum slope waveform shaping
76 DCC1 -
77 DCC - Drum DCC terminal current control (resistor connection)
78 D. UH Out
79 D. VH Out Drum motor output (pre-drive)
80 D. WH Out
Table 4-9-1 MECHA MDA (IC1601) pin functions 2/2
4-21
4.10 REGULATOR (IC6001)
4.10.1 REGULATOR (IC6001) block diagram & pin location
CREF
VREF
IN3+
IN4+
IN3-
IN4-
CT1
CT2
FB4
CV
CP
RT
12 11 10 9 8 7 6 5 4 3 2 1
TIMER
OSC
LATCH
FB3 13 POWER 48 DT1
Ref.V
CTL
IN2- 14 CTL 47 DT2
FB2 15 46 VCC1
IN1- 16 DRV4 45 OUT4
FB1 17 DRV3 44 OUT3
FB5 18 DRV2 43 OUT2
IN5+ 19 42 GND2
DEAD
TIME
IN5- 20 41 OUT1A
DRV1
IN6- 21 40 OUT1B
GND1 22 DRV6b DRV6a 39 OUT6A
OUT6B 23 DRV5 38 OUT5

SOFT START ON/OFF
FB6 24 37 VDRV
25 26 27 28 29 30 31 32 33 34 35 36
CNT5
CNT3
CNT2
CNT1
VCC2
CS4
CS5
CS1
SYN
CNT4
CS3
CS2
Fig. 4-10-1 REGULATOR (IC6001) block diagram & pin location
4-22
4.10.2 REGULATOR (IC6001) pin functions

1 RT - Timing resistance connection for oscillator
2 CT2 - OPEN
3 CT1 - Timing capacitor resistance connection for oscillator
4 VREF Out Reference power output
5 CREF - Bypass capacitor connection for reference power supply
6 CP - Timer latch timing capacitor connection
7 FB4 Out Channel 4 error amplifier output
8 IN4+ In Channel 4 error amplifier non-reverse input
9 IN4- In Channel 4 error amplifier reverse input
12 CV - Bypass capacitor connection for internally controlled power supply
22 GND1 - GND
23 OUT6b Out Channel 6 power output (Power through prevention in OFF)
25 CS4 - Channel 5 soft start capacitor connection
27 CNT5 In Channel 6 on/off control signal input, L: OFF
29 VCC2 - Power supply
30 CS3 - Channel 3, 4 soft start capacitor connection
33 CNT3 In Channel 3, 4 on/off control signal input, L: OFF
36 SYN In GND
37 VDRV - Driver power bypass capacitor connection
38 OUT5 Out Channel 5 output (PchMOS drive)
39 OUT6a Out Channel 6 output (NchMOS drive)
40 OUT1b - Not used
41 OUT1a Out Channel 1 output (PchMOS drive)
42 GND2 - GND
46 VCC1 - Power supply
47 DT2 In
DT2, DT1 shortcircuiting
48 DT1 Out
Table 4-10-1 REGULATOR (IC6001) pin functions

4-23
SECTION 5
MONITOR & SPEAKER / E. VF CIRCUITS
5.1 RGB DECODER / DRIVER (IC7502)
This IC converts composite signal, Y/C signal and Y/color difference signal into R, G, B signals for driving
the liquid crystal of the LCD.
5.1.1 RGB decoder / driver (IC7502) block diagram & pin location
SUB_CONTRAST_R
SUB_CONTRAST_B
SUB_BRIGHT_R
SUB_BRIGHT_B
BL_LIMITTER
GAMMA1
SYNC_IN
GAMMA2
BRIGHT
DL_ADJ
VCC2
FRP
36 35 34 33 32 31 30 29 28 27 26 25
VREF
SYNC_OUT 37 24 B_OUT
SYNC
SEP
SYNC_SEP 38 B-Y 23 B_DC_DET
BGP GEN DL γ BRIGHT INV
INT/EXT SW
MATRIX
EXTB_IN 39 BGP G-Y

γ BRIGHT INV 22 G_OUT
R-Y
EXTG_IN 40 DL γ BRIGHT INV 21 G_DC_DET
EXTR_IN 41 20 R OUT
G DEMOD
GEN
CONTRAST 42 19 R_DC_DET
N PP N
CLAMP PAL PHASE
VCC1 43 SW SHIFT 18 VEE
AGC AMP P N
P REG3
IDENT
F_ADJ 44 AGC DET F/F 17 GND
N REG2
EXT
CLAMP 45 PICTURE SYNC 16 VCO_OUT
REG1 HPF COLOR KILLER VXO
AGC_FILTER 46 COMP APC 15 APC_FILTER
TRAP Y/C
HUE
AGC_OUT 47 14 VCO_IN
H. ACC ACC DET
FILTER
PICTURE 48 13 TINT
NTSC/
PAL PAL/
ON COLOR
COMP Y/C DEFFER
1 2 3 4 5 6 7 8 9 10 11 12
BURST_OUT
C_IN
ACC_FILTER
H_FILTER_OUT
R-Y
COLOR
C_OUT
IDENT_FILTER
KILLER_FILTER
TRAP
VIDEO_IN
B-Y
Fig. 5-1-1 RGB decoder / driver (IC7502) block diagram & pin location
5-1
5.1.2 RGB decoder / driver (IC7502) pin functions

1 TRAP - Trap connection
2 H_FILTER_OUT Out Video signal output (for sync separator circuit)
3 VIDEO_IN In Composite video signal input (Y signal input)
4 IDENT_FILTER - Identity detection filter connection
5 C_IN In Chroma signal input in Y/C input
6 COLOR - Color adjustment
7 BURST_OUT - Burst cleaning coil in PAL
8 KILLER_FILTER - Killer detection filter connection
9 R_Y In
Color difference signal demodulation circuit input
10 B_Y In
11 ACC_FILTER - ACC detection filter connection
12 C_OUT Out Chroma signal output
13 TINT - Hue adjustment
14 VCO_IN In VXO input
15 APC_FILTER - APC detection filter connection
16 VCO_OUT Out VXO output
17 GND - GND
18 VEE - Lowest potential connection
19 R_DC_DET - RGB output DC level control smoothing capacitor connection
20 R_OUT Out RGB primary signal output
21 G_DC_DET - RGB output DC level control smoothing capacitor connection
22 G_OUT Out RGB primary signal output
23 B_DC_DET - RGB output DC level control smoothing capacitor connection
24 B_OUT Out RGB primary signal output
25 VCC2 - RGB output power connection
26 BL_LIMITTER - RGB output amplitude clipping level setup
27 SUB_BRIGHT_R - R brightness fine adjustment
28 SUB_BRIGHT_B - B brightness fine adjustment
29 FRP - RGB output polarity reversing timing pulse input (L: Reverse, H: Non-reverse)
30 GAMMA1 - Voltage gain alteration point gamma 1 adjustment
31 GAMMA2 - Voltage gain alteration point gamma 2 adjustment
32 BRIGHT - RGB output brightness adjustment
33 DL_ADJ - Delay time adjustment against R, B and G outputs
34 SUB_CONT_R - R signal contrast fine adjustment
35 SUB_CONT_B - B signal contrast fine adjustment
36 SYNC_IN In H input in synchronization, L input in other status
37 SYNC_OUT Out Output level of sync signal separated by sync separator circuit; H: sync, L: other
38 SYNC_SEPA In Sync separator circuit input
39 EXT_B_IN In External digital signal (B) input
40 EXT_G_IN In External digital signal (G) input
41 EXT_R_IN In External digital signal (R) input
42 CONTRAST - RGB contrast adjustment
43 VCC1 - Power connection terminal
44 F_ADJ - Internal filter adjustment
45 CLAMP - Y signal pedestal level clamp
46 AGC_FILTER - Y signal AGC detection filter connection
47 AGC_OUT Out Output of Y signal voltage detected by AGC detection circuit
48 PICTURE - Y signal frequency characteristic adjustment
Table 5-1-1 RGB decoder / driver (IC7502) pin functions

5-2
5.2 TIMING CONTROL (IC7505)
This IC serves as the timing controller for the TFT LCD.
5.2.1 Timing control (IC7505) block diagram & pin location
HALF_SHIFT
QH_SEL
VCO_I
CPH1
CPH2
CPH3
STV2
QVD
VDD
NC
PD
RL
36 35 34 33 32 31 30 29 28 27 26 25
S
FVCO
Frequency Phase Phase Shift &
VCO_O 37 VCO
Divider Comparator Selector S 24 STH2
GND 38 S 23 STH
Horizontal TFF
Counter
RESET 39 Selector 22 QH
HV_MODE 40 Horizontal TFF 21 OEH

Decoder
UONS 41 S 20 STV
Vertical
HPOS4 42 Decoder 19 OEV1
Black
HPOS3 43 Decoder
18 NC
HPOS2 44 Vertical Count 17 NC

Equalizing Pulse Field
Down
R Removing Counter Discriminator
HPOS1 45 16 CPV
PN1 46 Q D
15 INT/EXT
Thinning CTL/
φ Zoom CTL
Pulse
VDD 47 R Width ADJ 14 POL
GND 48 Wave 13 STVSEL

V. Sync Sepa
Shaping
S
1 2 3 4 5 6 7 8 9 10 11 12
H_OUT
ZOOM
VD_OUT
VPOS3
SYNC_IN
NC
VDB_IN
HDB_IN
VPOS2
VPOS1
NC
NC
Fig. 5-2-1 Timing control (IC7505) block diagram & pin location
5-3
5.2.2 Timing control (IC7505) pin function

1 SYNC_IN In Composite sync signal input
2 HDB_IN In Horizontal sync signal input
3 NC - Not used
4 NC - Not used
5 VDB_IN In Vertical sync signal input
6 H_OUT Out Horizontal sync signal output
7 VD_OUT Out Vertical sync signal output
8 NC - Not used
9 VPOS3 In
10 VPSO2 In Vertical display position adjustment
11 VPOS1 In
12 ZOOM In Zoom control terminal
13 STVSEL In Scanning direction switch (H: Normal direction scanning)
14 POL Out Video polarity switching/remote voltage switching pulse
15 INT/EXT In Internal sync/external sync switching
16 CPV Out Gate driver clock pulse
17 NC -
Not used
18 NC -
19 OEV1 Out Gate driver output step enable pulse
20 STV Out Gate driver scan start pulse
21 OEH Out Gate driver output step enable pulse
22 QH Out Source driver color data switching pulse
23 STH Out Source start pulse
24 STH2 Out Source driver clock pulse 4/Source start pulse 2
25 CPH3 Out Source driver clock pulse 3
26 STV2 Out Source driver clock pulse 6/Gate start pulse 2
28 RL In/Out Source driver clock pulse 5/STH switching
30 HALF_SHIFT In Clock half-pixel shift control
31 NC - Not used
32 QH_SEL In QH output switching
33 PD Out Phase comparison output
34 QVD In Internal clock one-sixth or one-third dividing switching
35 VDD (A) - Power supply
36 VCOI In VCO input
37 VCOO Out VCO output
38 GND (A) - GND
39 RESET In Reset
40 HV_MODE In Switching of number of horizontal panel dots
41 UONS In Lower part on-screen display control
42 HPOS4 In
43 HPOS3 In
Switching of number of horizontal display pixels
44 HPOS2 In
45 HPOS1 In
46 PN1 In PAL/NTSC switching
47 VDD (D) - Power supply
48 GND (D) - GND
Table 5-2-1 Timing control (IC7505) pin function

5-4
5.3 E. VF (IC7001)
5.3.1 E. VF (IC7001) block diagram & pin location
PHASE COMP
VIDEO OUT
H AFC OUT
VIDEO IN
H OSC R
HD OUT
GND
VCC
16 15 14 13 12 11 10 9
PHASE SYNC
H. OSC 6dB V. SEPA
COMP SEPA
AMP
H. BLK
V. BLK
V. DRIVE V. OSC
1 2 3 4 5 6 7 8
VCC
VD OUT
V CTL
POS
GND
NEG
V OSC R
V OSC C
Fig. 5-3-1 E. VF (IC7001) block diagram & pin location
5.3.2 E. VF (IC7001) pin functions

1 V CTL In Vertical control input
3 POS Out Vertical polarizing drive
4 GND - GND
5 NEG Out Vertical polarizing drive
6 V OSC R - Vertical oscillator resistor
7 V OSC C - Vertical oscillator capacitor
8 VD OUT Out VD output
9 HD OUT Out HD output
10 GND - GND
11 VIDEO IN In Video input
13 VIDEO OUT Out Video output
14 PHASE COMP Out Phase comparison output
15 H OSC R - Horizontal oscillator resistor
16 H AFC OUT Out Horizontal AFC output
Table 5-3-1 E. VF (IC7001) pin functions

5-5
SECTION 6
SECAM CIRCUIT
6.1 SECAM COLOR PROCESS (IC3401)
6.1.1 SECAM color process (IC3401) block diagram & pin location
PB REC
X2
AFC PASE PHASE
1 ADJ
AFC 24 REC IN
ADJ MUTE 4.3M
LIMITER
GATE BPF
ID MAIN TRICK PB ACC1

2 φ ADJ LP ACC1 23 ACC1
INTEG ID-DET ID-DET PB
DET
REC
REC
SYSTEM QUAD
I DENT
SW DET
1.1M 2.2M 4.3/1.1 BELL
ID ADJ 3 BPF BPF BELL ADJ
22 BELL ADJ
DAC φ IP
REC
PB X2 LIM
4.286 1/4 3.1M

4 IVCO
C/D
1/4
PRE-BPF
21 PB IN
X'TAL
1.1/4.3
ANTI BELL
VCC 5 20 GND
ACC
SDA 6 ACC2
DET
19 ACC2
IIC BUS
PB REC
ANTI BELL ANTI BELL

SCL 7 ADJ
18
SYNC
ADJ
GATE
SYNC
GND 8 COMPRESS 17 VCC
ATT
SECAM REC PAL/
SYNC IN 9 16
PAL/
NTSC IN
NTSC
PB
TRICK
PV IN 10 15 PB-C OUT
Slicer V SEP V C/D
ANTI BELL
AFC 11 AFC VCO H C/D
ADJ
14 S-ID OUT
REC
REC-C CONTROL
12 13
OUT MODE
Fig. 6-1-1 SECAM color process (IC3401) block diagram & pin location
6-1
6.1.2 SECAM color process (IC3401) pin functions

1 AFC PHASE ADJ - Filter terminal for automatic AFC adjustment
2 ID INTEG - Integral filter terminal for SECAM discrimination circuit
3 ID ADJ - Demodulating IDENT signal extracted for SECAM discrimination
4 4.286 X'tal - Crystal oscillator for automatic filter adjustment standard
5 DVCC - Power supply
6 PB(H) In I2C bus data input (Pin 13 = L in non-bus, H: PB, L: REC)
I2C bus clock input
7 SECAM(H) In
(Pin 13 = L in non-bus, H: SECAM, L: Not SECAM)
8 GND - GND
9 SYNC IN In Composite sync signal input
10 PV IN In Dummy sync signal input terminal in TRICK mode
AFC filter to synchronize internal VCO with H sync of composite sync signal input
11 AFC -
through pin 9
12 REC C OUT Out Output terminal in REC mode
Bus control and non-bus control switching terminal
13 ParaCTL(L) -
(Bus: Open, Non-bus: Pulled down to GND)
SECAM discrimination result output terminal
14 SYS SW Out
(L: Not SECAM, H: SECAM)
15 PB-C OUT Out Chroma output terminal in PB
REC If recording is performed in a mode other than SECAM mode, input signal to this
16 In
PAL/NTSC IN terminal is added to input signal to pin 13, and a resultant signal is output to pin 12.
17 VCC - Power supply terminal for analog circuit

Filter terminal
18 ANTI BELL ADJ -
(reverse bell filter automatic adjustment circuit)
19 ACC2 - Filter terminal (output ACC circuit)
20 AGND - GND
21 PB IN In Low-converted chroma signal input in PB
22 BELL ADJ - Filter terminal (bell filter automatic adjustment circuit)
23 ACC1 - Filter terminal (input ACC circuit)
Composite video signal or chroma signal input in REC
24 REC IN In
(In non-bus, PB mode; Open: Normal, L: Trick)
Table 6-1-1 SECAM color process (IC3401) pin functions
6-2
6.2 SECAM COLOR (IC4751)
6.2.1 SECAM color (IC4751) block diagram & pin location
BELL
NC 1 FILTER
ACC 20 CVBS IN
fref/IDENT 2 INTERFACE 19 NC
PULSE
BELL OUT 3 GEN.
18 SCP IN
AMP
VCC 4 17 BLACK ADJ B
BAND
BAND GAP 5 GAP
16 PLL AUTO 1
DE-
PLL
EMPHASIS
KILLER OUT 6 IDENT 15 PLL AUTO 2
SECAM
GND 7 SW 14 BLACK ADJ B
BELL
BELL REF. 8 TUNING
13 NC
B-Y
NC 9 OUTPUT
12 -(B-Y) OUT
PLL R-Y
PLL REF. 10 TUNING OUTPUT
11 -(R-Y) OUT
Fig. 6-2-1 SECAM color (IC4751) block diagram & pin location
6-3
6.2.2 SECAM color (IC4751) pin functions

1 NC - Not used
2 FSR In/Out Reference signal input (f = 4.433619 MHz)
3 BLO Out Bell filter output monitor terminal
4 VCC - Power supply terminal
5 BAG Out Internal reference voltage output terminal
6 KLO Out SECAM killer output terminal (SECAM: 3.1V, Non-SECAM: 0V)
7 GND - GND
8 BLR - Bell filter automatic adjustment voltage hold terminal
9 NC - Not used
10 PLR - PLL automatic adjustment voltage hold terminal
11 R-Y Out R-Y color difference signal output terminal (1 Vp-p typ.)
12 B-Y Out B-Y color difference signal output terminal (1.24 Vp-p typ.)
13 NC - Not used
14 BLB - Black level reference voltage terminal
15 PLO Out PLL automatic adjustment voltage output terminal
16 PLO Out PLL automatic adjustment voltage output terminal
17 BLR - Black level reference voltage terminal
18 SCP In Sand-castle pulse input terminal
19 NC - Not used
20 VBS In SECAM color signal input terminal
Table 6-2-1 SECAM color (IC4751) pin functions
6-4
6.3 BASEBAND DELAY LINE (IC4752)
6.3.1 Baseband delay line (IC4752) pin location
VCC 1 16 R-Y
NC 2 I C 4 7 5 2 15 NC
GND 3 14 B-Y
IC 4 13 NC
SCP 5 12 B-Y
NC 6 11 R-Y
IC 7 10 GND
IC 8 9 VCC
Fig. 6-3-1 Baseband delay line (IC4752) pin location
6.3.2 Baseband delay line (IC4752) block diagram
16 SIGNAL
(R-Y) CLAMPING 11
LINE
SAMPLE (R-Y)
AND LP
MEMORY
HOLD
colour-difference additio
pre-amplifiers output colour-difference
input signals n
buffers output signals
stages
14 SIGNAL
(B-Y) CLAMPING 12
LINE
SAMPLE (B-Y)
AND LP
MEMORY
HOLD
9 analog
V P1 2 NC
supply
3MHz shifting clock 6 NC
5 SAND FREQUENCY
DIVIDER 13 NC
CASTLE PHASE
sandcastle DETECTOR DETECTOR
BY 192 15 NC
pulse input
LP
6MHz DIVIDER 7 NC
CCO BY 2
digital supply
10 1 3 4, 8
GND1
V P2
Fig. 6-3-2 Baseband delay line (IC4752) block diagram
6-5
6.3.3 Baseband delay line (IC4752) pin functions

1 VCC In +5V supply voltage
2 NC - Not used
3 GND - GND
4 IC - Internally connected
5 SCP In Sandcastle pulse input
6 NC - Not used
9 VCC In +5V supply voltage
10 GND - GND
11 R-Y Out ± (R-Y) output signal
12 B-Y Out ± (B-Y) output signal
13 NC - Not used
14 B-Y In ± (B-Y) input signal
15 NC - Not used
16 R-Y In ± (R-Y) input signal
Table 6-3-1 Baseband delay line (IC4752) pin functions
6-6
6.4 SYNC SEPARATOR (IC4754)
6.4.1 Sync separator (IC4754) block diagram & pin location
VBS OSO OSI OSI VCC AFC HD

14 13 12 11 10 9 8
H VCO
AFC
32fH
Horizontal
Count Down
H Sync Sep V Sync Sep
1 2 3 4 5 6 7
CSY GND VSC VSC VSR VSF VD
Fig. 6-4-1 Sync separator (IC4754) block diagram & pin location
6.4.2 Sync separator (IC4754) pin functions

1 CSY Out H sync separation
2 GND - GND
3 VSC -
V sync separation reference control 1
4 VSC -
5 VSR In V sync separation reference control 2
6 VSF - V sync separation filter
7 VD Out VD output
8 HD Out HD output
9 AFC - AFC filter
10 VCC - VCC
11 OSI - H OSC in 2
12 OSI In H OSC in 1
13 OSO Out H OSC output
14 VBS In Sync separation
Table 6-4-1 Sync separator (IC4754) pin functions
6-7
VICTOR COMPANY OF JAPAN, LIMITED
Printed in Japan
9904 (TM2)

Video Technical Guide: GR-AXM700U/AXM500EK/AXM870S

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Video Technical Guide: GR-AXM700U/AXM500EK/AXM870S

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VIDEO TECHNICAL GUIDE

VHS VIDEO MOVIE

SECTION 2 DSC CIRCUIT GR-AXM700U/AXM500EK/AXM870S

2.2 SIGNAL FLOW ..................................................................................................................2-2

2.3 DSC BLOCK......................................................................................................................2-3

2.4 OUTLINE OF DSC CIRCUIT .............................................................................................2-4

2.5 CPU INTERFACE (IC8001) ...............................................................................................2-5

2.6 DSC CPU (IC8002)............................................................................................................2-11

2.7 1M FLASH MEMORY (IC8003) .........................................................................................2-16

2.8 RS232C INTERFACE (IC8006) .........................................................................................2-19

2.9 RESET CIRCUIT (IC8004, IC8007, IC8008, IC8009) ........................................................2-20

SECTION 3 CAMERA CIRCUIT

3.2 CDS / AGC / AD (IC5202)..................................................................................................3-3

3.4 DOWN CONVERTOR (IC5203/IC4002/IC4005)...................................................................3-7

3.5 DSP (IC4001) ....................................................................................................................3-8

3.6 FILTER & AMP (IC4003) ......................................................................................................3-14

3.7 Y/C (IC3001) ........................................................................................................................3-15

3.8 3 INPUT VIDEO SWITCH (IC3051) ...................................................................................3-18

3.9 1H DELAY LINE + CCD COMB FILTER (IC3101)..............................................................3-19

3.10 D/A CONVERTER (IC4301).............................................................................................3-20

3.11 STEPPING MOTOR DRIVE (IC4501) ..............................................................................3-22

SECTION 4 DECK CIRCUIT

4.2 AUDIO PROCESS (IC2001).................................................................................................4-3

4.3 CPU (IC101).........................................................................................................................4-5

4.5 EEPROM (IC105).................................................................................................................4-10

4.6 SYSCON SUB (IC108) .........................................................................................................4-12

4.7 OSD (IC109) ........................................................................................................................4-14

4.8 CTL AMP (IC1201)...............................................................................................................4-16

4.9 MECHA MDA (IC1601) ........................................................................................................4-18

4.10 REGULATOR (IC6001) ......................................................................................................4-22

SECTION 5 MONITOR & SPEAKER / E. VF CIRCUITS

5.2 TIMING CONTROL (IC7505) ...............................................................................................5-3

5.3 E. VF (IC7001) .....................................................................................................................5-5

SECTION 6 SECAM CIRCUIT

6.2 SECAM COLOR (IC4751) ....................................................................................................6-3

6.4 SYNC SEPARATOR (IC4754) ..............................................................................................6-7

1.2 TABLE OF CAMCORDER MODELS (NEWLY PUT ON THE MARKET IN 1998)

Color Y/C & Process VF LCD

Table 1-2-1 Table of camcorder models 1/2

Color Y/C & Process VF LCD

Table 1-2-1 Table of camcorder models 2/2

2.1 LIST OF CAMCORDER WITH A BUILT-IN DSC

Color Y/C & Process VF LCD

Table 2-1-1 List of camcorder with a built-in DSC

PRE / REC HEAD

Fig 2-1-1 Signal flow

0 1 MAIN1 0 8 DSC IC8006

90 INT2 SID 100 71 SID IC8003

Fig. 2-3-1 DSC block diagram

IC8001 IC8002 IC8003

CCD INTERFACE 1MByte

In the period that Y In recording, image data is

Fig. 2-4-1 DSC signal flow

B-Y 2 R-Y 2 B-Y 1 R-Y 1

Fig. 2-5-1 Y & C data transfer

Fig. 2-5-2 Image data transfer sync signal

Fig. 2-5-3 CPU interface (IC8001) pin location

DMA controller CCD image interface

Fig. 2-5-4 CPU interface (IC8001) block diagram