Design and Implementation of 8-bit RISC MCU

Yanfen Chen*,Wuchen Wu,Ligang Hou,Jie Hu

VLSI & Integrated System Lab.
Beijing University of Technology, Beijing,China
Email:chenyanfen237@yahoo.com.cn

Abstract—An 8-bit Reduced Instruction Set Computer (RISC)

Micro Controller Unit (MCU) has been implemented in this TABLE II. THE SPACE OF DATA ADDRESS
paper, including the design of pipeline and critical modules. The
whole design uses two-stage pipeline which enables instruction-
fetching modules and instruction-executing modules to work 0x00-0x1F SFR(Special Function Registers)
simultaneously. Its instruction set is compatible with
PIC16F87XA instruction set and it achieves the execution speed
0xA0-0xFF On-chip RAM (used as data memory)
of a single-cycle instruction (except for the program transfer
instruction).The design is described by Verilog HDL,simulated
by Modelsim and verificated by FPGA. The whole system can
work normally and can achieve 40MHz frequency.

I. INTRODUCTION
With the rapid development of deep submicron
manufacturing and designing technology, integrated circuits
have entered the era of System On Chip (SoC), and
Intellectual Property (IP) has become the most important part
in SoC technology[1]. MCU is particularly significant in the
design of IP, because it is the controlling core in almost all
applications. It has made great progress in application ‫ޔ‬
processing‫ޔ‬structure and integration with ASIC‫ޔ‬SoC and
other semiconductor products[2].

II. THE SYSTEM STRUCTURE OF MCU

The RISC MCU core is comprised of following modules:
Ifetch‫ޔ‬Idecoder‫ޔ‬ALU‫ޔ‬ALU Mux‫ޔ‬PC‫ޔ‬REG_CTRL‫ޔ‬
CLK_div ‫ ޔ‬INT_CTRL and REG_FILE, and peripheral
circuits include ROM ‫ ޔ‬RAM ‫ ޔ‬General-Purpose IO Figure 1 The system structure of MCU
ports(GPIO) ‫ ޔ‬TIMER0 ‫ ޔ‬TIMER1 ‫ ޔ‬UART(Universal
Asynchronous Receiver/Transmitter). One part of on-chip Ifetch is used to fetch instructions from memory and
RAM is used as data memory, and on-chip ROM and the adjust program counter.
other part of RAM are simultaneously used as program Idecoder is one of critical modules of the MCU. It
memory. Table 1 and Table 2 respectively shows the space generates a series of micro-control signals by decoding
of program address and the space of dada address ,and Figure instructions, then the signals will control related modules of
1 shows the system structure of the MCU. MCU to execute calculation and control operations, such as
fetching instructions, selecting operands and so on[3].
Arithmetic Logical Unit ˄ ALU ˅ is the core of RISC
TABLE I. THE SPACE OF PROGRAM ADDRESS MCU. It operates on operands sent by data bus according to
the controlling signals exported by Idecoder, and it performs
0x000-0x0FF On-chip ROM the function of adding‫ޔ‬subtracting‫ޔ‬logical calculations and
shifting[4]. Figure 2 shows the operations of ALU and the W
0x0FF-0x7FF On-chip RAM˄used as program memory˅ register which is a 8-bit register and used for calculating of
ALU.
 required by executing unit) except immediate data required
by internal computation and is responsible for storing all
computed results.
TIMER is used to accurately count trigger signals which
are input by port pins and generated by external event, and
complete corresponding operations according to count results.
TIMER has two modes: timer mode and counter mode. The
main difference between the two modes is the difference of
data source. The data source of timer and counter respectively
comes from internal system clock and the pins. There are two
TIMER modules configured in this design:TIMER0 and
TIMER1.
TIMER0 is an 8-bit wide circulatory accumulating counter
triggered by the rising edge of the clock. It has the function of
overflow interrupt.It is mainly composed of timer and
watchdog, and they share the same prescaler, but they can’t
use it at the same time. They can work simultaneously when
Figure 2 The opetations of ALU and W register the prescaler is used by only one of them, and the exeternal
Program Counter ˄ PC ˅ is usually called instruction clock is synchronized with the internal clock.
calculator. It provides the address of the next instruction to TIMER1 is a 16-bit wide circulatory accumulating
ensure the continuous implementation of the program. Before counter pair composed of two 8-bit registers TMR1L and
the program starts, the starting address of the PC,that is,the TMR1H triggered by the rising edge of the clock. It also has
address of the first instruction must be sent to it. At that time, the function of overflow interrupt. It can work in either timer
the content of PC is the address of the instruction which is mode or counter mode, and counter mode can be divided into
extracted from memory. CPU changes the content of PC synchronous and asynchronous counter mode depending on
when an instruction is executed so that PC’content can the setting of controlling signals.
always be the address of next instruction that is waiting to be UART consists of sampling module ‫ ޔ‬baud rate
extracted. Because instructions are usually executed generating module‫ޔ‬receiver module and sending module. It
sequentially, the process of modification is to simply add 1 to uses the general RS232-C serial interface standard, and a
PC’content. However, this is not the case when the CALLǃ frame of serial data transferred include a start bit, eight data
GOTO and RETLW instructions are executed. bits and a stop bit. Only 24 ports are used in the UART and
REG_CTRL is responsible for managing register file and sampling module is added in the system. Sampling and
internal data memory including special function registers receiving of data are implemented by the way of sampling
(SFR) and general purpose registers. The special function data at the middle time in receiver module and sending
registers are registers used by the CPU and peripheral module. The UART overcomes the shortcomings of common
functions to control the operation of the device. UART. It has simple ports, high accuracy and reliability. Its
CLK_div is used to divide the frequency of external clock structure is shown in Figure 3.
source or intertal clock to generate a four-phase
nonoverlapping clock.
INT_CTRL can control the generation of interrupts and
confirm the interrupt vector. It is mainly composed of
interrupt flag registers‫ޔ‬interrupt mask registers and global
interrupt enable/inhibit registers. There are three interrupt
sources in MCU,they are timer interrupt, UART interrupt and
external interrupt. Interrupt priority is defined by software,
and interrupt vector is 0x004H. The interrupt flag signals are
connected to INT_CTRL. When an interrupt occurs, the
content of PC will be pushed into the stack and the address of
program will jump to the interrupt address.
Register file is the core of the RISC MCU. All internal
Figure 3 7KH structure of UART
and external data have a direct reference to it and its
performance is closely related to the performance of the
whole MCU. All operations of the register file are Input and output port units consist of two bidirectional 8-
bit I/O port registers (PORTA and PORTB) and two I/O
synchronous with the rising edge of system clock. It provides
direction registers (TRISA and TRISB). Port registers’read
unique access for the MCU to exchange data with external
and write is controlled by direction registers.
memory, and it is the center in which MCU deals with
internal data[5]. It offers all data(mainly the source operands
 GPIO can make pins of I/O and functional modules IV.DESIGN OF PIPELINE
reused. When external interrupt is set to enable, with the Pipeline technology is able to make the speed of
arriving of the edge of interrupt signal, GPIO tells processor some times faster by increasing some hardwares or
INT_CTRL that the interrupt should be cleared by software. even not increasing the hardware. It is a generally used
Processor will read the output register of this module when it parallel processing mode.
is checking the port,while data will be directly sent to ports The MCU adopts two-stage pipeline structure to fetch and
when written. execute instructions. The first stage is the instruction-fetching
stage and the second stage is the instruction-executing
stage.An instruction is executed when the next instruction is
III. INSTRUCTION SET AND INSTRUCTION fetched. Figure 5 shows the two-stage pipeline. Clock
FORMAT generates four nonoverlapping clocks respectively named
The instruction set used by the MCU has 35 instructions and Q1,Q2,Q3 and Q4 after the frequency of clock is divided into
each instruction word length is 14 bits long. It is compatible a quarter of it. Here shows how the two-stage pipeline works:
with PIC16F87XA instruction set. The instructions include
byte operating instructions, bit operating instructions, A. At the instruction-fetching stage
immediate data operating instructions and controlling When the rising edge of Q1 arrives, the content of PC is
instructions. All instructions require only one cycle except for updated to destination address which is the present address
the program transfer instruction which requires two cycles[6]. plus 1 in normal circumstances. Destination address is given
Figure 4 shows the general format for instrucions. by control unit when program jumps and corresponding
interrupt vector when interrupt occurs. When the rising edge
of Q2 arrives, instructions are fetched from program memory
and latched in instruction register.

B. At the instruction-executing stage

The stage includes decoding, fetching operands,
executing operation and memory access. All of the above
operations are implemented between next Q1 to Q4.
In summary, the eight-bit MCU greatly increases its speed
by adopting the two-stage pipeline structure.

Figure 5 The structure of the two-stage pipeline

V. Simulation and hardware implementation

Hardware structure of the MCU is described by Verilog
HDL language and simulation and verification are
respectively implemented by the Modelsim software and
FPGA board. The MCU works normally ane the frequency is
Figure 4 General format for instructions 40MHz.
Figure 6 shows the results of simulation.The changes of
the PC pointer and the implementation process of instructions
can be seen in the simulation waveform.The chip used on the
FPGA board is ALTERA’s EP1C6T144C8N, as is shown in
Figure 7.

Figure 6 The results of simulation

tapeout,we can know that the area of the chip is

24mmx24mm and the power consumption is 34.4727
mw.The design is described by Verilog HDL language
which has good readability so that it is easy to modify the
functions of resources.The design can be easily used in
embedded systems.
REFERENCES
[1] LIU Tao,YING Jihong,Design and Research of MCU Core Based in
RISC Technique,Science Tcchnology and Engineering .
[2] FENG Hai-tao,WANG Yong-gang,SHI Jiang-tao,YAN Tian-
xin,WANG Yan-fang,Design and Implementation of 32-bit Integral
Microprocessor Based on FPGA,MINI-MICRO SYSTEMS,2005,6.
[3] Li Jia-rong,Liu Du-ren,Li Xin-hui,A Design of 8-bit RISC MCU IP
Core,ELECTRONICS & PACKAGING,2005 .
[4] JIANG Yan,LIAN Dian-bin,LI Yong,Structure Design of A 64-BIT
RISC Microprocessor,MICROELECTRONICS & COMPUTER,2005
Figure 7 The FPGA board used for verification [5] YANG Guang,QI Jia-yue,Design of a 32-Bit RISC
Microprocessor,Microelectronics,2001.
VI. CONCLUSION [6] PIC 16C5X Data Sheet (EPROM/ROM-Based 8 bit CMOS Micro-
From the results of simulation and verification, it can be controller
seen that the MCU has reached the design target. The key to
the design is the two-stage pipeline. )Uom the results of