TOPIC: Introduction to VLSI and Verilog

COURSE: VLSI design using Verilog

CHAPTER: - One

PPT SL.NO.: 01

VERSION: - 01 LAST UPDATED ON: 1/09/2020

Presentation By: Pragya Sharma

Integrated circuits classification:
VLSI
 Very-large-scale integration (VLSI) is the process of
creating an integrated circuit (IC) by combining
thousands of transistors into a single chip.
 VLSI began in the 1970s when complex
semiconductor and communication technologies
were being developed. The microprocessor is a
VLSI device..
What is Verilog?
 Verilog is a HARDWARE DESCRIPTION LANGUAGE
(HDL). It is a language used for describing a digital
system like a network switch or a microprocessor or a
memory or a flip−flop.
 It means, by using a HDL we can describe any digital
hardware at any level.
 Designs, which are described in HDL are independent
of technology, very easy for designing and debugging,
and are normally more useful than schematics,
particularly for large circuits.
 Used in both hardware simulation & synthesis.
Verilog History
 Introduced in 1984 by Gateway Design Automation
 1989 Cadence purchased Gateway and
subsequently released Verilog to the Public.
 Open Verilog International(OVI) was formed to
control the language specifications
 1995 IEEE accepted OVI Verilog as a standard
 2001 and 2005 IEEE revised standard
 2009 Merged with System Verilog becoming IEEE
Standard 1800-2009.
Verilog HDL terminology
 HDL: A text base programming language that is
used to model a piece of Hardware
 Behavior Modeling: A component is described by
its input/output response.
 Structural Modeling: A component is described by
interconnecting lower-level components/primitives.
Design Representation

A design can be represented at various levels from

three different point of view
 Behavioral
 Structural

 Physical

Design can be conveniently expressed by Y diagram

Design Representation (Y-chart):
Different ways by which we can write
a code in Verilog?
 Data flow modeling
 Gate level modeling
 Behavioral modeling
Data flow:
 Dataflow modeling in Verilog allows a digital system to be designed
in terms of it's function. Dataflow modeling utilizes Boolean
equations, and uses a number of operators that can acton inputs to
produce outputs operators like + - && & ! ~ || | << >> {} so if i want to
describe a 2 to 4 decoder in dataflow modeling i would be like this

module decoder2to4 ( e , a, b, do, dl, d2, d3);

input e, a, b;
output do, dl, d2, d3;
assign dO = ( e & ~a & ~b);
assign dl = (e & ~a & ~b);
assign d2 = (e & a & ~b);
assign d3 = ( e & a & b);
endmodu1e
Gate level:
 module dec2_4 (a,b,en,y0,y1,y2,y3)
input a, b, en;
output y0,y1,y2,y3;
assign y0= (~a) & (~b) & en;
assign y1= (~a) & b & en;
assign y2= a & (~ b) & en;
assign y3= a & b & en;
end module
Behavioral modeling:
 The Behavioral modeling in Verilog is used to describe the function
of a design in an algorithmic manner so if i want to describe a 2 to
4 decoder in dataflow modeling would be like this:
module decoder2to4 (e, i, d);
output [3:0] d;
input [l:0]i;
input e;
reg [3:0] d;
always @ (i or e) begin
if (e==l)
begin
case (i)
0: d = 4'b 0001;
1: d = 4'b 0010;
2: d = 4'b 0100;
3: d = 4'b 1000;
default d = 4'b xxxx;
endcase
end
else
d = 4'b0000;
endmodule
Two Main Components of Verilog
 Concurrent, event-triggered processes (behavioral)
 Initial and Always blocks
 Imperative code that can perform standard data
manipulation tasks (assignment, if-then, case)
 Processes run until they delay for a period of time or wait
for a triggering event
 Structure (Plumbing)
 Verilog program build from modules with I/O interfaces
 Modules may contain instances of other modules

 Modules contain local signals, etc.

 Module configuration is static and all run concurrently

Module & Instantiation of Instances:
 A Module in Verilog is declared within the pair of
keywords module and endmodule.
 Following the keyword module are the module name
and port interface list.
module my_module ( a, b, c, d );
output a, b;
input c, d; ...
endmodule
 All instances must be named except the instances of
primitives. Only primitives in Verilog can have
anonymous instances, i.e. and, or, nand, nor, xor, xnor,
buf, not, bufif1, bufi0, notif1, notif0, nmos, pmos, cmos,
tran, tranif1, tranif0, rnmos, rpmos, rcmos, rtran,
rtranif1, rtranif0.
Data Types:
There are 2 groups of data types in Verilog, namely physical and abstract.
a) Physical data type
 Net (wire, wand, wor, tri, triand, trior). Default value is z. Used mainly in
 structural modeling.
 Register (reg). Default value is x. Used in dataflow/RTL and behavioral
modelings.
 Charge storage node (trireg). Default value is x. Used in gate-level and switch
level modelings.
b) Abstract data type — used only in behavioral modeling and test fixture.
 Integer (integer) stores 32-bit signed quantity.
 Time (time) stores 64-bit unsigned quantity from system task $time.
 Real (real) stores floating-point quantity.
 Parameter (parameter) substitutes constant.
 Event (event) is only name reference — does not hold value.
Two Main Data Types:
 Nets represent connections between things
 Do not hold their value
 Take their value from a driver such as a gate or other module
 Cannot be assigned in an initial or always block

 Regs represent data storage

 Behave exactly like memory in a computer
 Hold their value until explicitly assigned in an initial or always
block.
 Never connected to something
 Can be used to model latches, flip-flops, etc., but do not
correspond exactly
 Shared variables with all their attendant problems
Values & Literals:
 Verilog provides 4 basic values,
 a) 0 — logic zero or false condition
 b) 1 — logic one, or true condition
 c) x — unknown/undefined logic value.
 d) z — high-impedance/floating state- Only for
physical data types.
4'b1011 // 4-bit binary of value 1011
234 // 3-digit decimal of value 234
2'h5A // 2-digit hexadecimal of value 5A
3'o671 // 3-digit octal of value 671
4b'1x0z // 4-bit binary. 2nd MSB is unknown. LSB is Hi Z.
3.14 // Floating point
1.28e5 // Scientific notation
Nets & Registers:
 Net is the connection between ports of modules within a
higher module.
 Net is used in test fixtures and all modeling abstraction
including behavioral.
 Default value of net is high-Z (z). Nets just only pass values
from one end to the other, i.e. it does not store the value.
 Once the output device discontinues driving the net, the
value in the net becomes high-Z (z).
 Besides the usual net (wire), Verilog also provides special
nets (wor, wand) to resolve the final logic when there is logic
contention by multiple drivers. tri, trior and triand are just
the aliases for wire, wor and wand for readability reason.
Nets & Registers:
 Register is the storage that retains (remembers) the
value last assigned to it, therefore, unlike wire, it
needs not to be continuously driven.
 It is only used in the test fixture, behavioral, and
dataflow modelings.
 The default value of a register is unknown (x).
 Other special nets in Verilog are the supplies like
VCC/VDD (supply1), Gnd (supply0), pullup (pullup)
and pulldown (pulldown), resistive pullup (tri1) and
resistive pulldown (tri0), and charge
storage/capacitive node (trireg) which has storage
strength associated with it.
Vectors & Arrays:
 In simple terms a vector is a single element which could be 1 to n bit wide.
For e.g.,
reg [7:0] temp; // where temp is vector of type reg and is 8 bit wide.
Note : while defining vectors index comes before identifier.

 int temp_array[11:0]; // an array of 12 elements of type int

Note : while declaring array, index comes after identifier

 We can also declare an array of vectors. Let it be an 8 bit wide array of 4

bit vectors elements of type reg.
reg [3:0] temp_array_of_vectors[7:0];
Operators:
Operators:
 Operators within the same precedence rank are
associated from left to right.
 Verilog has special syntax restriction on using both
reduction and bitwise operators within the same
expression — even though reduction operator has
higher precedence, parentheses must be used to avoid
confusion with a logical operator.
 a & (&b)
 a | (|b)
 Since bit-select, part-select, concatenation and
replication operators use pairs of delimiters to specify
their operands, there is no notion of operator
precedence associated with them.
Operators:
 There are 2 structured procedure statements, namely
initial and always. They are the basic statements for
behavioral modeling from which other behavioral
statements are declared. They cannot be nested, but
many of them can be declared within a module.
 a) initial statement initial statement executes exactly once
and becomes inactive upon exhaustion. If there are
multiple initial statements, they all start to execute
concurrently at time 0.
 b) always statement always statement continuously repeats
itself throughout the simulation. If there are multiple always
statements, they all start to execute concurrently at time 0.
always statements may be triggered by events using an
event recognizing list @( ).
Design Methdologies
Two basic types of digital design methodologies:
 Top-down Design Methodology

 Bottom-up Design Methodology

Design Methdologies
Top-down Design Methodology:
 Define the top-level block and identify the sub-blocks
necessary to build the top-level block.
 Further subdivide the sub-blocks until we come to leaf
cells, which are the cells that cannot further be divided
Design Methdologies
Bottom-up Design Methodology
 First identify the building blocks which are
available to us.
 Further, build bigger cells, using these building
blocks. These cells are then used for higher-level
blocks until we build the top-level block in the
design.
Design Methdologies
Typically, a combination of top-down and bottom-
up flows is used.
Design architects define the specifications of the
top-level block. Logic designers decide how the
design should be structured by breaking up the
functionality into blocks and sub-blocks.
At the same time, circuit designers are designing
optimized circuits for leaf-level cells. They build
higher-level cells by using these leaf cells.
Modules
 Basic building block.
 A module can be an element or a collection of lower-
level design blocks.
 Typically, elements are grouped into modules to
provide common functionality that is used at many
places in the design.
 A module provides the necessary functionality to the
higher-level block through its port interface (inputs and
outputs), but hides the internal implementation.
 This allows the designer to modify module internals
without affecting the rest of the design.
Modules
 A module is declared by the keyword module.
 A corresponding keyword endmodule must appear
at the end of the module definition.
 Each module must have a module_name, which is
the identifier for the module, and a
module_terminal_list (input and output terminals) of
the module. module <module_name> (<module_terminal_list>);
...
<module internals>
...
...
endmodule
Modules
for example, the T-flipflop could be defined as a
module as follows:

module T_FF (q, clock, reset);

.
.
<functionality of T-flipflop>
.
.
endmodule
Module Instances
 A module provides a template from which you can
create actual objects.
 When a module is invoked, Verilog creates a unique
object from the template.
 Each object has its own name, variables,
parameters, and I/O interface.
 The process of creating objects from a module
template is called instantiation, and the objects are
called instances.
Module Instances
/* Define the top-level module called ripple carry counter. It instantiates 4 T-
flipflops. Interconnections are shown, 4-bit Ripple Carry Counter. */
module ripple_carry_counter(q, clk, reset);
output [3:0] q; //I/O signals and vector declarations explained later.
input clk, reset; //I/O signals will be explained later.
//Four instances of the module T_FF are created. Each has a unique
//name. Each instance is passed a set of signals. Notice, that
//each instance is a copy of the module T_FF.
T_FF tff0(q[0],clk, reset);
T_FF tff1(q[1],q[0], reset);
T_FF tff2(q[2],q[1], reset);
T_FF tff3(q[3],q[2], reset);
endmodule
Illegal Module Nesting
 One module definition cannot contain another module
definition within the module and endmodule statements.
 Instead, a module definition can incorporate copies of other
modules by instantiating them.
module ripple_carry_counter(q, clk, reset);
output [3:0] q;
input clk, reset;
module T_FF(q, clock, reset);// ILLEGAL MODULE NESTING
...
<module T_FF internals>
...
endmodule // END OF ILLEGAL MODULE NESTING
endmodule
Basic Concepts:Lexical Conventions
 Lexical conventions similar to C programming
language.
 Verilog contains a stream of tokens. Tokens can be
comments, delimiters, numbers, strings, identifiers,
and keywords.
 Verilog HDL is a case-sensitive language. All
keywords are in lowercase.
Basic Concepts:Lexical Conventions
Whitespace
Blank spaces (\b) , tabs (\t) and newlines (\n)
comprise the whitespace. Whitespace is used in
strings.
Basic Concepts:Lexical Conventions
Comments
Comments can be inserted in the code for readability and documentation.
There are two ways to write comments.
one-line Comment: A one-line comment starts with "//".
Verilog skips from that point to the end of line.
Multiple-line comment: A multiple-line comment starts with "/*" and ends
with "*/“. Multiple-line comments cannot be nested.
However, one-line comments can be embedded in multiple-line comments.
a = b && c; // This is a one-line comment
/* This is a multiple line
comment */
/* This is /* an illegal */ comment */
/* This is //a legal comment */
Basic Concepts:Lexical Conventions
Operators
Operators are of three types: unary, binary, and ternary.
 Unary operators precede the operand.

 Binary operators appear between two operands.

 Ternary operators have two separate operators that

separate three operands.

a = ~ b; // ~ is a unary operator. b is the operand
a = b && c; // && is a binary operator. b and c are operands
a = b ? c : d; // ?: is a ternary operator. b, c and d are operands
Basic Concepts:Lexical Conventions
Number Specification
There are two types of number specification in Verilog: sized and
unsized.
Sized numbers
Sized numbers are represented as
<size> '<base format> <number>.
• <size> is written only in decimal and specifies the number of bits in
the number.
• Legal base formats are decimal ('d or 'D), hexadecimal ('h or 'H),
binary ('b or 'B) and octal (‘o or 'O).
• The number is specified as consecutive digits from 0, 1, 2, 3, 4, 5, 6,
7, 8, 9, a, b, c, d, e, f. Uppercase letters are legal for number
specification.
Basic Concepts:Lexical Conventions
Examples of sized numbers are as
4'b1111 // This is a 4-bit binary number
12'habc // This is a 12-bit hexadecimal number
16'd255 // This is a 16-bit decimal number.
Basic Concepts:Lexical Conventions
Unsized numbers
Numbers that are specified without a <base format>
specification are decimal numbers by default.
Numbers that are written without a <size> specification
have a default number of bits that is simulator- and
machine-specific (must be at least 32).
For example,
• 23456 // This is a 32-bit decimal number by default
• 'hc3 // This is a 32-bit hexadecimal number
• 'o21 // This is a 32-bit octal number
Basic Concepts:Lexical Conventions
Negative numbers
Negative numbers can be specified by putting a minus
sign before the size for a constant number.
Size constants are always positive.
It is illegal to have a minus sign between
<base format> and <number>.
For example,
-6'd3 //8-bit negative number stored as 2's complement of 3
4'd-2 // Illegal specification
Basic Concepts:Lexical Conventions
Underscore characters and question marks
An underscore character "_" is allowed anywhere in a number
except the first character.
Underscore characters are allowed only to improve readability of
numbers and are ignored by Verilog.
A question mark "?" is alternative for z in the context of numbers.
The ? is used to enhance readability in the casex and casez
statements where the high impedance value is a don't care condition.
For example,
12'b1111_0000_1010 // Use of underline characters for readability
4'b10?? // Equivalent of a 4'b10zz
Basic Concepts:Lexical Conventions
Whitespace
Blank spaces (\b) , tabs (\t) and newlines (\n) comprise
the whitespace. Whitespace is used in strings.
Strings
A string is a sequence of characters that are enclosed
by double quotes.
Strings are treated as a sequence of one-byte ASCII
values.
For example,
"Hello Verilog World" // is a string
"a / b" // is a string
Basic Concepts:Lexical Conventions
Parameters
A parameter is a named constant. When no size
specified, size of parameter is same as size of
constant itself.
parameter RED = -1, GREEN=2;
parameter READY = 2’b01, BUSY= 2’b11, EXIT= 2’b10;
• RED and GREEN are two 32-bit signed constants.
• READY, BUSY and EXIT are three parameters of size 2
bits each.
Basic Concepts: Date Types
Value Set
Verilog supports four logic values and eight strengths
to model the functionality of real hardware.
Value Levels:
Basic Concepts: Date Types
In addition to logic values, strength levels are often
used to resolve conflicts between drivers of different
strengths in digital circuits.
Strength Levels
Basic Concepts: Date Types
Strength levels are particularly useful for accurate
modeling of signal contention. If two signals of
unequal strengths are driven on a wire, the stronger
signal prevails.
 For example, if two signals of strength strong1 and
weak0 contend, the result is resolved as a strong1.
 If two signals of equal strengths are driven on a wire,
the result is unknown.
 If two signals of strength strong1 and strong0 conflict,
the result is an x. Strength
 Thank you!
If you have any query, please contact:

Pragya Sharma
Contact no: +91-xxxxxxxxxx
email: pragyasharma220@@gmail.com

www.nielit.gov.in/haridwar