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Cortex-M3/M4 Architecture

The document summarizes key aspects of the Cortex-M3/M4 architecture, including its memory system, exceptions and interrupts handled by the Nested Vectored Interrupt Controller (NVIC), debug interface, and reset sequence. The memory system uses a 4GB linear address space with predefined memory regions. Exceptions use a stack to save register contexts, with the main stack pointer (MSP) and process stack pointer (PSP) accessible via specific instructions. Debugging is supported via JTAG and SWD interfaces to control execution and access memory and registers.

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128 views

Cortex-M3/M4 Architecture

The document summarizes key aspects of the Cortex-M3/M4 architecture, including its memory system, exceptions and interrupts handled by the Nested Vectored Interrupt Controller (NVIC), debug interface, and reset sequence. The memory system uses a 4GB linear address space with predefined memory regions. Exceptions use a stack to save register contexts, with the main stack pointer (MSP) and process stack pointer (PSP) accessible via specific instructions. Debugging is supported via JTAG and SWD interfaces to control execution and access memory and registers.

Uploaded by

suhaskakade0075745
Copyright
© © All Rights Reserved
We take content rights seriously. If you suspect this is your content, claim it here.
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Download as PDF, TXT or read online on Scribd
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Cortex-M3/M4 Architecture

Architecture Features
• Memory System
• Exceptions and Interrupts
• System Control Block (SCB)
• Debug
• Reset and Reset Sequence
Memory System
• 4 GB Linear Address Space
– 32 bit busses with generic protocol AHB LITE
– Connections to 32/18/8 bit memory devices with suitable
controllers
• Predefined memory map
– Multiple bus interfaces to allow simultaneous access
– Code, SRAM, Peripheral Regions
• Bit Band Accesses
• Write Buffers
• Memory Protection Unit
• Unaligned Transfers
Memory Map
Stack Memory
• Temporary storage of original data when a
function being executed needs to use registers for
data processing. The values can be restored at
the end of the function so the program that
called the function will not lose its data.
• Passing of information to functions or
subroutines.
• For storing local variables.
• To hold processor status and register values in the
case of exceptions such as an interrupt
Stack Push and Pop Operation
Fully Descending Stack
Push and Pop Usage in Function
One Register in the Operation
Push and Pop Usage in Function
Multiple Registers in the Operation
Combining Stack Pop and Return Instruction
MSP used in Thread and Handler Modes
PSP used in Thread Mode and MSP used
in Handler Mode

• Which stack is used for stacking and unstacking while transition


into and from handler mode?
• Which stack would be used in case of nested exceptions?
Accessing SP
• Both the MSP and PSP can be acceded at privilege level
only.
• In ‘C’ language
– x = __get_MSP() ; // Read the value of MSP
– __set_MSP(x) ; // Set the value of MSP
– x = __get_PSP() ; // Read the value of PSP
– __set_PSP(x) ; // Set the value of PSP

• In Assembly language
– MRS R0, MSP ; Read Main Stack Pointer to R0
– MSR MSP, R0 ; Write R0 to Main Stack Pointer
– MRS R0, PSP ; Read Process Stack Pointer to R0
– MSR PSP, R0 ; Write R0 to Process Stack Pointer
Exceptions and Interrupts
Sources
Exception Types
Nested Vectored Interrupt Controller
(NVIC)
• Programmable registers located in the System
Control Space (SCS) of the memory map
• Handles the exceptions and interrupt
configurations, prioritization, and interrupt
masking
• Features:
– Flexible exception and interrupt management
• Pulsed and Level Triggered Interrupt Sources
– Nested exception/interrupt support
– Vectored exception/interrupt entry
– Interrupt masking
Vector Table
Fault Exception and Its Usage
Debug
• Cortex M3/M4 comprehensive debugging
features:
– Program execution controls including halting and
stepping
– Instruction breakpoints, data watchpoints
– Registers and memory accesses,
– Profiling and Traces
• Debug Interfaces
– Debug and Trace
Debug Interface
• Control debug features and access memory
space
• Two Protocols
– Traditional JTAG
– Serial Wire (SWD)
– Supported by many adaptors
Debug Interface
Trace Interface
• Used to collect information from the processor during
runtime such as
– data, event, profiling information, or even complete details
of program execution.
• Two types of trace interface are supported:
– Single pin protocol called Serial Wire Viewer (SWV)
– Multi-pin protocol called Trace Port (Higher trace bandwidth)
• Real-time program trace requires a companion
component called Embedded Trace Macrocell (ETM)
• Instrumentation Trace Macrocell (ITM) allows program
code running on the microcontroller to generate data to
be output through the trace interface.
Trace Port
Reset
• Power on reset:
– Reset everything in the microcontroller. This
includes the processor and its debug support
component and peripherals.
• System reset
– Reset just the processor and peripherals, but not
the debug support component of the processor.
• Processor reset:
– Reset the processor only.
Reset Sequence

• C Startup code:
• Update the value of the MSP before entering the main
program main().
• This two-step stack initialization allows a microcontroller
device with external memory to use the external memory
for the stack
Sample Snapshot of Memory After Boot-up

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