DIGITAL LOGIC DESIGN

VHDL Coding for FPGAs

Unit 5
✓SEQUENTIAL CIRCUITS
▪ Asynchronous sequential circuits: Latches
▪ Synchronous circuits: flip flops, counters,
registers.
▪ Testbench: Generating clock stimulus

Daniel Llamocca
✓ COMBINATIONAL CIRCUITS
▪ In combinational circuits, the output only
depends upon the present input values. COMBINATIONAL CIRCUIT

▪ There exist another class of logic circuits Inputs Combination Outputs

whose outputs not only depend on the al Logic

present input values but also on the past
values of inputs, outputs, and/or internal
signal. These circuits include storage
SEQUENTIAL CIRCUIT
elements to store those previous values. Inputs Outputs

Combination
▪ The content of those storage elements al Logic
represents the circuit state. When the
circuit inputs change, it can be that the
circuit stays in certain state or changes to a Storage
different one. Over time, the circuit goes elements
through a sequence of states as a result of
a change in the inputs. The circuits with
this behavior are called sequential circuits.
Daniel Llamocca
✓SEQUENTIAL CIRCUITS
▪ Combinational circuits can be described with concurrent
statements or behavioral statements.
▪ Sequential circuits are best described with sequential
statements.
▪ Sequential circuits can either be asynchronous or
synchronous. In VHDL, they are described with
asynchronous/synchronous processes.
✓ Basic asynchronous sequential circuits: Latches
✓ Basic synchronous sequential circuits: flip flops,
counters, and registers.

▪ Here, we cover the VHDL description of typical

asynchronous and synchronous sequential circuits.

Daniel Llamocca
✓ ASYNCHRONOUS PROCESS:
▪ SR Latch
▪ An SR Latch based on NOR gates:
S R Qt+1 Qt+1
R
Q 0 0 Qt Qt
0 1 0 1
1 0 1 0
S Q
1 1 0 0 restricted
▪ According to its truth table, the output can be assigned to
either ‘0’ or ‘1’. This circuit state (‘0’ or ‘1’) is stored in the
circuit when S=R=‘0’.
▪ FPGAs usually have trouble implementing these circuits as
FPGAs are synchronous circuits.
Daniel Llamocca
 library ieee;
▪ SR Latch: VHDL code use ieee.std_logic_1164.all;

entity latch_sr is
port ( s,r: in std_logic;
S Q q, qn: out std_logic);
end latch_sr;

R Q architecture bhv of latch_sr is

signal qt,qnt: std_logic;
begin
process (s,r)
begin
if s='1' and r='0' then
S qt<='1'; qnt<='0';
elsif s='0' and r='1' then
R qt<='0'; qnt <='1';
elsif s='1' and r='1' then
Q qt<='0'; qnt <= '0';
end if;
end process;
Q
-- we don't specify what happens
-- if s=r='0' --> q, qn kept their
-- previous values
q <= qt; qn <= qnt;
Daniel Llamocca
end bhv;
▪ SR Latch with enable
library ieee;
R
R' use ieee.std_logic_1164.all;
Q
entity latch_sr_E is
E port ( s,r, E: in std_logic;
q, qn: out std_logic);
end latch_sr_E;
S' Q
S
architecture bhv of latch_sr_E is
signal qt,qnt: std_logic;
E S R Qt+1 Qt+1 begin
process (s,r,E)
0 x x Qt Qt begin
if E = '1' then
1 0 0 Qt Qt if s='1' and r='0' then
qt<='1'; qnt<='0';
1 0 1 0 1 elsif s='0' and r='1' then
qt<='0'; qnt <='1';
1 1 0 1 0 elsif s='1' and r='1' then
qt<='0'; qnt <= '0';
1 1 1 0 0 end if;
end if;
▪ Note: If E = ‘0’, the end process;
previous output is kept. q <= qt; qn <= qnt;
end bhv;
Daniel Llamocca
▪ D Latch with enable
library ieee;
D
use ieee.std_logic_1164.all;
R'
Q
entity latch_D is
E port ( D, E: in std_logic;
q, qn: out std_logic);
S' Q
end latch_D;

architecture bhv of latch_D is

signal qt: std_logic;
E D Qt+1 begin
process (D,E)
0 x Qt begin
1 0 0 if E = '1' then
qt <= d;
1 1 1 end if;
end process;
q <= qt; qn <= not(qt);
end bhv;
Daniel Llamocca
✓ SYNCHRONOUS PROCESSES
▪ Flip Flops
▪ Unlike a Latch, a flip flop only changes its outputs on the edge
(rising or falling) of a signal called clock. A clock signal is a square
wave with a fixed frequency.
▪ To detect a rising or falling edge, flip flops include an edge
detector circuit. Input: a clock signal, Output: short duration
pulses during the rising (or falling) clock edges. These pulses are
then connected to the enable input in a Latch.
▪ For example, an SR flip flop is made out of: a SR Latch with an
edge detector circuit. The edge detector generates enable signals
during the during the rising (or falling) clock edges.
R
R'
Q

clock Edge E
Detector

S' Q
or S
Daniel Llamocca
✓ SYNCHRONOUS PROCESSES
Flip Flops:
▪ The edge detector circuit generates E=‘1’ during the edge (rising or
falling). We will work with circuits activated by either rising or falling
edge. We will not work with circuits activated by both edges.
▪ An example of a circuit that detects a rising edge is shown below. The
redundant NOT gates cause a delay that allows a pulse to be generated
during a rising edge (or positive edge).
clock
E
sig

clock

sig

E
Daniel Llamocca
✓ SYNCHRONOUS PROCESSES
library ieee;
▪ SR Flip Flop use ieee.std_logic_1164.all;

entity ff_sr is
S Q S Q port ( s,r, clock: in std_logic;
clock clock
q, qn: out std_logic);
end ff_sr;
Q Q
R R
Positive Negative architecture bhv of ff_sr is
edge-triggered edge-triggered signal qt,qnt: std_logic;
begin
process (s,r,clock)
begin
Positive-edge triggered if (clock'event and clock='1') then
Negative-edge triggered --if (clock'event and clock='0') then
R if s='1' and r='0' then
qt<='1'; qnt<='0';
Q
elsif s='0' and r='1' then
clock Edge E qt<='0'; qnt <='1';
Detector
elsif s='1' and r='1' then
Q qt<='0'; qnt <= '0';
S
end if;
end if;
end process;
q <= qt; qn <= qnt;
end bhv;
Daniel Llamocca
✓ SYNCHRONOUS PROCESSES
library ieee;
▪ D Flip Flop use ieee.std_logic_1164.all;

entity ff_d is
port ( d, clock: in std_logic;
D Q
q, qn: out std_logic);
end ff_d;
clock
Q architecture bhv of ff_d is
signal qt,qnt: std_logic;
begin
clock D Qt+1 process (d,clock)
begin
0 0 if (clock'event and clock='1') then
qt<=d;
1 1 end if;
end process;
q <= qt; qn <= not(qt);
D end bhv;
Q
* Note: Signal qt is needed.
clock Edge E
In VHDL, we cannot feedback
Detector an output (in this case q) as an
Q input of the circuit
Daniel Llamocca
✓ SYNCHRONOUS PROCESSES
▪ T Flip Flop
library ieee;
use ieee.std_logic_1164.all;

clock T Qt+1 entity ff_t is

port ( t, clock: in std_logic;
0 Qt
q, qn: out std_logic);
1 Qt end ff_t;

architecture bhv of ff_t is

signal qt,qnt: std_logic;
begin
process (t,clock)
begin
if (clock'event and clock='1') then
T D Q T Q
if t = '1' then
qt <= not(qt);
clock clock
Q Q end if;
end if;
end process;
q <= qt; qn <= not(qt);
end bhv;
Daniel Llamocca
✓ SYNCHRONOUS PROCESSES
library ieee;
▪ JK Flip Flop use ieee.std_logic_1164.all;

entity ff_jk is
J Q port ( s,r, clock: in std_logic;
q, qn: out std_logic);
clock end ff_jk;

K Q architecture bhv of ff_jk is

signal qt,qnt: std_logic;
begin
process (j,k,clock)
clock J K Qt+1 begin
if (clock'event and clock='1') then
0 0 Qt if j='1' and k='1' then
qt<= not(qt);
0 1 0 elsif j='1' and k='0' then
qt<='0';
1 0 1 elsif j='0' and k='1' then
qt<='1';
1 1 Qt end if;
end if;
end process;
q <= qt; qn <= qnt;
end bhv;
Daniel Llamocca
✓ SYNCHRONOUS PROCESSES
▪ D Flip Flop with asynchronous inputs: clrn, prn
library ieee;
▪ clrn = ‘0’ ➔ q = ‘0’ use ieee.std_logic_1164.all;
prn = ‘0’ ➔ q = ‘1’
entity ff_dp is
▪ These inputs force the port ( d,clrn,prn,clock: in std_logic;
outputs to a value q, qn: out std_logic);
immediately. end ff_dp;

▪ This is a useful feature architecture bhv of ff_dp is

if we want to initialize signal qt,qnt: std_logic;
begin
the circuit with no process (d,clrn,prn,clock)
regards to the rising begin
(or falling) clock edge if clrn = '0' then
qt <= '0';
prn elsif prn = '0' then
qt <= '1';
elsif (clock'event and clock='1') then
D Q qt <= d;
end if;
clock end process;
Q q <= qt; qn <= not(qt);
end bhv;
Daniel Llamocca clrn
✓ SYNCHRONOUS PROCESSES
▪ D Flip Flop with enable and synchronous clear
library ieee;
▪ This is a complete use ieee.std_logic_1164.all;
design that includes
entity dffes is
asynchronous inputs port ( d,clrn,prn,clk,E,sclr: in std_logic;
(prn, clrn) and q: out std_logic);
synchronous inputs end dffes;
(E, sclr, D). architecture bhv of dffes is
begin
prn
process (d,clrn,prn,E,clock)
begin
D Q if clrn = '0' then q <= '0';
E elsif prn = '0' then q <= '1';
sclr
elsif (clock'event and clock='1') then
clk
if E = '1' then
clrn if sclr = '1' then
q <= '0';
else
q <= d;
end if;
end if;
end if;
end process;
end bhv;
Daniel Llamocca
✓ SYNCHRONOUS PROCESSES
▪ Registers
▪ These are sequential circuits that store the values of signals.
There exist many register types: registers to handle interruptions
in a PC, microprocessor registers, pipelining registers, etc.

▪ n-bit Register: Storage element that can hold ‘n’ bits. It is a

collection of ‘n’ D-type flip flops

▪ Register types:
▪ Simple Register (with/without enable)
▪ Shift register (with/without enable)
Serial input, parallel output
Serial input, serial output
▪ Parallel access shift register (parallel/serial input,
parallel/serial output).
Daniel Llamocca
✓ PARALLEL LOAD, PARALLEL OUTPUT
▪ 8-bit register with enable and
asynchronous library ieee;
reset use ieee.std_logic_1164.all;

entity reg8 is
port (clock, resetn, E: in std_logic;
D: in std_logic_vector (7 downto 0);
Q: out std_logic_vector (7 downto 0));
end reg8;

Q architecture bhv of reg8 is

8 8
D D Q begin
process (resetn,E,clock)
E E
begin
clock Qn if resetn = '0' then
Q <= (others => '0');
elsif (clock'event and clock = '1') then
resetn
if E = '1' then
Q <= D;
end if;
end if;
end process;
end bhv;
Daniel Llamocca
✓ PARALLEL LOAD, PARALLEL OUTPUT
▪ n-bit register library ieee;
with enable, use ieee.std_logic_1164.all;
entity my_rege is
sclr and generic (N: INTEGER:= 4);
asynchronous port ( clock, resetn: in std_logic;
reset E, sclr: in std_logic;
D: in std_logic_vector (N-1 downto 0);
▪ sclr: only Q: out std_logic_vector (N-1 downto 0));
end my_rege;
considered
if E = ‘1’ architecture Behavioral of my_rege is
resetn signal Qt: std_logic_vector (N-1 downto 0);
begin
D n D Q n
process (resetn, clock)
E E begin
sclr sclr if resetn = '0' then Qt <= (others => '0');
clock elsif (clock'event and clock = '1') then
if E = '1' then
if sclr='1' then Qt <= (others =>'0');
else Qt <= D;
PARAMETRIC CODE: end if;
➢ my_rege.zip: end if;
my_rege.vhd, end if;
end process;
tb_my_rege.vhd Q <= Qt;
end Behavioral;
Daniel Llamocca
✓ TESTBENCH
▪ Generating clock stimulus
...
▪ A clock signal is an architecture bhv of tb_my_rege is
...
square wave with a ...
fixed frequency. The constant T: time:= 10 ns;
constant DC: real:= 0.5;
Duty Cycle is usually
50%. begin
uut: my_rege port map (clock=>clock,E=>E,
▪ The example shows a resetn=>resetn,sclr=>sclr,D=>D,Q=>Q);
code snippet of the
clock_process: process
testbench for begin
my_reg3.vhd: An clock <='0'; wait for (T - T*DC);
independent process is clock <='1'; wait for T*DC;
end process;
needed just to create
the clock signal stim_process: process
begin
DC(%) wait for 100 ns;
resetn <= '1'; wait for 2*T;
clock --
end process;
resetn end bhv;
T
Daniel Llamocca
✓ REGISTER: Example
▪ 3-state buffers and 6-to-6 LUT
▪ LUT6-to-6: built by grouping six LUT6-to-1 in parallel. LUT6-to-1:
made out of LUT4-to-1.
▪ Note that the port DATA can be input or output at different times.
In VHDL, we use the INOUT data type to specify this.
▪ LUT6-to-6 contents: Any function of 6 input bits and 6 output bits
can be pre-computed and stored in the LUT6-to-6. In the
example, the function is 𝑂𝐿𝑈𝑇 = 𝐼𝐿𝑈𝑇 0.95 LUT 6-to-6:
resetn b5 b4 b3 b2 b1 b0
0 0 0 0 0 C A
DI 6 D Q 6 6 DO 6 DATA 0 0 0 F C A
ILUT

OLUT

hexadecimals converted
LUT 0 0 F 0 8 6
clk 6-to-6 0 0 F E 9 5

in this direction
E
0 C 3 3 3 A
0 F 0 8 7 6
0 F 0 F E D
OE 0 F F 0 C A

...
0 F F E 9 5
C 3 3 3 3 B
clk
F 0 0 8 7 6
F 0 0 F E 9
resetn F 0 F 0 C 2
F 0 F E 9 5
F C 3 3 3 A
OE F F 0 8 6 5
63
DATA 110001 101001 100111 100001 000111 000111 100001 011100

data5
data4
data3
data2
data1
data0
DI 110001 100111 000111 100001

DO 000000 101001 100001 000111 011100

Daniel Llamocca
✓ REGISTER: Example
▪ 3-state buffers and 6-to-6 LUT
▪ Data: 64 rows of 6 bits. Or 6 columns of 64 bits. The figure shows
the entity VHDL portion of the system.
entity sysLUT6to6 is
generic( data5: std_logic_vector(63 downto 0):=x"ffffffc000000000";
data4: std_logic_vector(63 downto 0):=x"fc00003ffffc0000";
data3: std_logic_vector(63 downto 0):=x"03ff003ff003ff00";
data2: std_logic_vector(63 downto 0):=x"83e0f83e0f83e0f0";
data1: std_logic_vector(63 downto 0):=x"639ce739ce7398cc";
data0: std_logic_vector(63 downto 0):=x"5a5296b5ad6a56aa");
port (clk, resetn, OE: in std_logic;
data: inout std_logic_vector (5 downto 0));
end sysLUT6to6;
▪ Testbench: The code shows that when DATA is output (OE=0), it
MUST be assigned the value ‘Z’. ➢ sysLUT6to6.zip:
... sysLUT6to6.vhd,
resetn<='0'; DATA<="ZZZZZZ";wait for 100 ns; my6to6LUT.vhd,
resetn<='1'; wait for T; my6to1LUT.vhd,
OE<='1'; DATA<="110001";wait for 2*T; my5to1LUT.vhd,
OE<='0'; DATA<="ZZZZZZ";wait for 2*T; my4to1LUT.vhd,
OE<='1'; DATA<="100111";wait for 2*T; my_rege.vhd,
OE<='0'; DATA<="ZZZZZZ";wait for 2*T;
tb_sysLUT6to6.vhd
Daniel Llamocca
✓ SHIFT REGISTER: Serial Input,
Serial/ Parallel Output
▪ n-bit right shift register:
Qn-1 Qn-2 Qn-3 Q0
resetn

shiftin D Q D Q D Q ... D Q shiftout

clk

▪ n-bit left shift register:

Q0 Q1 Q2 Qn-1
resetn

shiftin D Q D Q D Q ... D Q shiftout

clk
PARAMETRIC CODE:
➢ my_shiftreg.zip: Generic n-bit left/right Shift Register
my_shiftreg.vhd,
tb_my_shiftreg.vhd
Daniel Llamocca
✓ PARALLEL ACCESS SHIFT REGISTER
▪ 4-bit right parallel access shift register with enable:
Q3 Q2 Q1 Q0

resetn

D Q D Q D Q D Q
E E E E E

clk

0 1 0 1 0 1 0 1

din D3 s_l D2 D1 D0

▪ 4-bit left parallel Access shift register with enable:

Q0 Q1 Q2 Q3

resetn

D Q D Q D Q D Q
E E E E E

clk

0 1 0 1 0 1 0 1

din D0 s_l D1 D2 D3

PARAMETRIC CODE:
➢ my_pashiftreg.zip: Generic n-bit left/right Parallel Access Shift Register
my_pashiftreg.vhd, tb_my_pashiftreg.vhd
Daniel Llamocca
✓ PARALLEL ACCESS
SHIFT REGISTER library ieee;
use ieee.std_logic_1164.all;
▪ Parallel/serial load entity pashreg4_right is
port (clock, resetn: in std_logic;
Parallel/serial output E, s_l, din: in std_logic;
Shift to the right, 4 bits dout: out std_logic;
D: in std_logic_vector (3 downto 0);
Q: out std_logic_vector (3 downto 0));
▪ s_l=1 -> Paralled load end pashreg4_right;
s_l=0 -> Serial load architecture bhv of pashreg4_right is
signal Qt: std_logic_vector (3 downto 0);
▪ ‘din’: serial input begin
process (resetn, clock, s_l, E)
▪ ‘D’: parallel input begin
▪ ‘dout’: serial output if resetn = '0' then Qt <= "0000";
elsif (clock'event and clock = '1') then
▪ ‘Q’: parallel output if E = '1' then
if s_l='1' then Qt <= D;
else
resetn Qt(0) <= Qt(1); Qt(1) <= Qt(2);
Qt(2) <= Qt(3); Qt(3) <= din;
D 4 D Q 4 end if;
E E end if;
dout
s_l s_l end if;
din din end process;
clock Q <= Qt; dout <= Qt(0);
end bhv;
Daniel Llamocca
✓ PARALLEL ACCESS
library ieee;
SHIFT REGISTER use ieee.std_logic_1164.all;
entity pashreg4_right is
▪ Parallel/serial load port (clock, resetn: in std_logic;
Parallel/serial output E, s_l, din: in std_logic;
dout: out std_logic;
Shift to the right, 4 bits D: in std_logic_vector (3 downto 0);
Q: out std_logic_vector (3 downto 0));
▪ Use of VHDL for loop end pashreg4_right;
▪ s_l=1 -> Parallel load architecture bhv of pashreg4_right is
s_l=0 -> Serial load signal Qt: std_logic_vector (3 downto 0);
begin
▪ ‘din’: serial input process (resetn, clock, s_l, E)
begin
▪ ‘D’: parallel input if resetn = '0' then Qt <= "0000";
elsif (clock'event and clock = '1') then
▪ ‘dout’: serial output if E = '1' then
if s_l='1' then Qt <= D;
▪ ‘Q’: parallel output else
gg: for i in 0 to 2 loop
resetn Qt(i) <= Qt(i+1);
end loop;
D 4 D Q 4 Qt(3) <= din;
E E dout
end if;
s_l s_l end if;
din din end if;
clock end process;
Q <= Qt; dout <= Qt(0);
Daniel Llamocca end bhv;
✓ PARALLEL ACCESS
SHIFT REGISTER library ieee;
use ieee.std_logic_1164.all;
▪ Parallel/serial load entity pashreg4_left is
Parallel/serial output port (clock, resetn: in std_logic;
E, s_l, din: in std_logic;
Shift to the left, 4 bits dout: out std_logic;
D: in std_logic_vector (3 downto 0);
Q: out std_logic_vector (3 downto 0));
▪ s_l=1 -> Paralled load end pashreg4_left;
s_l=0 -> Serial load architecture bhv of pashreg4_left is
▪ ‘din’: serial input signal Qt: std_logic_vector (3 downto 0);
begin
▪ ‘D’: parallel input process (resetn, clock, s_l, E)
begin
▪ ‘dout’: serial output if resetn = '0' then Qt <= "0000";
elsif (clock'event and clock = '1') then
▪ ‘Q’: parallel output if E = '1' then
if s_l='1' then Qt <= D;
else
resetn Qt(3) <= Qt(2); Qt(2) <= Qt(1);
Qt(1) <= Qt(0); Qt(0) <= din;
D 4 D Q 4 end if;
E E end if;
dout
s_l s_l end if;
din din
end process;
clock Q <= Qt; dout <= Qt(3);
Daniel Llamocca end bhv;
✓ PARALLEL ACCESS
SHIFT REGISTER
library ieee;
use ieee.std_logic_1164.all;
entity pashreg4_left is
▪ Parallel/serial load port (clock, resetn: in std_logic;
Parallel/serial output E, s_l, din: in std_logic;
dout: out std_logic;
Shift to the left, 4 bits D: in std_logic_vector (3 downto 0);
Q: out std_logic_vector (3 downto 0));
▪ Use of VHDL for loop end pashreg4_left;
▪ s_l=1 -> Parallel load architecture bhv of pashreg4_left is
s_l=0 -> Serial load signal Qt: std_logic_vector (3 downto 0);
begin
▪ ‘din’: serial input process (resetn, clock, s_l, E)
begin
▪ ‘D’: parallel input if resetn = '0' then Qt <= "0000";
elsif (clock'event and clock = '1') then
▪ ‘dout’: serial output if E = '1' then
if s_l='1' then Qt <= D;
▪ ‘Q’: parallel output else
gg: for i in 1 to 3 loop
resetn Qt(i) <= Qt(i-1);
end loop;
D 4 D Q 4 Qt(0) <= din;
E E end if;
dout
s_l s_l end if;
din din end if;
clock end process;
Q <= Qt; dout <= Qt(3);
Daniel Llamocca end bhv;
✓ SYNCHRONOUS PROCESSES
▪ Synchronous Counters
▪ Counters are very useful in digital systems. They can count the
number of occurrences of a certain event, generate time intervals for
task control, track elapsed time between two events, etc.
▪ Synchronous counters change their output on the clock edge (rising
or falling). Counters are made of flip flops and combinatorial logic.
Every flip flop in a synchronous counter shares the same clock
signal. The figure shows a 4-bit synchronous binary counter (0000
to 1111). A resetn signal is also included to initialize the count.
resetn

'1' T Q T Q T Q T Q

Qn Qn Qn Qn
clock

Q0 Q1 Q2 Q3

Daniel Llamocca
✓ 4-bit binary counter with asynchronous
active-low reset
▪ Count: 0 to 24-1 (once it gets to 24-1, it goes back to 0)
▪ resetn: active-low signal that sets Q to 0 as soon as it is 0, with no
regards to the clock library ieee;
use ieee.std_logic_1164.all;
▪ VHDL code: The
behavioral style is entity my_count4b is
preferred for counters port ( clock, resetn: in std_logic;
Q: out integer range 0 to 15);
(instead of the end my_count4b;
structural description).
architecture bhv of my_count4b is
▪ VHDL code: integer is signal Qt: integer range 0 to 15;
used instead of begin
std_logic_vector. The process (resetn,clock)
begin
number of bits (4) is if resetn = '0' then
automatically computed. Qt <= 0;
resetn elsif (clock'event and clock='1') then
Q 4 Qt <= Qt + 1;
end if;
clock end process;
binary counter Q <= Qt;
Daniel Llamocca 0 to 15 end bhv;
✓ 4-bit binary counter with enable and
asynchronous active-low reset
▪ Synchronous enable library ieee;
signal (‘E’): Only use ieee.std_logic_1164.all;
considered on the
entity my_count4b_E is
rising clock edge. port ( clock, resetn, E: in std_logic;
▪ This is also called a Q: out integer range 0 to 15);
end my_count4b_E;
counter modulo-15
▪ If Qt=1111, then architecture bhv of my_count4b_E is
signal Qt: integer range 0 to 15;
Qt  Qt+1 results in begin
Qt=0000 (since for process (resetn,clock, E)
4 bits, 1111+1=0000) begin
if resetn = '0' then
This is true of any Qt <= 0;
binary counter (0 to 2 -1) elsif (clock'event and clock='1') then
n
resetn if E = '1' then
E Q 4 Qt <= Qt + 1;
E
end if;
end if;
clock end process;
Q <= Qt;
counter
modulo-15
end bhv;
Daniel Llamocca
✓ 4-bit binary counter with enable,
asynchronous active-low reset and
library ieee;
synchronous clear use ieee.std_logic_1164.all;
▪ The signals ‘E’ and
entity my_count4b_E_sclr is
‘sclr’ are synchronous, port ( clock, resetn, E, sclr: in std_logic;
thus they are only Q: out integer range 0 to 15);
end my_count4b_E_sclr;
considered on the
rising clock edge. architecture bhv of my_count4b_E_sclr is
signal Qt: integer range 0 to 15;
▪ If E=sclr=1 then Qt begin
is set to 0. process (resetn,clock, E)
begin
▪ When Qt = 15, if resetn = '0' then
then Qt  Qt+1 will Qt <= 0;
elsif (clock'event and clock='1') then
result in Qt = 0. if E = '1' then
resetn if sclr = '1' then Qt <= 0;
else
Q 4
E E Qt <= Qt + 1;
sclr sclr end if;
end if;
clock
end if;
counter end process;
modulo-15 Q <= Qt;
Daniel Llamocca end bhv;
✓ BCD (or modulo-10) counter with
asynchronous active-low reset
▪ Count: 0 to 9 (4 bits) library ieee;
use ieee.std_logic_1164.all;
▪ When Qt = 9, then
Qt  Qt+1 results in entity my_bcd_count is
port ( clock, resetn: in std_logic;
Qt = 0. Q: out integer range 0 to 15);
Note: This behavior end my_bcd_count;
(9 → 0) must be
architecture bhv of my_bcd_count is
explicitly specified. signal Qt: integer range 0 to 15;
▪ This is different from begin
process (resetn,clock)
the 0-to-15 counter, begin
where the behavior if resetn = '0' then
Qt <= 0;
(15 → 0) was implicit. elsif (clock'event and clock='1') then
if Qt = 9 then
resetn Qt <= 0;
else
4 Qt <= Qt + 1;
Q end if;
end if;
clock
end process;
Q <= Qt;
Daniel Llamocca
BCD counter end bhv;
✓ modulo-13 counter with enable and
asynchronous active-low reset
▪ Count: 0 to 12 (4 bits) library ieee;
use ieee.std_logic_1164.all;
▪ Output ‘z’: Asserted use ieee.std_logic_arith.all;
entity my_mod13count is
when count is 12. port ( clock, resetn, E: in std_logic;
Q: out std_logic_vector(3 downto 0);
z: out std_logic);
end my_mod13count;

architecture bhv of my_mod13count is

resetn signal Qt: integer range 0 to 12);
begin
E 4 process (resetn,clock,E)
E Q
begin
clock
z if resetn = '0' then Qt <= 0;
elsif (clock'event and clock='1') then
Counter 0 to 12 if E = '1' then
0000 - 0001 - 0010 - ... - 1010 - 1011 - 1100 - 0000 - ... if Qt=12 then Qt <= 0;
else Qt <= Qt + 1;
end if;
➢ my_mod13count.zip: end if;
my_mod13count.vhd, end if;
tb_my_mod13count.vhd. end process;
Q <= conv_std_logic_vector(Qt,4);
z <= '1' when Qt = 12 else '0';
Daniel Llamocca end bhv;
✓ 4-bit synchronous up/down counter
with asynchronous active-low reset
▪ ud = 0 → down library ieee;
▪ ud = 1 → up use ieee.std_logic_1164.all;

▪ When Qt = 0000, then entity my_bcd_ud_count is

port ( clock, resetn,ud: in std_logic;
Qt  Qt-1 will result Q: out integer range 0 to 15);
end my_bcd_ud_count;
in Qt = 1111
architecture bhv of my_bcd_ud_count is
signal Qt: integer range 0 to 15;
resetn begin
process (resetn,clock,ud)
ud 4 begin
Q
if resetn = '0' then
clock Qt <= 0;
elsif (clock'event and clock='1') then
if ud = '0' then
u/d counter
Qt <= Qt - 1;
else
➢ mybcd_udcount.zip: Qt <= Qt + 1;
mybcd_udcount.vhd, end if;
tb_mybcd_udcount.vhd end if;
end process;
mybcd_udcount.ucf
Q <= Qt;
Daniel Llamocca end bhv;
✓ 4-bit Synchronous counter with
parallel load library ieee;
use ieee.std_logic_1164.all;
▪ Here, we use Q as use ieee.std_logic_unsigned.all;
a std_logic_vector.
entity my_lcount is
port ( clock, resetn,load: in std_logic;
data: in std_logic_vector(3 downto 0);
Q: out std_logic_vector(3 downto 0));
end my_lcount;

resetn architecture bhv of my_lcount is

signal Qt: std_logic_vector(3 downto 0);
load 4 begin
Q process (resetn,clock,load)
data 4 begin
clock if resetn = '0' then
Qt <= "0000";
counter elsif (clock'event and clock='1') then
if load = '1' then
Qt <= data;
else
Qt <= Qt + "0001";
end if;
end if;
end process;
Q <= Qt;
Daniel Llamocca end bhv;