PROCEDURE TO WORK WITH XILINX 9.

2i SOFTWARE
STEP : 1
Open Xilinx ISE 9.2i, and you will get a window like FIG 1.

FIG 1
STEP : 2
Go to FILE → New project, then New Project Wizard – create new Project window will open as shown in FIG 2.

FIG 2
STEP : 3
Give project name and select location store the project as shown in FIG 3.

FIG 3
STEP : 4
After giving the project name and location, then select next button and then the New project wizard – device
properties window appear as shown in FIG 4
In the device and design flow for this Project window, select the following,
Product category : All
Family : Spartan 3E
Device : XC3S100E
Package : VQ100
Speed : -4
Synthesis Tool : XST (VHDL/Verilog)
Simulator : ISE Simulator (VHDL/Verilog)
Preferred Language : VHDL or Verilog (Select any one based on your usage)
Then click next.

FIG 4
STEP : 6
Now the “New Project Wizard - Create New Source” window will open as shown in FIG5 below.

FIG 5
STEP : 7
Select the “New source” button and then “New Source Wizard – Select Source Type” will open and then
select “VHDL or Verilog Module” as shown in FIG:6 below

FIG 6
STEP : 8
Give the “file name” in the “New Source Wizard – Select source Type” as shown in FIG: 7

FIG 7
STEP : 9
After giving file name click Next, then New Source Wizard – Define module window will open as shown in
FIG 8. Then give PORT NAME, DIRECTION, and click NEXT.

FIG 8
STEP : 10
New Source Wizard – Summary window will open as shown in FIG 9. Verify the port details and give
FINISH.

FIG 9
STEP : 10
After clicking the finish button, then a window will open as shown in FIG 10. The window will display
“The particular file is not present. Would you like to create the file in the particular location”
Click YES.

FIG 10
STEP 11
And then click NEXT button two times and then FINISH and the windows will appeared as shown in FIG 11,
FIG 12, FIG 13 respectively.

FIG 11
FIG 12
FIG 13
STEP 11
A window as shown in FIG 14 will appear. You can type your VHDL/Verilog code in the right side of window
and save the code by pressing the save button in the toolbar of the ISE window.

FIG 14
STEP 12:
After typing the codes in the Workspace then save it. Then expand Synthesize XST and Right click on check
syntax option which is given in the left side of the workspace (Processes window) and give RUN or double click
the check syntax option. The window is shown in FIG 15.

FIG 15
 After running check syntax button, a message “check syntax successfully completed” will appear in the Process
window as shown in FIG 16. If there is any error then it will display the error message.

FIG 16
STEP 13
Select “View RTL Schematic” in Synthesis XST and right click this option and select run (FIG 17). And then the
schematic diagram for the particular coding will be displayed (FIG:18).

FIG 17
FIG 18
STEP 14:
Select the sub-option of Synthesis XST, “View technology Schematic” right click this option and select run. And
then the schematic diagram for the particular coding will be displayed (FIG 19)

FIG 19
STEP 15
Expand User Constraints and select - Assign Package Pins from the Processes window, right click and select run.
( FIG 20).

FIG 20

Then the Xilinx PACE window will open as shown in FIG 21

FIG 22.
STEP 16
Right click on IMPLEMENT DESIGN and select RUN (FIG 23). If it is successful, then it show like FIG 24

FIG 23
FIG 24
STEP 17
Right click on “GENERATE PROGRAMMING FILE” and select RUN. Once the bit file of that particular program
is generated then”Xilinx WebTalk dialog” will open. These dialog window identify the bit file generation and then
simply close this window. (FIG 25 and FIG 26)

FIG 25
FIG 26
STEP 18

Now, switch on the power supply for board and connect the JTAG cable to the Parallel Port connector (J9). Right
click on “Configure Device (iMPACT)” from “Generate programming file” and select Run. (FIG 27).

FIG 27
A New window will appear. In that choose “Configure Device using Boundary Scan (JTAG)” and then click Finish
as shown in FIG 28

FIG 28
Right click the “XC3S100E” and select the “Assign new configuration File” FIG 29.

FIG 29
 “Assign new configuration File” window will open and in that window choose the coressponding .bit file and
select the open button (FIG 30).

FIG 30
Again right click the “XC3S100E” and select the Program option (FIG 31)

FIG 31
After selecting the Program option, “Programming Properties” window will open and click APPLY and OK
(Don’t tick the verify and erase before programming options for FPGA Programming)

FIG 32
Once we give “OK” the Program will be configured in FPGA and the “Program Succeeded” message will be
displayed FIG 33

FIG 33