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TPS65218D0
SLDS234B – DECEMBER 2017 – REVISED SEPTEMBER 2018
TPS65218D0 Power Management for ARM® Cortex™-A8/A9 SOCs and FPGAs

1 Device Overview
1.1
1
Features
• Three Adjustable Step-Down Converters With – LDO1: 1.8-V Default up to 400 mA
Integrated Switching FETs (DCDC1, DCDC2, – VIN Range From 1.8 V to 5.5 V
DCDC3): – Adjustable Output Voltage Range From 0.9 V to
– DCDC1: 1.1-V Default, up to 1.8 A 3.4 V
– DCDC2: 1.1-V Default, up to 1.8 A – Active Output-Discharge When Disabled
– DCDC3: 1.2-V Default, up to 1.8 A • Low-Voltage Load Switch (LS1) With 350-mA
– VIN Range From 2.7 V to 5.5 V Current Limit
– Adjustable Output Voltage Range 0.85 V to – VIN Range From 1.2 V to 3.6 V
1.675 V (DCDC1 and DCDC2) – 110-mΩ (Max) Switch Impedance at 1.35 V
– Adjustable Output Voltage Range 0.9 V to 3.4 V • 5-V Load Switch (LS2) With 100-mA or 500-mA
(DCDC3) Selectable Current Limit
– Power Save Mode at Light Load Current – VIN Range From 3 V to 5.5 V
– 100% Duty Cycle for Lowest Dropout – 500-mΩ (Max) Switch Impedance at 5 V
– Active Output-Discharge When Disabled • High-Voltage Load Switch (LS3) With 100-mA or
• One Adjustable Buck-Boost Converter With 500-mA Selectable Current Limit
Integrated Switching FETs (DCDC4): – VIN Range From 1.8 V to 10 V
– DCDC4: 3.3 V Default, up to 1.6 A – 500-mΩ (Max) Switch Impedance
– VIN Range From 2.7 V to 5.5 V • Supervisor With Built-in Supervisor Function
– Adjustable Output Voltage Range 1.175 V to 3.4 Monitors
V – DCDC1, DCDC2 ±4% Tolerance
– Active Output-Discharge When Disabled – DCDC3, DCDC4 ±5% Tolerance
• Two Low-Quiescent Current, High Efficiency Step- – LDO1 ±5% Tolerance
Down Converters for Battery Backup Domain • Protection, Diagnostics, and Control:
(DCDC5, DCDC6) – Undervoltage Lockout (UVLO)
– DCDC5: 1-V Output – Always-on Push-Button Monitor
– DCDC6: 1.8-V Output – Overtemperature Warning and Shutdown
– VIN Range from 2.2 V to 5.5 V – Separate Power-Good Output for Backup and
– Supplied From System Power or Coin-Cell Main Supplies
Backup Battery – I2C Interface (Address 0x24) (See Timing
• Adjustable General-Purpose LDO (LDO1) Requirements for I2C Operation at 400 kHz)
1.2 Applications
• Industrial Automation • Industrial Communications
• Electronic Point of Sale (ePOS) • Backplane I/O
• Test and Measurement • Connected Industrial Drives
• Personal Navigation
1.3 Description
The TPS65218D0 is a single chip, power-management IC (PMIC) specifically designed to support the
AM335x and AM438x line of processors in both portable (Li-Ion battery) and nonportable (5-V adapter)
applications. The device is characterized across a –40°C to +105°C temperature range, making it suitable
for various industrial applications.
An IMPORTANT NOTICE at the end of this data sheet addresses availability, warranty, changes, use in safety-critical applications,
intellectual property matters and other important disclaimers. UNLESS OTHERWISE NOTED, this document contains PRODUCTION
DATA.
TPS65218D0
SLDS234B – DECEMBER 2017 – REVISED SEPTEMBER 2018 www.ti.com
The TPS65218D0 is specifically designed to provide power management for all the functionalities of the
AM438x processor. The DC/DC converters DCDC1 through DCDC4 are intended to power the core, MPU,
DDR memory, and 3.3-V analog and I/O, respectively. LDO1 provides the 1.8-V analog and I/O for the
processor. GPIO1 and GPO2 allow for memory reset and GPIO3 allows for warm reset (335x only) of the
DCDC1 and DCDC2 converters. The I2C interface allows the user to enable and disable all voltage
regulators, load switches, and GPIOs. Additionally, UVLO and supervisor voltage thresholds, power-up
sequence, and power-down sequence can be programmed through I2C. Interrupts for overtemperature,
overcurrent, and undervoltage can be monitored as well. The supervisor monitors DCDC1 through DCDC4
and LDO1. The supervisor has two settings, one for typical undervoltage tolerance (STRICT = 0b), and
one for tight undervoltage and overvoltage tolerances (STRICT = 1b). A power-good signal indicates
proper regulation of the five voltage regulators.
Three hysteretic step-down converters are targeted at providing power for the processor core, MPU, and
DDRx memory. The default output voltages for each converter can be adjusted through the I2C interface.
DCDC1 and DCDC2 feature dynamic voltage scaling to provide power at all operating points of the
processor. DCDC1 and DCDC2 also have programmable slew rates to help protect processor
components. DCDC3 remains powered while the processor is in a sleep mode to maintain power to DDRx
memory. Backup power provides two step-down converters for the tamper, RTC, or both domains of the
processor if system power fails or is disabled. If both system power and coin-cell battery are connected to
the PMIC, power is not drawn from the coin-cell battery. A separate power good signal monitors the
backup converters. A battery backup monitor determines the power level of the coin-cell battery.
The TPS65218D0 device is available in a 48-pin VQFN package (6 mm × 6 mm, 0.4-mm pitch).
Device Information (1)

PART NUMBER PACKAGE BODY SIZE (NOM)
VQFN (48) (2) 6.00 mm × 6.00 mm
TPS65218D0
HTQFP (48) 7.00 mm × 7.00 mm
(1) For all available packages, see the orderable addendum at the end of the data sheet.
(2) The VQFN package is only available for preview.
2 Device Overview Copyright © 2017–2018, Texas Instruments Incorporated

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Product Folder Links: TPS65218D0
TPS65218D0
www.ti.com SLDS234B – DECEMBER 2017 – REVISED SEPTEMBER 2018
1.4 Simplified Schematic
+
10 …F 10 …F ±
10
1 …F
VIO
VIO
4.7 …F
100 k
4.7 …F
100 k
IN_BIAS
INT_LDO
GPO2
LS2
IN_LS2
IN_LS1
LS1
NC
NC
IN_BU
GPIO3
CC
4.7 …F 1 …F
IN_DCDC3 SYS_BU
L3 L6
10 …F 1.5 µH 10 µH 22 …F
FB3 FB6
nWAKEUP FB5
VDD_18
(DCDC6) 100 k
FB2 L5
1.5 µH 22 …F
10 …F
L2 PGOOD_BU
1.5 µH TPS65218D0
IN_DCDC2 IN_nCC
4.7 …F
PB DC34_SEL
IN_BIAS
100 k
nINT PFI
VIO
100 k
PWR_EN DCDC4
100 nF 47 …F
100 k
FB1 L4B
1.5 µH
L1
10 …F 1.5 µH
IN_DCDC1
IN_DCDC4
IN_LDO1
AC_DET
L4A
PGOOD
IN_LS3
GPIO1
LDO1
nPFO
SDA
SCL
LS3
100 k
100 k
100 k
100 k
100 k
100 k
VIO
VIO
VIO
VIO
IN_BIAS
VIO
10 …F
4.7 …F 10 …F
4.7 …F
4.7 …F
Copyright © 2017, Texas Instruments Incorporated
Figure 1-1. Simplified Schematic
Copyright © 2017–2018, Texas Instruments Incorporated Device Overview 3

TPS65218D0
Table of Contents
1 Device Overview ......................................... 1 5.4 Device Functional Modes ........................... 47
1.1 Features .............................................. 1 5.5 Programming ........................................ 48
1.2 Applications ........................................... 1 5.6 Register Maps ....................................... 50
1.3 Description ............................................ 1 6 Application and Implementation .................... 92
1.4 Simplified Schematic ................................. 3 6.1 Application Information .............................. 92
2 Revision History ......................................... 4 6.2 Typical Application .................................. 94
3 Pin Configuration and Functions ..................... 5 7 Power Supply Recommendations .................. 98
3.1 Pin Functions ......................................... 5 8 Layout .................................................... 98
4 Specifications ............................................ 7 8.1 Layout Guidelines ................................... 98
4.1 Absolute Maximum Ratings .......................... 7 8.2 Layout Example ..................................... 98
4.2 ESD Ratings .......................................... 7 9 Device and Documentation Support .............. 100
4.3 Recommended Operating Conditions ................ 8 9.1 Device Support..................................... 100
4.4 Thermal Information .................................. 8 9.2 Documentation Support ............................ 100
4.5 Electrical Characteristics ............................. 9 9.3 Receiving Notification of Documentation Updates. 100
4.6 Timing Requirements ............................... 18 9.4 Community Resources............................. 100
4.7 Typical Characteristics .............................. 20 9.5 Trademarks ........................................ 100
5 Detailed Description ................................... 21 9.6 Electrostatic Discharge Caution ................... 101
5.1 Overview ............................................ 21 9.7 Glossary............................................ 101
5.2 Functional Block Diagram ........................... 22 10 Mechanical, Packaging, and Orderable
5.3 Feature Description ................................. 23 Information ............................................. 101
2 Revision History
NOTE: Page numbers for previous revisions may differ from page numbers in the current version.
Changes from Revision A (July 2018) to Revision B Page

• Added new applications ............................................................................................................. 1
• Added updates to Description column in the Pin Functions table .............................................................. 5
• Added table note ................................................................................................................... 19
• Changed the location of Backup Supply Power-Good section ............................................................... 28
• Added Programming section ...................................................................................................... 48
Changes from Original (December 2017) to Revision A Page

• Changed the maximum value for the input voltage for the LS3 parameter from 100 V to 10 V in the
Recommended Operating Conditions table ....................................................................................... 8
• Added the List of Recommended Capacitors table in the Output Capacitor Selection section ........................... 96
4 Revision History Copyright © 2017–2018, Texas Instruments Incorporated

TPS65218D0
3 Pin Configuration and Functions

Figure 3-1 shows the 48-pin RSL Plastic Quad Flatpack No-Lead. Figure 3-2 shows the 48-pin PHP
PowerPAD™ Plastic Quad Flatpack.
IN_DCDC2
IN_DCDC3
IN_DCDC2
IN_DCDC3
nWAKEUP
nWAKEUP
PWR_EN
PWR_EN
nINT
nINT
FB1
FB2
FB3
FB1
FB2
FB3
PB
L1
L2
L3
PB
L1
L2
L3
48
47
46
45
44
43
42
41
40
39
38
37
48
47
46
45
44
43
42
41
40
39
38
37
IN_DCDC1 1 36 IN_BIAS
IN_DCDC1 1 36 IN_BIAS
SDA 2 35 INT_LDO
SDA 2 35 INT_LDO
SCL 3 34 GPO2
SCL 3 34 GPO2
LDO1 4 33 LS2
LDO1 4 33 LS2
IN_LDO1 5 32 IN_LS2 IN_LDO1 5 32 IN_LS2
IN_LS3 6 31 IN_LS1 IN_LS3 6 31 IN_LS1

Thermal Thermal
LS3 7 Pad 30 LS1 LS3 7 Pad 30 LS1
PGOOD 8 29 N/C PGOOD 8 29 N/C
AC_DET 9 28 N/C AC_DET 9 28 N/C
nPFO 10 27 IN_BU nPFO 10 27 IN_BU
GPIO1 11 26 GPIO3
GPIO1 11 26 GPIO3
IN_DCDC4 12 25 CC
IN_DCDC4 12 25 CC
13
14
15
16
17
18
19
20
21
22
23
24
13
14
15
16
17
18
19
20
21
22
23
24
L4A
L4B
DCDC4
PFI
DC34_SEL
IN_nCC
PGOOD_BU
L5
FB5
FB6
L6
SYS_BU
Not to scale
L4A
L4B
DCDC4
PFI
DC34_SEL
IN_nCC
PGOOD_BU
L5
FB5
FB6
L6
SYS_BU
Not to scale
Figure 3-1. 48-Pin RSL VQFN With Exposed Figure 3-2. 48-Pin PHP PowerPAD™ HTQFP
Thermal Pad (Top View, 7 mm × 7 mm × 1 mm With 0.5-mm
(Top View, 6 mm × 6 mm × 1 mm With 0.4-mm Pitch)
Pitch)
3.1 Pin Functions

Pin Functions
PIN
TYPE DESCRIPTION
NO. NAME
1 IN_DCDC1 P Input supply pin for DCDC1.
2 SDA I/O Data line for the I2C interface. Connect to pullup resistor.
3 SCL I Clock input for the I2C interface. Connect to pullup resistor.
4 LDO1 O Output voltage pin for LDO1. Connect to capacitor.
5 IN_LDO1 P Input supply pin for LDO1.
6 IN_LS3 P Input supply pin for load switch 3.
7 LS3 O Output voltage pin for load switch 3. Connect to capacitor.
Power-good output (configured as open drain). Pulled low when either DCDC1-4 or LDO1 are out of
8 PGOOD O
regulation. Load switches and DCDC5-6 do not affect PGOOD pin.
AC monitor input and enable for DCDC1-4, LDO1 and load switches. See Section 5.4.1 for details. Tie pin to
9 AC_DET I
IN_BIAS if not used.
Power-fail comparator output, deglitched (open drain). Pin is pulled low when PFI input is below power-fail
10 nPFO O
threshold.
Pin configured as DDR reset-input (driving GPO2) or as general-purpose, open-drain output. See
11 GPIO1 I/O
Section 5.3.1.14 for more information.
13 L4A P Switch pin for DCDC4. Connect to inductor.
14 L4B P Switch pin for DCDC4. Connect to inductor.
15 DCDC4 P Output voltage pin for DCDC4. Connect to capacitor.
Copyright © 2017–2018, Texas Instruments Incorporated Pin Configuration and Functions 5

TPS65218D0
Pin Functions (continued)

PIN
TYPE DESCRIPTION
NO. NAME
16 PFI I Power-fail comparator input. Connect to resistor divider.
Power-up default selection pin for DCDC3 or DCDC4. Power-up default is programmed by a resistor
17 DC34_SEL I
connected to ground. See Section 5.3.1.13 for resistor options.
Output pin indicates if DCDC5 and DCDC6 are powered from main supply (IN_BU) or coin-cell battery (CC).
18 IN_nCC O Pin is push-pull output. Pulled low when PMIC is powered from coin cell battery. Pulled high when PMIC is
powered from main supply (IN_BU).
Power-good, push-pull output for DCDC5 and DCDC6. Pulled low when either DCDC5 or DCDC6 is out of
19 PGOOD_BU O
regulation. Pulled high (to DCDC6 output voltage) when both rails are in regulation.
20 L5 P Switch pin for DCDC5. Connect to inductor.
21 FB5 I Feedback voltage pin for DCDC5. Connect to output capacitor.
System voltage pin for battery-backup supply power path. Connect to 1-µF capacitor. Connecting any
24 SYS_BU P
external load to this pin is not recommended.
Coin cell battery input. Serves as the supply to DCDC5 and DCDC6 if no voltage is applied to IN_BU. Tie this
25 CC P
pin to ground if it is not in use.
Pin can be configured as warm reset (negative edge) for DCDC1/2 or as a general-purpose, open-drain
26 GPIO3 I/O
output. See Section 5.3.1.14 for more details.
27 IN_BU P Default input supply pin for battery backup supplies (DCDC5 and DCDC6).
28 N/C
— No connect. Leave pin floating.
29 N/C
Pin configured as DDR reset signal (controlled by GPIO1) or as general-purpose output. Buffer can be
34 GPO2 O
configured as push-pull or open-drain.
Internal bias voltage. Connect to a 1-μF capacitor. TI does not recommended connecting any external load to
35 INT_LDO P
this pin.
36 IN_BIAS P Input supply pin for reference system.
40 nWAKEUP O Signal to SOC to indicate a power on event (active low, open-drain output).
Push-button monitor input. Typically connected to a momentary switch to ground (active low). See
44 PB I
Section 5.4.1 for details.
Interrupt output (active low, open drain). Pin is pulled low if an interrupt bit is set. The pin returns to Hi-Z state
45 nINT O
after the bit causing the interrupt has been read. Interrupts can be masked.
46 PWR_EN I Power enable input for DCDC1-4, LDO1 and load switches. See Section 5.4.1 for details.
— Thermal Pad P Power ground and thermal relief. Connect to ground plane.
6 Pin Configuration and Functions Copyright © 2017–2018, Texas Instruments Incorporated

TPS65218D0
4 Specifications
4.1 Absolute Maximum Ratings

Operating under free-air temperature range (unless otherwise noted) (1)
MIN MAX UNIT
IN_BIAS, IN_LDO1, IN_LS2, IN_DCDC1, IN_DCDC2,
–0.3 7
IN_DCDC3, IN_DCDC4
Supply voltage IN_LS1, CC –0.3 3.6 V
IN_LS3 –0.3 11.2
IN_BU –0.3 5.8
Input voltage All pins unless specified separately –0.3 7 V
Output voltage All pins unless specified separately –0.3 7 V
Source or sink GPO2 6
mA
current PGOOD_BU, IN_nCC 1
Sink current PGOOD, nWAKEUP, nINT, nPFO, SDA, GPIO1, GPIO3 6 mA
TA Operating ambient temperature –40 105 °C
TJ Junction temperature –40 125 °C
Tstg Storage temperature –65 150 °C
(1) Stresses beyond those listed under Absolute Maximum Ratings may cause permanent damage to the device. These are stress ratings
only and functional operation of the device at these or any other conditions beyond those indicated under Recommended Operating
Conditions is not implied. Exposure to absolute-maximum-rated conditions for extended periods may affect device reliability.
4.2 ESD Ratings

VALUE UNIT
Electrostatic Human-body model (HBM), per ANSI/ESDA/JEDEC JS-001 (1) ±2000
V(ESD) V
discharge Charged-device model (CDM), per JEDEC specification JESD22-C101 (2) ±500
(1) JEDEC document JEP155 states that 500-V HBM allows safe manufacturing with a standard ESD control process.
(2) JEDEC document JEP157 states that 250-V CDM allows safe manufacturing with a standard ESD control process.
Copyright © 2017–2018, Texas Instruments Incorporated Specifications 7

TPS65218D0
4.3 Recommended Operating Conditions

over operating free-air temperature range (unless otherwise noted)
MIN NOM MAX UNIT
Supply voltage, IN_BIAS 2.7 5.5 V
Input voltage for DCDC1, DCDC2, DCDC3, DCDC4 2.7 5.5 V
Supply voltage, IN_BU 2.2 5.5 V
Supply voltage, CC 2.2 3.3 V
Input voltage for LDO1 1.8 5.5 V
Input voltage for LS1 1.2 3.6 V
Input voltage for LS2 3 5.5 V
Input voltage for LS3 1.8 10 V
Output voltage for DCDC1 0.85 1.675 V
Output voltage for DCDC5 1 V
Output voltage for DCDC6 1.8 V
Output voltage for LDO1 0.9 3.4 V
Output current for DCDC1, DCDC2, DCDC3 0 1.8 A
VIN_DCDC4 = 2.8 V 1
Output current for DCDC4 VIN_DCDC4 = 3.6 V 1.3 A
VIN_DCDC4 = 5 V 1.6
Output current for DCDC5, DCDC6 0 25 mA
Output current for LDO1 0 400 mA
Output current for LS1 0 300 mA
Output current for LS2 0 920 mA
VIN_LS3 > 2.3 V 0 900
Output current for LS3 mA
VIN_LS3 ≤ 2.3 V 0 475
4.4 Thermal Information

TPS65218D0
(1)
THERMAL METRIC RSL (VQFN) PHP (HTQFP) UNIT
16 PINS 16 PINS
RθJC(top) Junction-to-case (top) 17.2 13.3 °C/W
RθJB Junction-to-board 5.8 7.9 °C/W
RθJA Thermal resistance, junction to ambient. JEDEC 4-layer, high-K board. 30.6 26.7 °C/W
ΨJT Junction-to-package top 0.2 0.3 °C/W
ΨJB Junction-to-board 5.6 7.8 °C/W
RθJC(bot) Junction-to-case (bottom) 1.5 0.7 °C/W
(1) For more information about traditional and new thermal metrics, see the Semiconductor and IC Package Thermal Metrics application
report.
8 Specifications Copyright © 2017–2018, Texas Instruments Incorporated

TPS65218D0
4.5 Electrical Characteristics

PARAMETER TEST CONDITIONS MIN TYP MAX UNIT
INPUT VOLTAGE AND CURRENTS
Normal operation 2.7 5.5
VIN_BIAS Input supply voltage range V
EEPROM programming 4.5 5.5
UVLOHYS = 0b 200 mV
VUVLO Hysteresis Supply rising
UVLOHYS = 1b 400 mV
Deglitch time 5 ms
OFF state current, total current
VIN = 3.6 V; All rails disabled.
IOFF into IN_BIAS, IN_DCDCx, 5 µA
TJ = 0°C to 85°C
IN_LDO1, IN_LSx, IN_BU
VIN = 3.6 V; DCDC3 enabled, low-power mode, no
SUSPEND current, total current
load.
ISUSPEND into IN_BIAS, IN_DCDCx, 220 µA
All other rails disabled.
IN_LDO1, IN_LSx, IN_BU
TJ = 0°C to 105°C
SYS_BU
VSYS_BU SYS_BU voltage range Powered from VIN_BU or VCC 2.2 5.5 V
Recommended SYS_BU
Ceramic, X5R or X7R, see Table 6-3 1 µF
CSYS_BU capacitor
Tolerance Ceramic, X5R or X7R, rated voltage ≥ 6.3 V –20% 20%
INT_LDO
Output voltage 2.5 V
VINT_LDO
DC accuracy IOUT < 10 mA –2% 2%
IOUT Output current range Maximum allowable external load 0 10 mA
ILIMIT Short circuit current limit Output shorted to GND 23 mA
Measured from VINT_LDO = 2.3 V to VINT_LDO = 1.8 V
All rails enabled before power off,
IN_BIAS tied to IN_DCDC1-4, IN_LDO1
tHOLD Hold-up time 150 ms
VIN_BIAS = 2.8 V to 0 V in < 5 µs
No external load on INT_LDO
CINT_LDO = 1 µF, see Table 6-3
Nominal output capacitor value Ceramic, X5R or X7R, see Table 6-3 0.1 1 22 µF
COUT
Tolerance Ceramic, X5R or X7R, rated voltage ≥ 6.3 V –20% 20%
DCDC1 (1.1-V BUCK)
VIN_DCDC1 Input voltage range VIN_BIAS > VUVLO 2.7 5.5 V
Output voltage range Adjustable through I2C 0.85 1.675 V
VDCDC1
DC accuracy 2.7 V ≤ VIN ≤ 5.5 V; 0 A ≤ IOUT ≤ 1.8 A –2% 2%
In respect to nominal output voltage
Dynamic accuracy IOUT = 50 mA to 450 mA in < 1 µs –2.5% 2.5%
COUT ≥ 10 µF, over full input voltage range
IOUT Continuous output current VIN_DCDC1 > 2.7 V 1.8 A
Total current from IN_DCDC1 pin; Device not
IQ Quiescent current 25 50 µA
switching, no load
High-side FET on resistance VIN_DCDC1 = 3.6 V 230 355
RDS(ON) mΩ
Low-side FET on resistance VIN_DCDC1 = 3.6 V 90 145
High-side current limit VIN_DCDC1 = 3.6 V 2.8
ILIMIT A
Low-side current limit VIN_DCDC1 = 3.6 V 3.1

TPS65218D0
Electrical Characteristics (continued)

STRICT = 0b 88.5% 90% 91.5%
Power-good threshold VOUT falling
STRICT = 1b 96% 96.5% 97%
STRICT = 0b 3.8% 4.1% 4.4%
Hysteresis VOUT rising
STRICT = 1b 0.25%
STRICT = 0b 1 ms
VPG VOUT falling
STRICT = 1b 50 µs
Deglitch
STRICT = 0b 10 µs
VOUT rising
STRICT = 1b 10 µs
Occurs at enable of DCDC1 and after DCDC1
Time-out 5 ms
register write (register 0x16)
Overvoltage detection threshold VOUT rising, STRICT = 1b 103% 103.5% 104%
VOV Hysteresis VOUT falling, STRICT = 1b 0.25%
Deglitch VOUT rising, STRICT = 1b 50 µs
IINRUSH Inrush current VIN_DCDC1 = 3.6 V; COUT = 10 µF to 100 µF 500 mA
RDIS Discharge resistor 150 250 350 Ω
Nominal inductor value See Table 6-2 1 1.5 2.2 µH
L
Tolerance –30% 30%
COUT Output capacitance value Ceramic, X5R or X7R, see Table 6-3 10 22 100 (1) µF
DCDC2 (1.1-V BUCK)
VDCDC2
DC accuracy 2.7 V ≤ VIN ≤ 5.5 V; 0 A ≤ IOUT ≤ 1.8 A –2% 2%
Dynamic accuracy IOUT = 50 mA to 450 mA in < 1 µs –2.5% 2.5%
switching, no load
RDS(ON) mΩ
ILIMIT A
Low-side current limit VIN_DCDC2 = 3.6 V 3.1
STRICT = 0b 88.5% 90% 91.5%
STRICT = 1b 96% 96.5% 97%
STRICT = 0b 3.8% 4.1% 4.4%
STRICT = 1b 0.25%
STRICT = 0b 1 ms
VPG VOUT falling
STRICT = 1b 50 µs
Deglitch
STRICT = 0b 10 µs
VOUT rising
STRICT = 1b 10 µs
Time-out 5 ms
(1) 500-µF of remote capacitance can be supported for DCDC1/2.

TPS65218D0

Nominal inductor value See Table 6-2 1 1.5 2.2 µH
L
COUT Output capacitance value Ceramic, X5R or X7R, see Table 6-3 10 22 100 (1) µF
DCDC3 (1.2-V BUCK)
2
Output voltage range Adjustable through I C 0.9 3.4 V
VDCDC3 2.7 V ≤ VIN ≤ 5.5 V; 0 A ≤ IOUT ≤ 1.8 A,
DC accuracy –2% 2%
VIN_DCDC3 ≥ (VDCDC3 + 700 mV)
Dynamic accuracy IOUT = 50 mA to 450 mA in < 1 µs –2.5% –2.5%
Total current from IN_DCDC3 pin;
Device not switching, no load
RDS(ON) mΩ
ILIMIT A
Low-side current limit VIN_DCDC3 = 3.6 V 3
STRICT = 0b 88.5% 90% 91.5%
STRICT = 1b 95% 95.5% 96%
STRICT = 0b 3.8% 4.1% 4.4%
STRICT = 1b 0.25%
STRICT = 0b 1 ms
VPG VOUT falling
STRICT = 1b 50 µs
Deglitch
STRICT = 0b 10 µs
VOUT rising
STRICT = 1b 10 µs
Time-out 5 ms
Nominal inductor value See Table 6-2 1.0 1.5 2.2 µH
L
COUT Output capacitance value Ceramic, X5R or X7R, see Table 6-3 10 22 100 µF
DCDC4 (3.3-V BUCK-BOOST) / ANALOG AND I/O
VIN_DCDC4 Input voltage operating range VIN_BIAS > VUVLO, –40°C to +105°C 2.8 5.5 V
VDCDC4 Output voltage range Adjustable through I2C 1.175 3.4 V

TPS65218D0

4.2 V ≤ VIN ≤ 5.5 V;
3 V < VOUT ≤ 3.4 V –2% 2%
0 A ≤ IOUT ≤ 1.6 A
3.3 V ≤ VIN ≤ 4.2 V;
3 V < VOUT ≤ 3.4 V –2% 2%
0 A ≤ IOUT ≤ 1.3 A
2.8 V ≤ VIN ≤ 3.3 V;
VDCDC4 DC accuracy 3 V < VOUT ≤ 3.4 V –2% 2%
0 A ≤ IOUT ≤ 1 A
2.8 V ≤ VIN ≤ 5.5 V;
1.65 V < VOUT ≤ 3 V –2% 2%
0 A ≤ IOUT ≤ 1 A
2.8 V ≤ VIN ≤ 5.5 V;
1.175 V < VOUT ≤ 1.65 V –2.5% 2.5%
0 A ≤ IOUT ≤ 1 A
PFM mode enabled;
4.2 V ≤ VIN ≤ 5.5 V;
Output voltage ripple 150 mVpp
0 A ≤ IOUT ≤ 1.6 A
VOUT = 3.3 V
Minimum duty cycle in step-
18%
down mode
VIN_DCDC4 = 2.8 V, VOUT = 3.3 V 1
IOUT Continuous output current VIN_DCDC4 = 3.6 V, VOUT = 3.3 V 1.3 A
VIN_DCDC4 = 5 V, VOUT = 3.3 V 1.6
switching, no load
fSW Switching frequency 2400 kHz
IN_DCDC4 to L4A 166
High-side FET on resistance VIN_DCDC3 = 3.6 V
L4B to DCDC4 149
RDS(ON) mΩ
L4A to GND 142 190
Low-side FET on resistance VIN_DCDC3 = 3.6 V
L4B to GND 144 190
ILIMIT Average switch current limit VIN_DCDC4 = 3.6 V 3000 mA
STRICT = 0b 88.5% 90% 91.5%
STRICT = 1b 95% 95.5% 96%
STRICT = 0b 3.8% 4.1% 4.4%
STRICT = 1b 0.25%
STRICT = 0b 1 ms
VPG VOUT falling
STRICT = 1b 50 µs
Deglitch
STRICT = 0b 10 µs
VOUT rising
STRICT = 1b 10 µs
Time-out 5 ms
VIN_DCDC4 = 3.3 V ≤ VINDCDC4 ≤ 5.5 V; 40 µF ≤ COUT
IINRUSH Inrush current 500 mA
≤ 100 µF
Nominal inductor value See Table 6-2 1.2 1.5 2.2 µH
L
COUT Output capacitance value Ceramic, X5R or X7R, see Table 6-3 40 80 100 µF
DCDC5, DCDC6 POWER PATH

TPS65218D0

VCC DCDC5, 6 input voltage range VIN_BU = 0 V 2.2 3.3 V
VIN_BU DCDC5, 6 input voltage range (2) 2.2 5.5 V
tRISE VCC, VIN_BU rise time VCC = 0 V to 3.3 V, VIN_BU = 0 V to 5.5 V 30 µs
CC to SYS_BU
Power path switch impedance 14.5
VCC = 2.4 V, VIN_BU = 0 V
RDS(ON) Ω
IN_BU to SYS_BU
Power path switch impedance 10.5
VIN_BU = 3.6 V
Into CC pin;
VCC = 3.3 V, VIN_BU = 0 V;
Forward leakage current 50 300
OFF state; FSEAL = 0b;
ILEAK over full temperature range nA
Out of CC pin;
Reverse leakage current VCC = 1.5 V; VIN_BU = 5.5 V; 500
over full temperature range
Acceptable CC source IOUT, DCDC5 < 10 µA;
RCC 1000 Ω
impedance IOUT, DCDC6 < 10 µA
Average current into CC pin; RECOVERY or OFF
IQ Quiescent current state; VIN_BU = 0 V; VCC = 2.4 V; DCDC5 and 350 nA
DCDC6 enabled, no load TJ = 25°C
VIN_BIAS = decaying; CC = 3 V; CSYS_BU = 1 µF;
QINRUSH Inrush charge SYS_BU = 2.3 V to 3 V; CCseries_resist = 10 Ω CCC = 720 nC
4.7 µF
DCDC5 and DCDC6 band-gap
TJ = 25°C 400 ms
sampling period
DCDC5 (1-V BATTERY BACKUP SUPPLY)
Output voltage 1 V
2.7 V ≤ VIN_BU ≤ 5.5 V;
1.5 µA ≤ IOUT ≤ 25 mA –2.5% 2.5%
–40°C ≤ TA < 0°C
2.7 V ≤ VIN_BU ≤ 5.5 V
DC accuracy
VDCDC5 1.5 µA ≤ IOUT ≤ 25 mA –2% 2%
0°C ≤ TA < 105°C
2.2 V ≤ VCC ≤ 3.3 V; VIN_BU = 0;
–2.5% 2.5%
1.5 µA ≤ IOUT ≤ 100 µA
L = 10 µH; COUT = 22 µF; 100-µA load, occurs
Output voltage ripple 32 (3) mVpp
during band-gap sampling
2.2 V ≤ VCC ≤ 3.3 V
10 100 µA
IOUT Continuous output current VIN_BU = 0 V
2.7 V ≤ VIN_BU ≤ 5.5 V 25 mA
High-side FET on resistance VIN_BU = 2.8 V 2.5 3.5
RDS(ON) Ω
Low-side FET on resistance VIN_BU = 2.8 V 2 3
ILIMIT High-side current limit VIN_BU = 2.8 V 50 mA
Power-good threshold VOUT falling 79% 85% 91%
VPG
Hysteresis VOUT rising 6%
Nominal inductor value Chip inductor, see Table 6-2 4.7 10 22 µH
L
Output capacitance value Ceramic, X5R or X7R, see Table 6-3 20 (4) 47 µF
COUT
DCDC6 (1.8-V BATTERY BACKUP SUPPLY)
VDCDC6 Output voltage 1.8 V
(2) IN_BU has priority over CC input.

(3) For PHP package: 160mVpp at -40°C, and 120mVpp from 25°C to 105°C.
(4) For PHP package: 40µF.
TPS65218D0

2.7 V ≤ VIN_BU ≤ 5.5 V;
–2% 2%
1 µA ≤ IOUT ≤ 25 mA
VDCDC6 DC accuracy
2.2 V ≤ VCC ≤ 3.3 V, VIN_BU = 0;
–2% 2%
1 µA ≤ IOUT ≤ 100 µA
VDCDC6 Output voltage ripple L = 10 µH; COUT = 22 µF; 100-µA load 30 (3) mVpp
2.2 V ≤ VCC ≤ 3.3 V
10 100 µA
IOUT Continuous output current VIN_BU = 0 V
2.7 V ≤ VIN_BU ≤ 5.5 V 25 mA
High-side FET on resistance VIN_BU = 3 V 2.5 3.5
RDS(ON) Ω
Low-side FET on resistance VIN_BU = 3 V 2 3
ILIMIT High-side current limit VIN_BU = 3 V 50 mA
Power-good threshold VOUT falling 87% 91% 95%
VPG
Hysteresis VOUT rising 3%
Nominal inductor value Chip inductor, see Table 6-2 4.7 10 22 µH
L
Output capacitance value Ceramic, X5R or X7R, see Table 6-3 20 (4) 47 µF
COUT

TPS65218D0

LDO1 (1.8-V LDO)
VIN_LDO1 Input voltage range VIN_BIAS > VUVLO 1.8 5.5 V
IQ Quiescent current No load 35 µA
VOUT
DC accuracy VOUT + 0.2 V ≤ VIN ≤ 5.5 V; 0 A ≤ IOUT ≤ 200 mA –2% 2%
VIN_LDO1 – VDO = VOUT 0 200
IOUT Output current range mA
VIN_LDO1 > 2.7 V, VOUT = 1.8 V 0 400
ILIMIT Short circuit current limit Output shorted to GND 445 550 mA
VDO Dropout voltage IOUT = 100 mA, VIN = 3.6 V 200 mV
STRICT = 0b 86% 90% 94%
VOUT falling
STRICT = 1b 95% 95.5% 96%
Power-good threshold
STRICT = 0b 3% 4% 5%
Hysteresis, VOUT rising
STRICT = 1b 0.25%
STRICT = 0b 1 ms
VPG VOUT falling
STRICT = 1b 50 µs
Deglitch
STRICT = 0b 10 µs
VOUT rising
STRICT = 1b 10 µs
Occurs at enable of LDO and after LDO register
Time-out 5 ms
write (register 0x1B)
Hysteresis VOUT falling, STRICT = 1b 0.25%
VOV
VOUT rising, STRICT = 1b 50 µs
Deglitch
VOUT falling, STRICT = 1b 1 ms
COUT Output capacitance value Ceramic, X5R or X7R 22 100 µF
LOAD SWITCH 1 (LS1)
VIN_LS1 Input voltage range VIN_BIAS > VUVLO 1.2 3.6 V
VIN_LS1 = 3.3 V, IOUT = 300 mA, over full
110
temperature range
VIN_LS1 = 1.8 V, IOUT = 300 mA,
DDR2, LPDDR, MDDR at 266 MHz over full 110
temperature range
RDS(ON) Static on resistance VIN_LS1 = 1.5 V, IOUT = 300 mA, mΩ
110
DDR3 at 333 MHz over full temperature range
VIN_LS1 = 1.35 V, IOUT = 300 mA,
110
DDR3L at 333 MHz over full temperature range
VIN_LS1 = 1.2 V, IOUT = 200 mA,
150
LPDDR2 at 333 MHz over full temperature range
ILIMIT Short circuit current limit Output shorted to GND 350 mA
tBLANK Interrupt blanking time Output shorted to GND until interrupt is triggered 15 ms
Internal discharge resistor at
RDIS LS1DCHRG = 1 150 250 380 Ω
output (5)
(6)
Overtemperature shutdown 125 132 139
TOTS °C
Hysteresis 10
Nominal output capacitance
COUT Ceramic, X5R or X7R, see Table 6-3 10 100 µF
value
(5) Discharge function disabled by default.
(6) Switch is temporarily turned OFF if temperature exceeds OTS threshold.

TPS65218D0

LOAD SWITCH 2 (LS2)
VIN_LS2 Input voltage range VIN_BIAS > VUVLO 3 5.5 V
(7)
Undervoltage lockout Measured at IN_LS2. Supply falling 2.48 2.6 2.7 V
VUVLO
Hysteresis Input voltage rising 170 mV
VIN_LS2 = 5 V, IOUT = 500 mA, over full temperature
RDS(ON) Static on resistance 500 mΩ
range
LS2ILIM[1:0] = 00b 94 126
Output shorted to GND; LS2ILIM[1:0] = 01b 188 251
ILIMIT Short circuit current limit mA
VIN_LS2 ≥ 4 V LS2ILIM[1:0] = 10b 465 631
LS2ILIM[1:0] = 11b 922 1290
ILEAK Reverse leakage current VLS2 > VIN_LS2 + 1 V 12 30 µA
RDIS LS2DCHRG = 1b 150 250 380 Ω
output (5)
(7)
Overtemperature shutdown 125 132 139
TOTS °C
Hysteresis 10
COUT Ceramic, X5R or X7R, see Table 6-3 1 100 µF
value
LOAD SWITCH 3 (LS3)
VIN_LS3 Input voltage range VIN_BIAS > VUVLO 1.8 10 V
VIN_LS3 = 9 V, IOUT= 500 mA, over full temperature
440
range
VIN_LS3 = 5 V, IOUT= 500 mA, over full temperature
526
range
RDS(ON) Static on resistance mΩ
VIN_LS3 = 2.8 V, IOUT= 200 mA, over full temperature
656
range
VIN_LS3 = 1.8 V, IOUT= 200 mA, over full temperature
910
range
LS3ILIM[1:0] = 00b 98 126
VIN_LS3 > 2.3 V, LS3ILIM[1:0] = 01b 194 253
Output shorted to GND LS3ILIM[1:0] = 10b 475 738
ILIMIT Short circuit current limit LS3ILIM[1:0] = 11b 900 1234 mA
LS3ILIM[1:0] = 00b 98 126
VIN_LS3 ≤ 2.3 V,
LS3ILIM[1:0] = 01b 194 253
Output shorted to GND
LS3ILIM[1:0] = 10b 475 738
RDIS LS3DCHRG = 1 650 1000 1500 Ω
output (5)
(7)
Overtemperature shutdown 125 132 139 °C
TOTS
Hysteresis 10 °C
COUT Ceramic, X5R or X7R, see Table 6-3 1 100 220 µF
value
BACKUP BATTERY MONITOR
Ideal level 3 V
Comparator threshold Good level 2.6 V
VTH
Low level 2.3 V
Accuracy –3% 3%
RLOAD Load impedance Applied from CC to GND during comparison 70 100 130 kΩ
(7) Switch is temporarily turned OFF if input voltage drops below UVLO threshold.
TPS65218D0

RLOAD is connected during delay time. Measurement
tDLY Measurement delay 600 ms
is taken at the end of delay.
I/O LEVELS AND TIMING CHARACTERISTICS
PGDLY[1:0] = 00b 10
PGDLY[1:0] = 01b 20
PGDLY PGOOD delay time ms
PGDLY[1:0] = 10b 50
PGDLY[1:0] = 11b 150
Rising edge 100 ms
PB input
Falling edge 50 ms
Rising edge 100 µs
AC_DET input
Falling edge 10 ms
Rising edge 10 ms
tDG Deglitch time PWR_EN input
Falling edge 100 µs
Rising edge 1 ms
GPIO1
Falling edge 1 ms
Rising edge 5 µs
GPIO3
Falling edge 5 µs
TRST = 0b 8
tRESET Reset time PB input held low s
TRST = 1b 15
SCL, SDA, GPIO1, GPIO3 1.3
0.66 ×
VIH High level input voltage AC_DET, PB V
IN_BIAS
PWR_EN 1.3
VIL Low level input voltage SCL, SDA, PWR_EN, AC_DET, PB, GPIO1, GPIO3 0 0.4 V
VIN_LS1 –
GPO2; ISOURCE = 5 mA; GPO2_BUF = 1 VIN_LS1
0.3
VOH High level output voltage V
VDCDC6 –
PGOOD_BU; ISOURCE = 100 µA
10 mV
nWAKEUP, nINT, SDA, PGOOD, GPIO1, GPO2,
0 0.3
GPIO3; ISINK = 2 mA
VOL Low level output voltage V
nPFO; ISINK = 2 mA 0 0.35
PGOOD_BU; ISINK = 100 µA 0 0.3
Power-fail comparator threshold Input falling 800 mV
Hysteresis Input rising 40 mV
VPFI Accuracy –4% 4%
Input falling 25 µs
Deglitch
Input rising 10 ms
IDC34_SEL DC34_SEL bias current Enabled only at power-up 9.05 10 11.93 µA
Threshold 1 100
Threshold 2 163
Threshold 3 275
DCDC3 / DCDC4 power-up
VDC34_SEL Threshold 4 400 mV
default selection thresholds
Threshold 5 575
Threshold 6 825
Threshold 7 1200

TPS65218D0

Setting 0 0 0 7.7
Setting 1 11.8 12.1 12.4
Setting 2 19.5 20 20.5
DCDC3 / DCDC4 power-up Setting 3 30.9 31.6 32.3
RDC34_SEL kΩ
default selection resistor values Setting 4 44.4 45.3 46.3
Setting 5 64.8 66.1 67.3
Setting 6 93.6 95.3 97.2
Setting 7 146 150
SCL, SDA, GPIO1 (8), GPIO3 (8); VIN = 3.3 V 0.01 1 µA
IBIAS Input bias current
PB, AC_DET, PFI; VIN = 3.3 V 500 nA
nINT, nWAKEUP, nPFO, PGOOD, PWR_EN,
ILEAK Pin leakage current GPIO1 (9), GPO2 (10), GPIO3 (9) 500 nA
VOUT = 3.3 V
OSCILLATOR
Oscillator frequency 2400 kHz
ƒOSC
Frequency accuracy TJ = –40°C to +105°C –12% 12%
OVERTEMPERATURE SHUTDOWN
Overtemperature shutdown Increasing junction temperature 135 145 155
TOTS °C
Hysteresis Decreasing junction temperature 20
High-temperature warning Increasing junction temperature 90 100 110
TWARN °C
Hysteresis Decreasing junction temperature 15
(8) Configured as input.
(9) Configured as output.
(10) Configured as open-drain output.
4.6 Timing Requirements

MIN NOM MAX UNIT
100
fSCL Serial clock frequency kHz
400
Hold time (repeated) START condition. After this period, the SCL = 100 kHz 4 µs
tHD;STA
first clock pulse is generated. SCL = 400 kHz 600 ns
SCL = 100 kHz 4.7
tLOW LOW period of the SCL clock µs
SCL = 400 kHz 1.3
SCL = 100 kHz 4
tHIGH HIGH period of the SCL clock µs
SCL = 400 kHz (1) 1
SCL = 100 kHz 4.7 µs
tSU;STA Set-up time for a repeated START condition
SCL = 400 kHz 600 ns
SCL = 100 kHz 0 3.45 µs
tHD;DAT Data hold time
SCL = 400 kHz 0 900 ns
SCL = 100 kHz 250
tSU;DAT Data set-up time ns
SCL = 400 kHz 100
SCL = 100 kHz 1000
tr Rise time of both SDA and SCL signals ns
SCL = 400 kHz 300
SCL = 100 kHz 300
tf Fall time of both SDA and SCL signals ns
SCL = 400 kHz 300
SCL = 100 kHz 4 µs
tSU;STO Set-up time for STOP condition
SCL = 400 kHz 600 ns
(1) The SCL duty cycle at 400 kHz must be > 40%.
TPS65218D0
Timing Requirements (continued)

MIN NOM MAX UNIT
SCL = 100 kHz 4.7
tBUF Bus free time between STOP and START condition µs
SCL = 400 kHz 1.3
Pulse width of spikes which must be suppressed by the input SCL = 100 kHz — (2) — (2)
tSP ns
filter SCL = 400 kHz 0 50
SCL = 100 kHz 400
Cb Capacitive load for each bus line pF
SCL = 400 kHz 400
(2) The inputs of I2C devices in Standard-mode do not require spike suppression.

TPS65218D0
4.7 Typical Characteristics

at TJ = 25°C unless otherwise noted
0.3% 0.15%
0.25% VIN = 3.6 V 0.1% VIN = 3.6 V
0.2% VIN = 5 V 0.05% VIN = 5 V
0.15% 0
0.1% -0.05%
0.05% -0.1%
Accuracy
Accuracy
0 -0.15%
-0.05% -0.2%
-0.1% -0.25%
-0.15% -0.3%
-0.2% -0.35%
-0.25% -0.4%
-0.3% -0.45%
-0.35% -0.5%
-0.4% -0.55%
0 0.2 0.4 0.6 0.8 1 1.2 1.4 1.6 1.8 0 0.2 0.4 0.6 0.8 1 1.2 1.4 1.6 1.8
Output Current (A) D001
VOUT = 1.1 V VOUT = 1.1 V
Figure 4-1. DCDC1 Accuracy Figure 4-2. DCDC2 Accuracy
0.1% 0.75%
VIN = 3.6 V VIN = 3.6 V
0.05% VIN = 5 V 0.5% VIN = 5 V
0.25%
0
0
Accuracy
Accuracy
-0.05%
-0.25%
-0.1%
-0.5%
-0.15%
-0.75%
-0.2% -1%
-0.25% -1.25%
0 0.2 0.4 0.6 0.8 1 1.2 1.4 1.6 1.8 0 0.2 0.4 0.6 0.8 1 1.2 1.4 1.6
1.4% 0.05%
VIN = 3.6 V 0 VIN = 3.6 V
1.2%
VIN = 5 V VIN = 5 V
-0.05%
1%
-0.1%
0.8%
-0.15%
0.6% -0.2%
Accuracy
Accuracy
0.4% -0.25%
0.2% -0.3%
0 -0.35%
-0.4%
-0.2%
-0.45%
-0.4%
-0.5%
-0.6% -0.55%
-0.8% -0.6%
0 0.005 0.01 0.015 0.02 0.025 0 0.005 0.01 0.015 0.02 0.025
VOUT = 1 V VOUT = 1.8 V

TPS65218D0
5 Detailed Description
5.1 Overview
The TPS65218D0 provides three step-down converters, three load switches, three general-purpose I/Os,
two battery backup supplies, one buck-boost converter and one LDO. The system can be supplied by a
single cell Li-Ion battery or regulated 5-V supply. A coin-cell battery can be added to supply the two
always-on backup supplies. The device is characterized across a –40°C to +105°C temperature range,
which makes it suitable for various industrial applications.
The I2C interface provides comprehensive features for using TPS65218D0. All rails, load switches,, and
GPIOs can be enabled / disabled. Voltage thresholds for the UVLO and supervisor can be customized.
Power-up and power-down sequences can also be programmed through I2C. Interrupts for
overtemperature, overcurrent, and undervoltage can be monitored for the load-switches (LSx).
The integrated voltage supervisor monitors DCDC 1-4 and LDO1. It has two settings; the standard
settings only monitor for undervoltage, while the strict settings implement tight tolerances on both
undervoltage and overvoltage. A power good signal is provided to report the regulation state of the five
rails.
The three hysteretic step-down converters can each supply up to 1.8 A of current. The default output
voltages for each converter can be adjusted through the I2C interface. DCDC 1 and 2 feature dynamic
voltage scaling with adjustable slew rate. The step-down converters operate in a low power mode at light
load, and can be forced into PWM operation for noise sensitive applications.
The battery backup supplies consist of two low power step-down converters optimized for very light loads
and are monitored with a separate power good signal (PGOOD_BU). The converters can be configured to
operate as always-on supplies with the addition of a coin cell battery. The state of the battery can be
monitored over I2C.
Copyright © 2017–2018, Texas Instruments Incorporated Detailed Description 21

TPS65218D0
5.2 Functional Block Diagram
L5 10 µH VDD_10 (1 V)
DCDC6 (1.8 V) Battery-backup
PGOOD_BU DCDC5_PG FB5
To SOC DCDC5 22 …F domain supply
DCDC6_PG
DCDC6 (1.8 V)
IN_nCC L6 10 µH VDD_18 (1.8 V)
To SOC Battery-backup
DCDC6 FB6 22 …F
domain supply
2.7-V to 5.5-V IN_BU

system power
10 CC SYS_BU
Coin +
1 …F
cell ± 4.7 …F 4.7 …F
Always-on coin-cell battery backup supplies
From 1.8-V to 5.5-V IN_LDO1 IN_LS2 From 3-V to 5.5-V
supply supply
0.9-V to 3.3-V analog supply LDO1 LS2 100-mA / 500-mA
LDO1 LS2
(adjustable, default 1.8 V) load switch
10 …F 10 …F
From 1.2-V to 3.3-V IN_LS1 IN_LS3 From 1.8-V to 10-V
supply supply
LS1 LS3 500-mA load
200-mA load switch LS1 LS3
switch
10 …F 10 …F
From 2.7-V to 5.5-V IN_DCDC3 IN_DCDC1 From 2.7-V to 5.5-V

system power system power
4.7 …F 4.7 …F
1.5-V DDR3 supply L3 L1 10 µH 1.1-V core supply
(adjustable) (adjustable)
10 …F FB3 DCDC3 DCDC1 FB1 10 …F
From 2.7-V to 5.5-V IN_DCDC4 IN_DCDC2 From 2.7-V to 5.5-V

system power system power
4.7 …F L4A 4.7 …F
L2 10 µH 1.1-V MPU supply
L4B (adjustable)
DCDC4 DCDC2 FB2 10 …F
3.3-V I/O supply DCDC4

(adjustable) IN_BIAS From 2.7-V to 5.5-V
47 …F 100 nF system power
DC34_SEL INT_LDO
VSELECT BIAS
VDCDC1 1 …F
Supervisor
VDCDC2
and up, VIO VDD_18 VIO VIO
VDCDC3 (1.8 V / (DCDC6) (1.8 V / (1.8 V /
VDCDC4
down 3.3 V) 3.3 V) 3.3 V)
Input Power LDO1 sequencer
nPFO
PFI OD To SOC
+
PGOOD
VREF ± OD To SOC
VIO
10 nWAKEUP
SCL OD To SOC
From SOC
VIO
10 I2C nINT
SDA OD To SOC
From SOC
PWR_EN DIGITAL
From SOC GPIO1
100 k
From SOC
OD
IN_LS1
IN_BIAS To DDR3 memory
100 k GPIO2
From external AC_DET OD
charger IN_BIAS
100 k GPIO3
Momentary push-button PB From SOC
OD
Thermal
Pad
22 Detailed Description Copyright © 2017–2018, Texas Instruments Incorporated

TPS65218D0
5.3 Feature Description
5.3.1 Wake-Up and Power-Up and Power-Down Sequencing

The TPS65218D0 has a predefined power-up and power-down sequence, which in a typical application
does not need to be changed. The user can define custom sequences with I2C. The power-up sequence is
defined by a series of ten strobes and nine delay times. Each output rail is assigned to a strobe to
determine the order of enabling rails. A single rail is assigned to only one strobe, but multiple rails can be
assigned to the same strobe. The delay times between strobes are between 2 ms and 5 ms.
5.3.1.1 Power-Up Sequencing

When the power-up sequence initiates, STROBE1 occurs, and any rail assigned to this strobe is enabled.
After a delay time of DLY1, STROBE2 occurs and the rail assigned to this strobe is powered up. The
sequence continues until all strobes occur and all DLYx times execute. Strobe assignments and delay
times are defined in the SEQx registers, and are changed under I2C control. The power-up sequence
executes if one of the following events occurs:
• From the OFF state:
– The push-button (PB) is pressed (falling edge on PB) OR
– The AC_DET pin is pulled low (falling edge) OR
– The PWR_EN is asserted (driven to high-level) OR
– The main power is connected (IN_BIAS) and AC_DET is grounded AND
– The device is not in undervoltage lockout (UVLO) or overtemperature shutdown (OTS).
• From the PRE_OFF state:
– The PB is pressed (falling edge on PB) OR
– PWR_EN is asserted (driven to high-level) AND
– The device is not in UVLO or OTS.
• From the SUSPEND state:
– The PB is pressed (falling edge on PB) OR
– The PWR_EN pin is pulled high (level sensitive) AND
– The device is not in UVLO or OTS.
When a power-up event is detected, the device enters a WAIT_PWR_EN state and triggers the power-up
sequence. The device remains in WAIT_PWR_EN as long as the PWR_EN and either the PB or AC_DET
pin are held low. If both, the PB and AC_DET return to logic-high state and the PWR_EN pin has not been
asserted within 20 s of entering WAIT_PWR_EN state, the power-down sequence is triggered and the
device returns to OFF state. Once PWR_EN is asserted, the device advances to ACTIVE state, which is
functionally equivalent to WAIT_PWR_EN. However, the AC_DET pin is ignored and power-down is
controlled by the PWR_EN pin only.
Rails not assigned to a strobe (SEQ = 0000b) are not affected by power-up and power-down sequencing
and remain in their current ON/OFF state regardless of the sequencer. A rail can be enabled/disabled at
any time by setting the corresponding enable bit in the ENABLEx register, with the exception that the
ENABLEx register cannot be accessed while the sequencer is active. Enable bits always reflect the
current enable state of the rail, for example the sequencer sets and resets the enable bits for the rails
under its control.
NOTE
The power-up sequence is defined by strobes and delay times, and can be triggered by the
PB, AC_DET (not shown, same as PB), or PWR_EN pin.

TPS65218D0
PB (input)
nWAKEUP
(output)
PWR_EN
(input)
DLY1 DLY2 DLY3 DLY4 DLY5 DLY6 DLY7 DLY8 DLY9
STROBE1 STROBE2 STROBE 3 STROBE 4 STROBE 5 STROBE 6 STROBE 7 STROBE 8 STROBE 9 STROBE 10
SEQ = 0001b SEQ = 0010b SEQ = 0011b SEQ = 0100b SEQ = 0101b SEQ = 0110b SEQ = 0111b SEQ = 1000b SEQ = 1001b SEQ = 1010b
Push-button deglitch time is not shown.
Figure 5-1. Power-Up Sequences from OFF or SUSPEND State;

PB is Power-Up Event
PB (input)
nWAKEUP
(output)
PWR_EN
(input)
Figure 5-2. Power-Up Sequences from SUSPEND State;

PWR_EN is Power-Up Event
FAULT Recovery
PB (input)
nWAKEUP
(output)
PWR_EN
(input)
Figure 5-3. Power-Up Sequences from RECOVERY State

TPS65218D0
5.3.1.2 Power-Down Sequencing

By default, the power-down sequence follows the reverse of the power-up sequence. When the power-
down sequence is triggered, STROBE10 occurs and any rail assigned to STROBE10 is shut down and its
discharge circuit is enabled. After a delay time of DLY9, STROBE9 occurs and any rail assigned to it is
shut down and its discharge circuit is enabled. The sequence continues until all strobes occur and all
DLYx times execute. The DLYx times are extended by a factor of 10x to provide ample time for discharge,
and preventing output voltages from crossing during shut-down. The DLYFCTR bit is applied globally to all
power-down delay times. Regardless of the DLYx and DLYFCTR settings, the PMIC enters OFF,
SUSPEND, or RECOVERY state 500 ms after the power-down sequence initiates, to ensure that the
discharge circuits remain enabled for a minimum of 150 ms before the next power-up sequence starts.
A power-down sequence executes if one of the following events occurs:
• The device is in the WAIT_PWR_EN state, the PB and AC_DET pins are high, PWR_EN is low, and
the 20-s timer has expired.
• The device is in the ACTIVE state and the PWR_EN pin is pulled low.
• The device is in the WAIT_PWR_EN, ACTIVE, or SUSPEND state and the push-button is held low for
> 8 s (15 s if TRST = 1b)
• A fault occurs in the IC (OTS, UVLO, PGOOD failure).
When transitioning from ACTIVE to SUSPEND state, rails not controlled by the power-down sequencer
maintains the same ON/OFF state in SUSPEND state that it had in ACTIVE state. This allows for the
selected power rails to remain powered up when in the SUSPEND state.
When transitioning to the OFF or RECOVERY state, rails not under sequencer control are shut-down as
follows:
• DCDC1, 2, 3, 4, LDO1, and LS1 shut down at the beginning of the power-down sequence, if not under
sequencer control (SEQ = 0b).
• LS2 and LS3 shut down as the state machine enters an OFF or RECOVERY state; 500 ms after the
power-down sequence is triggered.
If the supply voltage on IN_BIAS drops below 2.5 V, the digital core is reset and all power rails are shut
down instantaneously and are pulled low to ground by their internal discharge circuitry (DCDC1-4, and
LDO1). The amount of time the discharge circuitry remains active is a function of the INT_LDO hold up
time (see Section 5.3.1.6 for more details).
5.3.1.3 Strobes 1 and 2

STROBE1 and STROBE2 are dedicated to DCDC5 and DCDC6 which are always-on; powered up as
soon as the device exits the OFF state, and ON in any other state. STROBE 1 and 2 options are available
only for DCDC5 and DCDC6, not for any other rails.
STROBE 1 and STROBE 2 occur in every power-up sequence, regardless if the rail is already powered
up. If the rail is not to be powered up, its respective strobe setting must be set to 0x00.
When a power-down sequence initiates, STROBE1 and STROBE2 occur only if the FSEAL bit is 0b.
Otherwise, both strobes are omitted and DCDC5 and DCDC6 maintain state.
NOTE
The power-down sequence follows the reverse of the power-up sequence. STROBE2 and
STROBE1 are executed only if FSEAL bit is 0b.

TPS65218D0
PB (input)
nWAKEUP
(output)
PWR_EN
(input)
STROBE 10 STROBE 9 STROBE 8 STROBE 7 STROBE 6 STROBE 5 STROBE 4 STROBE 3 STROBE2 STROBE1
Figure 5-4. Power-Down Sequences to OFF State;

PWR_EN is Power-Down Event; FSEAL = 0b
PB (input)
nWAKEUP
(output)
PWR_EN
(input)
DLY9 DLY8 DLY7 DLY6 DLY5 DLY4 DLY3
STROBE 10 STROBE 9 STROBE 8 STROBE 7 STROBE 6 STROBE 5 STROBE 4 STROBE 3

SEQ = 1010b SEQ = 1001b SEQ = 1000b SEQ = 0111b SEQ = 0110b SEQ = 0101b SEQ = 0100b SEQ = 0011b
STROBE2 and STROBE1 are not shown.
Figure 5-5. Power-Down Sequences to SUSPEND State;

PWR_EN is Power-Down Event; FSEAL = 1b
PB (input)
nWAKEUP
(output)
PWR_EN
FAULT
(input)
DLY9 DLY8 DLY7 DLY6 DLY5 DLY4 DLY3
STROBE 10 STROBE 9 STROBE 8 STROBE 7 STROBE 6 STROBE 5 STROBE 4 STROBE 3

SEQ = 1010b SEQ = 1001b SEQ = 1000b SEQ = 0111b SEQ = 0110b SEQ = 0101b SEQ = 0100b SEQ = 0011b
STROBE2 and STROBE1 are not shown.
Figure 5-6. Power-Down Sequences to RECOVERY State;

TSD or UV is Power-Down Event; FSEAL = 1b

TPS65218D0
5.3.1.4 Supply Voltage Supervisor and Power Good (PGOOD)

Power-good (PGOOD) is an open-drain output of the built-in voltage supervisor that monitors DCDC1,
DCDC2, DCDC3, DCDC4, and LDO1. The output is Hi-Z when all enabled rails are in regulation and
driven low when one or more rails encounter a fault which brings the output voltage outside the specified
tolerance range. In a typical application PGOOD drives the reset signal of the SOC.
The supervisor has two modes of operation, controlled by the STRICT bit. With the STRICT bit set to 0, all
enabled rails of the five regulators are monitored for undervoltage only with relaxed thresholds and
deglitch times. With the STRCT bit set to 1, all enabled rails of the five regulators are monitored for
undervoltage and overvoltage with tight limits and short deglitch times. Table 5-1 summarizes these
details.
Table 5-1. Supervisor Characteristics Controlled by the STRICT Bit

PARAMETER STRICT = 0b (TYP) STRICT = 1b (TYP)
96.5% (DCDC1, DCDC2)
Threshold (output falling) 90%
95.5% (DCDC3, DCDC4, LDO1)
Undervoltage
monitoring Deglitch (output falling) 1 ms 50 µs
Deglitch (output rising) 10 µs 10 µs
103.5% (DCDC1, DCDC2)
Threshold (output falling) N/A
104.5% (DCDC3, DCDC4, LDO1)
Overvoltage
monitoring Deglitch (output falling) N/A 1 ms
Deglitch (output rising) N/A 50 µs
Overvoltage threshold
(output rising)
LDO1
Hysteresis
Undervoltage threshold
(output falling)
Hysteresis
Power-good comparator
output (internal signal)
Voltage droop has no effect on Voltage droop has no effect on

PGOOD output if duration is PGOOD output if duration is
less than deglitch time. less than deglitch time.
PGOOD
Deglitch time
Figure 5-7. Definition of Undervoltage, Overvoltage Thresholds, Hysteresis, and Deglitch Times
The following rules apply to the PGOOD output:

• The power-up default state for PGOOD is low. When all rails are disabled, PGOOD output is driven
low.
• Only enabled rails are monitored. Disabled rails are ignored.
• Power-good monitoring of a particular rail starts 5 ms after the rail is enabled and is continuously
monitored thereafter. This allows the rail to power-up.
• PGOOD is delayed by PGDLY time after the sequencer is finished and the last rail is enabled.
• If an enabled rail is continuously outside the monitoring threshold for longer than the deglitch time,
PGOOD is pulled low, and all rails are shut-down following the power-down sequence. PGDLY does
not apply.

TPS65218D0
• Disabling a rail manually by resetting the DCx_EN or LDO1_EN bit has no effect on the PGOOD pin. If
all rails are disabled, PGOOD is driven low as the last rail is disabled.
• If the power-down sequencer is triggered, PGOOD is driven low.
• PGOOD is driven low in SUSPEND state, regardless of the number of rails that are enabled.
Figure 5-8 shows a typical power-up sequence and PGOOD timing.
VSYS
5 s (maximum)
PB
nWAKEUP
PWR_EN
(deglitched)
DLY1 + DLY2
LDO1
5 ms DLY4 + DLY3
PG LDO1
(internal) FAULT
DLY3 + DLY4
DCDC3
5 ms
PG DCDC3 DLY6 + DLY5
(internal)
DLY5 + DLY6
DCDC4
5 ms DLY7
PG DCDC4
(internal)
DLY7
DCDC1
5 ms DLY8
PG DCDC1
(internal)
DLY8
DCDC2
5 ms DLY9
PG DCDC2
(internal)
PG_DLY
PGOOD
Figure 5-8. Typical Power-Up Sequence of the Main Output Rails
5.3.1.5 Backup Supply Power-Good (PGOOD_BU)

PGOOD_BU is a push-pull output indicating if DCDC5 and DCDC6 are in regulation. The output is driven
to high when both rails are in regulation, and driven low if at least one of the rails is below the power-good
threshold. The output-high level is equal to the output voltage of DCDC6.
PGOOD_BU is the logical AND between PGOOD(DCDC5) and PGOOD(DCDC6), and has no delay time
built-in. Unlike main power-good, a fault on DCDC5 or DCDC6 does not trigger the power-down
sequencer, does not disable any of the rails in the system, and has no effect on the PGOOD pin. DCDC5
and DCDC6 recover automatically once the fault is removed.

TPS65218D0
NOTE
In this example, the power-down is triggered by a fault on DCDC3.
This timing diagram assumes each rail powers up within the strobe delay time. If a rail takes
longer than the strobe delay time to power up, the next rail will wait for the previous rail to
reach its PGOOD voltage, and then may wait an additional 1ms until it is enabled.
VSYS
5 s (maximum)
PB
nWAKEUP
PWR_EN
(deglitched)
DCDC6
PG DCDC6
(internal)
DLY1
DCDC5
PG DCDC5
(internal)
PGOOD_BU
Figure 5-9. Typical Power-Up Sequence of DCDC5 and DCDC6
5.3.1.6 Internal LDO (INT_LDO)

The internal LDO (INT_LDO) provides a regulated voltage to the internal digital core and analog circuitry.
The internal LDO has a nominal output voltage of 2.5 V and can support up to 10 mA of external load.
During EEPROM programming, the output voltage is elevated to 3.6 V as described in Section 5.5.1.
Therefore, any external circuitry connected to INT_LDO must be capable of supporting that voltage.
When system power fails, the UVLO comparator triggers the power-down sequence. If system power
drops below 2.3 V, the digital core is reset and all remaining power rails are shut down instantaneously
and are pulled low to ground by their internal discharge circuitry (DCDC1-4, and LDO1).
The internal LDO reverse blocks to prevent the discharging of the output capacitor (CINT_LDO) on the
INT_LDO pin. The remaining charge on the INT_LDO output capacitor provides a supply for the power rail
discharge circuitry to ensure the outputs are discharged to ground even if the system supply has failed.
The amount of hold-up time specified in Section 4.5 is a function of the output capacitor value (CINT_LDO)
and the amount of external load on the INT_LDO pin, if any. The design allows for enough hold-up time to
sufficiently discharge DCDC1-4, and LDO1 to ensure proper processor power-down sequencing.

TPS65218D0
IN_BIAS INT_LDO
From
system
power 10 …F
UVLO RESET
Digital Core
Power-Rail
Discharge Circuitry
EEPROM
Figure 5-10. Internal LDO and UVLO Sensing

TPS65218D0
5.3.1.7 Current Limited Load Switches

The TPS65218D0 provides three current limited load switches with individual inputs, outputs, and enable
control. Each switch provides the following control and diagnostic features:
• The ON/OFF state of the switch is controlled by the corresponding LSx_EN bit in the ENABLE register.
• LS1 can be controlled by the sequencer or through I2C communication.
• LS2 and LS3 can ONLY be controlled through I2C communication. The sequencer has no control over
LS2 and LS3.
• Each switch has an active discharge function, disabled by default, and enabled through the
LSxDCHRG bit. When enabled, the switch output is discharged to ground whenever the switch is
disabled.
• When the PFI input drops below the power-fail threshold (the power-fail comparator trips), the load
switches are automatically disabled to shed system load. This function must be individually enabled for
each switch through the corresponding LSxnPFO bit. The switches do not turn back on automatically
as the system voltage recovers, and must be manually re-enabled.
• An interrupt (LSx_I) issues whenever a load switch actively limits the output current, such as when the
output load exceeds the current limit value. The switch remains ON and provides current to the load
according to the current-limit setting.
• All three load switches have local overtemperature sensors which disable the corresponding switch if
the power dissipation and junction temperature exceeds safe operating value. The switch automatically
recovers once the temperature drops below the OTS threshold value minus hysteresis. The LSx_F
(fault) interrupt bit is set while the switch is held OFF by the OTS function.
5.3.1.7.1 Load Switch 1 (LS1)

LS1 is a non-reverse blocking, low-voltage (< 3.6 V), low-impedance switch intended to support DDRx
self-refresh mode by cutting off the DDRx supply to the SOC DDRx interface during SUSPEND mode. In a
typical application, the input of LS1 is tied to the output of DCDC3 while the output of LS1 is connected to
the memory-interface supply pin of the SOC. LS1 can be controlled by the internal sequencer, just as any
power rail.
LS1_EN
LS1DIS
LS1nPFO
SOC
IN_LS1 LS1
From DCDC3 DDR Memory
10 …F Interface
250
LS1_I
LS1_F
Figure 5-11. Typical Application of Load Switch 1

TPS65218D0

LS2 is a reverse-blocking, 5 V, low-impedance switch. Load switch 2 provides four different current limit
values (100/200/500/1000 mA) that are selectable through LS2ILIM[1:0] bits. Overcurrent is reported
through the LS2_I interrupt.
LS2 has its own input-undervoltage protection which forces the switch OFF if the switch input voltage
(VIN_LS2) is <2.7 V. Similar to OTS, the LS2_F interrupt is set when the switch is held OFF by the local
UVLO function, and the switch recovers automatically when the input voltage rises above the UVLO
threshold.
LS2_EN
LS2DIS
LS2nPFO
LS2ILIM[1:0]
IN_LS2 LS2 +5 V
5-V boost
0.1 …F 120 …F 5-V
250 GND Port
LS2_I
LS2_F

LS3 is a non-reverse blocking, medium-voltage (< 10 V), low-impedance switch that can be used to
provide 1.8-V to 10-V power to an auxiliary port. LS3 has four selectable current limit values that are
selectable through LS3ILIM[1:0].
LS3_EN
LS3DIS
LS3nPFO
LS3ILIM[1:0]
IN_LS3 LS3 VPORT

From any
1.8-V to 10-V supply
0.1 …F 120 …F AUX
250 GND Port
LS3_I
LS3_F

TPS65218D0
5.3.1.8 LDO1
LDO1 is a general-purpose LDO intended to provide power to analog circuitry on the SOC. LDO1 has an
input voltage range from 1.8 V to 5.5 V, and can be connected either directly to the system power or the
output of a DCDC converter. The output voltage is programmable in the range of 0.9 V to 3.4 V with a
default of 1.8 V. LDO1 supports up to 200 mA at the minimum specified headroom voltage, and up to 400
mA at the typical operating condition of VOUT = 1.8 V, VIN_LDO1 > 2.7 V.
5.3.1.9 Coin Cell Battery Voltage Acquisition
10 CC
LOW (2.3 V)
DISABLED +
+
Coin Cell VREF ±
±
CC_AQ = 1 GOOD (2.6 V)

+
Enable 100-k load resistor on CC VREF ±

input.
CC_STAT[1:0]
Enable comparators.
IDEAL (3 V)
+ LOGIC CORE
VREF ±
Wait 600 ms
LOAD ENABLE
Latch comparator outputs;

Store result in CC_STAT[1:0]
CC_STAT[1:0] = 00b ± VCC < VLOW; Coin cell is not present or at end-of-life (EOL)
CC_STAT[1:0] = 01b ± VLOW < VCC < VGOOD; Coin cell is LOW
CC_STAT[1:0] = 10b ± VGOOD < VCC < VIDEAL; Coin cell is GOOD
Disable 100-k load resistor. CC_STAT[1:0] = 11b ± VIDEAL < VCC; Coin cell voltage is IDEAL
Disable comparators
Restore CC_AQ bit to 0 (CC_AQ = 0)
Issue interrupt (CC_AQC = 1)
Figure 5-14. Left: Flow Chart for Acquiring Coin Cell Battery Voltage
Right: Comparator Circuit
5.3.1.10 UVLO
Depending on the slew rate of the input voltage into the IN_BIAS pin, the power rails of TPS65218D0 will
be enabled at either VULVO or VULVO + VHYS.
If the slew rate of the IN_BIAS voltage is greater than 30 V/s, then TPS65218D0 will power up at VULVO.
Once the input voltage rises above this level, the input voltage may drop to the VUVLO level before the
PMIC shuts down. In this scenario, if the input voltage were to fall below VUVLO but above 2.55 V, the input
voltage would have to recover above VUVLO in less than 5 ms for the device to remain active.

TPS65218D0
If the slew rate of the IN_BIAS voltage is less than 30 V/s, then TPS65218D0 will power up at VULVO +
VHYS. Once the input voltage rises above this level, the input voltage may drop to the VUVLO level before
the PMIC shuts down. In this scenario, if the input voltage were to fall below VUVLO but above 2.5 V, the
input voltage would have to recover above VUVLO + VHYS in less than 5 ms for the device to remain active.
In either slew rate scenario, if the input voltage were to fall below 2.5 V, the digital core is reset and all
remaining power rails are shut down instantaneously and are pulled low to ground by their internal
discharge circuitry (DCDC1-4, and LDO1).
UVLO hysteresis
UVLO threshold, supply falling
< 5 ms
VIN_BIAS
UVLO active
UVLO (internal signal)
UVLO inactive
> 5-ms
deglitch
Figure 5-15. Definition of UVLO and Hysteresis
After the UVLO triggers, the internal LDO blocks current flow from its output capacitor back to the IN_BIAS
pin, allowing the digital core and the discharge circuits to remain powered for a limited amount of time to
properly shut-down and discharge the output rails. The hold-up time is determined by the value of the
capacitor connected to INT_LDO. See Section 5.3.1.6 for more details.

TPS65218D0
5.3.1.11 Power-Fail Comparator

The power-fail comparator notifies the system host if the system supply voltage drops and the system is at
risk of shutting down. The comparator has an internal 800-mV threshold and the trip-point is adjusted by
an external resistor divider.
By default, the power-fail comparator has no impact on any of the power rails or load switches. Load
switches are configured individually, to be disabled when the PFI comparator trips to shed system load
and extend hold-up time as described in Section 5.3.1.7. The power-fail comparator also triggers the
power-down sequencer, such that all or selective rails power down when the system voltage fails. To tie
the power-fail comparator into the power-down sequence, the OFFnPFO bit in the CONTROL register
must be set to 1.
The power-fail comparator cannot be monitored by software, such that no interrupt or status bit is
associated to this function.
System supply voltage

nPFO
PFI
+
Deglitch
VREF ±
(800 mV)
PFI hysteresis
PFI threshold, supply falling
<25 µs
VPFI
nPFO inactive
nPFO (pin)
nPFO active
10-ms deglitch 25-µs deglitch
Figure 5-16. Power-Fail Comparator Simplified Circuit and Timing Diagram

TPS65218D0
5.3.1.12 Battery-Backup Supply Power-Path

DCDC5 and DCDC6 are supplied from either the CC (coin-cell battery) input or IN_BU (main system
supply). The power-path is designed to prioritize IN_BU to maximize coin-cell battery life. Whenever the
PMIC is powered-up (WAIT_PWR_EN, ACTIVE, SUSPEND, RECOVERY state), the power-path is forced
to select the IN_BU input. In OFF mode the power-path selects the higher of the two inputs with a built-in
hysteresis of 150 mV as shown in Figure 5-17.
VIN_BU
VSYS_BU
VIN_BU,
VSYS_BU VSYS_BU
VINT_LDO
VCC VCC
150 mV
VINT_LDO = 2.5 V
VnPUC = 2.3 V
0V
VCC VIN_BU ACTIVE STATE OFF STATE, FSEAL = 1b
Rapid decay of VIN_BIAS (preregulator)

Figure 5-17. Switching Behavior of the Battery- Figure 5-18. Switching Behavior of the Battery-
Backup-Supply Power-Path; Backup-Supply Power-Path;
Power-Path Hysteresis Main Power Supply Removal
VIN_BU VIN_BU
VSYS_BU VSYS_BU
VINT_LDO VINT_LDO
VUVLO + VHYST VUVLO + VHYST
VCC VINT_LDO = 2.5 V

VnPUC = 2.3 V
VINT_LDO = 2.5 V VCC = 2.2 V
VnPUC = 2.3 V VIN_BU = 2.05 V
ACTIVE STATE OFF STATE, FSEAL = 1b ACTIVE STATE OFF STATE, FSEAL = 1b
(VIN_BIAS slow decay) VIN_BIAS slow decay

Figure 5-19. Switching Behavior of the Battery- Figure 5-20. Switching Behavior of the Battery-
Backup-Supply Power-Path; Backup-Supply Power-Path;
Weakening Main Battery, Strong Coin-Cell Weakening Main Battery, Weak Coin-Cell
When VIN_BIAS drops below the UVLO threshold, the PMIC shuts down all rails and enters OFF mode. At
this point the power-path selects the higher of the two input supplies. If the coin-cell battery is less than
150 mV above the UVLO threshold, SYS_BU remains connected to IN_BU (see Figure 5-19). If the coin-
cell is >150 mV above the UVLO threshold, the power-path switches to the CC input as shown in
Figure 5-20. With no load on the main supply, the input voltage may recover over time to a value greater
than the coin-cell voltage and the power-path switches back to IN_BU. This is a typical behavior in a Li-Ion
battery powered system.
Depending on the system load, VIN_BIAS may drop below VINT_LDO before the power-down sequence is
completed. In that case, INT_LDO is turned OFF and the digital core is reset forcing the unit into OFF
mode and the power-path switches to IN_BU as shown in Figure 5-18.

TPS65218D0
5.3.1.13 DCDC3 / DCDC4 Power-Up Default Selection
INT_LDO
SOURCE ENABLE
DC34_SEL current source disabled. 10 µA
All comparators disabled.
DC34_SEL
+ V6
Sequence is triggered by any 1200 mV ±
RSEL
event forcing register reset
+
Enable 10 µA DC34_SEL current source. V5
Enable comparators. 825 mV ±
+
V4
Wait 100 µs
575 mV ±
DCDC3[5:0]
LOGIC CORE
+ V3
Latch comparator outputs; 400 mV ± DCDC4[5:0]
Depending on result, over-write
DCDC3[5:0] and / or DCDC4[5:0]
power-up default.
+
V2
275 mV ±
Disable comparators
+
Disable DC34_SEL current source. V1
163 mV ±
+ V0
Start power-up sequencer
100 mV ±
Figure 5-21. Left: Flow Chart for Selecting DCDC Power-Up Default Voltage
Right: Comparator Circuit
Table 5-2. Power-Up Default Values of DCDC3 and DCDC4

RSEL [KΩ] POWER-UP DEFAULT
MIN TYP MAX DCDC3[5:0] DCDC4[5:0]
0 0 7.7 Programmed default (1.2 V) Programmed default (3.3 V)
11.8 12.1 12.4 0x12 (1.35 V) Programmed default (3.3 V)
19.5 20 20.5 0x18 (1.5 V) Programmed default (3.3 V)
30.9 31.6 32.3 0x1F (1.8 V) Programmed default (3.3 V)
44.4 45.3 46.3 0x3D (3.3 V) 0x01 (1.2 V)
64.8 66.1 67.3 Programmed default (1.2 V) 0x07 (1.35 V)
93.6 95.3 97.2 Programmed default (1.2 V) 0x0D (1.5 V)
Tied to
146 150 Programmed default (1.2 V) 0x14 (1.8 V)
INT_LDO

TPS65218D0
5.3.1.14 I/O Configuration

The device has two GPIOs and one GPO pin which are configured as follows:
• GPIO1:
– General-purpose, open-drain output controlled by GPO1 user bit or sequencer
– DDR3 reset input signal from SOC. Signal is either latched or pass-through to GPO2 pin. See
Table 5-3 for details.
• GPO2:
– General-purpose output controlled by GPO2 user bit
– DDR3 reset output signal. Signal is controlled by GPIO1 and PGOOD. See Table 5-4 for details.
– Output buffer is configured as open-drain or push-pull.
• GPIO3:
– General-purpose, open-drain output controlled by GPO3 user bit or sequencer
– Reset input-signal for DCDC1 and DCDC2
Table 5-3. GPIO1 Configuration

IO1_SEL GPO1 PGOOD GPIO1
COMMENTS
(EEPROM) (USER BIT) (PMIC SIGNAL) (I/O PIN)
0 0 X 0 Open-drain output, driving low
0 1 X HiZ Open-drain output, HiZ
Pin is configured as input and intended as DDR RESET
signal. Coming out of POR, GPO2 is driven low. Otherwise,
1 X 0 X
GPO2 status is latched at falling edge of PGOOD. See
Figure 5-24.
1 X 1 0
signal. GPO2 is driven low.
1 X 1 1
signal. GPO2 is driven high.
Table 5-4. GPO2 Configuration

IO1_SEL GPO2_BUF GPO2
COMMENTS
(EEPROM) (EEPROM) (USER BIT)
0 0 0 GPO2 is open drain output controlled by GPO2 user bit (driving low).
0 0 1 GPO2 is open drain output controlled by GPO2 user bit (HiZ).
0 1 0 GPO2 is push-pull output controlled by GPO2 user bit (driving low).
0 1 1 GPO2 is push-pull output controlled by GPO2 user bit (driving high).
1 0 X GPO2 is open drain output controlled by GPIO1/PGOOD.
1 1 X GPO2 is push-pull output controlled by GPIO1/PGOOD.
Table 5-5. GPIO3 Configuration

DC12_RST GPO3 GPIO3
COMMENTS
(EEPROM) (USER BIT) (I/O PIN)
0 0 0 Open-drain output, driving low
0 1 HiZ Open-drain output, HiZ
GPIO3 is DCDC1 and DCDC2 reset input signal to PMIC (active low). See
1 X Active low
Section 5.3.1.14.2 for details.

TPS65218D0
5.3.1.14.1 Configuring GPO2 as Open-Drain Output

GPO2 may be configured as open-drain or push-pull output. The supply for the push-pull driver is
internally connected to the IN_LS1 input pin, whereas an external pullup resistor and supply are required
in the open-drain configuration. Because of the internal connection to IN_LS1, the external pullup supply
must not exceed the voltage on the IN_LS1 pin, otherwise leakage current may be observed from GPO2
to IN_LS1 as shown in Figure 5-22.
IN_LS1 External
pullup supply
Leakage path if external

pullup supply is > IN_LS1
GPO2
Push-Pull
Driver
Open-Drain
Driver
Figure 5-22. GPO2 as Open-Drain Output
NOTE
When configured as open-drain output, the external pullup supply must not exceed the
voltage level on IN_LS1 pin.
5.3.1.14.2 Using GPIO3 as Reset Signal to DCDC1 and DCDC2

With the DC12_RST bit set to 1, GPIO3 is an edge-sensitive reset input to the PMIC. The reset signal
affects DCDC1 and DCDC2 only, so that only those two registers are reset to the power-up default
whenever GPIO3 input transitions from high to low, while all other registers maintain their current values.
DCDC1 and DCDC2 transition back to the default value following the SLEW settings, and are not power
cycled. This function recovers the processor from reset events while in low-power mode.

TPS65218D0
PGOOD (1ms delayed)
GPIO1 Latch,
Gating
IO1_SEL (EEPROM: 0b = output, 1b = input)

GPO1 (user register bit / sequencer control enabled)
IN_LS1 GPO2_BUF (EEPROM: 0b = open drain, 1b = push-pull)
GPO2 EN
1
0 GPO2 (user register bit)
DC12_RST (EEPROM: 0b = disabled, 1b = enabled)
GPIO3
DCDC1/2 reset
GPO3 (user register bit, sequencer control enabled)
Figure 5-23. I/O Pin Logic
PMIC power-up
PGOOD
GPIO1 (DDR_RESET_IN)
(coming from SOC)
1 ms 1 ms
GPO2 (DDR_RESET_OUT)
RESET_OUT follows RESET_IN RESET_IN is latched RESET_OUT follows RESET_IN
(going to DDR memory)
Figure 5-24. DDR3 Reset Timing Diagram
NOTE
GPIO must be configured as input (IO1_SEL = 1b). GPO2 is automatically configured as
output.

TPS65218D0
5.3.1.15 Push Button Input (PB)

The PB pin is a CMOS-type input used to power-up the PMIC. Typically, the PB pin is connected to a
momentary switch to ground and an external pullup resistor. The power-up sequence is triggered if the PB
input is held low for 600 ms.
<100 ms
System Power PB pin (input)

(5.5 V)
Push 100 ms
Button 50 ms
100 k PB deglitched
PB
(internal signal)
550 ms
Power-up event
(internal signal)
Figure 5-25. Left: Typical PB Input Circuit

Right: Push-Button Input (PB) Deglitch and Power-Up Timing
In ACTIVE mode, the TPS65218D0 monitors the PB input and issues an interrupt when the pin status
changes, such as when it drops below or rises above the PB input-low or input-high thresholds. The
interrupt is masked by the PBM bit in the INT_MASK1 register.

TPS65218D0
PB is released before
PB is pressed, INT PB is released. PB is pressed, INT
INT register is read
pin is pulled low, INT pin is pulled pin is pulled low,
through I2C. INT pin
PB_STATE bit is low, PB_STATE bit PB_STATE bit is
remains low,
set is reset. set
PB_STATE bit is reset
PB pin
(50-ms deglitched input)
nWAKEUP
150 µs
PB interrupt bit
INT pin (output)
PB_STATE bit
I2C access to INT register
INT register is read INT register is read INT register is read

through I2C while PB through I2C. INT pin is through I2C.
remains pressed. INT released.
pin is released,
PB_STATE bit remains
set.
Figure 5-26. PB Input-Low or Input-High Thresholds
NOTE
Interrupts are issued whenever the PB pin status changes. The PB_STATE bit reflects the
current status of the PB input. nWAKEUP is pulled low for 150 µs on every falling edge of
PB.

TPS65218D0
5.3.1.15.1 Signaling PB-Low Event on the nWAKEUP Pin

In ACTIVE state, the nWAKEUP pin is pulled low for five 32-kHz clock cycles (approximately 150 µs)
whenever a falling edge on the PB input is detected. This allows the host processor to wakeup from DEEP
SLEEP mode of operation. It is recommended to pull-up the nWAKEUP pin to DCDC6 output through a 1-
MΩ resistor.
5.3.1.15.2 Push Button Reset

If the PB input is pulled low for 8 s (15 s if TRST = 1b) or longer, all rails except for DCDC5 and DCDC6
are disabled, and the device enters the RECOVERY state. The device powers up automatically after the
500 ms power-down sequence is complete, regardless of the state of the PB input. Holding the PB pin low
for 8 s (15 s if TRST = 1b), only turns off the device temporarily and forces a system restart, and is not a
power-down function. If the PB is held low continuously, the device power-cycles in 8-s and 15-s intervals.
5.3.1.16 AC_DET Input (AC_DET)

The AC_DET pin is a CMOS-type input used in three different ways to control the power-up of the PMIC:
• In a battery operated system, AC_DET is typically connected to an external battery charger with an
open-drain power-good output pulled low when a valid charger supply is connected to the system. A
falling edge on the AC_DET pin causes the PMIC to power up.
• In a non-portable system, the AC_DET pin may be shorted to ground and the IC powers up whenever
system power is applied to the chip.
• If none of the above behaviors are desired, AC_DET may be tied to system power (IN_BIAS). Power-
up is then controlled through the push-button input or PWR_EN input.
System Power System Power

(5.5 V) (5.5 V)
100 k
AC_DET AC_DET AC_DET
(A) (B) (C)

A. Portable Systems
B. Non-portable Systems
C. Disabled
Figure 5-27. AC_DET Pin Configurations
<100 ms
AC_DET pin
(input)
100 ms
10 ms
AC_DET
deglitched
(internal signal)
Power-up event
(internal signal)
Figure 5-28. AC_DET Input Deglitch and Power-Up Timing (Portable Systems)

TPS65218D0
In ACTIVE state, the TPS65218D0 monitors the AC_DET input and issues an interrupt when the pin
status changes, such as when it drops below or rises above the AC_DET input-low or input-high
thresholds. The interrupt is masked by the ACM bit in the INT_MASK1 register.
AC goes high before

AC goes low, INT AC goes high. INT AC goes low, INT
INT register is read
pin is pulled low, pin is pulled low, pin is pulled low,
through I2C. INT pin
PC_STATE bit is AC_STATE bit is AC_STATE bit is
remains low,
set reset. set
AC_STATE bit is reset
AC_DET pin
(10-ms deglitched input)
AC interrupt bit
INT pin (output)
AC_STATE bit
I2C access to INT register
INT register is read INT register is read INT register is read

through I2C while AC through I2C. INT pin is through I2C.
remains low. INT pin is released.
released, AC_STATE bit
remains set.
Figure 5-29. AC_STATE Pin
NOTE
Interrupts are issued whenever the AC_DET pin status changes. The AC_STATE bit reflects
the current status of the AC_DET input.
5.3.1.17 Interrupt Pin (INT)

The interrupt pin signals any event or fault condition to the host processor. Whenever a fault or event
occurs in the IC, the corresponding interrupt bit is set in the INT register, and the open-drain output is
pulled low. The INT pin is released (returns to Hi-Z state) and fault bits are cleared when the host reads
the INT register. If a failure persists, the corresponding INT bit remains set and the INT pin is pulled low
again after a maximum of 32 µs.
The MASK register masks events from generating interrupts. The MASK settings affect the INT pin only,
and have no impact on the protection and monitor circuits.

TPS65218D0
5.3.1.18 I2C Bus Operation

The TPS65218D0 hosts a slave I2C interface (address 0x24) that supports data rates up to 400kbps, auto-
increment addressing. (1)
Slave Address + R/nW Register Address Data
S A6 A5 A4 A3 A2 A1 A0 R/nW A S7 S6 S5 S4 S3 S2 S1 S0 A D7 D6 D5 D4 D3 D2 D1 D0 A P
S Start Condition A Acknowledge A6 ... A0 Device Address D7 ... D0 Data
R/nW Read, Not Write P Stop Condition S7 ... S0 Subaddress
Figure 5-30. Subaddress in I2C Transmission
The I2C bus is a communications link between a controller and a series of slave terminals. The link is
established using a two-wired bus consisting of a serial clock signal (SCL) and a serial data signal (SDA).
The serial clock is sourced from the controller in all cases where the serial data line is bi-directional for
data communication between the controller and the slave terminals. Each device has an open drain output
to transmit data on the serial data line. An external pullup resistor must be placed on the serial data line to
pull the drain output high during data transmission.
Data transmission initiates with a start bit from the controller as shown in Figure 5-32. The start condition
is recognized when the SDA line transitions from high to low during the high portion of the SCL signal.
Upon reception of a start bit, the device receives serial data on the SDA input and checks for valid
address and control information. If the appropriate slave address is set for the device, the device issues
an acknowledge pulse and prepares to receive register address and data. Data transmission is completed
by either the reception of a stop condition or the reception of the data word sent to the device. A stop
condition is recognized as a low to high transition of the SDA input during the high portion of the SCL
signal. All other transitions of the SDA line must occur during the low portion of the SCL signal. An
acknowledge issues after the reception of valid slave address, register-address, and data words. The I2C
interfaces auto-sequence through register addresses, so that multiple data words can be sent for a given
I2C transmission. Reference Figure 5-31 and Figure 5-32 for details.
S SLAVE ADDRESS W A REGISTER ADDRESS A DATAREGADDR A
DATASUBADDR+n A DATASUBADDR+n+1 A P
n bytes + ACK
S SLAVE ADDRESS W A REGISTER ADDRESS A S SLAVE ADDRESS R A DATAREGADDR A
DATAREGADDR+n A DATAREGADDR+n+1 A P
n bytes + ACK
From master to slave R Read (high) S Start A Not Acknowledge
From slave to master W Write (low) P Stop A Acknowledge

Top: Master Writes Data to Slave
Bottom: Master Reads Data from Slave
Figure 5-31. I2C Data Protocol
(1) Note: The SCL duty cycle at 400 kHz must be >40%.
TPS65218D0
SDA
SCL 1-7 8 9 1-7 8 9 1-7 8 9
S P
START ADDRESS R/W ACK DATA ACK DATA ACK/nACK STOP

2
Figure 5-32. I C Protocol and Transmission Timing;
I2C Start/Stop/Acknowledge Protocol
SDA
tf tLOW tr tSU;DAT tHD;STA tSP tr tBUF
SCL
tHD;STA tSU;STA tSU;STO tf

tHD;DAT tHIGH
S Sr P S
2
Figure 5-33. I C Protocol and Transmission Timing;
I2C Data Transmission Timing

TPS65218D0
5.4 Device Functional Modes
5.4.1 Modes of Operation

External power and
ANY STATE NO POWER Coin Cell removed ANY STATE
FSEAL :0
VIN_BIAS < VUVLO || PB low for > 8 s ||

(OFFnPFO = 1 & VPFI < power-fail threshold) OTS ||
PGOOD fault
SEQ DOWN SEQ DOWN

VIN_BIAS > (VUVLO + hysteresis)
(500 ms) (500 ms)
DCDC1..4 = OFF VIN_BIAS > (VUVLO + hysteresis) & DCDC1..4 = OFF

DCDC5..6 = FSEAL dependent PB = high & DCDC5..6 = FSEAL dependent
LDO1 = OFF AC_DET = high & LDO1 = OFF DCDC1..4 = OFF
INT_LDO = ON PWR_EN = low INT_LDO = OFF DCDC5..6 = FSEAL dependent
OTS
I2C = NO PRE_OFF OFF I 2C = NO LDO1 = OFF
PGOOD = low PGOOD = low INT_LDO = ON
PGOOD_BU = rail dependent PGOOD_BU = rail dependent I 2C = NO
RECOVERY PGOOD = low
nWAKEUP = low nWAKEUP = low
VIN_BIAS > (VUVLO + hysteresis) & Registers : GHIDXOW PGOOD_BU = high
Registers : GHIDXOW
(PB (;) || AC_DET (;) || nWAKEUP = HiZ
PWR_EN = high) FSEAL = maintains state
Registers : GHIDXOW
VIN_BIAS > (VUVLO + hysteresis) & DCDC1..4 = ON

(PB (;) || DCDC5..6 = ON
AC_DET (;) || LDO1 = ON
PWR_EN = high) INT_LDO = ON
WAIT_PWR_EN I2C = YES
PGOOD = high (rail dependent)
PGOOD_BU = high (rail dependent)
FSEAL = can be set to 1 but not to 0
nWAKEUP = low
PWR_EN = high
20 s time-out & DCDC1..4 = ON
PB = high & DCDC5..6 = ON
PWR_EN = low LDO1 = ON
INT_LDO = ON
ACTIVE I2C = YES
PGOOD = high (rail dependent)
PWR_EN = low FSEAL = can be set to 1 but not to 0
nWAKEUP = HiZ
DCDC1..4 = OFF &

LDO1 = OFF SEQ DOWN
(500 ms)
DCDC1 = ON || DCDC2 = ON ||
DCDC3 = ON || DCDC4 = ON ||
LDO1 = ON DCDC1..4 = seq. dependent
DCDC5..6 = seq. / FSEAL dependent
LDO1 = seq. dependent
INT_LDO = ON
I2C = YES
SUSPEND
PGOOD = low
nWAKEUP = HiZ
PWR_EN = high || DCDC1 reg. : GHIDXOW
AC_DET (;) || DCDC2 reg. : GHIDXOW
PB (;)
PB (↓) has 50 ms debounce.

AC_DET (↓) has 10 ms debounce.
(↓) = denotes falling edge of signal.
Figure 5-34. Modes of Operation Diagram
5.4.2 OFF
In OFF mode, the PMIC is completely shut down with the exception of a few circuits to monitor the
AC_DET, PWR_EN and PB input. All power rails are turned off and the registers are reset to their default
values. The I2C communication interface is turned off. This is the lowest-power mode of operation. To exit
OFF mode VIN_BIAS must exceed the UVLO threshold and one of the following wake-up events must occur:
• The PB input is pulled low.
• THE AC_DET input is pulled low.
• The PWR_EN input is pulled high.
TPS65218D0
To enter OFF state, ensure all power rails are assigned to e sequencer, then pull the PWR_EN pin low.
Additionally, if the OFFnPFO bit is set to 1b and the PFI input falls below the power fail threshold the
device transitions to the OFF state. If the freshness seal is broken, DCDC5 and DCDC6 remains on in the
OFF state.
If a PGOOD or OTS fault occurs while in the ACTIVE state, TPS65218D0 will transition to the RESET
state.
5.4.3 ACTIVE
This is the typical mode of operation when the system is up and running. All DCDC converters, LDOs, and
load switches are operational and can be controlled through the I2C interface. After a wake-up event, the
PMIC enables all rails controlled by the sequencer and pulls the nWAKEUP pin low to signal the event to
the host processor. The device only enters ACTIVE state if the host asserts the PWR_EN pin within 20 s
after the wake-up event. Otherwise it will enter OFF state. The nWAKEUP pin returns to HiZ mode after
the PWR_EN pin is asserted. ACTIVE state can also be directly entered from SUSPEND state by pulling
the PWR_EN pin high. See SUSPEND state description for details. To exit ACTIVE mode, the PWR_EN
pin must be pulled low.
5.4.4 SUSPEND
SUSPEND state is a low-power mode of operation intended to support system standby. Typically all
power rails are turned off with the exception of any rail with an SEQ register set to 0h. DCDC5 and
DCDC6 also remain enabled if the freshness seal is broken. To enter SUSPEND state, pull the PWR_EN
pin low. All power rails controlled by the power-down sequencer are shut down, and after 500 ms the
device enters SUSPEND state. All rails not controlled by the power-down sequencer will maintain state.
Note that all register values are reset as the device enters the SUSPEND state. The device enters
ACTIVE state after it detects a wake-up event as described in the previous sections.
5.4.5 RESET
The TPS65218D0 can be reset by holding the PB pin low for more than 8 or 15 s, depending on the value
of the TRST bit. All rails are shut down by the sequencer and all register values reset to their default
values. Rails not controlled by the sequencer are shut down additionally. Note that the RESET function
power-cycles the device and only temporarily shuts down the output rails. Resetting the device does not
lead to OFF state. If the PB_IN pin is kept low for an extended amount of time, the device continues to
cycle between ACTIVE and RESET state, entering RESET every 8 or 15 s.
The device is also reset if a PGOOD or OTS fault occurs. The TPS65218D0 remains in the recovery state
until the fault is removed, at which time it transitions back to the ACTIVE state.
5.5 Programming
5.5.1 Programming Power-Up Default Values

A consecutive write of 0x50, 0x1A, or 0xCE to the password register commits the current register settings
to EEPROM memory so they become the new power-up default values.
NOTE
Only bits marked with (E2) in the register map have EEPROM programmable power-up
default settings. All other bits keep the factory settings listed in the register map. Changing
the power-up default values is not recommended in production but for prototyping only.
The EEPROM of a device can only be programmed up to 1000 times. The number of programming cycles
should never exceed this amount. Contact TI for changing production settings.

TPS65218D0
EEPROM values can only be changed if the input voltage (VIN_BIAS) is greater than 4.5 V. If the input
voltage is less than 4.5 V, EEPROM values remain unchanged and the VPROG interrupt is issued.
EEPROM programming requires less than 100 ms. During this time the supply voltage must be held
constant and all I2C write commands are ignored. Completion of EEPROM programming is signaled by
the EE_CMPL interrupt.
Program EEPROM Registers
IDLE
0x50, 0x1A, 0xCE written to the PASSWORD register
Check supply voltage

VIN_BIAS ” 4.5 V
(VIN_BIAS)
VIN_BIAS > 4.5 V
Lock I2C Interface for write

access
INT_LDO output
adjusted to 3.6 V
< 100 ms
Program EEPROM
EE bit permanently set to 1b
INT_LDO output
adjusted to 2.5 V
Unlock I2C Interface
Issue PRGC Interrupt Issue PRGC Interrupt
Figure 5-35. Flow Chart for Programming New Power-Up Default Values
NOTE
All re-programmed EEPROM settings must be validated during prototyping phase to ensure
desired functionality because parts cannot be returned in case of incorrect programming. Any
issues should be reported to the e2e forum.

TPS65218D0
5.6 Register Maps
5.6.1 Password Protection

Registers 0x11h through 0x26h are protected against accidental write by a 8-bit password. The password
must be written prior to writing to a protected register and automatically resets to 0x00h after the next I2C
transaction, regardless of the register accessed or transaction type (read or write). The password is
required for write access only and is not required for read access.
To write to a protected register:
1. Write the address of the destination register, XORed with the protection password (0x7Dh), to the
PASSWORD register (0x10h).
2. Write the data to the password protected register.
3. If the content of the PASSWORD register XORed with the address send matches 0x7Dh, the data
transfers to the protected register. Otherwise, the transaction is ignored. In either case the
PASSWORD register resets to 0x00 after the transaction.
The cycle must be repeated for any other register that is Level1 write protected.
5.6.2 Freshness Seal (FSEAL) Bit

The FSEAL (freshness seal) bit prevents accidental shut-down of the always-on supplies, DCDC5 and
DCDC6. The FSEAL bit exists in a default state of 0, and can be set to 1 and reset to 0 once for factory
testing. The second time the bit is set to 1, it remains 1 and cannot reset again under software control.
Coin-cell battery and main supply must be disconnected from the IC to reset the FSEAL bit again. With
the FSEAL bit set to 1, DCDC5 and DCDC6 are forced ON regardless of the state of the DC5_EN and
DC6_EN bit, and the rails do not turn off when the IC enters OFF mode.
A consecutive write of [0xB1, 0xFE, 0xA3] to the password register sets the FSEAL bit to 1. The three
bytes must be written consecutively for the sequence to be valid. No other read or write transactions are
allowed between the three bytes, or the sequence is invalid. After a valid sequence, the FSEAL bit in the
STATUS register reflects the new setting.
After setting the FSEAL bit, the IC can enter OFF or any other mode of operation without affecting the
state of the FSEAL bit, provided the coin-cell supply remains connected to the chip.
A second write of [0xB1, 0xFE, 0xA3] to the password register resets the FSEAL bit to 0. The three bytes
must be written consecutively for the sequence to be valid.
A third write of [0xB1, 0xFE, 0xA3] to the password register sets the FSEAL bit to 1 and locks it into this
state for as long as the coin-cell supply (CC) remains connected to the chip.
5.6.3 FLAG Register

The FLAG register contains a bit for each power rail and GPO to keep track of the enable state of the rails
while the system is suspended. The following rules apply to the FLAG register:
• The power-up default value for any flag bit is 0.
• Flag bits are read-only and cannot be written to.
• Upon entering a SUSPEND state, the flag bits are set to same value as their corresponding ENABLE
bits. Rails and GPOs enabled in a SUSPEND state have flag bits set to 1, while all other flag bits are
set to 0. Flag bits are not updated while in the SUSPEND state or when exiting the SUSPEND state.
• The FLAG register is static in WAIT_PWR_EN and ACTIVE state. The FLAG register reflects the
enable state of DCDC1, 2, 3, 4, LDO1, and GPO1, 2, 3 during the last SUSPEND state.
The host processor reads the FLAG register to determine if the system powered up from the OFF or
SUSPEND state. In the SUSPEND state, typically the DDR memory is kept in self refresh mode and
therefore the DC3_FLG or DC4_FLG bits are set.

TPS65218D0
5.6.4 TPS65218D0 Registers

Table 5-6 lists the memory-mapped registers for the TPS65218D0. All register offset addresses not listed
in Table 5-6 should be considered as reserved locations and the register contents should not be modified.
Table 5-6. TPS65218D0 Registers

PASSWORD
SUBADDRESS ACRONYM REGISTER NAME R/W SECTION
PROTECTED
0x0 CHIPID CHIP ID R No Go
0x1 INT1 INTERRUPT 1 R No Go
0x2 INT2 INTERRUPT 2 R No Go
0x3 INT_MASK1 INTERRUPT MASK 1 R/W No Go
0x4 INT_MASK2 INTERRUPT MASK 2 R/W No Go
0x5 STATUS STATUS R No Go
0x6 CONTROL CONTROL R/W No Go
0x7 FLAG FLAG R No Go
0x10 PASSWORD PASSWORD R/W No Go
0x11 ENABLE1 ENABLE 1 R/W Yes Go
0x12 ENABLE2 ENABLE 2 R/W Yes Go
0x13 CONFIG1 CONFIGURATION 1 R/W Yes Go
0x16 DCDC1 DCDC1 CONTROL R/W Yes Go
0x1A SLEW SLEW RATE CONTROL R/W Yes Go
0x1B LDO1 LDO1 CONTROL R/W Yes Go
0x20 SEQ1 SEQUENCER 1 R/W Yes Go
Table 5-7 explains the common abbreviations used in this section.
Table 5-7. Common Abbreviations

Abbreviation Description
R Read
W Write
R/W Read and write capable
E2 Backed by EEPROM
h Hexadecimal notation of a group of bits
b Hexadecimal notation of a bit or group of bits
X Don't care reset value

TPS65218D0
5.6.4.1 CHIPID Register (subaddress = 0x0) [reset = 0x5]

CHIPID is shown in Figure 5-36 and described in Table 5-8.
Return to Summary Table.
Figure 5-36. CHIPID Register

7 6 5 4 3 2 1 0
CHIP REV
R-0h R-5h
Table 5-8. CHIPID Register Field Descriptions

Bit Field Type Reset Description
7-3 CHIP R 0h
Chip ID
0h = TPS65218D0
1h = Future use
...
1Fh = Future use
2-0 REV R 5h
Revision code
0h = Revision 1.0
1h = Revision 1.1
2h = Revision 2.0
3h = Revision 2.1
4h = Revision 3.0
5h = Revision 4.0 (D0)
6h = Future use
7h = Future use

TPS65218D0
5.6.4.2 INT1 Register (subaddress = 0x1) [reset = 0x0]

INT1 is shown in Figure 5-37 and described in Table 5-9.
Figure 5-37. INT1 Register

7 6 5 4 3 2 1 0
RESERVED VPRG AC PB HOT CC_AQC PRGC
R-0h R-0b R-0b R-0b R-0b R-0b R-0b
Table 5-9. INT1 Register Field Descriptions

7-6 RESERVED R 0h
5 VPRG R 0b
Programming voltage interrupt
0b = No significance
1b = Input voltage is too low for programming power-up default
values.
4 AC R 0b
AC_DET pin status change interrupt. Note: Status information is
available in STATUS register
0b = No change in status
1b = AC_DET status change (AC_DET pin changed high to low or
low to high)
3 PB R 0b
Push-button status change interrupt. Note: Status information is
0b = No change in status
1b = Push-button status change (PB changed high to low or low to
high)
2 HOT R 0b
Thermal shutdown early warning
0b = Chip temperature is below HOT threshold
1b = Chip temperature exceeds HOT threshold
1 CC_AQC R 0b
Coin cell battery voltage acquisition complete interrupt
1b = Backup battery status comparators have settled and results are
0 PRGC R 0b
EEPROM programming complete interrupt
1b = Programming of power-up default settings has completed
successfully

TPS65218D0
5.6.4.3 INT2 Register (subaddress = 0x2) [reset = 0x0]

INT2 is shown in Figure 5-38 and described in Table 5-10.
Figure 5-38. INT2 Register

7 6 5 4 3 2 1 0
RESERVED LS3_F LS2_F LS1_F LS3_I LS2_I LS1_I
R-0h R-0b R-0b R-0b R-0b R-0b R-0b
Table 5-10. INT2 Register Field Descriptions

7-6 RESERVED R 0h
5 LS3_F R 0b
Load switch 3 fault interrupt
0b = No fault. Switch is working normally.
1b = Load switch exceeded operating temperature limit and is
temporarily disabled.
4 LS2_F R 0b
1b = Load switch exceeded operating temperature limit or input
voltage dropped below minimum value. Switch is temporarily
disabled.
3 LS1_F R 0b
1b = Load switch exceeded operating temperature limit and is
temporarily disabled.
2 LS3_I R 0b
Load switch 3 current-limit interrupt
0b = Load switch is disabled or not in current limit
1b = Load switch is actively limiting the output current (output load is
exceeding current limit value)
1 LS2_I R 0b
0 LS1_I R 0b

TPS65218D0
5.6.4.4 INT_MASK1 Register (subaddress = 0x3) [reset = 0x0]

INT_MASK1 is shown in Figure 5-39 and described in Table 5-11.
Figure 5-39. INT_MASK1 Register

7 6 5 4 3 2 1 0
RESERVED VPRGM ACM PBM HOTM CC_AQCM PRGCM
R-0h R/W-0b R/W-0b R/W-0b R/W-0b R/W-0b R/W-0b
Table 5-11. INT_MASK1 Register Field Descriptions

7-6 RESERVED R 0h
5 VPRGM R/W 0b
Programming voltage interrupt mask bit. Note: mask bit has no effect
on monitoring function
0b = Interrupt is unmasked (interrupt event pulls nINT pin low)
1b = Interrupt is masked (interrupt has no effect on nINT pin)
4 ACM R/W 0b
AC_DET interrupt masking bit.
Note: mask bit has no effect on monitoring function
3 PBM R/W 0b
PB interrupt masking bit. Note: mask bit has no effect on monitoring
function
2 HOTM R/W 0b
HOT interrupt masking bit. Note: mask bit has no effect on
monitoring function
1 CC_AQCM R/W 0b
C_AQC interrupt masking bit. Note: mask bit has no effect on
monitoring function
0 PRGCM R/W 0b
PRGC interrupt masking bit. Note: mask bit has no effect on
monitoring function

TPS65218D0
5.6.4.5 INT_MASK2 Register (subaddress = 0x4) [reset = 0x0]

INT_MASK2 is shown in Figure 5-40 and described in Table 5-12.
Figure 5-40. INT_MASK2 Register

7 6 5 4 3 2 1 0
RESERVED LS3_FM LS2_FM LS1_FM LS3_IM LS2_IM LS1_IM
Table 5-12. INT_MASK2 Register Field Descriptions

7-6 RESERVED R 0h
5 LS3_FM R/W 0b
LS3 fault interrupt mask bit. Note: mask bit has no effect on
monitoring function
4 LS2_FM R/W 0b
monitoring function
3 LS1_FM R/W 0b
monitoring function
2 LS3_IM R/W 0b
LS3 current-limit interrupt mask bit. Note: mask bit has no effect on
monitoring function
1 LS2_IM R/W 0b
monitoring function
0 LS1_IM R/W 0b
monitoring function

TPS65218D0
5.6.4.6 STATUS Register (subaddress = 0x5) [reset = 00XXXXXXb]

Register mask: C0h
STATUS is shown in Figure 5-41 and described in Table 5-13.
Figure 5-41. STATUS Register

7 6 5 4 3 2 1 0
FSEAL EE AC_STATE PB_STATE STATE CC_STAT
R-0b R-0b R-X R-X R-X R-X
Table 5-13. STATUS Register Field Descriptions

7 FSEAL R 0b
Freshness seal (FSEAL) status. Note: See Section 5.6.2 for details.
0b = FSEAL is in native state (fresh)
1b = FSEAL is broken
6 EE R 0b
EEPROM status
0b = EEPROM values have not been changed from factory default
setting
1b = EEPROM values have been changed from factory default
settings
5 AC_STATE R X
AC_DET input status bit
0b = AC_DET input is inactive (AC_DET input pin is high)
1b = AC_DET input is active (AC_DET input is low)
4 PB_STATE R X
PB input status bit
0b = Push Button input is inactive (PB input pin is high)
1b = Push Button input is active (PB input pin is low)
3-2 STATE R X
State machine STATE indication
0h = PMIC is in transitional state
1h = PMIC is in WAIT_PWR_EN state
2h = PMIC is in ACTIVE state
3h = PMIC is in SUSPEND state
1-0 CC_STAT R X
Coin cell state of charge. Note: Coin-cell voltage acquisition must be
triggered first before status bits are valid. See CC_AQ bit in
Section 5.6.4.7.
0h = VCC < VLOW_LEVEL; Coin cell is not present or approaching end-
of-life (EOL)
1h = VLOW_LEVEL < VCC < VGOOD_LEVEL; Coin cell voltage is LOW.
2h = VGOOD_LEVEL < VCC <VIDEAL_LEVEL; Coin cell voltage is GOOD.
3h = VIDEAL < VCC; Coin cell voltage is IDEAL.

TPS65218D0
5.6.4.7 CONTROL Register (subaddress = 0x6) [reset = 0x0]

CONTROL is shown in Figure 5-42 and described in Table 5-14.
Figure 5-42. CONTROL Register

7 6 5 4 3 2 1 0
RESERVED OFFnPFO CC_AQ
R-0h R/W-0b R/W-0b
Table 5-14. CONTROL Register Field Descriptions

7-2 RESERVED R 0h
1 OFFnPFO R/W 0h
Power-fail shutdown bit
0b = nPFO has no effect on PMIC state
1b = All rails are shut down and PMIC enters OFF state when PFI
comparator trips (nPFO is low)
0 CC_AQ R/W 0h
Coin Cell battery voltage acquisition start bit
1b = Triggers voltage acquisition. Bit is automatically reset to 0.

TPS65218D0
5.6.4.8 FLAG Register (subaddress = 0x7) [reset = 0x0]

FLAG is shown in Figure 5-43 and described in Table 5-15.
Figure 5-43. FLAG Register

7 6 5 4 3 2 1 0
GPO3_FLG GPO2_FLG GPO1_FLG LDO1_FLG DC4_FLG DC3_FLG DC2_FLG DC1_FLG
R-0b R-0b R-0b R-0b R-0b R-0b R-0b R-0b
Table 5-15. FLAG Register Field Descriptions

7 GPO3_FLG R 0b
GPO3 Flag bit
0b = Device powered up from OFF or SUSPEND state and GPO3
was disabled while in SUSPEND.
1b = Device powered up from SUSPEND state and GPO3 was
enabled while in SUSPEND.
6 GPO2_FLG R 0b
GPO2 Flag bit
5 GPO1_FLG R 0b
GPO1 Flag bit
4 LDO1_FLG R 0b
LDO1 Flag bit
0b = Device powered up from OFF or SUSPEND state and LDO1
1b = Device powered up from SUSPEND state and LDO1 was
3 DC4_FLG R 0b
DCDC4 Flag bit
0b = Device powered up from OFF or SUSPEND state and DCDC4
1b = Device powered up from SUSPEND state and DCDC4 was
2 DC3_FLG R 0b
DCDC3 Flag bit
1 DC2_FLG R 0b
DCDC2 Flag bit

TPS65218D0
Table 5-15. FLAG Register Field Descriptions (continued)

0 DC1_FLG R 0b
DCDC1 Flag bit
1b = Device powered up from SUSPEND state and GDCDC1PO3
was enabled while in SUSPEND.
5.6.4.9 PASSWORD Register (subaddress = 0x10) [reset = 0x0]

PASSWORD is shown in Figure 5-44 and described in Table 5-16.
Figure 5-44. PASSWORD Register

7 6 5 4 3 2 1 0
PWRD
R/W-0h
Table 5-16. PASSWORD Register Field Descriptions

7-0 PWRD R/W 0h
Register is used for accessing password protected registers (see
Section 5.6.1 for details). Breaking the freshness seal (see
Section 5.6.2 for details).Programming power-up default values (see
Section 5.5.1 for details). Read-back always yields 0x00.

TPS65218D0
5.6.4.10 ENABLE1 Register (subaddress = 0x11) [reset = 0x0]

ENABLE1 is shown in Figure 5-45 and described in Table 5-17.
Password protected.
Figure 5-45. ENABLE1 Register

7 6 5 4 3 2 1 0
RESERVED DC6_EN DC5_EN DC4_EN DC3_EN DC2_EN DC1_EN
Table 5-17. ENABLE1 Register Field Descriptions

7-6 RESERVED R 0h
5 DC6_EN R/W 0b
DCDC6 enable bit. DCDC6 can only be disabled if FSEAL = 0. See
Section 5.6.2 for details.
0b = Disabled
1b = Enabled
4 DC5_EN R/W 0b
DCDC5 enable bit. Note: At power-up/down this bit is automatically
updated by the internal power sequencer. DCDC5 can only be
disabled if FSEAL = 0. See Section 5.6.2 for details.
0b = Disabled
1b = Enabled
3 DC4_EN R/W 0b
updated by the internal power sequencer.
0b = Disabled
1b = Enabled
2 DC3_EN R/W 0b
0b = Disabled
1b = Enabled
1 DC2_EN R/W 0b
0b = Disabled
1b = Enabled
0 DC1_EN R/W 0b
0b = Disabled
1b = Enabled

TPS65218D0
5.6.4.11 ENABLE2 Register (subaddress = 0x12) [reset = 0x0]

ENABLE2 is shown in Figure 5-46 and described in Table 5-18.
Password protected.
Figure 5-46. ENABLE2 Register

7 6 5 4 3 2 1 0
RESERVED GPIO3 GPIO2 GPIO1 LS3_EN LS2_EN LS1_EN LDO1_EN
R-0b R/W-0b R/W-0b R/W-0b R/W-0b R/W-0b R/W-0b R/W-0b
Table 5-18. ENABLE2 Register Field Descriptions

7 RESERVED R 0b
6 GPIO3 R/W 0b
General purpose output 3 / reset polarity. Note: If DC12_RST bit
(register 0x14) is set to 1 this bit has no function.
0b = GPIO3 output is driven low
1b = GPIO3 output is HiZ
5 GPIO2 R/W 0b
General purpose output 2. Note: If IO_SEL bit (register 0x13) is set
to 1 this bit has no function.
0b = GPO2 output is driven low
1b = GPO2 output is HiZ
4 GPIO1 R/W 0b
General purpose output 1. Note: If IO_SEL bit (register 0x13) is set
to 1 this bit has no function.
0b = GPO1 output is driven low
1b = GPO1 output is HiZ
3 LS3_EN R/W 0b
Load switch 3 (LS3) enable bit
0b = Disabled
1b = Enabled
2 LS2_EN R/W 0b
Load switch 2 (LS2) enable bit
0b = Disabled
1b = Enabled
1 LS1_EN R/W 0b
Load switch 1 (LS1) enable bit.
0b = Disabled
1b = Enabled
Note: At power-up/down this bit is automatically updated by the
internal power sequencer.
0 LDO1_EN R/W 0b
LDO1 enable bit.
0b = Disabled
1b = Enabled
Note: At power-up/down this bit is automatically updated by the
internal power sequencer.

TPS65218D0
5.6.4.12 CONFIG1 Register (subaddress = 0x13) [reset = 0x4C]

CONFIG1 is shown in Figure 5-47 and described in Table 5-19.
Password protected.
Figure 5-47. CONFIG1 Register

7 6 5 4 3 2 1 0
TRST GPO2_BUF IO1_SEL PGDLY STRICT UVLO
R/W-0b R/W-1b R/W-0b R/W-1h R/W-1b R/W-0h
Table 5-19. CONFIG1 Register Field Descriptions

7 TRST R/W, E2 0b
Push-button reset time constant
0b = 8s
1b = 15s
6 GPO2_BUF R/W, E2 1b
GPO2 output buffer configuration
0b = GPO2 buffer is configured as open-drain
1b = GPO2 buffer is configured as push-pull (high-level is driven to
IN_LS1)
5 IO1_SEL R/W, E2 0b
GPIO1 / GPO2 configuration bit. See Section 5.3.1.14 for details.
0b = GPIO1 is configured as general-purpose, open-drain output.
GPO2 is independent output
1b = GPIO1 is configured as input, controlling GPO2. Intended for
DDR3 reset signal control.
4-3 PGDLY R/W, E2 1h
Power-Good delay. Note: Power-good delay applies to rising-edge
only (power-up), not falling edge (power-down or fault)
0h = 10 ms
1h = 20 ms
2h = 50 ms
3h = 150 ms
2 STRICT R/W, E2 1b
Supply Voltage Supervisor Sensitivity selection. See Section 4.5 for
details.
0b = Power-good threshold (VOUT falling) has wider limits.
Overvoltage is not monitored
1b = Power-good threshold (VOUT falling) has tight limits.
Overvoltage is monitored.
1-0 UVLO R/W, E2 0h
UVLO setting
0h = 2.75 V
1h = 2.95 V
2h = 3.25 V
3h = 3.35 V

TPS65218D0
5.6.4.13 CONFIG2 Register (subaddress = 0x14) [reset = 0xC0]

Password protected.

7 6 5 4 3 2 1 0
DC12_RST UVLOHYS RESERVED LS3ILIM LS2ILIM
R/W-1b R/W-1b R-0h R/W-0h R/W-0h

7 DC12_RST R/W 1b, E2
DCDC1 and DCDC2 reset-pin enable
0b = GPIO3 is configured as general-purpose output
1b = GPIO3 is configured as warm-reset input to DCDC1 and DCDC2
6 UVLOHYS R/W 1b, E2
UVLO hysteresis
0b = 200 mV
1b = 400 mV
5-4 RESERVED R 0h
3-2 LS3ILIM R/W 0h
Load switch 3 (LS3) current limit selection
0h = 100 mA, (MIN = 98 mA)
1h = 200 mA, (MIN = 194 mA)
2h = 500 mA, (MIN = 475 mA)
3h = 1000 mA, (MIN = 900 mA)
See the LS3 current limit specification in Section 4.5 for more details.
1-0 LS2ILIM R/W 0h
Load switch 2 (LS2) current limit selection
0h = 100 mA, (MIN = 94 mA)
1h = 200 mA, (MIN = 188 mA)
2h = 500 mA, (MIN = 465 mA)
3h = 1000 mA, (MIN = 922 mA)
See the LS2 current limit specification in Section 4.5 for more details.

TPS65218D0
5.6.4.14 CONFIG3 Register (subaddress = 0x15) [reset = 0x0]

Password protected.

7 6 5 4 3 2 1 0
RESERVED LS3nPFO LS2nPFO LS1nPFO LS3DCHRG LS2DCHRG LS1DCHRG

7-6 RESERVED R 0b
5 LS3nPFO R/W 0b
Load switch 3 power-fail disable bit
0b = Load switch status is not affected by power-fail comparator
1b = Load switch is disabled if power-fail comparator trips (nPFO is
low)
4 LS2nPFO R/W 0b
low)
3 LS1nPFO R/W 0b
low)
2 LS3DCHRG R/W 0b
Load switch 3 discharge enable bit
0b = Active discharge is disabled
1b = Active discharge is enabled (load switch output is actively
discharged when switch is OFF)
1 LS2DCHRG R/W 0b
0 LS1DCHRG R/W 0b

TPS65218D0
5.6.4.15 DCDC1 Register (offset = 0x16) [reset = 0x99]

DCDC1 is shown in Figure 5-50 and described in Table 5-22.
Note 1: This register is password protected. For more information, see Section 5.6.1.
Note 2: A 5-ms blanking time of the overvoltage and undervoltage monitoring occurs when a write is
performed on the DCDC1 register.
Note 3: To change the output voltage of DCDC1, the GO bit or the GODSBL bit must be set to 1b in
register 0x1A.
Figure 5-50. DCDC1 Register

7 6 5 4 3 2 1 0
PFM RESERVED DCDC1
R/W-1b R-0b R/W-19h
Table 5-22. DCDC1 Register Field Descriptions

7 PFM R/W 1b
Pulse Frequency Modulation (PFM, also known as pulse-skip-mode)
enable. PFM mode improves light-load efficiency. Actual PFM mode
operation depends on load condition.
0b = Disabled (forced PWM)
1b = Enabled
6 RESERVED R 0b

TPS65218D0
Table 5-22. DCDC1 Register Field Descriptions (continued)

5-0 DCDC1 R/W, E2 19h
DCDC1 output voltage setting
0h = 0.850
1h = 0.860
2h = 0.870
3h = 0.880
4h = 0.890
5h = 0.900
6h = 0.910
7h = 0.920
8h = 0.930
9h = 0.940
Ah = 0.950
Bh = 0.960
Ch = 0.970
Dh = 0.980
Eh = 0.990
Fh = 1.000
10h = 1.010
11h = 1.020
12h = 1.030
13h = 1.040
14h = 1.050
15h = 1.060
16h = 1.070
17h = 1.080
18h = 1.090
19h = 1.100
1Ah = 1.110
1Bh = 1.120
1Ch = 1.130
1Dh = 1.140
1Eh = 1.150
1Fh = 1.160
20h = 1.170
21h = 1.180
22h = 1.190
23h = 1.200

TPS65218D0

24h = 1.210
25h = 1.220
26h = 1.230
27h = 1.240
28h = 1.250
29h = 1.260
2Ah = 1.270
2Bh = 1.280
2Ch = 1.290
2Dh = 1.300
2Eh = 1.310
2Fh = 1.320
30h = 1.330
31h = 1.340
32h = 1.350
33h = 1.375
34h = 1.400
35h = 1.425
36h = 1.450
37h = 1.475
38h = 1.500
39h = 1.525
3Ah = 1.550
3Bh = 1.575
3Ch = 1.600
3Dh = 1.625
3Eh = 1.650
3Fh = 1.675

TPS65218D0
5.6.4.16 DCDC2 Register (subaddress = 0x17) [reset = 0x99]

Note 3: To change the output voltage of DCDC2, the GO bit or the GODSBL bit must be set to 1b in
register 0x1A.

7 6 5 4 3 2 1 0
PFM RESERVED DCDC2
R/W-1b R-0b R/W-19h

7 PFM R/W 1b
Pulse frequency modulation (PFM, also known as pulse-skip-mode)
1b = Enabled
6 RESERVED R 0b

TPS65218D0

5-0 DCDC2 R/W, E2 19h
0h = 0.850
1h = 0.860
2h = 0.870
3h = 0.880
4h = 0.890
5h = 0.900
6h = 0.910
7h = 0.920
8h = 0.930
9h = 0.940
Ah = 0.950
Bh = 0.960
Ch = 0.970
Dh = 0.980
Eh = 0.990
Fh = 1.000
10h = 1.010
11h = 1.020
12h = 1.030
13h = 1.040
14h = 1.050
15h = 1.060
16h = 1.070
17h = 1.080
18h = 1.090
19h = 1.100
1Ah = 1.110
1Bh = 1.120
1Ch = 1.130
1Dh = 1.140
1Eh = 1.150
1Fh = 1.160
20h = 1.170
21h = 1.180
22h = 1.190
23h = 1.200

TPS65218D0

24h = 1.210
25h = 1.220
26h = 1.230
27h = 1.240
28h = 1.250
29h = 1.260
2Ah = 1.270
2Bh = 1.280
2Ch = 1.290
2Dh = 1.300
2Eh = 1.310
2Fh = 1.320
30h = 1.330
31h = 1.340
32h = 1.350
33h = 1.375
34h = 1.400
35h = 1.425
36h = 1.450
37h = 1.475
38h = 1.500
39h = 1.525
3Ah = 1.550
3Bh = 1.575
3Ch = 1.600
3Dh = 1.625
3Eh = 1.650
3Fh = 1.675

TPS65218D0
5.6.4.17 DCDC3 Register (subaddress = 0x18) [reset = 0x8C]

NOTE
Power-up default may differ depending on RSEL value. See Section 5.3.1.13 for details.

7 6 5 4 3 2 1 0
PFM RESERVED DCDC3
R/W-1b R-0b R/W-Ch

7 PFM R/W 1b
1b = Enabled
6 RESERVED R 0b

TPS65218D0

5-0 DCDC3 R/W, E2 Ch
0h = 0.900
1h = 0.925
2h = 0.950
3h = 0.975
4h = 1.000
5h = 1.025
6h = 1.050
7h = 1.075
8h = 1.100
9h = 1.125
Ah = 1.150
Bh = 1.175
Ch = 1.200
Dh = 1.225
Eh = 1.250
Fh = 1.275
10h = 1.300
11h = 1.325
12h = 1.350
13h = 1.375
14h = 1.400
15h = 1.425
16h = 1.450
17h = 1.475
18h = 1.500
19h = 1.525
1Ah = 1.550
1Bh = 1.600
1Ch = 1.650
1Dh = 1.700
1Eh = 1.750
1Fh = 1.800
20h = 1.850
21h = 1.900
22h = 1.950
23h = 2.000

TPS65218D0

24h = 2.050
25h = 2.100
26h = 2.150
27h = 2.200
28h = 2.250
29h = 2.300
2Ah = 2.350
2Bh = 2.400
2Ch = 2.450
2Dh = 2.500
2Eh = 2.550
2Fh = 2.600
30h = 2.650
31h = 2.700
32h = 2.750
33h = 2.800
34h = 2.850
35h = 2.900
36h = 2.950
37h = 3.000
38h = 3.050
39h = 3.100
3Ah = 3.150
3Bh = 3.200
3Ch = 3.250
3Dh = 3.300
3Eh = 3.350
3Fh = 3.400

TPS65218D0
5.6.4.18 DCDC4 Register (subaddress = 0x19) [reset = 0xB2]

NOTE
Power-up default may differ depending on RSEL value. See Section 5.3.1.13 for details. The
Reserved setting should not be selected and the output voltage settings should not be
modified while the converter is operating.

7 6 5 4 3 2 1 0
PFM RESERVED DCDC4
R/W-1b R-0b R/W-32h

7 PFM R/W 1b
1b = Enabled
6 RESERVED R 0b

TPS65218D0

5-0 DCDC4 R/W, E2 32h
0h = 1.175
1h = 1.200
2h = 1.225
3h = 1.250
4h = 1.275
5h = 1.300
6h = 1.325
7h = 1.350
8h = 1.375
9h = 1.400
Ah = 1.425
Bh = 1.450
Ch = 1.475
Dh = 1.500
Eh = 1.525
Fh = 1.550
10h = 1.600
11h = 1.650
12h = 1.700
13h = 1.750
14h = 1.800
15h = 1.850
16h = 1.900
17h = 1.950
18h = 2.000
19h = 2.050
1Ah = 2.100
1Bh = 2.150
1Ch = 2.200
1Dh = 2.250
1Eh = 2.300
1Fh = 2.3500
20h = 2.400
21h = 2.450
22h = 2.500
23h = 2.550

TPS65218D0

24h = 2.600
25h = 2.650
26h = 2.700
27h = 2.750
28h = 2.800
29h = 2.850
2Ah = 2.900
2Bh = 2.950
2Ch = 3.000
2Dh = 3.050
2Eh = 3.100
2Fh = 3.150
30h = 3.200
31h = 3.250
32h = 3.300
33h = 3.350
34h = 3.400
35h = reserved
36h = reserved
37h = reserved
38h = reserved
39h = reserved
3Ah = reserved
3Bh = reserved
3Ch = reserved
3Dh = reserved
3Eh = reserved
3Fh = reserved

TPS65218D0
5.6.4.19 SLEW Register (subaddress = 0x1A) [reset = 0x6]

SLEW is shown in Figure 5-54 and described in Table 5-26.
NOTE
Slew-rate control applies to DCDC1 and DCDC2 only. If changing from a higher voltage to
lower voltage while STRICT = 1 and converters are in a no load state, PFM bit for DCDC1
and DCDC2 must be set to 0.
Figure 5-54. SLEW Register

7 6 5 4 3 2 1 0
GO GODSBL RESERVED SLEW
R/W-0b R/W-0b R-0h R/W-6h
Table 5-26. SLEW Register Field Descriptions

7 GO R/W 0b
Go bit. Note: Bit is automatically reset at the end of the voltage
transition
0b = No change
1b = Initiates the transition from present state to the output voltage
setting currently stored in DCDC1 / DCDC2 register. SLEW setting
does apply.
6 GODSBL R/W 0b
Go disable bit
0b = Enabled
1b = Disabled; DCDC1 and DCDC2 output voltage changes
whenever set-point is updated in DCDC1 / DCDC2 register without
having to write to the GO bit. SLEW setting does apply.
5-3 RESERVED R 0h
2-0 SLEW R/W 6h
Output slew rate setting
0h = 160 µs/step (0.0625 mV/µs at 10 mV per step)
6h = 2.5 µs/step (4.0 mV/µs at 10 mV per step)
7h = Immediate; Slew rate is only limited by control loop response
time. Note: The actual slew rate depends on the voltage step per
code. Refer to DCDCx registers for details.

TPS65218D0
5.6.4.20 LDO1 Register (subaddress = 0x1B) [reset = 0x1F]

LDO1 is shown in Figure 5-55 and described in Table 5-27.
performed on the LDO1 register.
Figure 5-55. LDO1 Register

7 6 5 4 3 2 1 0
RESERVED LDO1
R-0h R/W-1Fh
Table 5-27. LDO1 Register Field Descriptions

7-6 RESERVED R 0h
5-0 LDO1 R/W, E2 1Fh
LDO1 output voltage setting
0h = 0.900
1h = 0.925
2h = 0.950
3h = 0.975
4h = 1.000
5h = 1.025
6h = 1.050
7h = 1.075
8h = 1.100
9h = 1.125
Ah = 1.150
Bh = 1.175
Ch = 1.200
Dh = 1.225
Eh = 1.250
Fh = 1.275
10h = 1.300
11h = 1.325
12h = 1.350
13h = 1.375
14h = 1.400
15h = 1.425
16h = 1.450
17h = 1.475
18h = 1.500
19h = 1.525

TPS65218D0
Table 5-27. LDO1 Register Field Descriptions (continued)

1Ah = 1.550
1Bh = 1.600
1Ch = 1.650
1Dh = 1.700
1Eh = 1.750
1Fh = 1.800
20h = 1.850
21h = 1.900
22h = 1.950
23h = 2.000
24h = 2.050
25h = 2.100
26h = 2.150
27h = 2.200
28h = 2.250
29h = 2.300
2Ah = 2.350
2Bh = 2.400
2Ch = 2.450
2Dh = 2.500
2Eh = 2.550
2Fh = 2.600
30h = 2.650
31h = 2.700
32h = 2.750
33h = 2.800
34h = 2.850
35h = 2.900
36h = 2.950
37h = 3.000
38h = 3.050
39h = 3.100
3Ah = 3.150
3Bh = 3.200
3Ch = 3.250
3Dh = 3.300
3Eh = 3.350
3Fh = 3.400

TPS65218D0
5.6.4.21 SEQ1 Register (subaddress = 0x20) [reset = 0x0]

SEQ1 is shown in Figure 5-56 and described in Table 5-28.
Password protected.
Figure 5-56. SEQ1 Register

7 6 5 4 3 2 1 0
DLY8 DLY7 DLY6 DLY5 DLY4 DLY3 DLY2 DLY1
R/W-0b R/W-0b R/W-0b R/W-0b R/W-0b R/W-0b R/W-0b R/W-0b
Table 5-28. SEQ1 Register Field Descriptions

7 DLY8 R/W, E2 0b
Delay8 (occurs after Strobe8 and before Strobe9)
0b = 2 ms
1b = 5 ms
6 DLY7 R/W, E2 0b
0b = 2 ms
1b = 5 ms
5 DLY6 R/W, E2 0b
0b = 2 ms
1b = 5 ms
4 DLY5 R/W, E2 0b
0b = 2 ms
1b = 5 ms
3 DLY4 R/W, E2 0b
0b = 2 ms
1b = 5 ms
2 DLY3 R/W, E2 0b
0b = 2 ms
1b = 5 ms
1 DLY2 R/W, E2 0b
0b = 2 ms
1b = 5 ms
0 DLY1 R/W, E2 0b
0b = 2 ms
1b = 5 ms

TPS65218D0

Password protected.

7 6 5 4 3 2 1 0
DLYFCTR RESERVED DLY9
R/W -0b R-0h R/W -0b

7 DLYFCTR R/W, E2 0b
Power-down delay factor
0b = 1x
1b = 10x (delay times are multiplied by 10x during power-down)
Note: DLYFCTR has no effect on power-up timing.
6-1 RESERVED R 0h
0 DLY9 R/W, E2 0b
0b = 2 ms
1b = 5 ms

TPS65218D0

Password protected.

7 6 5 4 3 2 1 0
DC2_SEQ DC1_SEQ
R/W-9h R/W-8h

7-4 DC2_SEQ R/W, E2 9h
DCDC2 enable STROBE
0h = Rail is not controlled by sequencer
3h = Enable at STROBE3
Ah = Enable at STROBE10
Bh = Rail is not controlled by sequencer
Ch = Rail is not controlled by sequencer
Dh = Rail is not controlled by sequencer
Eh = Rail is not controlled by sequencer
Fh = Rail is not controlled by sequencer

TPS65218D0
Table 5-30. SEQ3 Register Field Descriptions (continued)

DCDC1 enable STROBE

TPS65218D0

Password protected.

7 6 5 4 3 2 1 0
DC4_SEQ DC3_SEQ
R/W-7h R/W-5h

DCDC4 enable STROBE

TPS65218D0

DCDC3 enable STROBE

TPS65218D0

Password protected.

7 6 5 4 3 2 1 0
RESERVED DC6_SEQ RESERVED DC5_SEQ
R-0h R/W-1h R-0h R/W-2h

7-6 RESERVED R 0h
DCDC6 enable STROBE. Note: Strobe 1 and 2 are executed only if
FSEAL = 0. DCDC5 and 6 cannot be disabled by sequencer once
freshness seal is broken.
3-2 RESERVED R 0h
DCDC5 enable STROBE. Note: Strobe 1 and 2 are executed only if
FSEAL = 0. DCDC5 and 6 cannot be disabled by sequencer once
freshness seal is broken.

TPS65218D0

Password protected.

7 6 5 4 3 2 1 0
LS1_SEQ LDO1_SEQ
R/W-6h R/W-3h

7-4 LS1_SEQ R/W, E2 6h
LS1 enable STROBE

TPS65218D0

3-0 LDO1_SEQ R/W, E2 3h
LDO1 enable STROBE

TPS65218D0

Password protected.

7 6 5 4 3 2 1 0
GPO3_SEQ GPO1_SEQ
R/W-0h R/W-3h

7-4 GPO3_SEQ R/W, E2 0h
GPO3 enable STROBE

TPS65218D0

3-0 GPO1_SEQ R/W, E2 3h
GPO1 enable STROBE

TPS65218D0
6 Application and Implementation
NOTE
Information in the following applications sections is not part of the TI component
specification, and TI does not warrant its accuracy or completeness. TI’s customers are
responsible for determining suitability of components for their purposes. Customers should
validate and test their design implementation to confirm system functionality.
6.1 Application Information

The TPS65218D0 is designed to pair with various application processors. For detailed information on
using TPS65218D0 with Sitara™ AM335x or Sitara AM437x processors, refer to Powering the
AM335x/AM437x with TPS65218.The typical application in Section 6.2 is based on and uses terminology
consistent with the Sitara™ family of processors.
6.1.1 Applications Without Backup Battery

In applications that require always-on supplies but no battery backup, the CC input to the power path must
be connected to ground.
DCDC6 (1.8 V) 10 µH VDD_10 (1 V)

L5
Battery backup
PGOOD_BU DCDC5_PG 22 …F domain supply
To SOC DCDC5 FB5
DCDC6_PG
DCDC6 (1.8 V) VDD_18 (1.8 V)

L6 10 µH
Battery backup
IN_nCC 22 …F domain supply
To SOC DCDC6 FB6
2.7-V to 5.5-V IN_BU

system power
4.7 …F
CC SYS_BU
1 …F
IN_BIAS From 2.7-V to 6.5-V

system power
INT_LDO
BIAS
100 nF
Figure 6-1. CC Input to Power Path
NOTE
In applications without backup battery, CC input must be tied to ground.
92 Application and Implementation Copyright © 2017–2018, Texas Instruments Incorporated

TPS65218D0
6.1.2 Applications Without Battery Backup Supplies

In applications that do not require always-on supplies, both inputs and the output of the power-path can
simply be grounded. All pins related to DCDC5 and DCDC6 are also tied to ground, and PGOOD_BU and
IN_nCC are kept floating. With the backup supplies completely disabled, the FSEAL bit in the STATUS
register is undefined and should be ignored.
DCDC6 (1.8 V)
L5
PGOOD_BU DCDC5_PG
DCDC5 FB5
No connect DCDC6_PG
DCDC6 (1.8 V)
L6
IN_nCC
DCDC6 FB6
No connect
IN_BU
CC SYS_BU
Figure 6-2. DCDC5 and DCDC6 Pins
NOTE
In applications that do not require always-on supplies, PGOOD_BU and IN_nCC can be kept
floating. All other pins are tied to ground.
Copyright © 2017–2018, Texas Instruments Incorporated Application and Implementation 93

TPS65218D0
6.2 Typical Application

VDDSHVx
for GPIOx
System Power (5.5 V) DCDC6 VDDSHV3
Push
Button
nWAKEUP
PB RTC_WAKEUP
nINT
GPIOx
PGOOD
PWRONRSTn
Digital
PWR_EN
RTC_PMIC_EN
AC_DET
SCL/SDA
I2C0_SCL/SDA
GPIO3
10
CC PGOOD_BU
RTC_PWRONRSTn
Battery Backup IN_nCC
Coin + Supplies
Cell ± 1.0V (DCDC5)
IN_BU DCDC5 CAP_VDD_RTC
DCDC6 1.8V (DCDC6)
VDDS_RTC
IN_LDO1 1.8V
2.7-V to 5.5-V LDO1 1.8V Analog & I/O
system power
IN_DCDC1 0.95/1.1V
DCDC1 (buck) VDD_CORE
IN_DCDC2 0.95/1.1/1.2/1.26/1.325V
DCDC2 (buck)
VDD_MPU
IN_DCDC3 1.35/1.5V
DCDC3 (buck)
IN_DCDC4 3.3V
DCDC4 (buck-boost) 3.3V Analog & I/O
IN_BIAS
BIAS DDR_RESETn
IN_LS1 LS1
From DCDC3 LS1 VDDS_DDR
TPS65218
DDR3/L Memory
Figure 6-3. Typical Application Schematic

TPS65218D0
6.2.1 Design Requirements

Table 6-1 lists the design requirements.
Table 6-1. Design Parameters

VOLTAGE SEQUENCE
DCDC1 1.1 V 8
DCDC2 1.1 V 9
DCDC3 1.2 V 5
DCDC4 3.3 V 7
DCDC5 1.0 V 2
DCDC6 1.8 V 1
LDO1 1.8 V 3
6.2.2 Detailed Design Procedure
6.2.2.1 Output Filter Design

The step down converters (DCDC1, DCDC2, and DCDC3) on TPS65218D0 are designed to operate with
effective inductance values in the range of 1 to 2.2 µH and with effective output capacitance in the range
of 10 to 100 µF. The internal compensation is optimized to operate with an output filter of L = 1.5 µH and
COUT = 10 µF.
The buck boost converter (DCDC4) on TPS65218D0 is designed to operate with effective inductance
values in the range of 1.2 to 2.2 µH. The internal compensation is optimized to operate with an output filter
of L = 1.5 µH and COUT = 47 µF.
The two battery backup converters (DCDC5 and DCDC6) are designed to operate with effective
inductance values in the range of 4.7 to 22 µH. The internal compensation is optimized with an output filter
of L = 10 µH and COUT = 20 µF.
Larger or smaller inductor/capacitance values can be used to optimize performance of the device for
specific operation conditions.
6.2.2.2 Inductor Selection for Buck Converters

The inductor value affects its peak to peak ripple current, the PWM to PFM transition point, the output
voltage ripple, and the efficiency. The selected inductor must be rated for its DC resistance and saturation
current. The inductor ripple current (∆L) decreases with higher inductance and increases with higher VIN or
VOUT. Equation 1 calculates the maximum inductor current ripple under static load conditions. The
saturation current of the inductor should be rated higher than the maximum inductor current as calculated
with Equation 2. This is recommended as during heavy load transient the inductor current will rise above
the calculated value.
V
± OUT
VIN
'I L VOUT u
/u¦ (1)
'I L
I L max I OUT max
2
where
• F = Switching frequency
• L = Inductor value
• ∆IL = Peak-to-peak inductor ripple current
• ILmax = Maximum inductor current (2)

TPS65218D0
The following inductors have been used with the TPS65218D0 (see Table 6-2).
Table 6-2. List of Recommended Inductors

PART NUMBER VALUE SIZE (mm) [L × W × H] MANUFACTURER
INDUCTORS FOR DCDC1, DCDC2, DCDC3, DCDC4
SPM3012T-1R5M 1.5 µH, 2.8 A, 77 mΩ 3.2 × 3.0 × 1.2 TDK
IHLP1212BZER1R5M11 1.5 µH, 4.0 A, 28.5 mΩ 3.6 × 3.0 × 2.0 Vishay
INDUCTORS FOR DCDC5, DCDC6
2012 / 0805 (2.00 × 1.25 ×
MLZ2012N100L 10 µH, 110 mA, 300 mΩ TDK
1.25)
2012 / 0805 (2.00 × 1.25 ×
LQM21FN100M80 10 µH, 100 mA, 300 mΩ Murata
1.25)
6.2.2.3 Output Capacitor Selection

The hysteretic PWM control scheme of the TPS65218D0 switching converters allows the use of tiny
ceramic capacitors. Ceramic capacitors with low ESR values have the lowest output voltage ripple and are
recommended. The output capacitor requires either an X7R or X5R dielectric.
At light load currents the converter operates in power save mode, and the output voltage ripple is
dependent on the output capacitor value and the PFM peak inductor current. Higher output capacitor
values minimize the voltage ripple in PFM Mode and tighten DC output accuracy in PFM mode.
The two battery backup converters (DCDC5 and DCDC6) always operate in PFM mode. For these
converters, a capacitor of at least 20 µF is recommended on the output to help minimize voltage ripple.
The buck-boost converter requires additional output capacitance to help maintain converter stability during
high load conditions. At least 40 µF of output capacitance is recommended and an additional 100-nF
capacitor can be added to further filter output ripple at higher frequencies.
Table 6-2 lists the recommended capacitors.
Table 6-3. List of Recommended Capacitors

PART NUMBER VALUE SIZE (mm) [L × W × H] MANUFACTURER
CAPACITORS FOR VOLTAGES UP TO 5.5 V (1)
GRM188R60J105K 1µF 1608 / 0603 (1.6 × 0.8 × 0.8) Murata
GRM21BR60J475K 4.7µF 2012 / 0805 (2.0 × 1.25 × 1.25) Murata
GRM31MR60J106K 10µF 3216 / 1206 (3.2 × 1.6 × 1.6) Murata
GRM31CR60J226K 22µF 3216 / 1206 (3.2 × 1.6 × 1.6) Murata
(1)
CAPACITORS FOR VOLTAGES UP TO 3.3 V
GRM21BR60J106K 10µF 2012 / 0805 (2.0 × 1.25 × 1.25) Murata
GRM31CR60J476M 47µF 3216 / 1206 (3.2 × 1.6 × 1.6) Murata
(1) The DC bias effect of ceramic capacitors must be considered when selecting a capacitor.

TPS65218D0
6.2.3 Application Curves

at TJ = 25°C unless otherwise noted
100% 90%
80%
80% 70%
60%
60%
Efficiency
Efficiency
50%
40%
40%
30%
20% 20%
VIN = 2.8 V VIN = 2.8 V
VIN = 3.6 V 10% VIN = 3.6 V
VIN = 5 V VIN = 5 V
0 0
0 400.001 800.001 1200.001 1600.001 0 0.2 0.4 0.6 0.8 1 1.2 1.4 1.6 1.8
Output Current (mA) D007
Output Current(A) D008
Figure 6-4. DCDC1/DCDC2 Efficiency Figure 6-5. DCDC3 Efficiency
90% 100%
80%
70% 80%
60%
60%
Efficiency
Efficiency
50%
40%
40%
30%
20% 20%
VIN = 2.8 V VIN = 2.7 V
10% VIN = 3.6 V VIN = 3.6 V
VIN = 5 V VIN = 5 V
0 0
0 0.2 0.4 0.6 0.8 1 1.2 1.4 1.6 1.8 0 0.2 0.4 0.6 0.8 1 1.2 1.4 1.6
Figure 6-6. DCDC3 Efficiency Figure 6-7. DCDC4 Efficiency
90%
85%
80%
75%
70%
Efficiency
65%
60%
55%
50%
45% DCDC5 (1 V)
DCDC6 (1.8 V)
40%
0 0.01 0.02 0.03 0.04 0.05 0.06 0.07 0.08 0.09 0.1
Output Current (mA) D011
IN_BU = 0 V CC = 3 V
Figure 6-8. DCDC5/DCDC6 Efficiency

TPS65218D0
7 Power Supply Recommendations

The device is designed to operate with an input voltage supply range between 2.7 and 5.5 V. This input
supply can be from a single cell Li-Ion battery or other externally regulated supply. If the input supply is
located more than a few inches from the TPS65218D0 additional bulk capacitance may be required in
addition to the ceramic bypass capacitors. An electrolytic capacitor with a value of 47 µF is a typical
choice.
The coin cell back up input is designed to operate with a input voltage supply between 2.2 and 3.3 V This
input should be supplied by a coin cell battery with 3-V nominal voltage.
8 Layout
8.1 Layout Guidelines
Follow these layout guidelines:
• The IN_X pins should be bypassed to ground with a low ESR ceramic bypass capacitor. The typical
recommended bypass capacitance is 4.7-µF with a X5R or X7R dielectric.
• The optimum placement is closest to the IN_X pins of the device. Take care to minimize the loop area
formed by the bypass capacitor connection, the IN_X pin, and the thermal pad of the device.
• The thermal pad should be tied to the PCB ground plane with a minimum of 25 vias. See Figure 8-2 for
an example.
• The LX trace should be kept on the PCB top layer and free of any vias.
• The FBX traces should be routed away from any potential noise source to avoid coupling.
• DCDC4 Output capacitance should be placed immediately at the DCDC4 pin. Excessive distance
between the capacitance and DCDC4 pin may cause poor converter performance.
8.2 Layout Example
VOUT
Output Filter
Capacitor
Input Bypass
Capacitor
Via to Ground Plane

FB1
L1
Via to Internal Plane IN

Thermal
Pad
Figure 8-1. Layout Recommendation
98 Layout Copyright © 2017–2018, Texas Instruments Incorporated

TPS65218D0
s
Recommended Thermal Pad via size
Hole size (s) = 8 mil
Diameter (d) = 16 mil
d
Figure 8-2. Thermal Pad Layout Recommendation
Copyright © 2017–2018, Texas Instruments Incorporated Layout 99

TPS65218D0
9 Device and Documentation Support

9.1 Device Support
9.1.1 Third-Party Products Disclaimer

TI'S PUBLICATION OF INFORMATION REGARDING THIRD-PARTY PRODUCTS OR SERVICES DOES
NOT CONSTITUTE AN ENDORSEMENT REGARDING THE SUITABILITY OF SUCH PRODUCTS OR
SERVICES OR A WARRANTY, REPRESENTATION OR ENDORSEMENT OF SUCH PRODUCTS OR
SERVICES, EITHER ALONE OR IN COMBINATION WITH ANY TI PRODUCT OR SERVICE.
9.2 Documentation Support
9.2.1 Related Documentation

For related documentation see the following:
• Texas Instruments, Basic Calculation of a Buck Converter's Power Stage application report
• Texas Instruments, Design Calculations for Buck-Boost Converters application report
• Texas Instruments, Empowering Designs With Power Management IC (PMIC) for Processor
Applications application report
• Texas Instruments, Powering the AM335x/AM437x with TPS65218 user's guide
• Texas Instruments, TPS65218EVM user's guide
• Texas Instruments, TPS65218 Power Management Integrated Circuit (PMIC) for Industrial Applications
application report
9.3 Receiving Notification of Documentation Updates

To receive notification of documentation updates, navigate to the device product folder on ti.com. In the
upper right corner, click on Alert me to register and receive a weekly digest of any product information that
has changed. For change details, review the revision history included in any revised document.
9.4 Community Resources

The following links connect to TI community resources. Linked contents are provided "AS IS" by the
respective contributors. They do not constitute TI specifications and do not necessarily reflect TI's views;
see TI's Terms of Use.
TI E2E™ Online Community The TI engineer-to-engineer (E2E) community was created to foster
collaboration among engineers. At e2e.ti.com, you can ask questions, share knowledge,
explore ideas and help solve problems with fellow engineers.
Design Support TI's Design Support Quickly find helpful E2E forums along with design support tools
and contact information for technical support.
9.5 Trademarks
PowerPAD, Sitara, E2E are trademarks of Texas Instruments.
Cortex is a trademark of ARM Ltd.
ARM is a registered trademark of ARM Ltd.
100 Device and Documentation Support Copyright © 2017–2018, Texas Instruments Incorporated
TPS65218D0
9.6 Electrostatic Discharge Caution

This integrated circuit can be damaged by ESD. Texas Instruments recommends that all integrated circuits be handled with
appropriate precautions. Failure to observe proper handling and installation procedures can cause damage.
ESD damage can range from subtle performance degradation to complete device failure. Precision integrated circuits may be more
susceptible to damage because very small parametric changes could cause the device not to meet its published specifications.
9.7 Glossary
TI Glossary This glossary lists and explains terms, acronyms, and definitions.
10 Mechanical, Packaging, and Orderable Information

The following pages include mechanical packaging and orderable information. This information is the most
current data available for the designated devices. This data is subject to change without notice and
revision of this document. For browser-based versions of this data sheet, refer to the left-hand navigation.
Copyright © 2017–2018, Texas Instruments Incorporated Mechanical, Packaging, and Orderable Information 101
PACKAGE OPTION ADDENDUM
www.ti.com 10-Dec-2020
PACKAGING INFORMATION
Orderable Device Status Package Type Package Pins Package Eco Plan Lead finish/ MSL Peak Temp Op Temp (°C) Device Marking Samples
(1) Drawing Qty (2) Ball material (3) (4/5)
(6)
TPS65218D0PHPR ACTIVE HTQFP PHP 48 1000 RoHS & Green NIPDAU Level-3-260C-168 HR -40 to 105 T65218D0
TPS65218D0PHPT ACTIVE HTQFP PHP 48 250 RoHS & Green NIPDAU Level-3-260C-168 HR -40 to 105 T65218D0
TPS65218D0RSLR ACTIVE VQFN RSL 48 2500 RoHS & Green NIPDAU Level-3-260C-168 HR -40 to 105 T65218D0
TPS65218D0RSLT ACTIVE VQFN RSL 48 250 RoHS & Green NIPDAU Level-3-260C-168 HR -40 to 105 T65218D0
(1)
The marketing status values are defined as follows:
ACTIVE: Product device recommended for new designs.
LIFEBUY: TI has announced that the device will be discontinued, and a lifetime-buy period is in effect.
NRND: Not recommended for new designs. Device is in production to support existing customers, but TI does not recommend using this part in a new design.
PREVIEW: Device has been announced but is not in production. Samples may or may not be available.
OBSOLETE: TI has discontinued the production of the device.
(2)
RoHS: TI defines "RoHS" to mean semiconductor products that are compliant with the current EU RoHS requirements for all 10 RoHS substances, including the requirement that RoHS substance
do not exceed 0.1% by weight in homogeneous materials. Where designed to be soldered at high temperatures, "RoHS" products are suitable for use in specified lead-free processes. TI may
reference these types of products as "Pb-Free".
RoHS Exempt: TI defines "RoHS Exempt" to mean products that contain lead but are compliant with EU RoHS pursuant to a specific EU RoHS exemption.
Green: TI defines "Green" to mean the content of Chlorine (Cl) and Bromine (Br) based flame retardants meet JS709B low halogen requirements of <=1000ppm threshold. Antimony trioxide based
flame retardants must also meet the <=1000ppm threshold requirement.
(3)
MSL, Peak Temp. - The Moisture Sensitivity Level rating according to the JEDEC industry standard classifications, and peak solder temperature.
(4)
There may be additional marking, which relates to the logo, the lot trace code information, or the environmental category on the device.
(5)
Multiple Device Markings will be inside parentheses. Only one Device Marking contained in parentheses and separated by a "~" will appear on a device. If a line is indented then it is a continuation
of the previous line and the two combined represent the entire Device Marking for that device.
(6)
Lead finish/Ball material - Orderable Devices may have multiple material finish options. Finish options are separated by a vertical ruled line. Lead finish/Ball material values may wrap to two
lines if the finish value exceeds the maximum column width.
Important Information and Disclaimer:The information provided on this page represents TI's knowledge and belief as of the date that it is provided. TI bases its knowledge and belief on information
provided by third parties, and makes no representation or warranty as to the accuracy of such information. Efforts are underway to better integrate information from third parties. TI has taken and
Addendum-Page 1
PACKAGE OPTION ADDENDUM
www.ti.com 10-Dec-2020
continues to take reasonable steps to provide representative and accurate information but may not have conducted destructive testing or chemical analysis on incoming materials and chemicals.
TI and TI suppliers consider certain information to be proprietary, and thus CAS numbers and other limited information may not be available for release.
In no event shall TI's liability arising out of such information exceed the total purchase price of the TI part(s) at issue in this document sold by TI to Customer on an annual basis.
Addendum-Page 2
PACKAGE MATERIALS INFORMATION
www.ti.com 28-Sep-2018
TAPE AND REEL INFORMATION
*All dimensions are nominal

Device Package Package Pins SPQ Reel Reel A0 B0 K0 P1 W Pin1
Type Drawing Diameter Width (mm) (mm) (mm) (mm) (mm) Quadrant
(mm) W1 (mm)
TPS65218D0PHPR HTQFP PHP 48 1000 330.0 16.4 9.6 9.6 1.5 12.0 16.0 Q2
TPS65218D0PHPT HTQFP PHP 48 250 330.0 16.4 9.6 9.6 1.5 12.0 16.0 Q2
TPS65218D0RSLR VQFN RSL 48 2500 330.0 16.4 6.3 6.3 1.1 12.0 16.0 Q2
TPS65218D0RSLT VQFN RSL 48 250 180.0 16.4 6.3 6.3 1.1 12.0 16.0 Q2
Pack Materials-Page 1
PACKAGE MATERIALS INFORMATION
www.ti.com 28-Sep-2018
*All dimensions are nominal

Device Package Type Package Drawing Pins SPQ Length (mm) Width (mm) Height (mm)
TPS65218D0PHPR HTQFP PHP 48 1000 336.6 336.6 31.8
TPS65218D0PHPT HTQFP PHP 48 250 336.6 336.6 31.8
TPS65218D0RSLR VQFN RSL 48 2500 367.0 367.0 38.0
TPS65218D0RSLT VQFN RSL 48 250 210.0 185.0 35.0
Pack Materials-Page 2
GENERIC PACKAGE VIEW
PHP 48 TQFP - 1.2 mm max height
7 x 7, 0.5 mm pitch QUAD FLATPACK
This image is a representation of the package family, actual package may vary.
Refer to the product data sheet for package details.
4226443/A
www.ti.com
IMPORTANT NOTICE AND DISCLAIMER
TI PROVIDES TECHNICAL AND RELIABILITY DATA (INCLUDING DATASHEETS), DESIGN RESOURCES (INCLUDING REFERENCE
DESIGNS), APPLICATION OR OTHER DESIGN ADVICE, WEB TOOLS, SAFETY INFORMATION, AND OTHER RESOURCES “AS IS”
AND WITH ALL FAULTS, AND DISCLAIMS ALL WARRANTIES, EXPRESS AND IMPLIED, INCLUDING WITHOUT LIMITATION ANY
IMPLIED WARRANTIES OF MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE OR NON-INFRINGEMENT OF THIRD
PARTY INTELLECTUAL PROPERTY RIGHTS.
These resources are intended for skilled developers designing with TI products. You are solely responsible for (1) selecting the appropriate
TI products for your application, (2) designing, validating and testing your application, and (3) ensuring your application meets applicable
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TPS65218D0 Power Management for ARM® Cortex™-A8/A9 SOCs and FPGAs

Device Information (1)

2 Device Overview Copyright © 2017–2018, Texas Instruments Incorporated

1.4 Simplified Schematic

Copyright © 2017, Texas Instruments Incorporated

Figure 1-1. Simplified Schematic

Copyright © 2017–2018, Texas Instruments Incorporated Device Overview 3

Changes from Revision A (July 2018) to Revision B Page

Changes from Original (December 2017) to Revision A Page

4 Revision History Copyright © 2017–2018, Texas Instruments Incorporated

3 Pin Configuration and Functions

IN_LDO1 5 32 IN_LS2 IN_LDO1 5 32 IN_LS2

IN_LS3 6 31 IN_LS1 IN_LS3 6 31 IN_LS1

PGOOD 8 29 N/C PGOOD 8 29 N/C

AC_DET 9 28 N/C AC_DET 9 28 N/C

nPFO 10 27 IN_BU nPFO 10 27 IN_BU

3.1 Pin Functions

Copyright © 2017–2018, Texas Instruments Incorporated Pin Configuration and Functions 5

Pin Functions (continued)

6 Pin Configuration and Functions Copyright © 2017–2018, Texas Instruments Incorporated

4.1 Absolute Maximum Ratings

4.2 ESD Ratings

Copyright © 2017–2018, Texas Instruments Incorporated Specifications 7

4.3 Recommended Operating Conditions

4.4 Thermal Information

8 Specifications Copyright © 2017–2018, Texas Instruments Incorporated

4.5 Electrical Characteristics

Copyright © 2017–2018, Texas Instruments Incorporated Specifications 9

Electrical Characteristics (continued)

(1) 500-µF of remote capacitance can be supported for DCDC1/2.

Electrical Characteristics (continued)

Copyright © 2017–2018, Texas Instruments Incorporated Specifications 11

Electrical Characteristics (continued)

12 Specifications Copyright © 2017–2018, Texas Instruments Incorporated

Electrical Characteristics (continued)

(2) IN_BU has priority over CC input.

Electrical Characteristics (continued)

14 Specifications Copyright © 2017–2018, Texas Instruments Incorporated

Electrical Characteristics (continued)

Copyright © 2017–2018, Texas Instruments Incorporated Specifications 15

Electrical Characteristics (continued)

Electrical Characteristics (continued)

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Electrical Characteristics (continued)

4.6 Timing Requirements

Timing Requirements (continued)

Copyright © 2017–2018, Texas Instruments Incorporated Specifications 19

4.7 Typical Characteristics

20 Specifications Copyright © 2017–2018, Texas Instruments Incorporated

Copyright © 2017–2018, Texas Instruments Incorporated Detailed Description 21

5.2 Functional Block Diagram

2.7-V to 5.5-V IN_BU

From 2.7-V to 5.5-V IN_DCDC3 IN_DCDC1 From 2.7-V to 5.5-V

From 2.7-V to 5.5-V IN_DCDC4 IN_DCDC2 From 2.7-V to 5.5-V

3.3-V I/O supply DCDC4

22 Detailed Description Copyright © 2017–2018, Texas Instruments Incorporated

5.3 Feature Description