1.

Draw detailed structure of IAS

 The IAS operates by repetitively performing an instruction cycle. Each instruction cycle
consists of two subcycles.
 During the fetch cycle, the opcode of the next instruction is loaded into the IR and the
address portion is loaded into the MAR.
 This instruction may be taken from the IBR,or it can be obtained from memory by
loading a word into the MBR, and then down to the IBR, IR,and MAR.
 These operations are controlled by electronic circuitry and result in the use of data
paths.
 To simplify the electronics, there is only one register that is used to specify the address
in memory for a read or write and only one register used for the source or destination.
 Once the opcode is in the IR,the execute cycleis performed.Control circuitry interprets
the opcode and executes the instruction by sending out the appropriate control signals
to cause data to be moved or an operation to be performed by the ALU.

 These can be grouped as follows:

 1. Data transfer:Move data between memory and ALU registers or between two
ALU registers.
2. Unconditional branch: Normally, the control unit executes instructions in
sequence from memory.This sequence can be changed by a branch instruction,
which facilitates repetitive operations.
3. Conditional branch: The branch can be made dependent on a condition,thus
allowing decision points.
4. Arithmetic: Operations performed by the ALU.
5. Address modify: Permits addresses to be computed in the ALU and then
inserted into instructions stored in memory.
6. This allows a program considerable addressing flexibility.

2. Write symbolic representation of interrupt cycle. Give meaning of each line

 At the completion of the Execute Cycle, a test is made to determine whether any
enabled interrupt has occurred or not.
 If an enabled interrupt has occurred then Interrupt Cycle occurs.
 The nature of this cycle varies greatly from one machine to another.
Lets take a sequence of micro-operation:-

Step 1: Contents of the PC is transferred to the MBR, so that they can be saved for
return.
Step 2: MAR is loaded with the address at which the contents of the PC are to be
saved.
PC is loaded with the address of the start of the interrupt-processing routine.
Step 3: MBR, containing the old value of PC, is stored in memory.
Note: In step 2, two actions are implemented as one micro-operation. However, most
processor provide multiple types of interrupts, it may take one or more micro-
operation to obtain the save_address and the routine_address before they are
transferred to the MAR and PC respectively.
3. List and briefly define the main structural components of computer and
Processor

Components of computer:
The main elements associated with a computer system are as follows:
1. Central Processing Unit (CPU): The CPU or processor acts as the controller of all
actions or services provided by the system. The operations of a CPU can be reduced
into the following:
 Fetch the next instruction from memory.
 Decode the instruction.
 Execute the instruction.
 Store the result of the instruction into main memory.
2. Main Memory: Main Memory: used to store information for immediate access by
the CPU. Main Memory is also referred to as Primary Storage or Main Store. Main
memory includes:
 Random Access memory (RAM): for temporary storage.
 Read-only memory (ROM): for permanent storage.
 3. Secondary Storage Devices: Devices provide permanent storage of large amounts
of data. Secondary storage is also called: secondary memory, external memory. This
storage may consist of magnetic tapes, magnetic disk, optical memory device
4. Input and Output (I/O) Devices: Input/output devices provide an interface between
the computer and the user. There is at least one input device and at least one output
device
5. System interconnection: Some mechanism that provides for communication among
CPU, main memory, and I/O. A common example of system interconnection is by
means of a system bus, consisting of a number of conducting wires to which all the
other components attach.
There are three types of busses:
1. Address Buss
2. Data Bus
3. Control Bus

Components of Processor:
CPU has three main units: (See the figure below)
 Arithmetic and Logic Unit (ALU): Performs arithmetic and logical operations. For
example, it can add together two binary numbers either from memory or from some of
the CPU registers.
 Control Unit: controls the action of the other computer components so that
instructions are executed in the correct sequence.
 Registers - Temporary storage inside CPU. Registers can be read and written at high
speed as they are inside the CPU.

4. Give detailed idea on how operands of an instructions are specified

An instruction can act on zero or more operands, which are the data manipulated by the
instruction. An example of a zero-operand instruction is NOP (no operation). Operands are
entities operated upon by the instruction. An operand can be in any of these locations:

 In the instruction itself

 In a register
 In memory
 At an I/O port

An x86 instruction can have zero to three operands. Operands are separated by commas (,).
For instructions with two operands, the first (lefthand) operand is the source operand, and the
second (righthand) operand is the destination operand (that is, source->destination).

Note – The Intel assembler uses the opposite order (destination<-source) for operands.
5. Draw flowchart of instruction cycle code

6. What types of operand are in typical machine instruction set? Give example.
Machine instructions operate on data. The most important general categories of data are
• Addresses
• Numbers
• Characters
• Logical data
Addresses
 Addresses are, in fact, a form of data. In many cases, some calculation must be
performed on the operand reference in an instruction to determine the main or
virtual memory address.
 Addresses can be considered to be unsigned integers.
Numbers
 All machine languages include numeric data types. Even in nonnumeric data
processing,there is a need for numbers to act as counters,field widths,and so
forth. Three types of numerical data are common in computers:
 Binary integer or binary fixed point
 Binary floating point
 Decimal
 Although all internal computer operations are binary in nature, the human users
of the system deal with decimal numbers.Thus,there is a necessity to convert
from decimal to binary on input and from binary to decimal on output.
 For applications in which there is a great deal of I/O and comparatively little,
comparatively simple computation,it is preferable to store and operate on the
numbers in decimal form.
 The most common representation for this purpose is packed decimal.
  With packed decimal,each decimal digit is represented by a 4-bit code,in the
obvious way, with two digits stored per byte.Thus, 0=0000,1=0001,….8=1000
and 9=1001.
 Negative numbers can be represented by including a 4-bit sign digit at either the
left or right end of a string of packed decimal digits.Standard sign values are
1100 for positive and 1101 for negative .
Characters
 A common form of data is text or character strings.
 While textual data are most convenient for human beings,they cannot,in
character form,be easily stored or transmitted by data processing and
communications systems.
 Such systems are designed for binary data.
 Thus,a number of codes have been devised by which characters are represented
by a sequence of bits. Perhaps the earliest common example of this is the Morse
code.
 Today,the most commonly used character code in the International Reference
Alphabet (IRA). Each character in this code is represented by a unique 7-bit
pattern;thus,128 different characters can be represented. This is a larger number
than is necessary to represent printable characters, and some of the patterns
represent control characters.Some of these control characters have to do with
controlling the printing of characters on a page.
 Others are concerned with communications procedures. IRA-encoded
characters are almost always stored and transmitted using 8 bits per
character.The eighth bit may be set to 0 or used as a parity bit for error
detection.In the latter case,the bit is set such that the total number of binary 1s
in each octet is always odd (odd parity) or always even (even parity).
 Another code used to encode characters is the Extended Binary Coded Decimal
Interchange Code (EBCDIC).EBCDIC is used on IBM mainframes.It is an 8-
bit code.In the case of EBCDIC, the codes 11110000 through 11111001
represent the digits 0 through 9.
Logical Data
 Normally each word or other addressable unit (byte,halfword,and so on) is
treated as a single unit of data.It is sometimes useful,however,to consider an n-
bit unit as consisting of n 1-bit items of data,each item having the value 0 or
1.When data are viewed this way,they are considered to be logical data.
 There are two advantages to the bit-oriented view. First, we may sometimes
wish to store an array of Boolean or binary data items,in which each item can
take on only the values 1 (true) and 0 (false).With logical data,memory can be
used most efficiently for this storage.
 Second,there are occasions when we wish to manipulate the bits of a data item.
 For example,if floating-point operations are implemented in software,we need
to be able to shift significant bits in some operations.
 Another example:To convert from IRA to packed decimal, we need to extract
the rightmost 4 bits of each byte.
7. Draw intel 8085 CPU block diagram

8. Explain hardwired implementation of control unit

In a hardwired implementation, the control unit is essentially a state machine circuit.Its
input logic signals are transformed into a set of output logic signals,which are the
control signals.
Control Unit Inputs
 The key inputs are the instruction register,the clock,flags,and control bus
signals.
 In the case of the flags and control bus signals, each individual bit typically has
some meaning (e.g., overflow).
 The other two inputs,however,are not directly useful to the control unit.
  The control unit is implemented using hardware (for example: NAND gates,
flip-flops, and counters).We need a special digital circuit that uses , as inputs,
the bits from the Opcode field in our instructions, bits from the flag (or status)
register, signals from the bus, and signals from the clock. It should produce, as
outputs, the control signals to drive the various components in the computer.
 The control unit makes use of the opcode and will perform different actions
(issue a different combination of control signals) for different instructions.
 To simplify the control unit logic, there should be a unique logic input for each
opcode.
 This function can be performed by a decoder, which takes an encoded input and
produces a single output. In general, a decoder will have n binary inputs and 2n
binary outputs.
 The clock portion of the control unit issues a repetitive sequence of pulses. This
is useful for measuring the duration of micro-operations. Essentially the period
of the clock pulses must be long enough to allow the propagation of signals
along data paths and through processor circuitry.
 The control unit emits different control signals at different time units within a
single instruction cycle. Thus we would like a counter as input to the control
unit with a different control signal being used for and so forth. At the end of an
instruction cycle the control unit must feed back to the counter to reinitialize it.
Control Unit Logic
 To define the hardwired implementation of a control unit all that remains is to
discuss the internal logic of the control unit that produces output control signals
as a function of its input signals.
 Essentially what must be done is for each control signal to derive a Boolean
expression of that signal as a function of the inputs

9. Explain 2’s complement method of multiplication to solve 14*(-5). Where 14 as

multiplicand (-5) as multiplier. Draw a flowchart for the same.
10. Write the Booths algorithm for multiplying two binary no.s in signed 2’s
complement representation.
The booth algorithm is a multiplication algorithm that allows us to multiply the two signed
binary integers in 2's complement, respectively. It is also used to speed up the performance of
the multiplication process. It is very efficient too. It works on the string bits 0's in the multiplier
that requires no additional bit only shift the right-most string bits and a string of 1's in a
multiplier bit weight 2k to weight 2m that can be considered as 2k+ 1 - 2m.

Working on the Booth Algorithm

1. Set the Multiplicand and Multiplier binary bits as M and Q, respectively.
2. Initially, we set the AC and Qn + 1 registers value to 0.
3. SC represents the number of Multiplier bits (Q), and it is a sequence counter that is
continuously decremented till equal to the number of bits (n) or reached to 0.
4. A Qn represents the last bit of the Q, and the Qn+1 shows the incremented bit of Qn by
1.
5. On each cycle of the booth algorithm, Qn and Qn + 1 bits will be checked on the following
parameters as follows:
i. When two bits Qn and Qn + 1 are 00 or 11, we simply perform the arithmetic shift
right operation (ashr) to the partial product AC. And the bits of Qn and Qn + 1 is
incremented by 1 bit.
ii. If the bits of Qn and Qn + 1 is shows to 01, the multiplicand bits (M) will be added
to the AC (Accumulator register). After that, we perform the right shift
operation to the AC and QR bits by 1.
iii. If the bits of Qn and Qn + 1 is shows to 10, the multiplicand bits (M) will be
subtracted from the AC (Accumulator register). After that, we perform the right
shift operation to the AC and QR bits by 1.
6. The operation continuously works till we reached n - 1 bit in the booth algorithm.
7. Results of the Multiplication binary bits will be stored in the AC and QR registers.

11. What is a need of microprogrammed control unit? Draw a block diagram of

microprogrammed control unit to explain conditional branching in the microprogram.
1) A control unit with its binary control values stored as words in memory is called as
microprogrammed control. Each word in the control memory contains microinstruction that
specifies one or more microperations for the system. A sequence of microinstructions
constitutes a micro program.
2) Microprogrammed implementation is a software approach in contrast to the hardwired
approach.
3) It deals with various units of software but at the micro level i.e. micro-operation, micro-
instruction, micro-program etc.

Conditional Branching

1. We have some instructions whose execution depends on the status of condition codes
and status flag, as for example, the branch instruction. During branch instruction
execution it is required to take the decision between alternative actions.
2. To handle such type of instructions with microprogrammed control, the design of
control unit is based on the concept of conditional branching in the micro program. For
that it is required to include some conditional branch microinstructions.In conditional
microinstructions, it is required to specify the address of the microprogram memory to
which the control must be directed. It is known as branch address. Apart from branch
address, these microinstructions can specify which of the flags, condition codes, or
possibly, bits of the instruction register should be checked as a condition for branching
to take place.
 3. To support micro program branching, the organization of control unit should be
modified to accommodate the branching decision.
4. To generate the branch address, it is required to know the status of the condition codes
and status flag.
5. To generate the starting address, we need the instruction which is present in IR. But for
branch address generation we have to check the content of condition codes and status
flag.

12. List and briefly discuss the types of pipeline hazard

Pipeline hazards are situations that prevent the next instruction in the instruction stream from
executing during its designated clock cycles.

Any condition that causes a stall in the pipeline operations can be called a hazard.

There are primarily three types of hazards:

i. Data Hazards
ii. Control Hazards or instruction Hazards
iii. Structural Hazards.
i. Data Hazards:
A data hazard is any condition in which either the source or the destination operands of an
instruction are not available at the time expected in the pipeline. As a result of which some
operation has to be delayed and the pipeline stalls. It can occur whenever there are two
instructions one of which depends on the data obtained from the other.
ii. Structural Hazards:
This situation arises mainly when two instructions require a given hardware resource at the
same time and hence for one of the instructions the pipeline needs to be stalled.
The most common case is when memory is accessed at the same time by two instructions.
One instruction may need to access the memory as part of the Execute or Write back phase
while other instruction is being fetched. In this case if both the instructions and data reside in
the same memory. Both the instructions can’t proceed together and one of them needs to be
stalled till the other is done with the memory access part.
iii. Control hazards:
The instruction fetch unit of the CPU is responsible for providing a stream of instructions to
the execution unit. The instructions fetched by the fetch unit are in consecutive memory
locations and they are executed.
However the problem arises when one of the instructions is a branching instruction to some
other memory location. Thus all the instruction fetched in the pipeline from consecutive
memory locations are invalid now and need to removed.This induces a stall till new
instructions are again fetched from the memory address specified in the branch instruction.
13. What are the problems faced in instruction pipeline
There are two overarching issues with the pipelining of instructions.

1. You want the pipeline to always be full and never to have to empty it. This
means that sometimes you have to fill it with instructions when you don’t
know yet what the next instructions will be. You also want to make sure
that when an instruction reaches the execution stage you also have the data
ready otherwise you would stall.
2. You want your computer architecture to still execute programs in the way
the programmers intended. The techniques you use to make the pipelining
work (better) cannot change the semantics of the code.

14. Write an algorithm for the division of floating-point number and illustrate with an
example.
1) If divisor X2 = zero then set the result to "infinity", if both X1 and X2 are zero's set it to
"NAN"
2) Sign bit S3 = (S1 xor S1).
3) Find mantissa by dividing M1/M2
4) Exponent E3 = (E1 - E2) + bias
5) Normalize if required, i.e by left shifting the mantissa and decrementing the resultant
exponent.
6) Check for overflow/underflow
If E3 > Emax return overflow i.e. "infinity"
If E3 < Emin return underflow i.e. zero
Example:
X1=127.03125
X2=16.9375

1) S3 = S1 xor S2 = 0
2) E3 = (E1 - E2) + bias = (10000101) - (10000011)+ (1111111)
= 133-131+127 => 129 => (10000001)
3) Divide the mantissas M1/M2
4) Result

X3 in decimal = 7.5

15. Differentiate between Synchronous and Asynchronous bus.

1.Synchronous bus:
Transmitter and receivers are synchronized of clock.
Data bits are transmitted with synchronization of clock.
Character is received at constant Rate.
Data transfer takes place in block.
Start and stop bit are required to establish communication of each character.
Used in high – speed transmission

2.Asynchronous bus:
Transmitters and receivers are not synchronized by clock.
Bit’s of data are transmitted at constant rate.
Character may arrive at any rate at receiver.
Data transfer is character oriented.
Start and stop bits are required to establish communication of each character.
Used in low – speed transmission.
16. Draw the diagram of a bus system with three states buffers and decoders.

17. Show the use of one address, two address and zero address instruction to compute
Y= (A-B)/(C*D)