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A) Von Neumann Architecture

The Von Neumann architecture has three main components: a central processing unit (CPU) consisting of a control unit, arithmetic logic unit (ALU), and registers; a main memory system that holds programs; and an input/output (I/O) system. It operates by fetching instructions from memory, decoding and executing them using the ALU, and fetching any required data from memory into registers. SPARC (Scalable Processor Architecture) was designed for optimizing compilers and efficient hardware implementations. It allows implementations to scale from embedded systems to servers. SPARC uses register windows, delay slots, and registers/stack to pass arguments. It has integer and floating point units that use registers to perform operations.

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58 views

A) Von Neumann Architecture

The Von Neumann architecture has three main components: a central processing unit (CPU) consisting of a control unit, arithmetic logic unit (ALU), and registers; a main memory system that holds programs; and an input/output (I/O) system. It operates by fetching instructions from memory, decoding and executing them using the ALU, and fetching any required data from memory into registers. SPARC (Scalable Processor Architecture) was designed for optimizing compilers and efficient hardware implementations. It allows implementations to scale from embedded systems to servers. SPARC uses register windows, delay slots, and registers/stack to pass arguments. It has integer and floating point units that use registers to perform operations.

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driftwood 069
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A) VON NEUMANN ARCHITECTURE

Von-Neumann architecture has the following basic characteristics:

• Consists of three hardware systems: A central processing unit (CPU) (which consists of a control unit,
an arithmetic logic unit (ALU), registers (small storage areas), and a program counter);

a main-memory system, which holds programs that control the computer’s operation; and

an I/O system.

• Capacity to carry out sequential instruction processing

• Contains a single path, either physically or logically, between the main memory system and the control
unit of the CPU, forcing alternation of instruction and execution cycles. This single path is often referred
to as the von Neumann bottleneck.

MODE OF OPERATION

MODE OF OPERATION

1. The control unit fetches the next program instruction from the memory, using the program counter to
determine where the instruction is located.

2. The instruction is decoded into a language the ALU can understand.

3. Any data operands required to execute the instruction are fetched from memory and placed into
registers within the CPU.
4. The ALU executes the instruction and places the results in registers or memory

B) SPARC stands for Scalable Processor Architecture

SPARC was designed as a target for optimizing compilers and easily pipelined hardware
implementations. SPARC implementations provide exceptionally high execution rates (MIPS)
and short time-to-market development schedules.

Provide the scalability of the cost/performance ratio of successive implementations with the
current improvements in circuit technology.

The "Scalable" in SPARC comes from the fact that the SPARC specification allows
implementations to scale from processors required in embedded systems to processors used for
servers.

It is a Load and store architecture. Operations are always done over registers.

Uses “register window” concept thus offering a large number of registers.

Uses delay slot to optimize branch instruction.

Passes arguments using registers and the stack.

Integer Unit

Contains the general-purpose registers and controls the overall operation of the processor.

It may contain from 64 to 528 general-purpose 64-bit r registers. They are partitioned into
8 global registers, 8 alternate global registers, plus a circular stack of from 3 to 32 sets of
16 registers each, known as register windows.
Executes the integer arithmetic instructions and computes memory addresses for loads
and stores. -Maintains the program counters and controls instruction execution for the
FPU.
Floating Point Unit

The FPU has 32-bit (single-precision) floating-point registers, 64-bit (double-precision)


floating-point registers, and 128-bit (quad-precision) floating-point registers.

Double-precision values occupy an even-odd pair of single-precision registers.

Quad-precision values occupy an odd-even number pair of double precision registers.

Floating-point load/store instructions are used to move data between the FPU and
memory.

The memory address is calculated by the IU.

Floating-Point operate instructions perform the floating-point arithmetic operations and


comparisons.
Coprocessor Unit

The instruction set includes support for a single, implementation-dependent coprocessor.


The coprocessor has its own set of registers.

Coprocessor load/store instructions are used to move data between the coprocessor
registers and memory floating-point instructions mirrors coprocessor instructions.

MEMBERS:
JAPHALY, GADAFI J 2020-04-02654
MAGEMBE, DAUD K 2020-04-05183
MUTEKANGA, ANDOCIUS 2020-04-08516

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