Cpe G4

CPE 301 PRACTICAL REPORT
FOR
GROUP 4
14TH MARCH, 2021.

STUDENTS IN GROUP 4
1. FRANCIS-ALFRED MICHAELANGELO IFEANYI ------------------------- CPE/16/7838
2. JOHN ABUTU EZEKIEL ---------------------------------------------------------- CPE/16/7844
3. ERINLE FOLASADE MARY ----------------------------------------------------- CPE/16/7830
4. EZEOKOLI GOODNESS ---------------------------------------------------------- CPE/16/7833
5. ADESOLAPE OGEDENGBE ----------------------------------------------------- CPE/16/7854
6. AWOSEMO COMFORT OLUWAFUNMILAYO ----------------------------- CPE/16/7817
7. OWONIPA BABAJIDE JOSEPH ------------------------------------------------- CPE/16/7871
8. ABUBAKAR AHMED ABIODUN ----------------------------------------------- CPE/16/7795
9. ODESHILE OYINKANSAYO ABDULSABU --------------------------------- CPE/16/7852
10. ARINOLA DANIEL .O. ------------------------------------------------------------ CPE/16/7815
11. OYAWOYE ISEOLUWA AYOMIDE ------------------------------------------- CPE/16/7872
12. FAKUNLE SAMSON .A. ---------------------------------------------------------- CPE/16/7834
13. KEHINDE DOYINSOLA ADEGBOLA ----------------------------------------- CPE/16/7845
14. ADESIDA ADEMOLA MICHAEL ----------------------------------------------- CPE/16/7805
15. ADEDARA OLUWAFEMI MAYOWA ----------------------------------------- CPE/16/7797
16. ADEYEMO ADEDOYIN ENIOLA ---------------------------------------------- CPE/16/7806
17. OMOSULE BABATUNDE O. ---------------------------------------------------- CPE/16/7867
18. NABENA ANNABEL -------------------------------------------------------------- CPE/16/7849
19. MEDU EMMANUEL OGENEOCHUKO --------------------------------------- CPE/16/7848
20. ABIOYE TOMIWA SUNDAY ---------------------------------------------------- CPE/16/7794
21. ADENIYI TOFUNWA RICHARD ----------------------------------------------- CPE/16/7800
22. DAPO-OSALUSI TOMILADE ---------------------------------------------------- CPE/16/7826
23. IBE MICHAEL OLUWATIMILEHIN ------------------------------------------ CPE/16/7840
24. AJAYI KEHINDE SOLOMON ---------------------------------------------------- CPE/16/7808
25. ADU ADERONKE ADEDOYIN -------------------------------------------------- CPE/16/7807
26. BERNARD VICTOR ---------------------------------------------------------------- CPE/16/7823
27. OMOTUNDE OLUWATOBILOBA O ------------------------------------------- CPE/16/7868
28. KENECHUKWU OKECHUKWU ------------------------------------------------ CPE/16/7859
29. BENJAMIN EHIMARE DAMILARE -------------------------------------------- CPE/16/7822
30. ARAOYE ADEDAMOLA EMMANUEL --------------------------------------- CPE/15/2396
31. NDUKWE DAVID KANMA ------------------------------------------------------ CPE/15/2431
AIM AND OBJECTIVES
AIM
Building a BCD – a 7-Segment Decoder Using VERY HIGH SPEED INTERGRATION
HARDWARE DESCRIPTION LANGUAGE (VHDL) Code.
OBJECTIVES
• To design a BCD – a 7-segment decoder using VHDL coding.
• To show the truth table for this design.
• To show the 7-segment decoder display circuit and its Boolean expressions.
• To also show the VHDL Code using combinational logic and case statement.
APPARATUS:
1. Field Programmable Gate Array (FPGA).
2. Programmable Logic Devices (PLDs).
3. Computer Aided Design (CAD) Tool eg; Cyclone IV.
PROBLEM ANALYSIS:
The BCD to 7 Segment Decoder converts 4 bit binary to 7 bit control signal which can be
displayed on a 7 segment display. The 7 segment display consist of 7 LED Segments to display
the number 0 to 9 to F.
FIG 1.1: A BCD – 7 SEGMENT DISPLAY AND THE ACTUAL 7 SEGEMENT

ARRANGEMENT.
PROCEDURE
VHDL Code of BCD to 7 segment display decoder can be implemented by simplifying the
Boolean expression to implement structural and behavioural design.
To construct BCD to 7 segment display, first construct the truth table and simplify them to
Boolean expression using K Map, then finally build the combinational circuit.
TRUTH TABLE SHOWING THE INPUT AND OUTPUT VALUES OF A BCD – 7

SEGMENT DISPLAY DECODER.
B3 B2 B1 B0 ABCDEFG
0000 0000001
0001 1001111
0010 0010010
0011 0000110
0100 1001100
0101 0100100
0110 0100000
0111 0001111
1000 0000000
1001 0000100
CIRCUIT DIAGRAM: The circuit diagram above was sniped from Cyclone IV and it is made up
7 OR GATES, 9 AND GATES and 4 NOT GATES (acting as INVERTERS).
FIG 1.2: BCD TO 7 SEGMENT DISPLAY DECODER LOGIC CIRCUIT DIAGRAM.

BOOLEAN EXPRESSION FOR THE ABOVE CIRUIT DIAGRAM
A = B0 + B2 + B1B3 + B1'B3
B = B1' + B2'B3' + B2B3
C = B1 + B2' + B3
D = B1'B3' + B2B3' + B1B2'B3 + B1'B2 + B0
E = B1'B3' + B2B3'
F = B0 + B2'B3' + B1B2' + B1B3'
G = B0 + B1B2' + B1'B2 + b2b3'
CODE
• VHDL CODE FOR A BCD TO 7 SEGMENT DISPLAY DECODER USING
COMBINATORIAL LOGIC.
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
entity bcd_7seg is
Port ( B0,B1,B2,B3 : in STD_LOGIC;
A,B,C,D,E,F,G : out STD_LOGIC);
end bcd_7seg;
architecture Behavioral of bcd_7seg is
begin
A <= B0 OR B2 OR (B1 AND B3) OR (NOT B1 AND NOT B3);

B <= (NOT B1) OR (NOT B2 AND NOT B3) OR (B2 AND B3);
C <= B1 OR NOT B2 OR B3;
D <=
(NOT B1 AND NOT B3) OR (B2 AND NOT B3) OR (B1 AND NOT B2 AND B3) OR (NOT B1 AND B2) OR
B0;
E <= (NOT B1 AND NOT B3) OR (B2 AND NOT B3);
F <= B0 OR (NOT B2 AND NOT B3) OR (B1 AND NOT B2) OR (B1 AND NOT B3);
G <= B0 OR (B1 AND NOT B2) OR ( NOT B1 AND B2) OR (B2 AND NOT B3);
end Behavioral;
• VHDL CODE FOR A BCD TO 7 SEGMENT DISPLAY DECODEE USING CASE

STATEMENT.
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
entity bcd_7segment is
Port ( BCDin : in STD_LOGIC_VECTOR (3 downto 0);
Seven_Segment : out STD_LOGIC_VECTOR (6 downto 0));
end bcd_7segment;
architecture Behavioral of bcd_7segment is
begin
process(BCDin)
begin
case BCDin is
when "0000" =>
Seven_Segment <= "0000001"; – -0
when "0001" =>
Seven_Segment <= "1001111"; – -1
when "0010" =>
Seven_Segment <= "0010010"; – -2
when "0011" =>
Seven_Segment <= "0000110"; – -3
when "0100" =>
Seven_Segment <= "1001100"; – -4
when "0101" =>
Seven_Segment <= "0100100"; – -5
when "0110" =>
Seven_Segment <= "0100000"; – -6
when "0111" =>
Seven_Segment <= "0001111"; – -7
when "1000" =>
Seven_Segment <= "0000000"; – -8
when "1001" =>
Seven_Segment <= "0000100"; – -9
when others =>
Seven_Segment <= "1111111"; – -null

end case;
end process;
end Behavioral;
WAVEFORM FOR A BCD TO 7 SEGMENT DISPLAY DECODER.
To get the waveform for this design, we had to write a VHDL TESTBENCH Code for the
design.
VHDL TESTBENCH CODE:
LIBRARY ieee;
USE ieee.std_logic_1164.ALL;
ENTITY tb_bcd_7seg IS
END tb_bcd_7seg;
ARCHITECTURE behavior OF tb_bcd_7seg IS
– Component Declaration for the Unit Under Test (UUT)
COMPONENT bcd_7segment
PORT(
BCDin : IN std_logic_vector(3 downto 0);
Seven_Segment : OUT std_logic_vector(6 downto 0)
);
END COMPONENT;
--Inputs
signal BCDin : std_logic_vector(3 downto 0) := (others => '0');
--Outputs
signal Seven_Segment : std_logic_vector(6 downto 0);
BEGIN
– Instantiate the Unit Under Test (UUT)
uut: bcd_7segment PORT MAP (
BCDin => BCDin,
Seven_Segment => Seven_Segment
);
– Stimulus process
stim_proc: process
begin
BCDin <= "0000";
wait for 100 ns;
BCDin <= "0001";
wait for 100 ns;
BCDin <= "0010";
wait for 100 ns;
BCDin <= "0011";
wait for 100 ns;

BCDin <= "0100";
wait for 100 ns;
BCDin <= "0101";
wait for 100 ns;
BCDin <= "0110";
wait for 100 ns;
BCDin <= "0111";
wait for 100 ns;
BCDin <= "1000";
wait for 100 ns;
BCDin <= "1001";
wait for 100 ns;
end process;
END;
FIG 1.3: WAVEFORM OUTPUT FOR A BCD TO 7 SEGMENT DISPLAY DECODER

USING VHDL TESTBENCH.

Cpe G4

Uploaded by

Copyright:

Available Formats

Cpe G4

Uploaded by

Document Information

Original Title

Copyright

Available Formats

Share this document

Share or Embed Document

Sharing Options

Did you find this document useful?

Is this content inappropriate?

Copyright:

Available Formats

Cpe G4

Uploaded by

Copyright:

Available Formats

CPE 301 PRACTICAL REPORT

14TH MARCH, 2021.

FIG 1.1: A BCD – 7 SEGMENT DISPLAY AND THE ACTUAL 7 SEGEMENT

TRUTH TABLE SHOWING THE INPUT AND OUTPUT VALUES OF A BCD – 7

FIG 1.2: BCD TO 7 SEGMENT DISPLAY DECODER LOGIC CIRCUIT DIAGRAM.

Port ( B0,B1,B2,B3 : in STD_LOGIC;

A,B,C,D,E,F,G : out STD_LOGIC);

architecture Behavioral of bcd_7seg is

A <= B0 OR B2 OR (B1 AND B3) OR (NOT B1 AND NOT B3);

C <= B1 OR NOT B2 OR B3;

E <= (NOT B1 AND NOT B3) OR (B2 AND NOT B3);

• VHDL CODE FOR A BCD TO 7 SEGMENT DISPLAY DECODEE USING CASE

Port ( BCDin : in STD_LOGIC_VECTOR (3 downto 0);

Seven_Segment : out STD_LOGIC_VECTOR (6 downto 0));

architecture Behavioral of bcd_7segment is

when "0000" =>

Seven_Segment <= "0000001"; – -0

when "0001" =>

Seven_Segment <= "1001111"; – -1

when "0010" =>

Seven_Segment <= "0010010"; – -2

when "0011" =>

Seven_Segment <= "0000110"; – -3

when "0100" =>

Seven_Segment <= "1001100"; – -4

when "0101" =>

Seven_Segment <= "0100100"; – -5

when "0110" =>

Seven_Segment <= "0100000"; – -6

when "0111" =>

Seven_Segment <= "0001111"; – -7

when "1000" =>

Seven_Segment <= "0000000"; – -8

when "1001" =>

Seven_Segment <= "0000100"; – -9

when others =>

Seven_Segment <= "1111111"; – -null

VHDL TESTBENCH CODE:

ARCHITECTURE behavior OF tb_bcd_7seg IS

– Component Declaration for the Unit Under Test (UUT)

BCDin : IN std_logic_vector(3 downto 0);

Seven_Segment : OUT std_logic_vector(6 downto 0)

signal Seven_Segment : std_logic_vector(6 downto 0);

– Instantiate the Unit Under Test (UUT)

uut: bcd_7segment PORT MAP (

BCDin => BCDin,

Seven_Segment => Seven_Segment

BCDin <= "0000";

wait for 100 ns;

BCDin <= "0001";

wait for 100 ns;

BCDin <= "0010";

wait for 100 ns;

BCDin <= "0011";

wait for 100 ns;

wait for 100 ns;

BCDin <= "0101";

wait for 100 ns;

BCDin <= "0110";