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    M.Tech (MVD)

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    rishi teju
    This document outlines a course on Advanced Computer Architecture. The course aims to introduce advanced concepts of computer architecture, knowledge of interconnect topologies for multiprocessor systems, and memory hierarchies for multiprocessor/multicomputer systems. Expected outcomes include understanding multiprocessor/multicomputer architecture, identifying parallel execution, designing interconnects, applying pipelining techniques, and analyzing memory designs. The course contains 8 modules covering topics such as parallel computer models, program properties, interconnect architectures, pipelining, memory hierarchy design, shared memory architectures, and contemporary issues. Student learning outcomes involve the ability to apply mathematics/science and design thinking capability.

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    M.Tech (MVD)

    Uploaded by

    rishi teju
    42 views2 pages
    This document outlines a course on Advanced Computer Architecture. The course aims to introduce advanced concepts of computer architecture, knowledge of interconnect topologies for multiprocessor systems, and memory hierarchies for multiprocessor/multicomputer systems. Expected outcomes include understanding multiprocessor/multicomputer architecture, identifying parallel execution, designing interconnects, applying pipelining techniques, and analyzing memory designs. The course contains 8 modules covering topics such as parallel computer models, program properties, interconnect architectures, pipelining, memory hierarchy design, shared memory architectures, and contemporary issues. Student learning outcomes involve the ability to apply mathematics/science and design thinking capability.

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    This document outlines a course on Advanced Computer Architecture. The course aims to introduce advanced concepts of computer architecture, knowledge of interconnect topologies for multiprocessor systems, and memory hierarchies for multiprocessor/multicomputer systems. Expected outcomes include understanding multiprocessor/multicomputer architecture, identifying parallel execution, designing interconnects, applying pipelining techniques, and analyzing memory designs. The course contains 8 modules covering topics such as parallel computer models, program properties, interconnect architectures, pipelining, memory hierarchy design, shared memory architectures, and contemporary issues. Student learning outcomes involve the ability to apply mathematics/science and design thinking capability.

    Copyright:

    © All Rights Reserved
    Download as PDF, TXT or read online from Scribd
    Download as pdf or txt
    42 views2 pages

    M.Tech (MVD)

    Uploaded by

    rishi teju
    This document outlines a course on Advanced Computer Architecture. The course aims to introduce advanced concepts of computer architecture, knowledge of interconnect topologies for multiprocessor systems, and memory hierarchies for multiprocessor/multicomputer systems. Expected outcomes include understanding multiprocessor/multicomputer architecture, identifying parallel execution, designing interconnects, applying pipelining techniques, and analyzing memory designs. The course contains 8 modules covering topics such as parallel computer models, program properties, interconnect architectures, pipelining, memory hierarchy design, shared memory architectures, and contemporary issues. Student learning outcomes involve the ability to apply mathematics/science and design thinking capability.

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    Course Code Course Title L T P J C

    ECE5027 ADVANCED COMPUTER ARCHITECTURE 3 0 0 0 3


    Pre-requisite Nil

    Course Objective :
    The course is aimed to
    1. Introduce advanced concepts of computer architecture.
    2. Acquire knowledge on various interconnect topology for multiprocessor system and
    different pipelining techniques.
    3. Understanding different memory hierarchy for multiprocessor and multicomputer systems.

    Expected Course Outcomes:


    At the end of the course the student will be able to:
    1. Understand the architecture of the various multiprocessors and multicomputer.
    2. Identify possible parallel execution at hardware and software level.
    3. Design required static or dynamic interconnect network for a multiprocessor system.
    4. Apply different pipelining techniques to reduce computation time.
    5. Analyse the various memory design for multiprocessor and multicomputer.
    6. Design scalable parallel architecture for multiprocessor system.

    Student Learning Outcomes (SLO): 1,5


    1. Ability to apply mathematics and science in engineering applications
    5. Design thinking capability
    Module:1 Parallel computer models 3 hours
    cThe state of computing - Classification of parallel computers - Multiprocessors and
    Multicomputer - Multivector and SIMD computers.

    Module:2 Program and network properties 7 hours


    Conditions of parallelism - Data and resource Dependences - Hardware and software parallelism -
    Program partitioning and scheduling - Grain Size and latency - Program flow mechanisms -
    Control flow vs data flow - Data flow Architectures.

    Module:3 System Interconnect Architectures 7 hours


    Network properties and routing - Static interconnection Networks - Dynamic interconnection
    Networks - Multiprocessor system Interconnects - Hierarchical bus systems - Crossbar switch and
    multiport memory - Multistage and combining network.

    Module:4 Pipelining 7 hours


    Linear pipeline processor - nonlinear pipeline processor - Instruction pipeline Design -
    Mechanisms for instruction pipelining - Dynamic instruction scheduling - Branch Handling
    techniques - branch prediction - Arithmetic Pipeline Design

    Module:5 Memory Hierarchy Design 6 hours


    Cache basics & cache performance - reducing miss rate and miss penalty - multilevel cache
    hierarchies - main memory organizations - design of memory hierarchies.

    Module:6 Shared Memory Architectures 7 hours

    Symmetric shared memory architectures - distributed shared memory architectures - cache

    M.TECH (MVD) Page 36


    coherence protocols - scalable cache coherence - directory protocols - memory based directory
    protocols - cache based directory protocols.

    Module:7 Multiprocessor Architectures 6 hours


    Computational models - An Argument for parallel Architectures - Scalability of Parallel
    Architectures - Benchmark Performances.

    Module:8 Contemporary issues: 2 hours

    Total Lecture hours: 45 hours


    Text Book(s)
    1. Kai Hwang, NareshJotwani, Advanced Computer Architecture: Parallelism, Scalability,
    Programmability,Tata McGraw Hill Education Pvt. Ltd., India, Second Edition, 2011.
    Reference Books
    1. John L. Hennessy, David A. Patterson, Computer Architecture: A Quantitative Approach,
    Morgan Kaufmann, Fifth Edition, 2011.
    2. DezsoSima, Terence Fountain, PeterrKarsuk Advanced computer Architectures – A Design
    Space Approach, Pearson, 2014.
    Mode of Evaluation:Continuous Assessment Test –I (CAT-I) , Continuous Assessment Test –II
    (CAT-II), Seminar / Challenging Assignments / Completion of MOOC / Innovative ideas leading
    to solutions for industrial problems, Final Assessment Test (FAT).
    Recommended by Board of Studies 13-12-2015
    Approved by Academic Council No. 40 18-03-2016

    M.TECH (MVD) Page 37

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