Sem 3

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B.Sc. Electronics - III Semester – Paper- 3

DIGITAL ELECTRONICS
UNIT- I
NUMBER SYSTEM AND CODES
Number System:
A set of values used to represent different quantities is known as Number
System. For example, a number system can be used to represent the number of
students in a class or number of viewers watching a certain TV program etc. The
digital computer represents all kinds of data and information in binary numbers. It
includes audio, graphics, video, text and numbers.
There are mainly 2 types of Number Systems.
1. Non Positional Number System
2. Positional Number System
Roman Numbers are examples of the Non Positional Number System. This
is quite difficult to use and has no symbol for Zero. Ex: I, II, III, V, L, C… etc.
The most widely used number system is Positional Number System. The
total number of digits used in a number system is called its base or radix. The base
is written after the number as subscript. The weight of a digit in number depends on
its relative position with in the number.
Some important number systems are as follows.
Number System Base Digits
 Decimal number system 10 0,1,2,3,4,5,6,7,8,9
 Binary number system 2 0,1
 Octal number system 8 0,1,2,3,4,5,6,7
 Hexadecimal number system 16 0,1,2,3,4,5,6,7,8,9,A,B,C,D,E,F
The decimal number system is used in general. However, the computers use
binary number system. The octal and hexadecimal number systems are also used
in the computer.
Decimal number System
The Decimal Number System consists of ten digits from 0 to 9. These digits
can be used to represent any numeric value. The base of decimal number system
is 10. It is the most widely used number system. The value represented by
individual digit depends on weight and position of the digit.
The value of the number is determined by multiplying the digits with the
weight of their position and adding the results. This method is known as expansion
method.
The weights and positions of each digit of the number 453 are as follows:
The value of digit 4 = 4 x100 = 400
B.Sc. Electronics R L V P rasad, Sr. Lect in Electronics, SGCSR College, Rajam

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Binary Number System

Digital computer represents all kinds of data and information in the binary
system. Binary Number System consists of two digits 0 and 1. Its base is 2. Each
digit or bit in binary number system can be 0 or 1. A combination of binary numbers
may be used to represent different quantities like 1001. The weight of each position
is a power of 2.
Ex: Convert binary no. (10111)2 to decimal no.
24 23 22 21 2 0
1 0 1 1 1
= 20 x 1 + 2 1 x 1 + 22 x 1+ 2 3 x0 + 24 x 1
= 1 x 1 + 2 x 1 + 4 x1 + 8 x 0 + 16 x 1
= 1 + 2 + 4 + 0 + 16
= 2310
Ex: Convert (101.101)2 to decimal no.
22 21 20 2-1 2-2 2-3
1 0 1 .1 0 1
= 1 x 2 + 0 x21 + 1 x 20 + 1 x 2-1 + 0 x 2-2 + 1 x 2-3
2
= 1 x 4 + 0 + 1 x 1 + ½ + 0 + 1/8
= 4 + 0 + 1 + 0.5 + 0.125
= 5.62510
Octal Number System
Octal Number System consists of eight digits from 0 to 7. The base of octal
system is 8. Each digit position in this system represents a power of 8. Any digit in
this system is always less than 8. Octal number system is used as a shorthand
representation of long binary numbers. The number 6418 is not valid in this number
system as 8 is not a valid digit.
Ex : convert 458 to decimal number
458 = 4 x 81 + 5 x 80
= 4 x 8 + 5 x1
= 32 + 5
= 3710
Hexadecimal number system
The Hexadecimal Number System consists of 16 digits from 0 to 9 and A to
F. The alphabets A to F represent decimal numbers from 10 to 15. The base of this
number system is 16. Each digit position in hexadecimal system represents a
power of 16. The number 764 16 is valid hexadecimal number. It is different from
76410 which is seven hundred and sixty four. This number system provides shortcut
method to represent long binary numbers.
Ex: Convert 3 A16 to decimal number
3A16 = 3 x 161 + A x 160
= 3 x 16 + 10 x 1
= 48 + 10 = 5810

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NUMBER SYSTEM CONVERSION

Decimal to Other Base System
Step 1 − Divide the decimal number to be converted by the value of the new base.
Step 2 − Get the remainder from Step 1 as the rightmost digit least significant digit
of new base number.
Step 3 − Divide the quotient of the previous divide by the new base.
Step 4 − Record the remainder from Step 3 as the next digit to the left of the new
base number.
Repeat Steps 3 and 4, getting remainders from right to left, until the quotient
becomes zero in Step 3.
The last remainder thus obtained will be the Most Significant Digit MSD of the new
base number.
Binary to Octal
Step 1 − Divide the binary digits into groups of three starting from the right.
Step 2 − Convert each group of three binary digits to one octal digit.
Ex: Convert Binary no. 1101010 2 to octal no.
001 101 010
1 5 2
1101010 2 = 1528
Octal to Binary
Step 1 − Convert each octal digit to a 3 digit binary number
Step 2 − Combine all the resulting binary groups of 3 digits each into a single binary
number.
Ex: Convert octal no. 3548 to Binary no.
3 5 4
011 101 100
3548 = 011101100 2
Binary to Hexadecimal
Step 1 − Divide the binary digits into groups of four starting from the right.
Step 2 − Convert each group of four binary digits to one hexadecimal symbol.
Ex: Convert Binary no. 1101010 2 to Hexadecimal no.
0110 1010
6 A
1101010 2 = 6A16

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Hexadecimal to Binary
Step 1 − Convert each hexadecimal digit to a 4 digit binary number
Step 2 − Combine all the resulting binary groups of 4digits each into a single binary
number.
Ex: Convert Hexadecimal no. 6A416 to Binary no.
6 A 4
0110 1010 0100
6A416 = 011010100100 2
CODES
When numbers, letters or words are represented by a specific group of
symbols, the group of symbols is called as a code. The digital data is represented,
stored and transmitted as group of binary bits. This group is also called as binary
code. The binary code is represented by the number as well as alphanumeric letter.
Advantages of Binary Code
 Binary codes are suitable for the computer applications.
 Binary codes are suitable for the digital communications.
 Binary codes make the analysis and designing of digital circuits.
 Since only 0 & 1 are being used, implementation becomes easy.
Binary Coded Decimal (BCD) code
In this code each decimal digit is represented by a 4-bit binary number. BCD
is a way to express each of the decimal digits with a binary code. In the BCD, with
four bits we can represent sixteen numbers (0000 to 1111). But in BCD code only
first ten of these are used (0000 to 1001). The remaining six code combinations i.e.
1010 to 1111 are invalid in BCD.
The most common BCD code is the 8421 BCD code. In this, the BCD
equivalent of a decimal number is written by replacing each decimal digit in integer
and fractional parts with its four-bit binary equivalent '(or nibble). Here 8, 4, 2 and 1
represent the weights of different bits in the four-bit groups.
Decimal
0 1 2 3 4 5 6 7 8 9
digit
BCD
0000 0001 0010 0011 0100 0101 0110 0111 1000 1001
Code
Advantages of BCD Codes
 It is very similar to decimal system.
 We need to remember binary equivalent of decimal numbers 0 to 9 only.
Disadvantages of BCD Codes
 The addition and subtraction of BCD have different rules.
 The BCD arithmetic is little more complicated.
 BCD needs more number of bits than binary to represent the decimal
number. So BCD is less efficient than binary.

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BCD-to-Binary Conversion
A given BCD number can be converted into an equivalent binary number by
first writing its decimal equivalent and then converting it into its binary equivalent.
Example: Find the binary equivalent of the BCD number 0010 1001 . 0111 0101
BCD number : 0010 1001.0111 0101
Corresponding decimal number : 29.75
The binary equivalent of 29.75 is 11101 for the integer part and .11 for the
fractional part.
Therefore, (0010 1001.0111 0101)BCD = (11101.11)2.
Binary-to-BCD Conversion
The process of binary-to-BCD conversion is the same as the process of
BCD-to-binary conversion executed in reverse order. A given binary number can be
converted into an equivalent BCD number by first determining its decimal
equivalent and then writing the corresponding BCD equivalent.
Example: Find the BCD equivalent of the binary number 10101011.101
The decimal equivalent of this binary number can be determined to be
171.625.
The BCD equivalent can then be written as 0001 0111 0001.0110 0010 0101.
Excess-3 code
The Excess-3 code is also called as XS-3 code. It is non-weighted code
used to express decimal numbers. The Excess-3 code words are derived from the
8421 BCD code words adding (0011)2 or (3)10 to each code word in 8421. The
excess-3 codes are obtained as follows −
BCD Excess – 3
Decimal
8421 BCD+0011
0 0000 0011
1 0001 0100
2 0010 0101
3 0011 0110
4 0100 0111
5 0101 1000
6 0110 1001
7 0111 1010
8 1000 1011
9 1001 1100

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Ex: Convert Decimal number 25 to excess-3 code:

First, add 3 to each digit in the decimal number, and then convert each digit to its
equivalent 4 bit binary code
25  25 + 33 = 58
Excess 3 code is 0101 1000
Gray Code
The Gray code was designed by Frank Gray at Bell Labs and patented in
1953. It is the non-weighted code and it is not arithmetic codes. That means there
are no specific weights assigned to the bit position. It has a very special feature
that, only one bit will change each time the decimal number is incremented as
shown in table. As only one bit changes at a time, the gray code is called as a unit
distance code. The gray code is a cyclic code. Gray code cannot be used for
arithmetic operation.
Decimal Binary code Gray code
0 0000 0000
1 0001 0001
2 0010 0011
3 0011 0010
4 0100 0110
5 0101 0111
6 0110 0101
7 0111 0100
8 1000 1100
9 1001 1101
Application of Gra y code

 The Gray code is used in the transmission of digital signals as it minimizes
the occurrence of errors.
 The Gray code is preferred over the straight binary code in angle-measuring
devices.
 The Gray code is used for labeling the axes of Karnaugh maps, a graphical
technique used for minimization of Boolean expressions.
 The use of Gray codes to address program memory in computers minimizes
power consumption.
Binary to Gray Code Conversion
A gi ven binary number can be converted into its Gray code equivalent by
going through the following steps:
 Begin with the most significant bit (MSB) of the binary number. The MSB of
the Gray code equivalent is the same as the MSB of the given binary
number.
 The second most significant bit, adjacent to the MSB, in the Gray code
number is obtained by adding the MSB and the second MSB of the binary
number and ignoring the carry, if any. That is, if the MSB and the bit adjacent
to it are both ‘1’, then the corresponding Gray code bit would be a ‘0’.

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 The third most significant bit, adjacent to the second MSB, in the Gray code
number is obtained by adding the second MSB and the third MSB in the
binary number and ignoring the carry, if any.
 The process continues until we obtain the LSB of the Gray code number by
the addition of the LSB and the next higher adjacent bit of the binary
number.
Binary No : 11101
Gray code : 10011
Gray Code to Binary Conversion
A gi ven Gray code number can be converted into its binary equivalent by
going through the following steps:
 Begin with the most significant bit (MSB). The MSB of the binary number is
the same as the MSB of the Gray code number.
 The bit next to the MSB (the second MSB) in the binary number is obtained
by adding the MSB in the binary number to the second MSB in the Gray
code number and ignoring the carry, if an y.
 The third MSB in the binary number is obtained by adding the second MSB
in the binary number to the third MSB in the Gra y code number. Again, carry,
if any, is to be ignored.
 The process continues until we obtain the LSB of the binary number.
Gray code : 10011

Binary No : 11101
ASCII code
The code ASCII stands for American Standard Code for Information
Interchange and this is pronounced as ‘ask-ee’. They are used to represent
alphanumeric data in computers, communication equipment in electronic device to
represent the input and output in a more scientific manner. In 1967 this code was
first published as a standard.
It is able to represent 27 = 128 codes as it is a seven bit code. Currently a
total number of 95 printable characters are represented by this code including 26
upper case letters (A - Z), 26 lower case letters (a - z), 10 numerals (0 - 9) and
there are 33 special characters which include mathematical symbols, punctuation

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marks and space characters. The latest development in the field of ASCII code is
the development of 8 bit code which is known as US ASCII-8 or ASCII-8. As it is an
8 bit code it can represent 2 8 = 256 characters. Some of the ASCII codes are given
below.
6- 36H, A- 41H, a – 61H ..... etc.
Binary Addition
Binary arithmetic is essential part of all the digital computers and many other
digital systems.
101010011
010011010
111101101
Binary Subtraction
101010011
010011010
010111001
Binary Subtraction using complement methods
Complements are used in the digital computers in order to simplify the
subtraction operation. As the binary system has base2. So the two types of
complements for the binary system are 2's complement and 1's complement.
1's complement
The 1's complement of a number is found by changing all 1s to 0s and all 0s to 1s.
1's Complement = 2n – r - 1
n – No. of digits in given no, r – given no.
Ex. 1's Complement of 01011011 is 10100100
Subtraction using 1's complement
Note: If the number of bits in the subtrahend and minuend not equal, we
must make them equal in numbers of bits by taking 0s at left side
The steps to be followed in subtraction by 1’s complement are:
1. Write down 1's complement of the subtrahend.
2. Add this with the minuend.
3. If the result of addition has a carry over then it is dropped and 1 is added in the
last bit(End Around Carry - EAC ).
4. If there is no carry over, then 1’s complement of the result of addition is obtained
to get the final result and it is negative.

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Ex: 110101 – 100101

1’s complement of 100101 is 011010.
Minuend - 110101
1’s complement of subtrahend - 011010
Carry o ver (EAC) - 1 001111
1
010000
The required difference is 10000
Ex: 101011 – 111001
1’s complement of 111001 is 000110. Hence
Minuend - 101011
110001
There is no carry, Hence the difference is – 1 1 1 0
2's complement
The 2's complement of binary number is obtained by adding 1 to the 1's
complement of the number. 2's complement = 1's complement + 1
2's Complement = 2n-r
Another method to find 2's Complement is just copy the given no. starts from
LSB up to reach 1, then write complement for remaining digits of given no.
Ex. 2's Complement of 01011011 is 10100100 + 1 = 10100101
Subtraction using 2's complement
The steps to be followed in subtraction by 2’s complement are:
1. Write down 2's complement of the subtrahend.
2. Then it is added to the minuend.
3. If the final carry over of the sum is 1, it is dropped and the result is positive.
4. If there is no carry over, the two’s complement of the sum will be the result and it
is negative.
Ex: 110110 - 10110
110110 Minuend
101010 2’s complement of subtrahend
Carry over (ignore) 1 1 0 0 0 0 0
After dropping the carry over we get the result of subtraction to be 100000.
Ex: 10110 – 11010
Minued - 10110
Result of addition - 1 1 1 0 0 (no carry)
As there is no carry over, the result of subtraction is negative and is obtained
by writing the 2’s complement of 11100
Hence the difference is – 0100.

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9's complement
The complements are used to make the arithmetic operations in digital
system easier. To obtain the 9's complement of any number we have to subtract
the number with (10 n - 1) where n = number of digits in the number, or in a simple
manner we have to subtract each digit of the given decimal number from 9.
9's complement of 43 is 99 - 43 = 56
10's complement
To find out the 10's complement, after finding out the 9's complement of that
number. We have to add 1 with the 9,s complement
10's complement of 43 = 9's complement+1
= (99 – 43)+1 = 56+1= 57

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UNIT- II
BOOLEAN ALGEBRA AND THEOREMS
Positive and Negative Logic
The binary variables have either of the two states, i.e. the logic ‘0’ state or
the logic ‘1’ state. These logic states in digital systems such as computers, for
instance, are represented by two different voltage levels or two different current
levels.
If the two voltage levels are 0 V and +5 V, then in the positive logic system
the 0 V represents a logic ‘0’ and the +5 V represents a logic ‘1’. In the negative
logic system, 0 V represents a logic ‘1’ and +5 V represents a logic ‘0’.
If the two voltage levels are 0 V and −5 V, then in the positive logic system
the 0 V represents a logic ‘1’ and the −5 V represents a logic ‘0’. In the negative
logic system, 0 V represents a logic ‘0’ and −5 V represents a logic ‘1’.
Truth Table
A truth table lists all possible combinations of input binary variables and the
corresponding outputs of a logic system .
Logic Gates
Logic gates are the basic building blocks of any digital system. Logic gate
can be defined as an electronic circuit which makes decisions. It has one or more
than one input and only one output. The relationship between the input and the
output is based on certain logic. Basic logic gates are AND gate, OR gate, NOT
gate.
AND Gate
AND Gate is a logical gate which is widely used having two or more inputs
and a single output. This gate operates on logical multiplication. In this gate if either
of the inputs is low (0), then the output is also low, but if all the inputs are high (1)
the output will also be high (1)
Fig show 2 i/p AND gate, here i/ps are A & B and o/p is Y=A.B
Truth Table
A B Y=A.B
0 0 0
0 1 0
1 0 0
1 1 1

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AND Gate using Diodes

Normally an AND gate is designed by either diodes or transistors. While,
diodes are used to design AND gate, it is called diode AND gate. The basic circuit
of a diode AND gate is shown below
In the above circuit we first apply +5V at VCC.

Now if we apply +5V at A and B (i.e A=1 and B=1), both of the diodes are
reversed biased and hence behave as OFF or open circuit and no current will flow
through diodes and voltage appears at X (output), then the output of the circuit is
considered as high or logical 1.
Now, if either inputs A or B or both are applied with 0 Volt or they are
grounded, respective diode will become forward biased and hence behaves as ‘ON’
or short circuited. At this condition, supply voltage +5V at point VCC will get path
through either of diodes or both to the ground. As the current flowing from VCC to
ground through resistor R, entire 5V will be dropped across the resistor and hence
voltage at X will become low or zero (0).
AND Gate using Transistors
The circuit diagram of transistor AND gate is shown below.
In the above circuit when A or B or both A and B are grounded or at 0V

potential, transistor T1 or T2 or both T1 and T2 are in OFF condition respectively.
This is because inputs A and B are base terminal of transistor T1 and T2
respectively. Zero base voltage makes a transistor OFF. As the path through T1and
T2 is open circuited, base of transistor T3 has enough potential to make T3 ON.
Current then starts flowing through T3 and then grounded. As a result entire
potential of output X will become low or zero (0).

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If any of the transistors T1 and T2 is in OFF condition, same result will come
at output X as both the transistors are in series.
If we apply +5 V at both the inputs A and B i.e. at base of transistor T1 and T2
respectively. This makes both the transistors T1 and T2 are in ON condition. Entire
supply voltage grounded through T1 and T2 and the base potential of the transistor
T3 will be zero and T3 becomes in OFF condition. As a result the supply voltage
+5V appear at output and X will become 1 or high.
OR Gate
OR gate performs operation which means output is logical 1 if at least one of
the inputs is 1. Just like AND gate, an OR gate may also have two or any more
numbers of inputs but only one output. Only if all of the inputs are low or 0 the
output is low or 0 and in all other input conditions the output will be high or 1.The
logical symbol of OR gate is shown below,
A B Y=A+B
Truth Table 0 0 0
0 1 1
1 0 1
1 1 1
OR Gate using Diodes
A simple two inputs OR gate by using diode as follows,
In the above circuit, When any of the inputs is given with +5V, the respective
diode becomes forward biased and behaves as ideally short circuited hence this +5
V will appear at output X. +5 V means logical 1.
Now if both of the inputs are given with +5 V, both diodes will be forward
biased. Hence, similarly +5 V will appear at X.
Now if both of the inputs A and B are grounded or given 0V, There will be no
voltage appears at X and hence X is considered as logical 0.
OR Gate using Transistors
The OR gate by using transistor is shown in figure. In this case the OR gate
is referred as transistor OR gate.
Now if A and B both are given with 0V, both of the transistor are in OFF
condition, hence supply voltage + 5 V will not get path to the ground through either
of the transistors, T1 and T2. As a result base of the transistor T3 will get enough
potential to make it ON. In that condition supply + 5 V will get path to ground
through transistor T3. Then no voltage appears at output. i.e., logical 0

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Now, if base terminal either of the transistors T1 or T2 or both are given with
+ 5 V, the respective transistor or both will be in ON condition. In that case supply
voltage + 5 V will get path to ground through either of the transistors or both. As a
result base of T3 having 0 volts and T3 is in OFF condition. Hence, total supply
voltage appears at output. i.e., logical 1
NOT Gate
NOT gate is a logical gate which only inverts the input digital signal. NOT gate
sometimes is referred as inverter. A NOT gate always have high (1) output when its
input is low (0). On the other hand a logical NOT gate always have low (0) output
when input is high (1). The logical symbol of a NOT gate is shown below,
Truth Table
A Y= Α
0 1
1 0
NOT Gate using Transistors
A NOT gate can easily be designed by using a simple bipolar transistor. The
circuit of a
NOT gate or transistor inverter is shown below

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Let us examine the above simple circuit by applying high input variable, i.e.
+5V. At that condition the transistor T gets enough base potential to make the
transistor T ‘ON’.
As soon as the transistor becomes ON, the supply voltage (+5V) will get a
path to the ground through transistor T. As a result no voltage appears at output.
i.e., logical 0
Input A = 0V i.e. base terminal of the transistor is given with 0V. At this
condition, as the base of the transistor is at 0 potential, the transistor T will be in
OFF condition and hence, the supply voltage will not get any path to the ground
and entire supply voltage will appear at output terminal of the NOT gate high (1).
Ex-OR Gate
Ex-OR gate operation is same as that of OR gate, except that the o/p is 0
when all i/ps are high. Symbol of Ex-OR gate
Truth Table
A B Y=A  B Y  A B  AB  AB
0 0 0 Logical diagram for Ex-OR gate
0 1 1
1 0 1
1 1 0
Universal Gates
NOR and NAND gates have the particular property that any one of them can
create any logical Basic gate (Boolean expression). Hence, NAND and NOR gates
are called universal gates
NAND Gate
NAND gate has 2 or more i/p signals and only one o/p signal. It has low o/p
when all i/p signals are high, otherwise it has high o/p signal
Symbol of NAND gate Logical Structure of NAND gate truth table
A B Y= AB
0 0 1
0 1 1
1 0 1
1 1 0
In logical structure AND gate followed by NOT gate. So it is also called NOT-AND
gate

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NOR Gate
NOR gate has 2 or more i/p signals and only one o/p signal. It has high o/p
when all i/p signals are low, otherwise it has low o/p signal
Symbol of NOR gate Logical Structure of NORgate truth table
A B Y= A  B
0 0 1
0 1 0
1 0 0
1 1 0
In logical structure OR gate followed by NOT gate. So it is
also called NOT-OR gate.
Demorgan’s Theorems
Demorgan, a mathematician, proposed two theorems that are an important part of
Boolean algebra.
First Theorem:
The complement of a product of variables is equal to the sum of the complements
of the variables.
ΑB  Α  B
Proof:
Case1: A=0, B=0
ΑB  0 . 0  0  1
Α  B  0  0  11  1
Case2: A=0, B=1
ΑB  0 .1  0  1
Α  B  0  1  1 0  1
Case3: A=1, B=0
ΑB  1. 0  0  1
Α  B  1  0  0 1  1
Case4: A=1, B=1
ΑB  1.1  1  0
Α  B  1  1  0 0  0
Truth Table
A B AB ΑB Α B Α B
0 0 0 1 1 1 1
0 1 0 1 1 0 1
1 0 0 1 0 1 1
1 1 1 0 0 0 0

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Second Theorem:
The complement of a sum of variables is equal to the product of the complements
of the variables.
Α B  Α . B
Proof:
Case1: A=0, B=0
Α B  0  0  0  1
Α . B  0 . 0  1. 1  1
Case2: A=0, B=1
Α B  0  1  1  0
Α . B  0 . 1  1.0  0
Case3: A=1, B=0
Α B  1  0  1  0
Α . B  1. 0  0 .1 0
Case4: A=1, B=1
Α B  1  1  1  0
Α . B  1. 1  0 . 0  0
Truth Table
A B A+B Α B Α B Α .B
0 0 0 1 1 1 1
0 1 1 0 1 0 0
1 0 1 0 0 1 0
1 1 1 0 0 0 0
NAND gate as Universal Gate

NAND gate truth table
A B Y= AB
0 0 1
0 1 1
1 0 1
AND gate using NAND gates. 1 1 0

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OR gate using NAND gates.
NOT gate using NAND gate.
Ex-OR gate using NAND gates.
NOR gate as Universal Gate

NOR Gate truth table
A B Y= A  B
0 0 1
0 1 0
1 0 0
1 1 0
OR gate using NOR gates.
AND gate using NOR gates.
NOT gate using NOR gate.

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Ex-OR gate using NOR gates.
AB  A  B = AB. A  B = ( A  B). ( A  B) = AA  AB  AB  BB = A B  AB = A  B
BOOLEAN ALGEBRA AND THEOREMS
The operation of almost all modern digital computers is based on binary systems.
Boolean Algebra is used to analyze and simplify the digital logic circuits. It uses
only the binary numbers i.e. 0 and 1. It is also called as Binary Algebra or logical
Algebra. Boolean algebra was invented by George Boole in 1854.
Rule in Boolean Algebra
Following are the important rules used in Boolean algebra.
1. Variable used can have only two values. Binary 1 for HIGH and Binary 0 for
LOW.
2. Complement of a variable is represented by an overbar − . Thus, complement of
variable A is represented as Α .
3. Logical ORing of the variables is represented by a plus + sign between them. For
example ORing of A, B, C is represented as A + B + C.
4. Logical ANDing of the two or more variable is represented by writing a dot ( . )
between them such as A.B.C. Sometime the dot may be omitted like ABC.
Boolean Laws
There are six types of Boolean Laws.
Commutative law
Commutative law states that changing the sequence of the variables does not have
any effect on the output of a logic circuit.
A.B= B. A
A+ B = B + A
Associative law
This law states that the order in which the logic operations are performed is
irrelevant as their effect is the same.
(A . B) . C = A . (B . C)
(A + B) + C = A + (B + C)
Distributive law
Distributive law states the following condition.
A . (B + C) = A . B + A . C
A + (B . C) = (A + B) . (A + C)

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AND laws
These laws use the AND operation. Therefore they are called as AND laws.
A.0=0
A.1= A
A . A= A
A.Α =0
OR laws
These laws use the OR operation. Therefore they are called as OR laws.
A+ 0 = A
A+ 1 = 1
A+ A= A
A+ Α = 1
NOT law
This law uses the NOT operation. The NOT law states that double inversion of a
variable results in the original variable itself.
Α Α
Some simple logic expressions
A + AB = A
A . (A+B) = A
A+ ΑB = A + B
(A+B)(A+C) = A+BC
AB + BC + C A = AB+C
Ex: Simplify A + AB
A + AB = A( 1 + B)
=A.l
=A
Ex: Simplify Α  AB
Α  AB = Α  AB  AB
= ΑA  AB  AB
= ΑA  AB  AA  AB
 
= Α  A Α  B
= 1.Α  B  Α  B
Ex: Simplify (A + B)(A + C)
(A + B)(A + C) = AA + AC + AB + BC
= A +AC +AB +BC
= A(1+C) + AB + BC
= A . 1 + AB + BC
= A + AB + BC
= A(1 + B) + BC
= A .1 + BC
= A + BC

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Ex: Simplify (Α  B) (Α  B )  Α
(Α  B) (Α  B ) = ΑA  AB BA  BB
= A  A(B  B)  0
= A  A(1) = A  A = A
Ex: Simplify (Α  B) (Α  B ) (Α  C)  AC
(Α  B) (Α  B ) (Α  C) = (ΑΑ  AB BA  BB)( Α  C)
= Α ( Α  C) = Α Α  ΑC = 0 ΑC = AC
Ex: Simplify ΑBC  ΑBC  ΑBC
ΑBC  ΑBC  ΑBC = ΑB(C C)  ΑBC
= ΑB  ΑBC = Α(B BC) = Α(B C) = ΑB ΑC
Ex: Simplify ( Α  B  C) ( Α  B  C)
( Α  B  C) ( Α  B  C) = (Α  B  C)  ( Α  B  C)
= ( Α .B. C)  (Α . B. C)
= (Α . B. C) (Α. B. C) = Α B (C C) = Α B
Ex: Simplify A  B  C
A  B  C = ( AB  AB)  C
= ( AB  AB). C  (AB  AB). C
= ( AB. AB). C  ABC  ABC
= ((A  B)(A  B)).C  ABC  ABC
= (A A  B A  AB  BB). C  ABC  ABC
= ABC  ABC  ABC  ABC
Ex: Simplify AB  (A  B)C
AB  (A  B)C = AB  ( AB  AB)C
= AB  ABC ABC
= B(A  AC) ABC
= B(A  C) ABC = BA  BC ABC
= BA  C(B  AB) = BA  C(B  A) = AB  BC  AC
Ex: Simplify 1. ( Α  B  C) ( Α  B  C) ,
2. AB+ABC,
3. Α B C  Α BC
4. Α BC  Α BC  AB
5. A  B  C  Α B C

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Boolean Function standard Representation

A Boolean function is an algebraic form of Boolean expression. A Boolean
function of n-variables is represented by f(x1, x2, x3….xn). By using Boolean laws
and theorems, we can simplify the Boolean functions of digital circuits.
An y Boolean function that is expressed as a sum of minterms or as a
product of maxterms is said to be in its “canonical form”.
Min terms
A minterm is defined as the product term of n variables, in which each of the n
variables will appear once either in its complemented or un-complemented form.
The minterm is denoted as m i
For a 2-variable (A and B) Boolean function, the possible minterms are:
AB, AB, AB and AB

For a 3-variable (A, B and C) Boolean function, the possible minterms are:
ABC, ABC, ABC, ABC, ABC, ABC, ABC, and ABC

Max terms
A max term is defined as the sum of n variables, The maxterm is denoted as
Mi. In max term, each variable is complimented, if its value is assigned to 1, and
each variable is un-complimented if its value is assigned to 0.
For a 2-variable (A and B) Boolean function, the possible max terms are:
A  B, A  B, A  B and A  B
For a 3-variable (A, B and C) Boolean function, the possible maxterms are:
A  B  C, A  B  C, A  B  C, A  B  C, A  B  C, A  B  C, A  B  C, and A  B  C
Note that each minterm is complement of its corresponding maxterm or vice versa.
Minterms and maxterms for 3 binary variables

Variables Minterms maxterms
A B C mi Mi
0 0 0 ABC  m 0 A  B  C  M0
0 0 1 ABC  m1 A  B  C  M1
0 1 0 ABC  m2 A  B  C  M2
0 1 1 ABC  m3 A  B  C  M3
1 0 0 ABC  m 4 A  B  C  M4
1 0 1 ABC  m5 A  B  C  M5
1 1 0 AB C  m6 A  B  C  M6
1 1 1 ABC  m 7 A  B  C  M7

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Function of 3 binary variables

A B C f
0 0 0 0
0 0 1 1
0 1 0 1
0 1 1 0
1 0 0 1
1 0 1 1
1 1 0 0
1 1 1 1
The Boolean function may be expressed algebraically from above given truth
table by forming a minterm for each combination of the variables that produced a ‘1’
and then take OR of those minterms.
From above table minterms are ABC, ABC, ABC, ABC and ABC
Now function f  ABC  ABC  ABC  ABC  ABC
f  m1  m2  m4  m5  m7
Now consider complement of Boolean function from truth table by forming a
maxterm for each combination that produced ‘0’ and then take AND of those
maxterms.
From above table maxterms are A  B  C, A  B  C, A  B  C
Now function f  (A  B  C).(A  B  C).( A  B  C)

f  M0.M3.M6
Canonical Form (Standard SOP and POS Form)

There are two types of canonical forms
 Sum-of-Products (SOP) Form
 Product-of-sums (POS) form
Sum of Product (SOP) Form
The sum-of-products (SOP) form is a method of simplifying the Boolean
expressions of logic gates. In this SOP form of Boolean function representation, the
variables are operated by AND to form a product term and all these product terms
are ORed together to get the final function.
From above table f  ABC  ABC  ABC  ABC  ABC
f  m1  m2  m4  m5  m7
f   m(1, 2, 4, 5, 7)
Product of Sums (POS) Form
The product of sums (POS) form is a method of simplifying the Boolean
expressions of logic gates. In this POS form, all the variables are ORed, i.e. written
as sums to form sum terms. All these sum terms are ANDed together to get the

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product-of-sum form. This form is exactly opposite to the SOP form. So this can
also be said as “Dual of SOP form”.
From above table f  (A  B  C).(A  B  C).( A  B  C)
f  M0.M3.M6
f   M( 0, 3, 6)
Karnaugh Maps (K-maps)

K-map was developed by Karnaugh in 1953. K-map is a powerful tool for
simplification of Boolean expressions. The pattern of K-map depends on the no. of
variables. A Karnaugh map is a two-dimensional truth-table. The specific patterns
for 2, 3 and 4 variables shown below
C C CD CD CD CD
B B
AB AB
A
AB AB
A
AB AB
2 variable k-map
AB AB
3 variable k-map 4 variable k-map
Simplification using K-maps

Simplification is based on groupings. Group the 1s or 0s in the K-map by observing
following guide lines. Look maximum possible group of 1s or 0s.
Look for octets first then quad and finally a pair. An octet eliminates 3 variables, a
quad eliminates 2 variables and a pair eliminates 1 variable.
Overlapping of 1s or 0s is allowed.
Rolling and folding of a map is allowed.
Example:
A B C f The K-map is filled as per function row in truth table.
0 0 0 1
C C
0 0 1 0
0 1 0 1 1 0
AB
0 1 1 0 f  ABC  ABC  ABC  ABC
1 0 0 1 AB 1 0
1 0 1 1
AB 0 0
1 1 0 0 f  AC  AB
1 1 1 0 AB 1 1

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In the K-map there are 2 pairs. The above K-map gives two minterms AC, AB
The simplified Boolean expression is f  AC  AB

Before simplification the Boolean function is f  ABC  ABC  ABC  ABC
Example:
The K-map is filled as per function row in truth table
A B C D f
CD CD CD
0 0 0 0 1 CD
0 0 0 1 0
AB 1 0 1 1
0 0 1 0 1
0 0 1 1
0 0 1 1 1 AB
0 1 0 0 0 AB 0 1 0 0
0 1 0 1 0
0 1 1 0 1 AB 1 1 1 0
0 1 1 1 1
1 0 0 0 1
1 0 0 1 1 f  AC  ABD  ACD  BCD
1 0 1 0 0 The four groupings labeled as 1, 2, 3 and 4. group 1 is a
1 0 1 1 1 quad and 2, 3 and 4 are pairs. Group 4 involved in
1 1 0 0 0 rolling of the map.
1 1 0 1 1
1 1 1 0 0 Now terms obtained from these groupings are
1 1 1 1 0 AC, ABD, A CD, BCD
f  AC  ABD  ACD  BCD
Before simplification the Boolean function is
f  ABCD  ABCD  ABCD  ABCD  ABCD ABCD  ABCD  ABCD  ABCD

Simplifying K-map in POS
The K-map is filled as per function row in truth table
CD CD CD CD
AB 1 0 1 1
AB 0 0 1 1
AB 0 1 0 0
AB 1 1 1 0
f  (B  C  D)(A  C  D) (A  B  C) (A  C  D)
The four groupings are pairs and 2Groups involved in over lapping.
Now terms obtained from these groupings are
(B  C  D),(A  C  D) ,(A  B  C) ,(A  C  D)
f  (B  C  D)(A  C  D) (A  B  C) ( A  C  D)

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f  (A  B  C  D) (A  B  C  D)(A  B  C  D)( A  B  C  D)( A  B  C  D)
(A  B  C  D)( A  B  C  D)
Don't Care condition
Sometimes we do not care whether a 1 or 0 occurs for a certain set of
inputs. It may be that those inputs will never occur so it makes no difference what
the output is. For example, If we had a truth table as follows

A B C D f The K-map is filled as per function row
0 0 0 0 0 in truth table
0 0 0 1 0
0 0 1 0 1
CD
0 0 1 1 1 CD CD CD
0 1 0 0 0 0 0 1 1
AB
0 1 0 1 1
0 1 1 0 0 AB 0 1 1 0
0 1 1 1 1 AB X X X X
1 0 0 0 0
0 0 X X
1 0 0 1 0 AB
1 0 1 0 X
1 0 1 1 X f  BD B C
1 1 0 0 X
1 1 0 1 X The two groupings labeled as 1 and 2. Both groups are
1 1 1 0 X a quads. Group 2 involved in rolling of the map.
1 1 1 1 X Now terms obtained from these groupings are BD, B C
f  BD B C
f  ABCD  ABCD  ABCD  ABCD, The X in the above stand for "don’t care", we
don't care whether a 1 or 0 is the value for that combination of inputs because the
inputs will never occur.

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UNIT – III
COMBINATIONAL DIGITAL CIRCUITS

The combinational circuit consist of logic gates whose outputs at any time is
determined directly from the present input without any regard to the previous
output. A combinational circuit performs Boolean functions. A combinational circuit
is a generalized gate and has m inputs and n outputs.
Adders
In electronics, an adder or summer is a digital circuit that performs addition
of numbers. In modern computers adders reside in the arithmetic logic unit (ALU)
where other operations are performed. Although adders can be constructed for
many numerical representations, such as Binary-coded decimal or excess-3, the
most common adders operate on binary numbers.
Half Adder
A half adder is a logical circuit that performs an addition operation on two
binary digits. The half adder produces a sum and a carry.
A half adder has two inputs, generally labelled A and B, and two outputs, the
sum S and carry C. S is the two-bit XOR of A and B, and C is the AND of A and B.
Block diagram Logical circuit of Half Adder Truth Table
A B Sum Carry
0 0 0 0
0 1 1 0
1 0 1 0
1 1 0 1
Equations of the Sum and Carry are Sum= AB  AB Carry=AB

One can see that Sum can also be implemented using XOR gate as A B
Full Adder
A full adder has three inputs A, B, and C. A full adder is a logical circuit that
performs an addition operation on three binary digits. The full adder produces a
sum(S) and carry(Co), which are both binary digits.
Block diagram

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Logical circuit of Full Adder Truth table
Inputs Outputs
A B C S Co
0 0 0 0 0
0 0 1 1 0
0 1 0 1 0
0 1 1 0 1
1 0 0 1 0
1 0 1 0 1
Sum (S) = A  B  C 1 1 0 0 1
1 1 1 1 1
A  B  C = ( AB  AB)  C
= ( AB  AB) . C  (AB  AB). C
= ( AB. AB). C  ABC  ABC
= ((A  B)( A  B)). C  ABC  ABC
= (A A  BA  AB  BB). C  ABC  ABC
Carry (C 0 )= AB  (A  B)C
AB  (A  B)C = AB  (AB  AB)C
= AB  ABC ABC
= B(A  AC)  ABC
= B(A  C)  ABC = BA  BC  ABC
= BA  C(B  AB) = BA  C(B  A) = AB  BC  AC
Subtractor
In electronics, a subtractor can be designed using the same approach as
that of an adder.
Half subtractor
A combinational circuit which is used to perform subtraction of two bits and it
has two inputs, A (minuend) and B (subtrahend) and two outputs D (difference) and
Br (borrow). Such a circuit is called a half-subtractor because it enables borrow out
of the current arithmetic operation but no borrow in from a previous arithmetic
operation.
Truth table
Block diagram Logical circuit of Half Subtractor
A B D Br
0 0 0 0
0 1 1 1
1 0 1 0
1 1 0 0
Equations of the Difference (D) and Borrow (Br) are D= AB  AB
Br = A B

29
Full Subtractor
A full subtractor is made by combining two half-subtractors and an additional
OR-gate.
The truth table for a full subtractor
Block diagram A B C D Br
0 0 0 0 0
0 0 1 1 1
0 1 0 1 1
0 1 1 0 1
1 0 0 1 0
1 0 1 0 0
1 1 0 0 0
1 1 1 1 1
Logical circuit of Full Subtractor
Difference (D) = A BC

A BC = ( AB  AB)  C
= ( AB  AB). C  ( AB  AB) . C
= ( AB. AB) . C  ABC  ABC
= ((A  B)( A  B)). C  ABC  ABC
= (A A  BA  AB  BB). C  ABC  ABC
Borrow (Br) = AB  (A  B)C

AB  (A  B)C = AB  ( AB  AB)C
= AB  ( AB. AB )C
= AB  ((A  B).(A  B) )C
= AB  (AA  AB  AB  BB).C
= AB  ( AB  AB).C = AB  ABC  ABC
= A (B  BC)  ABC = A (B  C)  ABC = A B  A C  ABC
= A C  B (A  AC) = A C  B (A  C) = A C  AB  BC)

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Binary Parallel Adder

A full binary adder performs addition of any single bit of one binary number.
But a single full adder cannot add more than one bit binary number. This can be
done only by connecting as many full adders as the number of bits of the binary
numbers whose addition is to be performed. This parallel combination of full adders
which performs addition of binary numbers is called binary parallel adder. For
adding two 4 bit binary numbers we have to connect 4 full adders to make 4 bit
parallel adder.
The inter connection of 4 full adders in 4bit parallel adder is shown below
Let us examine the justification of the above circuit by taking an example of

addition of two 4 bit binary numbers. Let us add 1011 with 1101.
A4 A3 A2 A1 1011
B4 B 3 B2 B1 1101
C 4 S4 S3 S2 S1 11000
As there is no previous carry C 0=0. Therefore, final result of the addition

would be C 4 S4 S3 S 2 S1 = 1 1 0 0 0
Digital Comparator or Magnitude Comparator
Suppose we have two binary numbers which we have to compare according
to their magnitude. One number of these two numbers can either be greater, equal
or smaller than the other number. The digital circuit which performs this comparison
task between binary numbers is called digital comparator.
Let us consider two single bit binary numbers A and B. The value of A and B
either be 0 or 1. Now let us logically design a circuit which will have two inputs one
for A and other for B and have three output terminals, one for A > B condition, one
for A = B condition and one for A < B condition. Let us name the output terminals
G, E and L respectively. We want, G = 1 when A > B, E = 1 when A = B. And L = 1
when A < B. If we successfully design this logic circuit, it will compare two single bit
binary numbers A, B and gives high state at respective output terminal according to
the comparison conditions of A and B.

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When, A = 0 and B = 0, then A = B and E = 1

A B G E L
When, A = 0 and B = 1, then A < B and L = 1
0 0 0 1 0
When, A = 1 and B = 0, then A > B and G = 1
0 1 0 0 1
When, A = 1 and B = 1, then A = B and E = 1 1 0 1 0 0
1 1 0 1 0
G  A B , E  A B  A B  A B , L  A B
Now from above table, The circuit for comparator is
As the above circuit can only compare two single bit binary numbers, it is
called single bit digital comparator.
There are N bit binary comparators to compare multi bit binary numbers
which are normally4 bits and above.
Integrated circuit- IC (Scale integration component )
Digital circuits are constructed with integrated circuit (IC). An IC is a small
silicon semiconductor crystal called chip containing the electronic component for
digital gates. The various gates are interconnected inside the chip to form the
required circuit.
Digital IC are categorized according to their circuit complexity as measured
by the number of logic gates in a single packages.
 Small scale integration (SSI). SSI devices contain fewer than 10 gates. The
input and output of the gates are connected directly to the pins in the
package.
 Medium Scale Integration. MSI devices have the complexity of
approximately 10 to 100 gates in a single package.
 Large Scale Integration (LSI). LSI devices contain between 100 and a few
thousand gates in a single package.
 Very Large Scale Integration (VLSI). VLSI de vices contain thousand of gates
within a single package. VLSI devices have use in the computer system
design technology.

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Multiplexers
A multiplexer or MUX, also called a data
selector, is a special type of combinational circuit.
It is a digital circuit which selects one of the data
input and routes it to the output. The selection of
one of the input is done by the selected inputs.
Depending on the digital code applied at the
selected inputs, one out of input data sources is
selected and transmitted to the single output Y. E
is called the strobe or enable input which is useful for the cascading.
If there are n selection lines, then the number of maximum possible input
lines is 2n and the multiplexer is referred to as a 2 n -to-1 multiplexer or 2 n x1
multiplexer.
2 X1 multiplexer
The 2-to-1 multiplexer, the functional table, the logic diagram of this
multiplexer shown in the above figs.
The circuit functions as follows:
For S = 0, the output becomes Y = I 0.
For S = 1, the output becomes Y = I 1.
Thus, inputs I0 and I1 are respectively switched to the output for S = 0 and S = 1.
2 X1 multiplexer with Enable
Multiplexers usually have an ENABLE input that can be used to control the
multiplexing function. When this input is enabled, that is, when it is in logic ‘1’ or
logic ‘0’ state, depending upon whether the ENABLE input is active HIGH or active
LOW respectively, the output is enabled. When the ENABLE input is inactive, the
output is disabled Figure shows 2-to-1 multiplexer can be modified to include an
ENABLE input. The functional table of this modified multiplexer is also shown in
Fig. The ENABLE input here is active when HIGH.

33
4 X1 multiplexer
The 4-to-1 multiplexer, the functional table, the logic diagram of this
multiplexer shown in the above figs.
The circuit functions as follows:
For S1 = 0, S0 = 0 the output becomes Y = I0.
For S1 = 0, S0 = 1 the output becomes Y = I1
Thus, the input combinations 00, 01, 10 and 11 on the selection lines respectively
switch I0, I 1, I2 and I3 to the output.
Multiplexers usually have an ENABLE input that can be used to control the
multiplexing function. When this input is enabled, that is, when it is in logic ‘1’ or
logic ‘0’ state, depending upon whether the ENABLE input is active HIGH or active
LOW respectively, the output is enabled. When the ENABLE input is inactive, the
output is disabled Figure shows 4-to-1 multiplexer can be modified to include an
ENABLE input. The functional table of this modified multiplexer is also shown in
Fig. The ENABLE input here is active when LOW.

34
Decoders
A decoder is a combinational circuit that decodes the information on n input lines to
a maximum of 2 n unique output lines. Decoder is identical to a demultiplexer
without any data input. It performs operations which are exactly opposite to those of
an encoder.
Fig shows a decoder has n- inputs and 2 n outputs. Fig shows the block diagram of a typical
decoder with enable line.
3-to-8 decoder
Figure shows 3-to-8 line decoder with
enable input. In a 3 to 8 decoder, there are three
inputs and eight outputs, as shown in figure. The
three inputs are decoded into eight outputs. i.e.,
binary values at the input form a combination,
and based on this combination, the
corresponding output line is activated. Each
output represents one minterm. For example, for
input combination ABC = 001, output line D1
equals 1 while all other output lines equal 0s. It should be noted that at any given
instance of time, one and only one output line can be activated.
Since each input combination

represents one minterm, the
truth table contains eight
output functions, from D0 to
D7, D0 is A B C and Similarly
D7 is ABC. The
corresponding circuit is given
in Figure. In this figure, the
three inverters provide
complement of the inputs,
and each one of the AND
gates generates one of the
minterms. It is also possible
to add an Enable input to this
decoder.

35
Implementation of a full adder circuit using a 3-to-8 line decoder.

A decoder with an OR gate at the output can be used to implement the given
Boolean function. The decoder should at least have as many input lines as the
number of variables in the Boolean function to be implemented. The truth table of
the full adder is given in Table and Fig shows the implementation of full adder using
decoder.
From the truth table, Boolean functions for SUM and CARRY outputs are given by
the following equations:
Sum output S = ABC  ABC  ABC  ABC = m(1,2,4,7)

Carry output Co = ABC  ABC  ABC  ABC =  M(3,5,6,7)
Encoders
An Encoder is a combinational circuit which is designed to perform the
inverse operation of the decoder and it is a multiplexer without its single output line.
Encoder has 2n input lines and n output lines, which corresponds to n selection
lines in a multiplexer. The n output lines generate the binary code for the possible
2n input lines. The o/p lines generate binary code corresponding to i/p. Figure
shows 2n X n encoder

36
8-to-3 encoder
Figure shows 8-to-3 encoder. Let us
take the case of an octal-to-binary encoder. In
this encoder there are eight input lines, each
representing an octal digit, and three output
lines representing the three-bit binary
equivalent. The truth table of such an encoder
is given in Table. In the truth table, D0 to D7
represent octal digits 0 to 7. A, B and C
represent the binary digits.
Looking at the last row of the table, it implies that, if D7 = 1, then,

irrespective of the logic status of other inputs, the output is 111 as D7 will only be
encoded.
Demultiplexers
A demultiplexer performs the reverse operation of a
multiplexer i.e. it receives one input and distributes it
over several outputs. A demultiplexer has only one
input line, 2 n output lines and n selection lines. It
routes the information present on the input line to any
of the output lines. The output line that gets the
information present on the input line is decided by the
bit status of the selection lines. A decoder is a special
case of a demultiplexer without the input line.
1-to-4 demultiplexer

37
Figure shows the circuit representation of a 1-to-4 demultiplexer and the

truth table of the demultiplexer when the input line is held HIGH. Here this
demultiplexer has 4 o/p lines and 2 selection lines. As truth table the i/p routes to D2
o/p when selection AB is 10, similarly always i/p routes to only one o/p line basing
on selection lines.
1-to-2 demultiplexer
Select O/P
I/P
A D0 D1
1 0 0 1
1 1 1 0
Families of logic gates

There are several different families of logic gates. The following are the main
logic families and their characteristics.
Diode Logic (DL)
Diode logic gates use diodes to perform AND and OR logic functions. Diodes
have the property of easily passing an electrical current in one direction, but not the
other. Thus, diodes can act as a logical switch. Diode logic gates are very simple
and inexpensive, and can be used effectively in specific situations.
Resistor-Transistor Logic (RTL)
Resistor-transistor logic gates use Transistors to combine multiple input
signals, which also amplify and invert the resulting combined signal. Often an
additional transistor is included to re-invert the output signal. This combination
provides clean output signals and either inversion or non-inversion as needed. RTL
gates are almost as simple as DL gates, and remain inexpensive
Diode-Transistor Logic (DTL)
By letting diodes perform the logical AND or OR function and then amplifying
the result with a transistor, we can avoid some of the limitations of RTL. DTL takes
diode logic gates and adds a transistor to the output, in order to provide logic
inversion and to restore the signal to full logic levels.

38
Transistor-Transistor Logic (TTL)

The physical construction of integrated circuits made it more effective to
replace all the input diodes in a DTL gate with a transistor, built with multiple
emitters. The result is transistor-transistor logic, which became the standard logic
circuit in most applications. TTL integrated circuits were adapted slightly to handle a
wider range of requirements, but their basic functions remained the same. These
devices comprise the 7400 family of digital ICs.
Emitter-Coupled Logic (ECL)
Also known as Current Mode Logic (CML), ECL gates are specifically
designed to operate at extremely high speeds, by avoiding the "lag" inherent when
transistors are allowed to become saturated. Because of this, however, these gates
demand substantial amounts of electrical current to operate correctly.
CMOS Logic
One factor is common to all of the logic families that they use significant
amounts of electrical power. Many applications, especially portable, battery-
powered ones, require that the use of power be absolutely minimized. To
accomplish this, the CMOS (Complementary Metal-Oxide-Semiconductor) logic
family was developed. This family uses enhancement-mode MOSFETs as its
transistors, and is so designed that it requires almost no current to operate. CMOS
gates are limited in their speed of operation. Nevertheless, they are highly useful
and effective in a wide range of battery-powered applications.
Fan-in
Fan-in is a term that defines the maximum number of digital inputs that a
single logic gate can accept properly.
Fan-out
Fan-out is a term that defines the maximum number of digital inputs that the
output of a single logic gate can feed.
NAND Gate using DTL
NAND gate circuit by using diodes and transistors is called DTL NAND gate
or Diode Transistor Logical NAND Gate.
A B X = AB
0 0 1
0 1 1
1 0 1
1 1 0
When both input A and B are given with 0 V, both of the diodes are in
forward biased condition that is in ON condition. Supply voltage will get path to the
ground through diode D 1 and D2. Entire VCC +5 V will ideally drop across resistor R
and hence base terminal of transistor T will not get enough potential to turn ON,

39
and hence the transistor will be in OFF condition. As a result VCC +5 V will appear
at output terminal X and hence output X will become high or logical 1.
Now if either of diode D1 and D2, is applied with 0 V, the same thing happens
as in these cases also the supply voltage gets a path to the ground either of the
forward biased diode. In those cases also the output will be logical high or 1
When both of the inputs are given with +5 V that is logical 1, both of the
diodes are in OFF condition and hence supply voltage will appear at the base
terminal of the transistor T which makes it switched ON and supply voltage gets a
path to the ground through T. i.e., entire VCC +5 V will drop across resistor R’ and
output terminal X will get ‘0’ volts and hence the output is considered as logical 0.
Hence, the output is 0 only when both inputs are +5 V or logical 1.
NOR Gate using DTL
NOR gate circuit by using diodes and transistors is called DTL NOR gate or
Diode Transistor Logical NOR Gate.
A B X= A  B
0 0 1
0 1 0
1 0 0
1 1 0
When both input A and B are given with 0 V, both of the diodes are in
Reverse biased condition that is in OFF condition. Base terminal of transistor T will
not get enough potential to turn ON, and hence the transistor will be in OFF
condition. As a result VCC +5 V will appear at output terminal X and hence output X
will become high or logical 1.
Now if either of i/p A or B or both of the inputs are given with +5 V that is
logical 1, both of the diodes or corresponding diode D 1 or D 2 is in ON condition and
hence high voltage will appear at the base terminal of the transistor T which makes
it switched ON and supply voltage gets a path to the ground through T. i.e., entire
VCC +5 V will drop across resistor R’ and output terminal X will get ‘0’ volts and
hence the output is considered as logical 0.
Hence, the output is 1 when both inputs are 0 V or logical 0.
NOR gate using Resistor Transistor Logic (RTL)
A B X= A  B
0 0 1
0 1 0
1 0 0
1 1 0

40
A NOR gate can be realized by using two bipolar junction transistors. The circuit is
shown in fig.. This circuit is made by two parallel connected transistors
In the circuit when both A and B are given +5 V, base of the both transistors
get a high potential to make the transistors ‘ON’. As both transistors T1 and T2 are
in ON condition, supply voltage at terminal C gets path to the ground through
transistors. and hence o/p will be at logical 0 state.
Now, if either of inputs A and B is given with +5 V, the only corresponding
transistor will be in ON condition. But in this case also supply voltage will get path
to the ground and similarly the output will be in logical 0.
Now if both of the inputs A and B are given with 0 V or grounded, both
transistors will be in OFF condition as in this case the base of both transistors does
not have enough potential to make the transistors ON.
As the supply voltage will not get any path to the ground, the supply voltage
will appear at output X, hence output is in logical 1 or high.
Hence, in the circuit, the output is 1, only when both of the inputs are 0 and
in all other conditions, the output is 0.
CMOS Digital Logic
One of the main disadvantages with the TTL digital logic gate series is that
the logic gates are based on bipolar transistor logic technology and as transistors
are current operated devices, they consume large amounts of power from a fixed
+5 volt power supply. Also, TTL bipolar transistor gates have a limited operating
speed when switching from an “OFF” state to an “ON” state and vice-versa called
the “gate” or “propagation delay”. To overcome these limitations complementary
MOS (CMOS) logic gates using “Field Effect Transistors” or FET’s.
As these gates use both P-channel and N-channel MOSFET’s as their input
device, at quiescent conditions with no switching, the power consumption of CMOS
gates is almost zero,
NAND gate using CMOS Digital Logic
A B X = AB
0 0 1
0 1 1
1 0 1
1 1 0
The above figure shows CMOS NAND gate and it contains 2 N channel
MOS FETs (Q3 and Q4) and 2 P channel MOSFETs (Q1 and Q2). The FETs Q1 and
Q3 are controlled by same input signal (input A), the upper FET Q1 is turning OFF
and lower FET Q3 is turning ON when input is high and vice versa. Similarly FETS
Q2 and Q4 are controlled by same input B.

41
When one or both of the inputs are at logic 0, the corresponding FET Q1 or
Q2 or both are in ON and the corresponding FET Q3 or Q4 or both are in cut-off.
Hence, the output is at logic 1.
When both of the inputs are at logic 1, the FETs Q1 and Q2 are in cut-off and
FETs Q3 and Q4 are in ON. Hence, the output is at logic 0.
Truth table of NAND is gate shown in the table.
NOR gate using CMOS Digital Logic
A B X= A  B
0 0 1
0 1 0
1 0 0
1 1 0
The above figure shows CMOS NOR gate and it contains 2 N channel MOS
FETs (Q3 and Q4) and 2 P channel MOSFETs (Q1 and Q2). The FETs Q1 and Q 3 are
controlled by same input signal (input A), the upper FET Q 1 is turning OFF and
lower FET Q3 is turning ON when input is high and vice versa. Similarly FETS Q2
and Q4 are controlled by same input B.
When both of the inputs are at logic 0, the FETs Q1 and Q2 are in ON and
FETs Q3 and Q4 are in cut-off. Hence, the output is at logic 1.
When one or both of the inputs are at logic 1, current flows through the
corresponding FET giving output state at logic 0.
Truth table of NOR is gate shown in the table.
Bi-CMOS Inverter
Two bipolar transistors (T3 and T4), one nMOS and one pMOS transistor (both
enhancement-type devices, OFF at Vin=0V)
The MOS switches perform the logic function &
bipolar transistors drive output loads
Vin = 0 :
T1 is OFF. Therefore T3 is non-conducting
T2 ON - supplies current to base of T4
T4 base voltage set to Vdd.
T4 conducts & acts as current source to charge load
CL towards Vdd.
Vout rises to Vdd (i.e. Vout =1)
Vin = Vdd (1)
T2 is off. Therefore T4 is non-conducting.
T1 is on and supplies current to the base of T3
T3 conducts & acts as a current sink to discharge load C L towards 0V.

42
Vout falls to 0V
• Inverter has high input impedance, i.e., MOS gate input
• Inverter has low output impedance
• Inverter has high drive capability but occupies a relatively small area
• However, this is not a good arrangement to implement since no discharge
path exists for current from the base of either bipolar transis tor when it is
being turned off. hence, this will slow down the action of the circuit
NAND gate using TTL Logic

It uses a multi-emitter
transistor at the input and is the
fastest saturating logic circuit. It has
a, good fan-in and fan-out and a high
speed of switching.
Fig shows TTL NAND
modified version known as totem-
pole circuit because the three output
components Q3, Q4 and D are
stacked one on top of the other in
manner of a totem pole. This
arrangement of totem-pole
transistors increases the operating
speed and output current capability of this circuit. The function of diode D 1 in this
circuit is to prevent both Q3 and Q4 being turned ON simultaneously. If both Q3
and Q4 are ON at the same time, supply ckt sends a large current to ground which
may cause a spiked voltage drop on the VCC line and a large noise in the output. It
may also cause more power consumption.
Circuit operation:
Case I
When inputs are high (1), transistor Q1 is OFF, Q2 is ON, Q3 is OFF and Q4
is ON and, therefore, output becomes low (logic O).
If all the input emitters are given a logic 1, the emitter base junction is
reverse biased and hence there is no emitter current. Thus transistor Q1 is turned
OFF. But collector base junction of Q1 is forward biased; therefore, a base current
of Q2 flows from VCC through R 1. Thus transistor Q2 is turned ON. Consequently,
potential of point R falls to Low, then Q3 is turned OFF and transistor Q4 ON.
Therefore Collector current of Q4 ground through Q4. Hence, output becomes low
(logic O).
Case II
An y of the 2 i/ps or both are logic ‘0’, EB junction of Q1 is FBed and hence
Q1is ON. Then voltage at P falls, it turns Q2 OFF. Then Q3 is turned ON and Q4 is
turned OFF. The high voltage at point c appears at o/p. Hence, o/p is high (1)

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UNIT – IV
SEQUENTIAL DIGITAL CIRCUITS

The output of a combinational circuit depends solely upon the input. i.e.,
combinational circuits have no memory. In order to build sophisticated digital logic
circuits, including computers, we need more a powerful model. We need circuits
whose output depends upon both the input of the circuit and its previous state. In
other words, we need circuits that have memory. For a device to serve as a
memory, is called sequential circuits.
It must have three characteristics:
• The device must have two stable states
• There must be a way to read the state of the device
• There must be a way to set the state at least once.
Pulse (+ve and –ve Logics)
In the Logic system a bit represents one of the any voltage levels
In a +ve logic system, high voltage represents logic 1 ( V(5v)=1 ) and low
voltage represents logic 0 ( V(0v)=0 )
In a –ve logic system, low voltage represents logic 1 ( V(0v)=1 ) and high
voltage represents logic 0 ( V(5v)=0 )
The clock pulse goes through two signal transitions: from 0 to 1 and the
return from 1 to 0. As shown in Figure, the positive transition is defined as the
positive edge and the negative transition as the negative edge.
Difference between Combinational Logic Circuits and Sequential

Logic Circuits
Combinational Logic Circuits Sequential Logic Circuits
The digital logic circuits whose outputs The digital logic circuits whose outputs
can be determined using the logic can be determined using the logic
function of current state input are function of current state inputs and past
combinational logic circuits; hence, state outputs are called sequential logic
these are also called time independent circuits.
logic circuits.
Don’t have the capability to store a state Have the capability to store a state inside
inside them. them.
It is not a memory element It is a memory element
The combinational digital circuits don’t The sequential digital logic circuits utilize
require any feedbacks. the feedbacks from outputs to inputs.
These are independent of the clock. These are dependent of the clock.
Ex: Adders, Subtractors, .. Ex: Flip Flops, Registers,…

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Latches and flip-flops

Latches and flip-flops are the building blocks of sequential circuits. While
gates had to be built directly from transistors, latches can be built from gates, and
flip-flops can be built from latches.
Both latches and flip-flops are circuit elements whose output depends not
only on the current inputs, but also on previous inputs and outputs. The difference
between a latch and a flip-flop is that a latch does not have a clock signal, whereas
a flip-flop always does.
Latches are asynchronous, which means that the output changes very soon
after the input changes. Most computers are synchronous, which means that the
outputs of all the sequential circuits change simultaneously to the rhythm of a clock
signal.
A flip-flop is a synchronous version of the latch.
S R Flip Flop or S R Latch
SR Flip Flop has two inputs S and R and two outputs Q
and Q . The state of this flip flop is determined by condition of
Q. If Q is 1 the latch is said to be SET and if Q is 0 the latch is
said to be RESET. This S R Flip flop can be designed either by
two cross-coupled NAND gates or two-cross coupled NOR
gates. SR flip flop is also called SET RESET Flip Flop. Figure below shows the
logic circuit of S R flip flop.
Truth table
S R Q Q Comment
0 0 NC No Change
0 1 0 1 Reset (0)
1 0 1 0 Set (1)
1 1 X X Indeterminate
NOR gate always gives output 0 when at least one of the inputs is 1.
Case-1 if S = 1 and R = 0.
When S is applied as 1 the output of gate G2 i.e. Q is 0 irrespective of the

condition of second input Q to the gate. Now Q is input of gate G1 so both the
inputs of G1 become 0 as R is already 0. So, output of G1 is 1. Q = 1 and Q = 0
when, S = 1 and R = 0. This is called SET condition of the flip flop.
Case-2 if S = 0 and R = 1
R is input to G1, so the output of gate G1 i.e. Q is 0 irrespective of the
condition of second input Q to the gate. Now Q fed back to input of gate G2. As
here S is already 0, both inputs of G2 are 0. Hence output of G2 i.e. Q will be 1. Q
= 0 and Q = 1 when, S = 0 and R = 1. This is called RESET condition of the flip
flop.

45
Case - 3 if S = 0 and also R = 0.

First suppose Q is previously 1. The inputs of G2 are 0 and 1 as S=0 and
Q=1. So output of G2 i.e. Q is 0. Now both inputs of G1 are 0 as R=0 and Q =0. So
output of G1 i.e. Q is 1. Now suppose Q is previously 0. Now both inputs of G2 are
0 and 0 as S=0 and Q=0. So output of G2 i.e. Q is 1. Now the inputs of G1 are 0
and 1 as R=0 and Q =1. So output of G1 i.e. Q is 0. Q remains same as it is when S
= 0 and R = 0, this is called No Change condition of the flip flop.
Case – 4 S = 1 and also R = 1.
As S=1, output of G2 i.e. Q is 0. Now the inputs of G1 are 1 and 0 as R=1

and Q =0. So output of G1 i.e. Q is 0. Q = 0 and Q = 0 when, S = 1 and R = 1. This
is called Not Allowed condition of the flip flop.
Clocked S R Flip Flop
Flip flop changes its state instantaneously on
the application of required inputs conditions. They
are asynchronous flip flops. On the other hand, a
clocked S-R latch can only change its output state
when there is an enabling signal along with required
inputs. That means the inputs can only act upon
when the flip flop is enabled otherwise there will be
no change in output state even required inputs are applied. In other words, the
latch is active when Clk signal is HIGH and it is inactive when Clk signal is LOW.
This HIGH LOW Clk signal is applied to the flip flop in the form of clocked pulses.
So, clocked S-R Flip flop is also synchronous S-R latch or a Gated S-R flip flop.
Since this latch responds to the applied inputs only when the level of the clock
pulse is high, the logical circuit of a Clocked S-R Flip-Flop is shown below.
Truth table
Clk S R Q Q Comment
0 X X NC No Change
1 0 0 NC No Change
1 0 1 0 1 Reset (0)
1 1 0 1 0 Set (1)
1 1 1 X X Indeterminate
A clocked S-R flip flop is designed by adding two AND gates to a basic NOR
Gate flip flop. The circuit diagram and truth table are shown figs.
Case-1
A clock pulse (Clk) is given to the inputs of the AND Gate. When the value of
the clock pulse is ‘0’, the outputs of both the AND Gates remain ‘0’. i.e., with clk=0,
the SR FF is in No Change condition.
Case-2 Clk=1, S = 1 and R = 0.
In this case S’=1 and R’=0, the o/p of Clk SR FF is Q = 1 and Q = 0 when, S
= 1 and R = 0. This is called SET condition of the flip flop.

46
Case-3 Clk=1, S = 0 and R = 1
= 0 and R = 1. This is called RESET condition of the flip flop.
Case - 4 Clk=1, S = 0 and also R = 0.
In this case S’=0 and R’=0, the o/p of Clk SR FF is Q remains same as it is
when S = 0 and R = 0, This is called No Change condition of the flip flop.
Case - 5 Clk=1, S = 1 and also R = 1.
= 1 and R = 1. This is called Not Allowed condition of the flip flop.
JK Flip-Flop
A JK flip-flop is a modification of the SR flip-flop in
that the indeterminate state of the SR type is defined in the
JK type. Inputs J and K behave like inputs S and R to set
and clear the flip-flop. Note that in a JK flip-flop, the i/p J is
for set and the i/p K is for reset as S and R in SR FF. When
logic 1 inputs are applied to both J and K simultaneously, the flip-flop switches to its
complement state, ie., if Q=1, it switches to Q=0 and vice versa.
Clk J K Q Q Comment
0 X X NC No Change
1 0 0 NC No Change
1 0 1 0 1 Reset (0)
1 1 0 1 0 Set (1)
1 1 1 T Toggle
A clocked JK flip-flop is shown in Figure. Output Q is ANDed with K and Clk

inputs. Similarly, output Q is ANDed with J and Clk inputs.
Case1: With clk=0 and what ever J and K i/ps have, the S and R get 0 and hence,
the JK FF is in No change condition.
Case2: Clk = 1, J = K = 0, Q = 1 and Q = 0. This results in S=R=0. Then the output

1st NOR gate will become 1(Q=1) as R = 0 and Q = 0, while the output of 2nd Nor
gate become 0 ( Q =0) as S = 0 and Q = 1. Thus o/p gets Q = 1 and Q = 0. This
indicates that the state of flip-flop outputs Q and Q remains unchanged for the case
of J = K = 0.
Case3: Clk=1, J = 0, K = 1, Q = 1 and Q = 0. This results S=0 and R=1. Then the
output 1st NOR gate will become 0 (Q=0) as R = 1 and Q = 0, while the output of
2nd Nor gate become 1 ( Q =1) as S = 0 and Q = 0. Thus o/p gets Q = 0 and Q = 1.
This implies that if J = 0 and K = 1, then the flip-flop resets (Q = 0 and Q = 1).
Case4: Clk=1, J = 1, K = 0, Q = 0 and Q = 1. This results S=1 and R=0. Then the
output of 2nd Nor gate become 0 ( Q =0) as S = 1 and Q = 0, while the output 1 st
NOR gate will become 1 (Q=1) as R = 0 and Q = 0. Thus o/p gets Q = 1 and Q =

47
0. This means that for the case of J = 1 and K = 0, flip-flop output will always be set
(Q = 1 and Q = 0).
Case5: Clk=1, J = K = 1, Q = 1 and Q = 0. This results S=0 and R=1. Then the
output 1st NOR gate will become 0 (Q=0) as R = 1 and Q = 0, while the output of
2nd Nor gate become 1 (Q =1) as S = 0 and Q = 0. Thus o/p gets Q = 0 and Q = 1.
This implies that if J = 1 and K = 1, then the flip-flop complements the previous
o/ps. This condition is called toggle condition of JK FF.
D Flip-Flop (Delay FF)
Clk D Q Comment
0 X NC No Change
1 0 0 Reset
1 1 1 Set
D Flip Flops are used to delay the digital signal by 1 clock period. It is
achieved by modifying JK FF b y joining the J and K i/ps by NOT gate and one i/p D
taken out as shown in figure. Thus K is Complement of J i/p.
If D=0, we have J=0, K=1 at clk=1, we get Q=0 and Q =1
If D=1, we have J=1, K=0 at clk=1, we get Q=1 and Q =0

Thus the o/p is equal to the i/p when clk=1. here the bit on D i/p transferred
to o/p after 1 clk interval. Hence it called 1 bit delay FF or 1 bit Bi stable FF.
T Flip-Flop (Toggle FF)
Clk T Q Comment
0 X NC No Change
1 0 NC No Change
1 1 T Toggle
The T flip-flop is a single input version of the JK flip-flop. As shown in Figure,

the T flip-flop is obtained from the JK type if both inputs are tied together. The
output of the T flip-flop "toggles" with each clock pulse. T flip flop acts as a toggle
switch. Toggle means to change in the previous stage i.e. switch to opposite state.
If T=0, i.e., J=K=0, in this case T FF is in same state as previous state (No
change Condition)
If T=1, i.e., J=K=1, in this case T FF comes under Toggle condition.

48
Master-Slave JK Flip-Flop
A master-slave flip-flop is constructed from two separate flip-flops. One

circuit serves as a master and the other as a slave. The logic diagram of an JK flip-
flop is shown in Figure. The master flip-flop is enabled on the positive edge of the
clock pulse and the slave flip-flop is disabled by the inverter. The information at the
external J and K inputs is transmitted to the master flip-flop. When the clk pulse
returns to 0, the master flip-flop is disabled and the slave flip-flop is enabled. The
slave flip-flop then goes to the same state as the master flip-flop.
When J=K=0, the o/p of the master and slave does not change.
When J=0 and K=1, the master Resets on +ve clk edge and low Q o/p of
master drives the slave to Reset on –ve clk edge. i.e., slave coping the action of
master.
When J=1 and K=0, the master Sets on +ve clk edge and high Q o/p of
master drives the slave to Set on –ve clk edge. i.e., slave coping the action of
master.
When J=1 and K=1, the master Toggles on +ve clk edge and slave Toggles
on –ve clk edge.
The truth table for this same as that of JK FF.

49
Flip-flop Types
FLIP-
FLIP-FLOP CHARACTERISTIC CHARACTERISTIC
FLOP EXCITATION TABLE
SYMBOL TABLE EQUATION
NAME
S R Q (next) Q Q (next) S R
0 0 Q 0 0 0 X
Q (next) = S + R'Q
SR 0 1 0 0 1 1 0
SR = 0
1 0 1 1 0 0 1
1 1 ? 1 1 X 0
J K Q (next) Q Q (next) J K
0 0 Q 0 0 0 X
JK 0 1 0 Q (next) = JQ' + K'Q 0 1 1 X
1 0 1 1 0 X 1
1 1 Q' 1 1 X 0
Q Q (next) D
D Q (next) 0 0 0
D 0 0 Q (next) = D 0 1 1
1 1 1 0 0
1 1 1
Q Q (next) T
T Q (next) 0 0 0
T 0 Q Q (next) = TQ' + T'Q 0 1 1
1 Q' 1 0 1
1 1 0
Registers
A register is a sequential circuit. A register is a group of binary cells suitable
for holding binary information. A group of FFs constitutes a register, since each FF
is binary cell having capable to store 1 bit of information. An n-bit register is group
of n- flip flops capable of store n bit of binary information. Registers play an
important role in computers. Some of them are visible to the programmer, and are
used to hold variable values for later use. Some of them are hidden to the
programmer, and are used to hold values that are internal to the central processing
unit.
A register capable of shifting binary information either to the left or to the
right is called a shift register. It consists of a chain of FFs connected in cascade,
with the o/p of one FF connected to the i/p of next FF and all flip flops receives
common clk pulse that causes the shift from one stage to next stage.
Shift registers have provisions to shift data serially, parallely or both, and to
the left or to the right. The basic types of shift registers are

50
1. Serial In - Serial Out shift register (SISO).
Block diagram of a serial-in/serial-out shift register shown in fig, which is 4-

stages long. Data at the input will be delayed by four clock periods from the input to
the output of the shift register.
2. Serial In - Parallel Out shift register (SIPO).
Fig shows block diagram of Serial In - Parallel Out shift register. Four data
bits will be shifted from “data in” by four clock pulses and be available at data out
at once.
3. Parallel In - Serial Out shift register (PISO).
Data is loaded into all stages at once of a parallel-in/serial-out shift register.

The data is then shifted out via “data out” by clock pulses. Since a 4- stage shift
register is shown above, four clock pulses are required to shift out all of the data.
4. Parallel In - Parallel Out shift register (PIPO).
Fig shows block diagram of Parallel In - Parallel Out shift register. Data in
and out take place by one clock pulse.
Serial-in to Parallel-out (SIPO) Shift Register

51
The operation is as follows. Lets assume that all the flip-flops ( FFA to FFD )
have been RESET ( CLEAR input ) and that all the outputs QA to QD are at logic
level “0”.
If a logic 1 is connected to the DATA input pin of FFA then on the first clock
pulse the output of FFA QA will be set “1” with all the other outputs still remaining
at “0”.
The second clock pulse will change the output of FFA to logic “0” and the
output of FFB and QB HIGH to logic “1” as its input D has the logic “1” from QA. The
logic “1” has now moved or been “shifted” one place along the register to the right
as it is now at QB.
When the third clock pulse arrives this logic “1” value moves to the output of
FFC ( QC ) and so on until the arrival of the fifth clock pulse which sets all the
outputs QA to QD back again to logic level “0” because the input to FFA has
remained constant at logic level “0”.
The effect of each clock pulse is to shift the data contents of each stage one
place to the right, and this is shown in the following table until the complete data
value of 0-0-0-1 is stored in the register. This data value can now be read directly
from the outputs of QA to QD.
Then the data has been converted from a serial data input signal to a
parallel data output. The truth table and following waveforms show the propagation
of the logic “1” through the register from left to right as follows.
Basic Data Movement through a Shift Register
Clock Pulse
QA QB QC QD
No
0 0 0 0 0
1 1 0 0 0
2 0 1 0 0
3 0 0 1 0
4 0 0 0 1
5 0 0 0 0
Note that after the

fourth clock pulse has ended
the 4-bits of data ( 0-0-0-1 )
are stored in the register and
will remain there provided
clocking of the register has
stopped. In practice the input
data to the register may
consist of various
combinations of logic “1” and
“0”.

52
Serial-in to Serial-out (SISO) Shift Register

This shift register is very similar to the SIPO above, except that before the
data was read directly in a parallel form from the outputs QA to QD, this time the
data is allowed to flow straight through the register and out of the other end. Since
there is only one output, the DATA leaves the shift register one bit at a time in a
serial pattern, hence the name Serial-in to Serial-Out Shift Register or SISO.
The SISO shift register is one of the simplest of the four configurations as it
has only three connections, the serial input (SI) which determines what enters the
left hand flip-flop, the serial output (SO) which is taken from the output of the right
hand flip-flop and the sequencing clock signal (Clk). The logic circuit diagram below
shows a generalized serial-in serial-out shift register.
This type of Shift Register also acts as a temporary storage device or it can
act as a time delay device for the data, with the amount of time delay being
controlled by the number of stages in the register.
Parallel-in to Serial-out (PISO) Shift Register
The Parallel-in to Serial-out shift register acts in the opposite way to the
serial-in to parallel-out one above. The data is loaded into the register in a parallel
format in which all the data bits enter their inputs simultaneously, to the parallel
input pins PA to PD of the register. The data is then read out sequentially in the
normal shift-right mode from the register at Q representing the data present at PA to
PD .
This data is outputted one bit at a time on each clock cycle in a serial format.
It is important to note that with this type of data register a clock pulse is not required
to parallel load the register as it is already present, but four clock pulses are
required to unload the data.
As this type of shift register converts parallel data, such as an 8-bit data
word into serial format, it can be used to multiplex many different input lines into a
single serial DATA stream which can be sent directly to a computer or transmitted
over a communications line.

53
Parallel-in to Parallel-out (PIPO) Shift Register

The final mode of operation is the Parallel-in to Parallel-out Shift Register.
This type of shift register also acts as a temporary storage device or as a time delay
device similar to the SISO configuration. The data is presented in a parallel format
to the parallel input pins PA to PD and then transferred together directly to their
respective output pins QA to QD b y the same clock pulse. Then one clock pulse
loads and unloads the register. This arrangement for parallel loading and unloading
is shown below.
4-bit Parallel-in to Parallel-out Shift Register
The PIPO shift register is the simplest of the four configurations as it has
only three connections, the parallel input (PI) which determines what enters the flip-
flop, the parallel output (PO) and the sequencing clock signal (Clk).
Shift Left Register
A four stage shift-left register is shown in figure. The single data input line is
connected as the D-input.
The shift pulse is applied to each stage operating each

simultaneously. When the shift pulse occur the data input is
shifted in to that stage. Each stage is set or reset
corresponding to the input data at the time the shift pulse
occurs. Thus the input data bit is shift in to stage A by the first
shift pulse. At the same time the data of stage A is shifted
into the stage B and so on for the following stages. At each
shift pulse data stored in the register stages shifts left by one stage. New data
shifted into stage A, whereas the data present in stage D is shifted out to the left for
use by some other.

54
For example consider starting with all stages reset all Q-outputs to logical 0 and
applying logical 1 input as data input stage A. Table shows the data in each stage
after each of four shift pulses.
Shift Right Register
Sometimes it is necessary to shift the least significant

digit first, as when addition is to be carried out serially. In
that case a shift right register is used as in Figure input
data is applied to stage D and shifted right. Thus the input
data bit is shift in to stage D by the first shift pulse. At the
same time the data of stage D is shifted into the stage C
and so on for the following stages. At each shift pulse
data stored in the register stages shifts right by one
stage. New data shifted into stage D, whereas the data present in stage A is shifted
out to the right for use by some other.
Table shows the action of shifting all logical 1 inputs into an shift register.
Counters
Counter is a sequential circuit. A digital circuit which is used for counting
pulses is known counter. Counter is the widest application of flip-flops. It is a group
of flip-flops with a clock signal applied. Since flip flop has 2 states, a cascade of flip
flops will count 2n i/p pulses. After count, it will again start from initial stage. A
counter may count up or count down depending on the input control.
Counters are classified into two categories:
Asynchronous Counters (Ripple counters)
Synchronous Counters
Asynchronous :
The events do not have a fixed time relationship with each other and do not
occur at the same time. In asynchronous counters, the first flip-flop is clocked by
the external clock pulse and then each successive flip-flop is by clocked the output
of the preceding flip-flop.
Synchronous :
The events have a fixed time relationship with each other and do occur at the same
time. In synchronous counters, the clock input is connected to all of the flip-flop so
that they are clocked simultaneously.
A counter may count up or count down depending on the input control.

55
Uses of Counters
The most typical uses of counters are
 To count the number of times that a certain event takes place; the
occurrence of event to be counted is represented by the input signal to
the counter.
 To control a fixed sequence of actions in a digital system.
 To generate timing signals.
 To generate clocks of different frequencies.
Mod 4 Asynchronous counter or 2 bit ripple counter
A two-bit asynchronous counter is shown in fig. The external clock is

connected to the clock input of the first flip-flop (FF0) only. So, FF0 changes state
at the falling edge of each clock pulse, but FF1 changes only when triggered by the
falling edge of the Q output of FF0. Because clk of FF1 connected to Q of FF0 and
a transition of the Q output of FF0 can never occur exactly at the same time.
Therefore, the flip-flops cannot be triggered simultaneously, producing an
asynchronous operation. Usually, all the CLEAR inputs are connected together, so
that a single pulse can clear all the flip-flops before counting starts.
Initially let both the FFs be in the reset state, i.e., QBQA = 00. At the first
negative clock edge is applied, FF-0 will toggle and QA will be equal to 1. QA is
connected to clock input of FF-1. Since QA has changed from 0 to 1, it is treated as
the positive clock edge by FF1. There is no change in QB because FF1 is a +ve
edge triggered. QBQA = 01 after the first clock pulse. On the arrival of second
negative clock edge, FF0 toggles again and QA = 0. The change in QA acts as a
negative clock edge for FF1. So it will also toggle, and QB will be 1. QBQA = 10
after the second clock pulse. On the arrival of 3rd negative clock edge, FF0 toggles
again and QA become 1 from 0. Since this is a positive going change, FF1 does
not respond to it and remains inactive. So QB does not change and continues to be
equal to 1. QBQA = 11 after the third clock pulse. On the arrival of 4th negative
clock edge, FF0 toggles again and QA becomes 1 from 0. This negative change in
QA acts as clock pulse for FF-2. Hence it toggles to change QB from 1 to 0. QBQA
= 00 after the fourth clock pulse.

56
Counting completed and counter back to initial condition.
CLK QB QA
0 0 0
1 0 1
2 1 0
3 1 1
4 0 0
A 4-bit asynchronous binary counter is shown in Fig. Each flip-flop is

negative edge-triggered. The external clock is connected to the clock input of the
first flip-flop (FF0) only. So, FF0 changes state at the falling edge of each clock
pulse, FF1 changes only when triggered by the falling edge of the Q output of FF0.
FF2 changes only when triggered by the falling edge of the Q output of FF1. FF3
changes only when triggered by the falling edge of the Q output of FF2.
When the Q output of a flip-flop transitions from 1 to 0, it commands the next
flip-flop to toggle. If the next flip-flop toggle is a transition from 1 to 0, it will
command the flip-flop after it to toggle as well.
This 4 bit counter can count 16 clk pulses. Usually, all the CLEAR inputs are
connected together, so that a single pulse can clear all the flip-flops before counting
starts. i.e., QA=QB=QC=QD=0
When first –ve clk edge applied, the FF0 toggles and QA=1 and remaining
o/ps are remains same. i.e., 0, because the clk pulse of remaing FFs are not
activated. After 1st clk pulse, the counter will be 0001.
When 2nd –ve clk edge arrives at FF0, first FF toggles, i.e., QA moves from 1
to 0, which changes the state of FF1. That means QB changes from 0 to 1. now
counter will be in 0010.
This process continuous up to 15 th clk pulse, at which all FF’s o/ps are high,
the counter will be in 1111.
At 16th pulse, o/ps of all FFs become 0. i.e., counter back to initial position.

57
CLK QD QC QB QA
0 0 0 0 0
1 0 0 0 1
2 0 0 1 0
3 0 0 1 1
4 0 1 0 0
5 0 1 0 1
6 0 1 1 0
7 0 1 1 1
8 1 0 0 0
9 1 0 0 1
10 1 0 1 0
11 1 0 1 1
12 1 1 0 0
13 1 1 0 1
14 1 1 1 0
15 1 1 1 1
Mod 10 counter or Decade counter
The modulus is the number of unique states that counter can count. The
maximum possible number of states of a counter is 2n where n is the number of flip-
flops. Counters can be designed to have a number of states in their sequence that
is less than the maximum of 2 n. This type of sequence is called a truncated
sequence. One common modulus for counters with truncated sequences is 10
(Modules10) and is called decade counter. A decade counter requires 4 flip-flops

58
and counter back to initial after the count of 9 (1001). It can count total of 10
pulses from 0000 to 1001 as like mod 16 asynchronous counters. Here the output
of the NAND gate connected to the clear (CLR) inputs of the flip-flops, as shown in
Fig. this NAND gate turns the counter to it initial position when count is 1010.
CLK QD QC QB QA
0 0 0 0 0
1 0 0 0 1
2 0 0 1 0
3 0 0 1 1
4 0 1 0 0
5 0 1 0 1
6 0 1 1 0
7 0 1 1 1
8 1 0 0 0
9 1 0 0 1
A 3-bit asynchronous counter is shown in fig. The external clock is

connected to the clock input of the first flip-flop (FF0) only. So, FF0 changes state
at the falling edge of each clock pulse.
Usually, all the CLEAR inputs are connected together, so that a single pulse
can clear all the flip-flops before counting starts.
Initially let both the FFs be in the reset state, i.e., QCQBQA = 000. At the
first negative clock edge is applied, FF-0 will toggle and QA will be equal to 1. QA is
connected to clock input of FF-1. Since QA has changed from 0 to 1, it is treated as
the positive clock edge by FF1. There is no change in QB because FF1 is a +ve
edge triggered. State of FF2 is also remains same, because o/p Q of FF1
connected to Clk i/p of FF2. QCQBQA = 001 after the first clock pulse. After the
second clock pulse QCQBQA = 010. This process continuous up to 7 clk pulse,
After the 7th clock pulse QCQBQA = 111. On the arrival of 8 th negative clock edge,
QCQBQA = 000.

59
Counting completed and counter back to initial condition.
CLK QC QB QA
0 0 0 0
1 0 0 1
2 0 1 0
3 0 1 1
4 1 0 0
5 1 0 1
6 1 1 0
7 1 1 1
Mod 16 Synchronous counter or 4 bit Synchronous counter
Ripple counter are slow, because cumulative FF’s delay. A relatively simple
way to reduce the program time delay is to use a synchronous counter.
All the FFs in the synchronous counter are triggered by common clk pulse,
although the synchronous counter more complicated than ripple counter. A mod 16
synchronous counter is shown in figure.
It consists of –ve edge triggered JK FFs. Initially all the FFs are in reset
state. i.e. Q0= Q1= Q2= Q3=0, since JK FF0 have high i/p, the FF0 toggles on first –
ve clk edge and the same clk does not change state of FFs 1, 2 and 3, because
i/ps are low. Hence, at 1st clk pulse the o/p is 0001.
The first and second FFs toggles on 2 nd –ve clk pulse, because J, K i/ps of
FF0 and FF1 FFs are high. Remaing 2, 3 FFs remain in same state, because their
i/ps are low. Hence, after 2nd clk pulse counter becomes 0010
When the 3rd clk pulse arrived, the counter becomes 0011, after 1
propagation delay time, the counter becomes 0100. This process continuous up to
counter reaches 1111 and for next clk pulse the counter back to initial position or
state.
By adding more FFs and AND gates , we can construct synchronous
counter of any length. The advantage of synchronous over asynchronous is its fast
operating feature.

60
CLK Q3 Q2 Q1 Q0
0 0 0 0 0
1 0 0 0 1
2 0 0 1 0
3 0 0 1 1
4 0 1 0 0
5 0 1 0 1
6 0 1 1 0
7 0 1 1 1
8 1 0 0 0
9 1 0 0 1
10 1 0 1 0
11 1 0 1 1
12 1 1 0 0
13 1 1 0 1
14 1 1 1 0
15 1 1 1 1
Down Counter
Fig shows down counter. It counts from 1111 to 0000. each FF toggles when
it clk goes from 0 to 1. initially with the clear signal, all FFs are reset to 0 and the
o/p is 1111.
The FF0 toggles for every clk pulse.
The 1st clk pulse produces o/p word 1110
The 2nd clk pulse produces o/p word 1101
The 3rd clk pulse produces o/p word 1100

61
The counter is counting down from 15 to 0, when it reaches 0, the o/p is

0000. on the next clk pulse, all the FFs toggles +vely to get 1111. i.e. cycle repeats.
CLK Q3 Q2 Q1 Q0
0 1 1 1 1
1 1 1 1 0
2 1 1 0 1
3 1 1 0 0
4 1 0 1 1
5 1 0 1 0
6 1 0 0 1
7 1 0 0 0
8 0 1 1 1
9 0 1 1 0
10 0 1 0 1
11 0 1 0 0
12 0 0 1 1
13 0 0 1 0
14 0 0 0 1
15 0 0 0 0
Ring Counters
A ring counter is basically a circulating shift register in which the output of

the most significant stage is fed back to the input of the least significant stage. The
following is a 4-bit ring counter constructed from D flip-flops. The output of each
stage is shifted into the next stage on the positive edge of a clock pulse. If the
CLEAR signal is high, all the flip-flops except the first one FF0 are reset to 0. FF0 is
preset to 1 instead.
Since the count sequence has 4 distinct states, the counter can be
considered as a mod-4 counter. Only 4 of the maximum 16 states are used, making
ring counters very inefficient in terms of state usage. But the major advantage of a
ring counter over a binary counter is that it is self-decoding. No extra decoding
circuit is needed to determine what state the counter is in.

62
UNIT – V
MEMORY DEVICES
The basic goal of digital memory is to provide a means to store and access
binary data: sequences of 1’s and 0’s. The digital storage of information has
advantages over analog techniques. This is not to say that digital data storage is
extremely superior to analog, but it does address some of the more common
problems associated with analog techniques and thus finds immense popularity in
both consumer and industrial applications. Digital data storage is also use in digital
computations, and thus finds natural application in the world of computers. The
most advantage of digital data storage is the resistance to corruption.
A memory is just like a human brain. It is used to store data and instruction.
Computer memory is the storage space in computer where data is to be processed
and instructions required for processing are stored. The memory is divided into
large number of small parts. Each part is called a cell. Each location or cell has a
unique address which varies from zero to memory size minus one.
For example if computer has 64k words, then this memory unit has 64 *
1024 = 65536 memory location. The address of these locations varies from 0 to
65535.
Memory is primarily of two types
1. Internal Memory − cache memory and primary/main memory
2. External Memory − secondary memory /magnetic disk / optical disk etc.
The main memory of the computer system is volatile, it holds
information(data, programs and results) as long as power supply is on. Therefore,
to store information and supervise programs, a computer must have a permanent
storage memory. Magnetic/optical memories can used as permanent memory and
is called secondary memory.
Memory Operations in calculator
Calculator can remember results of operations for you, and reuse them in
later calculations. You can access these functions via several buttons labeled MR,
MS, M+ and MC.
MS : The MS button stores the currently displayed result in memory.
M+ : The M+ button adds the current result to the one in memory. So, if
you had stored 20, and the current result is 5, your memory would
contain 25 when you press it. If the memory is empty, it acts like MS
and simply stores the result.
MR : The MR button gets the value stored in memory and puts it in the
display.
MC : The MC button clears the memory.

63
General Memory Operations

There are two key operations on
memory:
1. Fetch (address) returns value
without changing the value stored at that
address.
2. Store (address, value) writes new
value into the cell at the given address.
This type of memory is random-
access, meaning that CPU can access any
value of the array at any time (vs.
sequential access, like on a tape). Such memories are called RAM (random-access
memory.) Some memory is non-volatile, or read-only (ROM or read-only memory.)
MAR stands for memory address register:
 MAR is connected to the address bus.
 MAR is "the only way" for the CPU to communicate with address bus.
 Tri-state buffer between MAR and the address bus prevents MAR from
continuously dumping its output to the address bus.
 MAR can hold either an instruction address or a data address.
MDR Stands for memory data register.
 MDR is connected to the data bus.
 Data can go in both directions: to and from memory. Therefore, MDR can
load its data from the data bus (for reading data) or to one of the CPU
registers (for storing data.)
Semiconductor memories
Semiconductor memory is a static device. It is faster, smaller in size, lighter
in weight and consumes less power compared to other types of memory devices.
Semiconductor memories are used as main memory. There are 2 types’
semiconductor memories.
1. RAM - Random Access Memory
2. ROM - Read Only Memory
RAM - Random Access Memory
A RAM constitutes the internal memory of the CPU for storing data, program
and program result. It is read/write memory. It is called random access memory
RAM. We can access the memory at random, extremely fast and quite expensive.
RAM is volatile, i.e. data stored in it is lost when we switch off the power. Hence, a
backup uninterruptible power system UPS is often used with computers. RAM is
small, both in terms of its physical size and in the amount of data it can hold.
RAM is of two types
Static RAM SR AM
Dynamic RAM DRAM

64
Static RAM - SRAM

The word static indicates that the memory retains its contents as long as
power remains applied. However, data is lost when the power gets down due to
volatile nature. SRAM chips use a matrix of 6-transistors and no capacitors.
Transistors do not require power to prevent leakage, so SRAM need not have to be
refreshed on a regular basis. Because of the extra space in the matrix, SRAM uses
more chips than DRAM for the same amount of storage space, thus making the
manufacturing costs higher.
Static RAM is used as cache memory needs to be very fast and small.
Dynamic RAM - DRAM
DRAM, unlike SRAM, must be continually refreshed in order to maintain the
data. This is done by placing the memory on a refresh circuit that rewrites the data
several hundred times per second. DRAM is used for most system memory
because it is cheap and small. All DRAMs are made up of memory cells. These
cells are composed of one capacitor and one transistor.
Differences between Static RAM and Dynamic RAM
SRAM DRAM
SRAM is made up of DRAM is made up of
FFs. MOS transistor gates.
It stores bit as a voltage. It stores bit as a charge.
It retains stored It losses it information in
information as long as very short time even
power supply is ON. power supply is ON.
It has less package It has more package
density. density.
It require an additional
It does not require ckt for refreshing,
refreshing. because of leakage of
charge.
It consumes more power It consumes less power
and expansive and economic compared
compared to DRAM. to SRAM
It is used where medium It is used where large
size of memory is size of memory is
required. required.
ROM
ROM stands for Read Only Memory. We can only read but cannot write on it. ROM
is non-volatile. The information is stored permanently in such memories during
manufacture. A ROM, stores such instruction as are required to start computer
when is first turned on, this operation is referred to as bootstrap. ROM chips are not
only used in the computer but also in other electronic items like washing machine
and microwave oven.
ROMs are divided in 2 types
1. Masked Programmable ROMs
2. User Programmable ROMs

65
MROM- Masked ROM

The very first ROMs were hard-wired devices that contained a pre-
programmed set of data or instructions. These kinds of ROMs are known as
masked ROMs. It is inexpensive ROM. In this ROM the bit pattern is permanently
recorded by masking and metallization process. i.e., contents are stored at the time
of manufacturing only.
User Programmable ROMs
User Programmable ROMs are
1. PROM (Programmable Read Only Memory)
2. EPROM (Erasable and Programmable ROM)
3. EEPROM (Electrically Erasable and Programmable ROM)
PROM - Programmable Read Only Memory
PROM is read-only memory that can be modified only once by a user. The
user buys a blank PROM and enters the desired contents using a PROM
programmer. Inside the PROM chip there are small fuses which are burnt open
during programming. It can be programmed only once and is not erasable.
EPROM - Erasable and Programmable Read Only Memory
The EPROM can be erased by exposing it to ultra-violet light for duration of
up to 40 minutes. Usually, an EPROM eraser achieves this function. During
programming an electrical charge is trapped in an insulated gate region. The
charge is retained for more than ten years because the charge has no leakage
path. For erasing this charge, ultra-violet light is passed through a quartz crystal
window lid. This exposure to ultra-violet light dissipates the charge. During normal
use the quartz lid is sealed with a sticker.
EEPROM - Electrically Erasable and Programmable Read Only
Memory
The EEPROM is programmed and erased electrically. It can be erased and
reprogrammed about ten thousand times. Both erasing and programming take
about 4 to 10 milliseconds. In EEPROM, an y location can be selectively erased and
programmed. EEPROMs can be erased one byte at a time, rather than erasing the
entire chip. Hence, the process of re-programming is flexible but slow.
Serial Access Memory
Sequential access means the system must search the storage device from
the beginning of the memory address until it finds the required piece of data.
Memory device which supports such access is called a Sequential Access Memory
or Serial Access Memory. Magnetic tape is an example of serial access memory.
Direct Access Memory
Direct access memory or Random Access Memory, refers to conditions in
which a system can go directly to the information that the user wants. Memory
device which supports such access is called a Direct Access Memory. Magnetic
disks, optical disks are examples of direct access memory.

66
Cache Memory
Cache memory is a very high speed semiconductor memory which can
speed up CPU. It acts as a buffer between the CPU and main memory. It is used to
hold those parts of data and program which are most frequently used by CPU. The
parts of data and programs, are transferred from disk to cache memory by
operating system, from where CPU can access them.
Advantages
 Cache memory is faster than main memory.
 It consumes less access time as compared to main memory.
 It stores the program that can be executed within a short period of
time.
 It stores data for temporary use.
Disadvantages
 Cache memory has limited capacity.
 It is very e xpensive.
Auxiliary Memory
Au xiliary memory is much larger in size than main memory but is slower. It
normally stores system programs, instruction and data files. It is also known as
secondary memory. It can also be used as an overflow/virtual memory in case the
main memory capacity has been exceeded. Secondary memories cannot be
accessed directly by a processor. First the data/information of auxiliary memory is
transferred to the main memory and then that information can be accessed by the
CPU.
Programmable Logic Array (PLA)
A PLA consists of two levels of logic gates: a programmable, “wired” AND-
plane followed by a programmable, “wired” OR-plane. A PLA's structure allows any
of its inputs (or their complements) to be AND-ed together in the AND plane; each
AND plane output can thus correspond to any product term of the inputs. Similarly,
users can configure each OR plane output to produce the logical sum of any AND
plane output. With this structure, PLAs are well-suited for implementing logic
functions in sum-of-products form.
In a PLA, the number of AND functions is independent of the number of
inputs, and the number of OR functions is independent of both the number of inputs
and the number of AND functions.
The PLA design can implement following

functions.
X  ΑBC  ΑBC ΑBC
Y  ΑBC ΑBC
Example:

67
Before Simplification the functions are

F1  ΑBC
F2  Α B C  ΑBC  ΑBC  Α B C  Α BC  ABC  ΑBC
F3  ΑB C
F4  ΑB C  Α BC  ΑBC  ΑBC  Α B C  ΑB C  ABC
F5  ΑB C  ΑBC  ΑB C  ΑBC
Programmable Array Logic (PAL)

PALs use an OR gate array with fixed logic while an AND gate array which
can be programmed as per the requirement of the user. As a result, these devices
express the output as a combination of inputs in sum-of-products form.
The PAL design can implement following functions.

X  ΑBC  ΑBC
Y  ΑBC  ΑBC
PLAs are more flexible than PALs, but PALs operate faster, because hard-wired
connections take less time to switch than their programmable equivalents. Due to
the fact they are fast and cheap to manufacture.

68
Example:
In this given PAL, Four product terms for each OR gate.

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B.Sc. Electronics - III Semester – Paper- 3

B.Sc. Electronics R L V P rasad, Sr. Lect in Electronics, SGCSR College, Rajam

Binary Number System

B.Sc. Electronics R L V P rasad, Sr. Lect in Electronics, SGCSR College, Rajam

NUMBER SYSTEM CONVERSION

B.Sc. Electronics R L V P rasad, Sr. Lect in Electronics, SGCSR College, Rajam

B.Sc. Electronics R L V P rasad, Sr. Lect in Electronics, SGCSR College, Rajam

B.Sc. Electronics R L V P rasad, Sr. Lect in Electronics, SGCSR College, Rajam

Ex: Convert Decimal number 25 to excess-3 code:

Application of Gra y code

B.Sc. Electronics R L V P rasad, Sr. Lect in Electronics, SGCSR College, Rajam

Gray code : 10011

B.Sc. Electronics R L V P rasad, Sr. Lect in Electronics, SGCSR College, Rajam

B.Sc. Electronics R L V P rasad, Sr. Lect in Electronics, SGCSR College, Rajam

Ex: 110101 – 100101

B.Sc. Electronics R L V P rasad, Sr. Lect in Electronics, SGCSR College, Rajam

B.Sc. Electronics R L V P rasad, Sr. Lect in Electronics, SGCSR College, Rajam

B.Sc. Electronics R L V P rasad, Sr. Lect in Electronics, SGCSR College, Rajam

AND Gate using Diodes

In the above circuit we first apply +5V at VCC.

In the above circuit when A or B or both A and B are grounded or at 0V

B.Sc. Electronics R L V P rasad, Sr. Lect in Electronics, SGCSR College, Rajam

B.Sc. Electronics R L V P rasad, Sr. Lect in Electronics, SGCSR College, Rajam

B.Sc. Electronics R L V P rasad, Sr. Lect in Electronics, SGCSR College, Rajam

B.Sc. Electronics R L V P rasad, Sr. Lect in Electronics, SGCSR College, Rajam

B.Sc. Electronics R L V P rasad, Sr. Lect in Electronics, SGCSR College, Rajam

NAND gate as Universal Gate

B.Sc. Electronics R L V P rasad, Sr. Lect in Electronics, SGCSR College, Rajam

OR gate using NAND gates.

NOT gate using NAND gate.

Ex-OR gate using NAND gates.

NOR gate as Universal Gate

AND gate using NOR gates.

NOT gate using NOR gate.

B.Sc. Electronics R L V P rasad, Sr. Lect in Electronics, SGCSR College, Rajam

Ex-OR gate using NOR gates.

B.Sc. Electronics R L V P rasad, Sr. Lect in Electronics, SGCSR College, Rajam

B.Sc. Electronics R L V P rasad, Sr. Lect in Electronics, SGCSR College, Rajam

B.Sc. Electronics R L V P rasad, Sr. Lect in Electronics, SGCSR College, Rajam

Boolean Function standard Representation

AB, AB, AB and AB

ABC, ABC, ABC, ABC, ABC, ABC, ABC, and ABC

Minterms and maxterms for 3 binary variables

B.Sc. Electronics R L V P rasad, Sr. Lect in Electronics, SGCSR College, Rajam

Function of 3 binary variables

Now function f  ABC  ABC  ABC  ABC  ABC

From above table maxterms are A  B  C, A  B  C, A  B  C

Now function f  (A  B  C).(A  B  C).( A  B  C)

Canonical Form (Standard SOP and POS Form)

From above table f  ABC  ABC  ABC  ABC  ABC

B.Sc. Electronics R L V P rasad, Sr. Lect in Electronics, SGCSR College, Rajam

Karnaugh Maps (K-maps)

Simplification using K-maps

B.Sc. Electronics R L V P rasad, Sr. Lect in Electronics, SGCSR College, Rajam

The simplified Boolean expression is f  AC  AB

f  ABCD  ABCD  ABCD  ABCD  ABCD ABCD  ABCD  ABCD  ABCD

B.Sc. Electronics R L V P rasad, Sr. Lect in Electronics, SGCSR College, Rajam

Before simplification the Boolean function is