5.

ADVANCED MICROPROCESSORS
5.1 80286 MICROPROCESSOR
The 80286 microprocessor is a third generation,16-bit microprocessor. It is the advanced version of the
8086 processor and is designed for multiuser and multitasking environments. The 80286 performance is six
times faster than the 8086 microprocessor.
Features of 80286:
 The Intel 80286 is a high performance 16-bit microprocessor designed for multitasking and multi
programming.
 The 80286 can be operated at three different clock speeds. These are 12.5MHz, 10MHz, 8MHz.
 It has 24-bit address bus so it can directly address 16M bytes of physical memory.
 It has 1G bytes of virtual (not physical) memory.
 It is housed in a 68 pin leadless flat package.
 It is operated in two modes they are Real Address Mode and Protected Virtual Address Mode (PVAM).
 It has four functional units they are bus unit (BU), address unit (AU), instruction unit (IU), and
execution unit (EU).
 It has four general purpose registers of size 16-bit and they are AX, BX, CX, DX and four special purpose
registers of size 16-bit and they are SP, BP, SI, DI.
 It has four segment registers of size 16-bit and they are CS, DS, ES, and SS.
 It has a 16 bit flag register in that 15 flags are used. They are AF (auxiliary carry flag), CF (carry flag), ZF
(zero flag), OF (overflow flag), SF (sign flag), TF (trap flag), IF (interrupt flag), DF (direction flag),
similar to 8086. The additional 6 flags are IOPL(i/o privilege field),NT (nested task),
In MSW: PE (protection enable), MP (monitor processor extension), EM (processor extension emulator),
and TS (task switch).
 Through memory management unit the 80286 addresses a virtual memory space of 1G bytes.
 The 80286 performance is six times faster than the 8086 microprocessor.

5.2 ARHITECTURE OF 80286

The architecture of 80286 is divided into four functional units. They are Bus unit (BU), Address Unit (AU),
Instruction Unit (IU), and Execution Unit (EU). The Architecture of 80286 is shown in figure. The function
of each block is explained as follows.
Bus unit (BU):
The bus unit main purpose is to provide the communication between the 80286 microprocessor with the
outside of the world (peripheral devices). The functions of bus unit is given below
 The physical address computed by the AU is handed over the bus unit (BU).
 BU fetches the instructions, reads data from memory and I/O ports & writes data to memory and I/O ports.
 This BU involves the concept of “instruction pipelining” which fetches the instructions from the memory
and stored them in 6-byte pre fetch instruction queue.
 The BU also contains the processor extension interface block which is used to connect the math processors
(80287) to the 80286.
 The data transceivers interface and control the internal data bus with the system bus.

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 Address unit (AU):
The address unit is responsible for calculating the 20-bit physical address of instructions and data that
the CPU wants to access it.
 This unit calculates the 20-bit physical address based on the contents of the 16-bit segment register and a
16-bit offset value.
 The 80286 addresses a 1M byte of physical memory as same as 8086 in Real Address Mode.
 In Protected Virtual Address Mode (PVAM), the AU operates as a Memory Management Unit(MMU)
and utilizes all 24 address lines to provide 16M bytes of physical memory.
 In PVAM mode the physical address is calculated by using the selector, data descriptor table, and data
descriptor.

Instruction Unit (IU):

The instruction unit receives the pre-fetched instructions from 6-byte pre-fetch instruction queue of the bus
unit (BU) and decode it. The functions of IU is given below
 The instruction decoder in the IU is used to decode the instructions from the 6-byte pre-fetch
instruction queue and is given to the 3-decoded instruction queue.
 The 3-decoded instruction queue is used to store the decoded instructions from the instruction decoder.
Execution Unit (EU):
The execution unit takes the decoded instructions from the IU and execute them. The functions of EU is
given below
 The EU has a 16-bit ALU which performs the arithmetic and logical operations.

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  It has 4 general purpose registers for handling the data and 4 special purpose registers for offset
address calculation.
 It has a control unit which generates the necessary control signals for the system operations.
5.3 OPERATING MODES OF 80286
The 80286 operates in two modes:
1. Real address mode (RAM)
2. Protected Virtual address mode (PVAM)
REAL ADDRESS MODE:
 In the real addressing mode the operation of 80286, it just acts as a fast 8086.
 The instruction set is upwardly compatible with that of 8086.
 In this mode it can access up to 1MB of physical memory using A0- A19 address lines. The lines A20- A23
are not used by the internal circuit of 80286 in this mode.
 In this mode the 80286 uses 𝐵𝐻𝐸 along with A0- A19 for addressing the physical memory.
 To produce 20-bit physical address by simply adding an offset (IP, BX, BP, SP, SI, DI and SI) to a
segment base (CS, DS, ES and SS) as in case of 8086.
 The 80286 reserves two fixed areas of physical memory for system initialisation and interrupt vector
table.
 In this mode the first 1 Kbyte of memory starting from 00000H to 003FFH is reserved for interrupt
vector table. Also the addresses from FFFF0H to FFFFFH is reserved for system initialization.
 The program execution starts from FFFF0H after reset and initialization.
 The below figure shows how 80286 calculates physical address in real mode

Fig. Physical address calculation in 80286 real mode

PROTECTED VIRTUAL ADDRESS MODE (PVAM):
 The 80286 microprocessor enters into the protected virtual address mode from the real address
mode by setting the PE (protection enable) bit of Machine Status Word(MSW).

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  The main features of Protected Virtual Address Mode are:
 Memory management
 Virtual addressing
 Memory protection mechanism
 Task switching and interrupt processing.
 In this mode, 80286 access 16MB of (From 000000H to FFFFFFH) physical memory and 1GB
of virtual memory.
 In this mode the physical address (24-bit) is generated by adding 24-bit segment base address to
16-bit offset address
 The segment base address is provided by the descriptors
 The descriptor is a block of contiguous eight memory locations containing information of a
segment, like segment base address, segment limit, segment type, privilege level, segment
availability in physical memory.

Fig. Translation of 80286 32-bit virtual address to 24-bit physical address

COMPARISION BETWEEN REAL ADDRESS MODE & PVAM

REAL ADDRESS MODE PVAM
1. Upon reset, the 80286 operates in this mode. 1. By setting PE bit of MSW the 80286 entering into
PVAM
2. In real mode, the 80286 acts as fast 8086. 2. In PVAM, 80286 supports the concept of virtual

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 memory and the memory management.
3. In this mode 80286 access only 1MB of physical 3. In this mode 80286 access 16MB of physical
memory using A0- A19 memory & 1 GB of virtual memory.
4. In this mode 20-bit physical address is generated in 4. In this mode 24-bit physical address is generated by
the same way as 8086. adding 24-bit base address of the selected descriptor
and 16-bit offset.
5. In this mode all memory management & protection 5. In this mode 80286 works with all of the memory
mechanism are disables. management and protection capabilities.

5.4 MEMORY MANAGEMENT OF 80286

In protected mode the Address Unit is called as Memory Management Unit (MMU)
The memory management unit (MMU) of 80286 has two functions:
1. Converts the logical address into physical address
2. It avoids the interference between users and operating systems. This feature is called
protection
 The address in programs is called logical address.
 The address required by the memory hardware is known as physical address.

Conversion of logical address into physical address:

 When the 80286 is switched to Protected Virtual Mode, the virtual memory comes in use.
 In 80286, the physical memory is 16MB and the virtual memory is 1GB
 When a part of the program to be executed is transferred from secondary memory to physical memory,
the MMU computes the physical address (Translates 32-bit Virtual Address to 24-bit PA) where it will
be placed in physical memory.
 The 32-bit virtual address consists of two components – 16-bit selector and 16-bit offset.
 16-bit selector is used to fetch the descriptor from descriptor table. The descriptor
provides Segment Base address, segment limit, privilege level of segment and some
control bits.
 Out of 16 –bits o selector, 14 bits are address bits and two privilege level bits. By using
14 bits any one of 16,384 (214) descriptors can be selected from the descriptor table.

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  Now the 24-bit segment base address is added to 16-bit offset address to generate 24-bit physical
address.
 In 80286, the number of descriptors = 16K (214) and the maximum size of segment = 64KB (216).
 Then Virtual memory space = No of segments * size of each segment
16K (214) * 64KB (216) = 1GB (230).

5.5 FEATURES OF 80386:

 It is a high performance 32-bit microprocessor.

 It has a separate 32-bit data bus and 32-bit address bus.
 It can access 232 = 4 GB of physical memory.
 It can access 64TB of virtual memory.
 It is upward compatible with 8086 instruction set.
 It has 2, 75, 000 transistors.
 It has on-chip address translation cache.
 The memory management unit of 80386 can support the concept of paging, used to organize the
segmented memory into pages. Each page is of 4KB size.
 The 80386 can be supported by 80387 for mathematical data processing.
 80386 are available in 132-pin grid array package and have 20MHz and 33MHz versions.
 In 80386 memory management unit provides four level protection mechanism for protecting and
isolating the system code and data from application program.
 The 80386 can run 8086 applications under protected mode in its virtual 8086 mode of operation.

5.6 ARCHITECTURE OF 80386:

The internal architecture of 80386 is divided into three sections they are central processing unit, memory
management unit and bus control unit.
Central processing unit:
The central processing unit is further divided into execution unit and instruction unit.
 The execution unit has eight general purpose and eight special function registers, they are used to store
data operands and offset addresses.
 The instruction unit decodes the op-code bytes received from the 16-byte code queue and the decoded
instructions are stored in 3-decoded instruction queue.
 The decoded instructions then passed to the control section for deriving the necessary control signals.
 The barrel shifter is used to increase the speed of the shift and rotate operations.
 The multiply/divide logic implements bit-shift-rotate algorithms to complete the operations (arithmetic
operations like division and multiplication) in minimum time.
Memory management unit:
The memory management unit consists of segmentation and paging unit.
 The segmentation unit allows two address components. They are segment address and offset address for
sharing of code and data.
 The segmentation allows maximum size of 4GB segments.
 The paging unit organizes the physical and virtual memory in terms of pages of size 4KB.

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  The paging unit works under the control of segmentation unit.
 Each segment is further divided into pages of size 4KB.
 The segmentation unit provides four level protection mechanism for protecting and isolating system
code from application program.

Bus control unit:

Bus control unit is used to control the system bus in allocating bus to various external devices.
 The bus control unit has a prioritizer to resolve the priority of various bus requests, to control the access
of the bus.
 The address driver drives the bus enable and address lines A0-A31.
 The pipeline and dynamic bus sizing units handle the related control signals like M/IO#, D/C#, W/R#,
LOCK# etc.
 The data buffers interfaces the internal data bus with the system bus.

5.7 OPERATING MODES OF 80386:

The 80386 microprocessor can he operated in three modes. They are:

1. Real Address Mode (Real mode)
2. Protected Virtual Address Mode (Protected Mode)
3. Virtual 8086 Mode (V86 Mode)

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1. REAL MODE:

Fig. Physical address calculation in 80386 Real mode

 Real address mode is the simplest and most basic operating mode that the 80386 supports.
 Whenever the 80386 is reset or powered up it begins operating in real mode.
 In the real mode 80386 works as fast 8086 with 32-bit registers and data types.
 In this mode the processor 80386 can access 1 MB of physical memory with 20-bit physical address just
like as 8086.
 Paging unit is disabled in real mode, and hence the real addresses are the same as the physical addresses.
 To form a physical memory address, appropriate segment registers contents (16-bits) are shifted left by
four positions and then added to the 16-bit offset address.
2. PROTECTED MODE:
 The 80386 processor can switched to protected mode from real mode by setting the PE (Protection
Enable) bit in CR0 or MSW register.
 In this mode the processor 80386 can run all the programs of 80286 and 8086 under the control of
memory management and protection abilities of 80386.
 In this mode the processor 80386 can access 4GB (232) of physical memory 64TB (246) of virtual memory
per task.
 Once 80386 enter the protected mode from real mode, it cannot return back to the real mode without reset
operation
 Protected mode vastly increases the linear address space to 4GB and allows the running of virtual memory
programs of size 64TB. It also provides sophisticated memory management and protection mechanism.
Virtual memory space = 16K (214) Selectors * Size of segment 4 GB (232) = 64 TB (246).

Fig. Address calculation in Protected mode without paging.

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 Fig. shows addressing in protected mode without paging. The content of segment registers are used to
access descriptors. The segment descriptor contains segment base address (32-bit), limit and access rights
byte.
 The offset (32-bit) is added with 32-bit segment base address to obtain linear address. This is the physical
Address when paging is not enabled.
 When paging is enabled the linear address is translated to 32-bit physical address as shown in fig.
 When paging is enabled (By setting MSB bit (PG) of CR0) the memory segments are divided into 4KB
pages.

Fig. Address calculation in Protected mode when paging is enabled

3. V86 MODE
 In this mode 80386 can go back and forth repeatedly between V86 mode and protected mode at a fast
speed. The processor 80386 can switched to V86 mode from protected mode by setting VM (Virtual
mode) bit of EFLAG register.
 The VM bit may be reset to zero to pull back the 80386 into protected mode.
 The processor can then leave V86 mode and enter protected mode to execute an 80386 program
 In this mode the processor access 1MB of physical memory that may be anywhere in 4GB address space
of protected mode.
 In this mode the paging mechanism and protection capabilities are available.
 Paging unit may not be necessarily enabled in the virtual mode, but may be needed to run the 8086
programs which require more than 1MB of memory for memory management functions.

5.8 MEMORY ORGANIZATION IN 80386

 The physical memory system of the 80386 is 4 GB in size.
 Fig. shows the organization of the 80386 physical memory systems. The memory of 80386 is divided into
four 8-bit wide memory banks, each containing up to 1 GB of memory.
 This 32-bit wide (4 x 8 = 32) memory organization allows bytes, words, or double words of memory data
to be accessed directly.
 The 80386 transfers up to 32-bit data in a single memory or machine cycle.
 The address generated to select any memory location in 80386 is range from 00000000H to FFFFFFFFH.

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  The memory banks are accessed by using four bank enable signals 𝐵𝐸 0- 𝐵𝐸 3 which are generated using
A0 and A1 address bits.
 A single byte is accessed when one bank enable (𝐵𝐸0) signal is activated.
 A word is accessed when two bank enable signals(𝐵𝐸1 𝑎𝑛𝑑 𝐵𝐸0) are activated.
 A double word is accessed when all four bank enable signals are activated.
 Memory locations 0000 0000H is in bank0, location 0000 0001H is in bank1, location 0000 0002H is in
bank2 and location 0000 0003H is in bank 3.

Fig. Memory Organization in 80386

5.9 DESCRIBE PIPE LINING.

 Pipelining is the process of fetching the next instruction before the current instruction is executed.
 It is useful to speed up program execution.
 A pipeline allows multiple instructions to be processed at the same time.
Example: Compare the three-instruction sequences as shown in figures.
Non-pipelined: On a non-pipelined machine, 9 clock cycles are needed for the individual fetch (F), decode (D),
and execute (E) cycles.

Fig. Sequential processing

Pipelined: On a pipelined machine, where fetch, decode and execute operations are performed in parallel. Only
five cycles are needed to execute the same three instructions as in fig. The first instruction requires three cycles
to complete. Additional instructions then completes at a rate of one per cycles.

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 Fig. Pipeline processing

5.10 INSTRUCTION LEVEL PARALLELISM:

Pipelining can overlap the execution of instructions when they are independent of one another. The
potential overlap among instructions is called Instruction Level Parallelism (ILP) since the instructions
are executed in parallel.
Instruction level parallelism is a measure of how many of the operations in a computer program can be
performed simultaneously. Consider the following program
Example 1:
Operation 1: e = a + b;
Operation 2: f = c + d;
Operation 3: g = e * f;
Operation 3 depends on the results of operations 1 and 2, so it cannot be calculated until both of them are
completed. However, operations 1 and 2 do not depend on any other operation, so they can be calculated
simultaneously. If it is assumed that each operation can be completed in one unit of time then these three
instructions can be completed in a total of two units of time, giving an ILP of 3/2.
A goal of compiler and processor designers is to identify and take advantage of as much ILP as possible.
Ordinary programs are typically written under a sequential execution model where instructions execute one
after the other and in the order specified by the programmer. ILP allows the compiler and the processor to
overlap the execution of multiple instructions or even to change the order in which instructions are executed.

5.11 COMPARE RISC & CISC:

The term RISC stands for ‘Reduced Instruction Set Computer’.

RISC is a microprocessor that is designed to carry out few instructions at the same time. Based on small
instructions, these chips require fewer transistors, which make the transistors cheaper to design and produce.
Some other features of RISC include:
 Less decoding demand
 Uniform instruction set
 Identical general purpose register
 Simple addressing nodes
 Few data types in hardware
Also, while writing codes, RISC makes it easier by allowing the programmer to remove unnecessary codes and
prevents wasting of cycles.

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 Fig. RISC architecture Fig. CISC architecture
The term CISC stands for ‘Complex Instruction Set Computer’. It is a CPU design strategy based on
single instructions, which are capable of performing multi-step operations. CISC computers have shorted
programs. It has a large number of complex instructions, which takes long time to execute. Here, a single set of
instruction is covered in multiple steps; each instruction set has more than three hundred separate instructions.
Most instructions are completed in two to ten machine cycles. In CISC, instruction pipelining is not easily
implemented.
COMPARISION BETWEEN RISC & CISC
S. No RISC CISC
1. Emphasis is on Software Emphasis is on hardware
2. Clock rate is 50-150 Mhz Clock rate is 33- 50 Mhz
One cycle for almost all instructions and an Complex instructions take multiple cycles. An
3. average CPI (Cycles Per Instruction) < 1.5. average CPI is between 2 and 15
4. Simple instructions take one cycle Complex instructions take multiple cycles.
5. Very few instructions refer memory Most of the instruction s may refer memory
6. Instructions are executed by hardware Instructions are executed by program
7. Fixed format instructions Variable format instructions
8. Few instructions Many instructions
9. Few addressing modes Many addressing modes
10. Highly pipelined Not pipelined or less pipelined.
11. Complexity in the compiler Complexity in the micro program.
12. Multiple register sets Single register set.

5.12 FEATURES OF 80486

 80486 is a 32-bit microprocessor.
 80486 is 168 pin IC available in Pin Grid Array package.
 80486 is available in different versions with different clock frequencies, i.e., 25MHz, 33MHz, 50 MHz
and 100MHz.
 It has 32-bit data bus &32-bit address bus.
 It can access the 4GB physical memory.
 It can access 64TB virtual memory.
 It is the first CPU with on chip Floating point unit (FPU).
 For fast execution of complex instructions 80486 has introduced 5 stage pipeline.
 It has 8KB on chip cache, used to store programs and data.

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  It has built in math coprocessor
 It is fabricated using CHMOS-IV technology.
 80486 is a CISC processor.
 It contains more than 1.2 million transistors.

5.13 ARCHITECTURE OF 80486

The internal architecture of 80486 is broadly divided into three sections, namely bus interface unit,
execution and control unit and floating point unit.
Bus interface unit:
 The bus interface unit is responsible for coordinating all the bus operations.
 The address driver interfaces the internal address bus output of cache unit with the system bus.
 The data bus transceivers interface the internal 32-bit data bus with the system bus.
 The 4 X 80 write data buffer is used to hold the 80-bit data to be written to the memory.
 The bus control and request sequencer handles the signals like ADS#, W/R#, D/C#, M/IO#, HOLD and
HLDA etc.
 The burst control signals BRDY# and BLAST# are used during burst cycle.
 The cache control signals KEN#, FLUSH, AHOLD and EADS# used to control and maintain the cache.

 The bus size control signals BS16# and BS8 are used for dynamic bus sizing.
 Parity generation and control unit is used to generate the parity and to detect the errors.
 Boundary scan control unit is used to perform boundary scan tests to ensure the correct functioning of
the hardware components.

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Execution and control unit:
The execution and control unit is used to fetch the instruction, decode the instructions and generate the control
signals for execution of the instructions.
 The pre-fetcher fetches the codes from memory ahead of execution time and arranges them in 32-byte
code queue.
 The instruction decoder fetches the code from the 32-byte queue and decodes it sequentially. The
decoded instructions are given to the control unit.
 The control ROM stores the micro-program for deriving the control signals for execution of different
instructions.
 The ALU and register bank is used for execution.
 The segmentation unit, descriptor registers, paging unit, translation look aside buffer and limit and
attribute PLA work together to manage virtual memory.
Floating point unit:
The 80486 has on-chip floating point unit used to perform floating point mathematical operations. The floating
point unit has floating point registers to perform mathematical operations.
 The floating point unit with register bank communicates with the bus interface unit under the control of
memory management unit via its 64-bit internal data bus.
 The floating point unit is responsible for carrying out mathematical data processing at a higher speed
compared to ALU, with its built in floating point algorithms.

5.14 FEATURES OF PENTIUM MICROPOCESSOR:

 Super Scalar and super pipelined architecture.
 The super scalar architecture of Pentium contains three independent processing units
o Floating Point Processor.
o Two integer processing units labelled U and V.
 Pipelined floating point unit.
 Separate code 8 KB and data cache of 8KB.
 64-bit data bus and 32-bit address bus.
 It can access 4GB of physical memory and 64TB of virtual memory.
 Pipelined bus cycles.
 Address parity.
 Internal parity checking.
 Branch prediction.
 Dual processing support.

ARCHITECTURE OF PENTIUM MICROPROCESSOR:

 The Pentium processor has super scalar architecture which allows parallel execution of two instructions.
 For execution of multiple instructions concurrently, Pentium issues two instructions in parallel to the two
independent integer pipelines known as U and V pipelines. Each of these are five stage pipelines.

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 The super scalar architecture is explained by using the below figure.
 From the figure the first stage is pre-fetch stage. In this stage, the instructions are pre-fetched from the code
cache and stored in the pre-fetch buffer.

 Decoding stage ‘1’ is used to decode the simple instructions and generate the control words.
 The output of decoding stage ‘1’ is given to the decoding stage ‘2’.
 The decode stage ‘2’ is further decodes the control words and generate memory address.
 By using the memory address from the D2 stage, the data is accessed from the data cache and given to the
ALU.
 Last stage in pipelining is Write back stage. In this stage the processor updates the registers contents based
on the executed result.
Separate code cache and Data cache:
 The 80586 has separate 8KB code and Data cache memories. The 8KB code cache memory is used to store
the code or instructions.
 The 8KB data cache memory is used to store the data.

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Floating point unit (FPU):
 The Pentium has 8 stage pipelined floating point unit, hence the speed of the Pentium is higher than the
speed of 80486.
 FPU is used to perform the floating point operations.

5.15 COMPARE THE FEATURES OF 80286, 80386, 80486 & PENTIUMPROCESSORS

Parameter 80286 80386 80486 PENTIUM
CPU clock 12.5MHz, 10MHz 20,25 and 33MHz 33MHz, 50MHz 60-200 MHZ
speed and 8MHz versions clock versions
No of pins 68-pin IC available in 132-pin IC available 168-pin IC available 237 PGA
leadless flat package in Pin Grid Array in Pin Grid Array
(PGA) package. (PGA) package.
Word length 16- bit 32-bit 32-bit 64-Bit
Address bits 24-bit 32-bit 32-bit 32-bit
Physical 16MB 4GB 4GB 4GB
memory
Virtual 1GB 64TB 64TB 64 TB
memory
Processing BU – Bus Unit, BU – Bus Unit, BU – Bus Unit, Two Integer
units IU- Instruction Unit, IPU- Instruction Pre- IPU- Instruction Pre- Processing units U &
AU- Address Unit fetch Unit, fetch & Decode Unit, V pipeline, FPU-
EU-Execution Unit IDU- Decode Unit SU –Segment Unit, Floating Point Unit
SU –Segment Unit PU- Paging Unit,
PU- Paging Unit FPU, Cache,
EU-Execution Unit EU-Execution Unit
Operating Real addressing  Protected virtual  Protected virtual
modes mode address mode address mode
 Protected virtual  Real address mode  Virtual 8086
addressing mode  Virtual 8086 mode mode
Cache Not present. Address translation 8KB data and code 8KB data and 8 KB
cache cache code cache
Segment 4- CS, DS, SS, ES 6- CS, DS, SS, 6- CS, DS, SS, 6- CS, DS, SS,
registers ES,FS,GS ES,FS,GS ES,FS,GS
General AX,BX,CX,DX, EAX,EBX,ECX,EDX, EAX,EBX,ECX,EDX, EAX,EBX,ECX,EDX,
Purpose SI,DI,SP,BP ESI,EDI,ESP,EBP ESI,EDI,ESP,EBP ESI,EDI,ESP,EBP
Registers

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