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    (Esquemas) Compal La-D051p r1.0 (Wtecmanutenção - Com)

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    claudston
    1. The document is a block diagram of a Skylake U+2+2 system that includes features like dual channel DDR3L memory, integrated graphics, USB 3.0/2.0 ports, WiFi/Bluetooth, Ethernet, SATA, and audio capabilities. 2. The core components are a Skylake U dual core processor and Skylake PCH-LP chipset along with up to 8GB of DDR3L memory across two channels. 3. Peripheral interfaces include PCIe x1, M.2 for WiFi/Bluetooth, SATA, USB 3.0, HDMI, eDP for display, and audio features like an ALC

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    (Esquemas) Compal La-D051p r1.0 (Wtecmanutenção - Com)

    Uploaded by

    claudston
    128 views54 pages
    1. The document is a block diagram of a Skylake U+2+2 system that includes features like dual channel DDR3L memory, integrated graphics, USB 3.0/2.0 ports, WiFi/Bluetooth, Ethernet, SATA, and audio capabilities. 2. The core components are a Skylake U dual core processor and Skylake PCH-LP chipset along with up to 8GB of DDR3L memory across two channels. 3. Peripheral interfaces include PCIe x1, M.2 for WiFi/Bluetooth, SATA, USB 3.0, HDMI, eDP for display, and audio features like an ALC

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    [Esquemas] Compal La-d051p r1.0 [Wtecmanutenção.com]

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    1. The document is a block diagram of a Skylake U+2+2 system that includes features like dual channel DDR3L memory, integrated graphics, USB 3.0/2.0 ports, WiFi/Bluetooth, Ethernet, SATA, and audio capabilities. 2. The core components are a Skylake U dual core processor and Skylake PCH-LP chipset along with up to 8GB of DDR3L memory across two channels. 3. Peripheral interfaces include PCIe x1, M.2 for WiFi/Bluetooth, SATA, USB 3.0, HDMI, eDP for display, and audio features like an ALC

    Copyright:

    © All Rights Reserved
    Download as PDF, TXT or read online from Scribd
    Download as pdf or txt
    128 views54 pages

    (Esquemas) Compal La-D051p r1.0 (Wtecmanutenção - Com)

    Uploaded by

    claudston
    1. The document is a block diagram of a Skylake U+2+2 system that includes features like dual channel DDR3L memory, integrated graphics, USB 3.0/2.0 ports, WiFi/Bluetooth, Ethernet, SATA, and audio capabilities. 2. The core components are a Skylake U dual core processor and Skylake PCH-LP chipset along with up to 8GB of DDR3L memory across two channels. 3. Peripheral interfaces include PCIe x1, M.2 for WiFi/Bluetooth, SATA, USB 3.0, HDMI, eDP for display, and audio features like an ALC

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    © All Rights Reserved
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    You are on page 1of 54

    A B C D E

    ZZZ PCB@

    PCB 1G7 LA-D051P REV1 M/B


    DA80013U010 Vinafix.com
    1 1

    BAV00 / BAV10
    2 2

    MB Schematic Document
    LA-D051P

    Rev: 1.0
    2015.07.15
    3 3

    4 4

    Security Classification
    2014/05/19
    Compal Secret Data
    2015/12/31 Title
    Compal Electronics, Inc.
    Issued Date Deciphered Date
    THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
    Cover Sheet
    AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&DSize Document Number Rev
    DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS Custom 0.2
    MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC. LA-C071P
    Date: Tuesday, July 28, 2015 Sheet 1 of 55
    A B C D E
    A B C D E

    Skylake U_2+2 Block Diagram


    Vinafix.com
    1 1

    VRAM 256M*16 32bit


    DDR3L *2 / *4 pcs PEG 3.0 _4 Lane
    NV N16S-GM
    32bit
    VRAM 256M*16 Memory Bus (DDR3L)
    DDR3L *2 / *4 pcs Dual Channel DDR3L-DIMM X2
    BANK 0, 1, 2, 3, 4 ,5 ,6 ,7
    1.35V DDR3L SO-DIMM

    Skylake U 8GB Max


    eDP Conn. eDP + (for each Channel)
    Skylake PCH-LP(MCP) USB 3.0
    HDMI Conn. USB 3.0 Conn. 1
    DDI
    (SKL-U_2+2) USB2.0
    USB 3.0 Conn. 2

    2 Dual Core USB3.0 Rediver 3D Camera 2

    PCI-E
    x1 x1
    TDP : 15W USB 2.0 Conn. 3
    NGFF 2230 Ethernet
    WiFi / BT RTL8106E BGA 1356 balls Digital Camera
    (With Digital MIC)
    NGFF 2230
    42 x 24 mm WiFi/BT4.0

    Touch Screen

    Card Reader
    SATA HDD Conn. RTS5170
    Port 0 SATA Rediver SATA3.0

    Digital Mic.
    3 3

    HD Audio Headphone Jack /


    Audio Codec
    ALC3234 Mic. Jack combo

    Int. Speaker R / L
    SPI ROM SPI
    16M Bytes

    I2C
    LPC Bus

    EC PS/2 Touch Pad


    Int.KBD MEC1404

    4 4

    Security Classification
    2014/05/19
    Compal Secret Data
    2015/12/31 Title
    Compal Electronics, Inc.
    Issued Date Deciphered Date
    THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
    SKL-U_2+2 Block Diagrams
    AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&DSize Document Number Rev
    DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS Custom 0.2
    MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC. LA-C071P
    Date: Tuesday, July 28, 2015 Sheet 2 of 55
    A B C D E
    A

    Vinafix.com

    1
    (Blanking) 1

    Security Classification
    2014/05/19
    Compal Secret Data
    2015/12/31 Title
    Compal Electronics, Inc.
    Issued Date Deciphered Date
    THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
    Notes List
    AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&DSize Document Number Rev
    DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS Custom 0.2
    MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC. LA-C071P
    Date: Tuesday, July 28, 2015 Sheet 3 of 55
    A
    5 4 3 2 1

    Vinafix.com
    D D

    C C

    (Blanking)

    B B

    A A

    Security Classification Compal Secret Data Compal Electronics, Inc.


    Issued Date 2013/11/19 Deciphered Date 2015/12/31 Title

    THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
    Power MAP
    Size
    AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D Document Number Rev
    DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS 0.2
    MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.
    Date: Tuesday, July 28, 2015 Sheet 4 of 55
    5 4 3 2 1
    5 4 3 2 1

    Vinafix.com
    D D

    C C

    (Blanking)

    B B

    A A

    Security Classification Compal Secret Data Compal Electronics, Inc.


    Issued Date 2014/05/19 Deciphered Date 2015/12/31 Title

    THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
    Power Sequence
    Size
    AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D Document Number Rev
    DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS 0.2
    MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.
    Date: Tuesday, July 28, 2015 Sheet 5 of 55
    5 4 3 2 1
    A B C D E

    Main Func : CPU

    Vinafix.com
    UC1A @ SKL-U
    1 Rev_1.0 1
    E55 C47
    +3VS <26> HDMI_DATA2# DDI1_TXN[0] EDP_TXN[0] EDP_TX0_DN <25>
    F55 C46
    <26> HDMI_DATA2 DDI1_TXP[0] EDP_TXP[0] EDP_TX0_DP <25> +3V_PRIM
    E58 D46 <eDP_FHD>
    <26> HDMI_DATA1# DDI1_TXN[1] EDP_TXN[1] EDP_TX1_DN <25>
    F58 C45
    <26> HDMI_DATA1 DDI1_TXP[1] EDP_TXP[1] EDP_TX1_DP <25>
    RPC1 <HDMI> F53 A45
    <26> HDMI_DATA0# DDI1_TXN[2] EDP_TXN[2]
    1 8 G53 B45 RC234 2 1 10K_0402_5%
    <26> HDMI_DATA0 DDI1_TXP[2] EDP_TXP[2]
    2 7 F56 A47
    <26> HDMI_CLK# DDI1_TXN[3] EDP_TXN[3] +3VS
    3 6 PCH_HDMI_CLK G56 B47
    <26> HDMI_CLK DDI1_TXP[3] EDP_TXP[3]
    4 5 PCH_HDMI_DATA
    C50 E45 EDP_AUX_DN <25>
    2.2K_0804_8P4R_5% D50 DDI2_TXN[0] DDI EDP EDP_AUXN F45 SIO_EXT_SMI# RC222 2 @ 1 10K_0402_5%
    DDI2_TXP[0] EDP_AUXP EDP_AUX_DP <25>
    C52
    D52 DDI2_TXN[1] B52
    A50 DDI2_TXP[1] EDP_DISP_UTIL
    B50 DDI2_TXN[2] G50 HDMI_DET RC312 2 @ 1 100K_0402_5%
    D51 DDI2_TXP[2] DDI1_AUXN F50 EDP_HPD RC220 2 1 100K_0402_5%
    C51 DDI2_TXN[3] DDI1_AUXP E48 L_BKLT_EN_EC RC223 2 1 100K_0402_5%
    DDI2_TXP[3] DDI2_AUXN F48
    DDI2_AUXP G46
    DISPLAY SIDEBANDS RSVD F46
    PCH_HDMI_CLK L13 RSVD
    <26> PCH_HDMI_CLK GPP_E18/DDPB_CTRLCLK
    <HDMI DDC> PCH_HDMI_DATA L12 L9 HDMI_DET HDMI_DET <26> From HDMI
    <26> PCH_HDMI_DATA GPP_E19/DDPB_CTRLDATA GPP_E13/DDPB_HPD0 L7
    N7 GPP_E14/DDPC_HPD1 L6 SIO_EXT_SMI#
    GPP_E20/DDPC_CTRLCLK GPP_E15/DDPD_HPD2 SIO_EXT_SMI# <23>
    N8 N9
    GPP_E21/DDPC_CTRLDATA GPP_E16/DDPE_HPD3 L10 EDP_HPD
    GPP_E17/EDP_HPD EDP_HPD <25> From eDP
    N11
    +1.0VS_VCCIO N12 GPP_E22 R12
    GPP_E23 EDP_BKLTEN L_BKLT_EN_EC <23>
    2 R11 2
    EDP_BKLTCTL L_BKLT_CTRL <25>
    RC1 1 2 24.9_0402_1% EDP_COMP E52 1 OF 20 U13
    EDP_RCOMP EDP_VDDEN EDP_VDD_EN <25>
    CAD note: SKL-U_BGA1356
    Trace width=5 mils,Spacing=25mil,Max length=600mils
    ( PDG_V1.2_Update)

    UC1 ES_2.3G@ UC1 ES_1.6G@

    S IC A31 FJ8066201924925 QHMF C0 2.3G S IC A31 FJ8066201924932 QHMG C0 1.6G UC1I @ SKL-U
    Rev_1.0
    SA00008M40L SA00008M30L CSI-2

    A36 C37
    3 B36 CSI2_DN0 CSI2_CLKN0 D37 3
    UC1 QS_i5@ UC1 SQS_i5@ C38 CSI2_DP0 CSI2_CLKP0 C32
    D38 CSI2_DN1 CSI2_CLKN1 D32
    C36 CSI2_DP1 CSI2_CLKP1 C29
    D36 CSI2_DN2 CSI2_CLKN2 D29
    A38 CSI2_DP2 CSI2_CLKP2 B26
    B38 CSI2_DN3 CSI2_CLKN3 A26
    CSI2_DP3 CSI2_CLKP3
    S IC A31 FJ8066201930409 QJ8N D0 2.3G S IC A31 FJ8066201930409 QJKP D1 2.3G
    C31 E13 CSI2_COMP RC80 2 1 100_0402_1%
    SA000092O0L SA000092O1L D31 CSI2_DN4 CSI2_COMP B7
    C33 CSI2_DP4 GPP_D4/FLASHTRIG +3VS
    D33 CSI2_DN5
    UC1 QS_i7@ UC1 SQS_i7@ A31 CSI2_DP5 EMMC
    RC224 2 1 10K_0402_5%
    B31 CSI2_DN6 AP2
    A33 CSI2_DP6 GPP_F13/EMMC_DATA0 AP1
    B33 CSI2_DN7 GPP_F14/EMMC_DATA1 AP3
    CSI2_DP7 GPP_F15/EMMC_DATA2 WLAN_RADIO_DIS# <28>
    AN3
    A29 GPP_F16/EMMC_DATA3 AN1
    B29 CSI2_DN8 GPP_F17/EMMC_DATA4 AN2
    S IC A31 FJ8066201930408 QJ8L D0 2.5G S IC A31 FJ8066201930408 QJKK D1 2.5G CSI2_DP8 GPP_F18/EMMC_DATA5
    C28 AM4
    SA000092P0L SA000092P1L D28 CSI2_DN9 GPP_F19/EMMC_DATA6 AM1
    A27 CSI2_DP9 GPP_F20/EMMC_DATA7
    B27 CSI2_DN10 AM2
    UC1 MP_i5@ UC1 MP_i7@ C27 CSI2_DP10 GPP_F21/EMMC_RCLK AM3
    D27 CSI2_DN11 GPP_F22/EMMC_CLK AP4
    CSI2_DP11 GPP_F12/EMMC_CMD
    9 OF 20 AT1 EMMC_RCOMP RC89 2 1 200_0402_1%
    EMMC_RCOMP
    SKL-U_BGA1356
    4 4
    S IC FJ8066201930409 SR2EY D1 2.3G A31! S IC FJ8066201930408 SR2EZ D1 2.5G A31!
    SA000092O3L SA000092P3L

    UC1 SQS_2.1G@ UC1 MP_2.1G@


    Security Classification
    2014/05/19
    Compal Secret Data
    2015/12/31 Title
    Compal Electronics, Inc.
    Issued Date Deciphered Date
    THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
    SKL-U(1/12)DDI,MSIC,XDP,EDP
    S IC A31 FJ8066201930905 QJKT D1 2.1G S IC FJ8066201930905 SR2EX D1 2.1G BGA 1356 A31 ! Size Document Number
    AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D Rev
    DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS Custom 0.2
    SA00009420L SA00009422L MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC. LA-C071P
    Date: Tuesday, July 28, 2015 Sheet 6 of 55
    A B C D E
    5 4 3 2 1

    Main Func : CPU

    Interleaved Memory
    Vinafix.com
    D D

    SKL-U
    UC1C @
    UC1B @ SKL-U Rev_1.0
    Rev_1.0
    <18> DDR_A_D[0..15] <19> DDR_B_D[0..15] Interleave / Non-Interleaved
    DDR_A_D0 AL71 AU53 DDR_A_CLK#0 DDR_A_CLK#0 <18> DDR_B_D0 AF65 AN45 DDR_B_CLK#0 DDR_B_CLK#0 <19>
    DDR_A_D1 AL68 DDR0_DQ[0] DDR0_CKN[0] AT53 DDR_A_CLK0 DDR_B_D1 AF64 DDR1_DQ[0]/DDR0_DQ[16] DDR1_CKN[0] AN46 DDR_B_CLK#1
    DDR0_DQ[1] DDR0_CKP[0] DDR_A_CLK0 <18> DDR1_DQ[1]/DDR0_DQ[17] DDR1_CKN[1] DDR_B_CLK#1 <19>
    DDR_A_D2 AN68 AU55 DDR_A_CLK#1 DDR_A_CLK#1 <18> DDR_B_D2 AK65 AP45 DDR_B_CLK0 DDR_B_CLK0 <19>
    DDR_A_D3 AN69 DDR0_DQ[2] DDR0_CKN[1] AT55 DDR_A_CLK1 DDR_B_D3 AK64 DDR1_DQ[2]/DDR0_DQ[18] DDR1_CKP[0] AP46 DDR_B_CLK1
    DDR0_DQ[3] DDR0_CKP[1] DDR_A_CLK1 <18> DDR1_DQ[3]/DDR0_DQ[19] DDR1_CKP[1] DDR_B_CLK1 <19>
    DDR_A_D4 AL70 DDR_B_D4 AF66
    DDR_A_D5 AL69 DDR0_DQ[4] BA56 DDR_A_CKE0 DDR_B_D5 AF67 DDR1_DQ[4]/DDR0_DQ[20] AN56 DDR_B_CKE0
    DDR0_DQ[5] DDR0_CKE[0] DDR_A_CKE0 <18> DDR1_DQ[5]/DDR0_DQ[21] DDR1_CKE[0] DDR_B_CKE0 <19>
    DDR_A_D6 AN70 BB56 DDR_A_CKE1 DDR_A_CKE1 <18> DDR_B_D6 AK67 AP55 DDR_B_CKE1 DDR_B_CKE1 <19>
    DDR_A_D7 AN71 DDR0_DQ[6] DDR0_CKE[1] AW56 DDR_B_D7 AK66 DDR1_DQ[6]/DDR0_DQ[22] DDR1_CKE[1] AN55
    DDR0_DQ[7] DDR0_CKE[2] TP@ T14 DDR1_DQ[7]/DDR0_DQ[23] DDR1_CKE[2] TP@ T17
    DDR_A_D8 AR70 AY56 TP@ T15 DDR_B_D8 AF70 AP53 TP@ T18
    DDR_A_D9 AR68 DDR0_DQ[8] DDR0_CKE[3] DDR_B_D9 AF68 DDR1_DQ[8]/DDR0_DQ[24] DDR1_CKE[3]
    DDR_A_D10 AU71 DDR0_DQ[9] AU45 DDR_A_CS#0 DDR_B_D10 AH71 DDR1_DQ[9]/DDR0_DQ[25] BB42 DDR_B_CS#0
    DDR0_DQ[10] DDR0_CS#[0] DDR_A_CS#0 <18> DDR1_DQ[10]/DDR0_DQ[26] DDR1_CS#[0] DDR_B_CS#0 <19>
    DDR_A_D11 AU68 AU43 DDR_A_CS#1 DDR_A_CS#1 <18> DDR_B_D11 AH68 AY42 DDR_B_CS#1 DDR_B_CS#1 <19>
    DDR_A_D12 AR71 DDR0_DQ[11] DDR0_CS#[1] AT45 DDR_A_ODT0 DDR_B_D12 AF71 DDR1_DQ[11]/DDR0_DQ[27] DDR1_CS#[1] BA42 DDR_B_ODT0
    DDR0_DQ[12] DDR0_ODT[0] DDR_A_ODT0 <18> DDR1_DQ[12]/DDR0_DQ[28] DDR1_ODT[0] DDR_B_ODT0 <19>
    DDR_A_D13 AR69 AT43 DDR_A_ODT1 DDR_A_ODT1 <18> DDR_B_D13 AF69 AW42 DDR_B_ODT1 DDR_B_ODT1 <19>
    DDR_A_D14 AU70 DDR0_DQ[13] DDR0_ODT[1] DDR_B_D14 AH70 DDR1_DQ[13]/DDR0_DQ[29] DDR1_ODT[1]
    DDR_A_D15 AU69 DDR0_DQ[14] DDR_B_D15 AH69 DDR1_DQ[14]/DDR0_DQ[30]
    DDR0_DQ[15] DDR3L / LPDDR3 / DDR4 <19> DDR_B_D[16..31] DDR1_DQ[15]/DDR0_DQ[31] DDR3L / LPDDR3 / DDR4
    BA51 DDR_A_MA5 DDR_A_MA5 <18> DDR_B_D16 AT66 AY48 DDR_B_MA5 DDR_B_MA5 <19>
    DDR0_MA[5]/DDR0_CAA[0]/DDR0_MA[5] BB54 DDR_A_MA9 DDR_B_D17 AU66 DDR1_DQ[16]/DDR0_DQ[48] DDR1_MA[5]/DDR1_CAA[0]/DDR1_MA[5] AP50 DDR_B_MA9
    <18> DDR_A_D[16..31] Interleave / Non-Interleaved DDR0_MA[9]/DDR0_CAA[1]/DDR0_MA[9] DDR_A_MA9 <18> DDR1_DQ[17]/DDR0_DQ[49] DDR1_MA[9]/DDR1_CAA[1]/DDR1_MA[9] DDR_B_MA9 <19>
    DDR_A_D16 BB65 BA52 DDR_A_MA6 DDR_A_MA6 <18> DDR_B_D18 AP65 BA48 DDR_B_MA6 DDR_B_MA6 <19>
    DDR_A_D17 AW65 DDR0_DQ[16]/DDR0_DQ[32] DDR0_MA[6]/DDR0_CAA[2]/DDR0_MA[6] AY52 DDR_A_MA8 DDR_B_D19 AN65 DDR1_DQ[18]/DDR0_DQ[50] DDR1_MA[6]/DDR1_CAA[2]/DDR1_MA[6] BB48 DDR_B_MA8
    DDR0_DQ[17]/DDR0_DQ[33] DDR0_MA[8]/DDR0_CAA[3]/DDR0_MA[8] DDR_A_MA8 <18> DDR1_DQ[19]/DDR0_DQ[51] DDR1_MA[8]/DDR1_CAA[3]/DDR1_MA[8] DDR_B_MA8 <19>
    DDR_A_D18 AW63 AW52 DDR_A_MA7 DDR_A_MA7 <18> DDR_B_D20 AN66 AP48 DDR_B_MA7 DDR_B_MA7 <19>
    DDR_A_D19 AY63 DDR0_DQ[18]/DDR0_DQ[34] DDR0_MA[7]/DDR0_CAA[4]/DDR0_MA[7] AY55 DDR_A_BS2 DDR_B_D21 AP66 DDR1_DQ[20]/DDR0_DQ[52] DDR1_MA[7]/DDR1_CAA[4]/DDR1_MA[7] AP52 DDR_B_BS2
    DDR0_DQ[19]/DDR0_DQ[35] DDR0_BA[2]/DDR0_CAA[5]/DDR0_BG[0] DDR_A_BS2 <18> DDR1_DQ[21]/DDR0_DQ[53] DDR1_BA[2]/DDR1_CAA[5]/DDR1_BG[0] DDR_B_BS2 <19>
    DDR_A_D20 BA65 AW54 DDR_A_MA12 DDR_A_MA12 <18> DDR_B_D22 AT65 AN50 DDR_B_MA12 DDR_B_MA12 <19>
    DDR_A_D21 AY65 DDR0_DQ[20]/DDR0_DQ[36] DDR0_MA[12]/DDR0_CAA[6]/DDR0_MA[12] BA54 DDR_A_MA11 DDR_B_D23 AU65 DDR1_DQ[22]/DDR0_DQ[54] DDR1_MA[12]/DDR1_CAA[6]/DDR1_MA[12] AN48 DDR_B_MA11
    DDR0_DQ[21]/DDR0_DQ[37] DDR0_MA[11]/DDR0_CAA[7]/DDR0_MA[11] DDR_A_MA11 <18> DDR1_DQ[23]/DDR0_DQ[55] DDR1_MA[11]/DDR1_CAA[7]/DDR1_MA[11] DDR_B_MA11 <19>
    DDR_A_D22 BA63 BA55 DDR_A_MA15 DDR_A_MA15 <18> DDR_B_D24 AT61 AN53 DDR_B_MA15 DDR_B_MA15 <19>
    C DDR_A_D23 BB63 DDR0_DQ[22]/DDR0_DQ[38] DDR0_MA[15]/DDR0_CAA[8]/DDR0_ACT# AY54 DDR_A_MA14 DDR_B_D25 AU61 DDR1_DQ[24]/DDR0_DQ[56] DDR1_MA[15]/DDR1_CAA[8]/DDR1_ACT# AN52 DDR_B_MA14 C
    DDR0_DQ[23]/DDR0_DQ[39] DDR0_MA[14]/DDR0_CAA[9]/DDR0_BG[1] DDR_A_MA14 <18> DDR1_DQ[25]/DDR0_DQ[57] DDR1_MA[14]/DDR1_CAA[9]/DDR1_BG[1] DDR_B_MA14 <19>
    DDR_A_D24 BA61 AU46 DDR_A_MA13 DDR_A_MA13 <18> DDR_B_D26 AP60 BA43 DDR_B_MA13 DDR_B_MA13 <19>
    DDR_A_D25 AW61 DDR0_DQ[24]/DDR0_DQ[40] DDR0_MA[13]/DDR0_CAB[0]/DDR0_MA[13] AU48 DDR_A_CAS# DDR_B_D27 AN60 DDR1_DQ[26]/DDR0_DQ[58] DDR1_MA[13]/DDR1_CAB[0]/DDR1_MA[13] AY43 DDR_B_CAS#
    DDR0_DQ[25]/DDR0_DQ[41] DDR0_CAS#/DDR0_CAB[1]/DDR0_MA[15] DDR_A_CAS# <18> DDR1_DQ[27]/DDR0_DQ[59] DDR1_CAS#/DDR1_CAB[1]/DDR1_MA[15] DDR_B_CAS# <19>
    DDR_A_D26 BB59 AT46 DDR_A_WE# DDR_A_WE# <18> DDR_B_D28 AN61 AY44 DDR_B_WE# DDR_B_WE# <19>
    DDR_A_D27 AW59 DDR0_DQ[26]/DDR0_DQ[42] DDR0_WE#/DDR0_CAB[2]/DDR0_MA[14] AU50 DDR_A_RAS# DDR_B_D29 AP61 DDR1_DQ[28]/DDR0_DQ[60] DDR1_WE#/DDR1_CAB[2]/DDR1_MA[14] AW44 DDR_B_RAS#
    DDR0_DQ[27]/DDR0_DQ[43] DDR0_RAS#/DDR0_CAB[3]/DDR0_MA[16] DDR_A_RAS# <18> DDR1_DQ[29]/DDR0_DQ[61] DDR1_RAS#/DDR1_CAB[3]/DDR1_MA[16] DDR_B_RAS# <19>
    DDR_A_D28 BB61 AU52 DDR_A_BS0 DDR_A_BS0 <18> DDR_B_D30 AT60 BB44 DDR_B_BS0 DDR_B_BS0 <19>
    DDR_A_D29 AY61 DDR0_DQ[28]/DDR0_DQ[44] DDR0_BA[0]/DDR0_CAB[4]/DDR0_BA[0] AY51 DDR_A_MA2 DDR_B_D31 AU60 DDR1_DQ[30]/DDR0_DQ[62] DDR1_BA[0]/DDR1_CAB[4]/DDR1_BA[0] AY47 DDR_B_MA2
    DDR0_DQ[29]/DDR0_DQ[45] DDR0_MA[2]/DDR0_CAB[5]/DDR0_MA[2] DDR_A_MA2 <18> <19> DDR_B_D[32..47] DDR1_DQ[31]/DDR0_DQ[63] DDR1_MA[2]/DDR1_CAB[5]/DDR1_MA[2] DDR_B_MA2 <19>
    DDR_A_D30 BA59 AT48 DDR_A_BS1 DDR_A_BS1 <18> DDR_B_D32 AU40 BA44 DDR_B_BS1 DDR_B_BS1 <19>
    DDR_A_D31 AY59 DDR0_DQ[30]/DDR0_DQ[46] DDR0_BA[1]/DDR0_CAB[6]/DDR0_BA[1] AT50 DDR_A_MA10 DDR_B_D33 AT40 DDR1_DQ[32]/DDR1_DQ[16] DDR1_BA[1]/DDR1_CAB[6]/DDR1_BA[1] AW46 DDR_B_MA10
    <18> DDR_A_D[32..47] DDR0_DQ[31]/DDR0_DQ[47] DDR0_MA[10]/DDR0_CAB[7]/DDR0_MA[10] DDR_A_MA10 <18> DDR1_DQ[33]/DDR1_DQ[17] DDR1_MA[10]/DDR1_CAB[7]/DDR1_MA[10] DDR_B_MA10 <19>
    DDR_A_D32 AY39 BB50 DDR_A_MA1 DDR_A_MA1 <18> DDR_B_D34 AT37 AY46 DDR_B_MA1 DDR_B_MA1 <19>
    DDR_A_D33 AW39 DDR0_DQ[32]/DDR1_DQ[0] DDR0_MA[1]/DDR0_CAB[8]/DDR0_MA[1] AY50 DDR_A_MA0 DDR_B_D35 AU37 DDR1_DQ[34]/DDR1_DQ[18] DDR1_MA[1]/DDR1_CAB[8]/DDR1_MA[1] BA46 DDR_B_MA0
    DDR0_DQ[33]/DDR1_DQ[1] DDR0_MA[0]/DDR0_CAB[9]/DDR0_MA[0] DDR_A_MA0 <18> DDR1_DQ[35]/DDR1_DQ[19] DDR1_MA[0]/DDR1_CAB[9]/DDR1_MA[0] DDR_B_MA0 <19>
    DDR_A_D34 AY37 DDR_B_D36 AR40
    DDR_A_D35 AW37 DDR0_DQ[34]/DDR1_DQ[2] BA50 DDR_A_MA3 DDR_B_D37 AP40 DDR1_DQ[36]/DDR1_DQ[20] BB46 DDR_B_MA3
    DDR0_DQ[35]/DDR1_DQ[3] DDR0_MA[3] DDR_A_MA3 <18> DDR1_DQ[37]/DDR1_DQ[21] DDR1_MA[3] DDR_B_MA3 <19>
    DDR_A_D36 BB39 BB52 DDR_A_MA4 DDR_A_MA4 <18> DDR_B_D38 AP37 BA47 DDR_B_MA4 DDR_B_MA4 <19>
    DDR_A_D37 BA39 DDR0_DQ[36]/DDR1_DQ[4] DDR0_MA[4] AM70 DDR_A_DQS#0 DDR_B_D39 AR37 DDR1_DQ[38]/DDR1_DQ[22] DDR1_MA[4]
    DDR0_DQ[37]/DDR1_DQ[5] DDR0_DQSN[0] DDR_A_DQS#0 <18> DDR1_DQ[39]/DDR1_DQ[23]
    DDR_A_D38 BA37 AM69 DDR_A_DQS0 DDR_A_DQS0 <18> DDR_B_D40 AT33
    DDR0_DQ[38]/DDR1_DQ[6] DDR0_DQSP[0] DDR1_DQ[40]/DDR1_DQ[24] Interleave / Non-Interleaved
    DDR_A_D39 BB37 AT69 DDR_A_DQS#1 DDR_A_DQS#1 <18> DDR_B_D41 AU33 AH66 DDR_B_DQS#0 DDR_B_DQS#0 <19>
    DDR_A_D40 AY35 DDR0_DQ[39]/DDR1_DQ[7] DDR0_DQSN[1] AT70 DDR_A_DQS1 DDR_B_D42 AU30 DDR1_DQ[41]/DDR1_DQ[25] DDR1_DQSN[0]/DDR0_DQSN[2] AH65 DDR_B_DQS0
    DDR0_DQ[40]/DDR1_DQ[8] DDR0_DQSP[1] DDR_A_DQS1 <18> DDR1_DQ[42]/DDR1_DQ[26] DDR1_DQSP[0]/DDR0_DQSP[2] DDR_B_DQS0 <19>
    DDR_A_D41 AW35 DDR_B_D43 AT30 AG69 DDR_B_DQS#1 DDR_B_DQS#1 <19>
    DDR_A_D42 AY33 DDR0_DQ[41]/DDR1_DQ[9] DDR_B_D44 AR33 DDR1_DQ[43]/DDR1_DQ[27] DDR1_DQSN[1]/DDR0_DQSN[3] AG70 DDR_B_DQS1
    DDR0_DQ[42]/DDR1_DQ[10] Interleave / Non-Interleaved DDR1_DQ[44]/DDR1_DQ[28] DDR1_DQSP[1]/DDR0_DQSP[3] DDR_B_DQS1 <19>
    DDR_A_D43 AW33 BA64 DDR_A_DQS#2 DDR_A_DQS#2 <18> DDR_B_D45 AP33 AR66 DDR_B_DQS#2 DDR_B_DQS#2 <19>
    DDR_A_D44 BB35 DDR0_DQ[43]/DDR1_DQ[11] DDR0_DQSN[2]/DDR0_DQSN[4] AY64 DDR_A_DQS2 DDR_B_D46 AR30 DDR1_DQ[45]/DDR1_DQ[29] DDR1_DQSN[2]/DDR0_DQSN[6] AR65 DDR_B_DQS2
    DDR0_DQ[44]/DDR1_DQ[12] DDR0_DQSP[2]/DDR0_DQSP[4] DDR_A_DQS2 <18> DDR1_DQ[46]/DDR1_DQ[30] DDR1_DQSP[2]/DDR0_DQSP[6] DDR_B_DQS2 <19>
    DDR_A_D45 BA35 AY60 DDR_A_DQS#3 DDR_A_DQS#3 <18> DDR_B_D47 AP30 AR61 DDR_B_DQS#3 DDR_B_DQS#3 <19>
    DDR_A_D46 BA33 DDR0_DQ[45]/DDR1_DQ[13] DDR0_DQSN[3]/DDR0_DQSN[5] BA60 DDR_A_DQS3 DDR1_DQ[47]/DDR1_DQ[31] DDR1_DQSN[3]/DDR0_DQSN[7] AR60 DDR_B_DQS3
    DDR0_DQ[46]/DDR1_DQ[14] DDR0_DQSP[3]/DDR0_DQSP[5] DDR_A_DQS3 <18> <19> DDR_B_D[48..63] DDR1_DQSP[3]/DDR0_DQSP[7] DDR_B_DQS3 <19>
    DDR_A_D47 BB33 BA38 DDR_A_DQS#4 DDR_A_DQS#4 <18> DDR_B_D48 AU27 AT38 DDR_B_DQS#4 DDR_B_DQS#4 <19>
    <18> DDR_A_D[48..63] DDR0_DQ[47]/DDR1_DQ[15] DDR0_DQSN[4]/DDR1_DQSN[0] DDR1_DQ[48] DDR1_DQSN[4]/DDR1_DQSN[2]
    DDR_A_D48 AY31 AY38 DDR_A_DQS4 DDR_A_DQS4 <18> DDR_B_D49 AT27 AR38 DDR_B_DQS4 DDR_B_DQS4 <19>
    DDR_A_D49 AW31 DDR0_DQ[48]/DDR1_DQ[32] DDR0_DQSP[4]/DDR1_DQSP[0] AY34 DDR_A_DQS#5 DDR_B_D50 AT25 DDR1_DQ[49] DDR1_DQSP[4]/DDR1_DQSP[2] AT32 DDR_B_DQS#5
    DDR0_DQ[49]/DDR1_DQ[33] DDR0_DQSN[5]/DDR1_DQSN[1] DDR_A_DQS#5 <18> DDR1_DQ[50] DDR1_DQSN[5]/DDR1_DQSN[3] DDR_B_DQS#5 <19>
    DDR_A_D50 AY29 BA34 DDR_A_DQS5 DDR_A_DQS5 <18> DDR_B_D51 AU25 AR32 DDR_B_DQS5 DDR_B_DQS5 <19>
    DDR_A_D51 AW29 DDR0_DQ[50]/DDR1_DQ[34] DDR0_DQSP[5]/DDR1_DQSP[1] BA30 DDR_A_DQS#6 DDR_B_D52 AP27 DDR1_DQ[51] DDR1_DQSP[5]/DDR1_DQSP[3]
    DDR0_DQ[51]/DDR1_DQ[35] DDR0_DQSN[6]/DDR1_DQSN[4] DDR_A_DQS#6 <18> DDR1_DQ[52]
    DDR_A_D52 BB31 AY30 DDR_A_DQS6 DDR_A_DQS6 <18> DDR_B_D53 AN27 AR25 DDR_B_DQS#6 DDR_B_DQS#6 <19>
    DDR_A_D53 BA31 DDR0_DQ[52]/DDR1_DQ[36] DDR0_DQSP[6]/DDR1_DQSP[4] AY26 DDR_A_DQS#7 DDR_B_D54 AN25 DDR1_DQ[53] DDR1_DQSN[6] AR27 DDR_B_DQS6
    DDR0_DQ[53]/DDR1_DQ[37] DDR0_DQSN[7]/DDR1_DQSN[5] DDR_A_DQS#7 <18> DDR1_DQ[54] DDR1_DQSP[6] DDR_B_DQS6 <19>
    DDR_A_D54 BA29 BA26 DDR_A_DQS7 DDR_A_DQS7 <18> DDR_B_D55 AP25 AR22 DDR_B_DQS#7 DDR_B_DQS#7 <19>
    DDR_A_D55 BB29 DDR0_DQ[54]/DDR1_DQ[38] DDR0_DQSP[7]/DDR1_DQSP[5] DDR_B_D56 AT22 DDR1_DQ[55] DDR1_DQSN[7] AR21 DDR_B_DQS7
    DDR0_DQ[55]/DDR1_DQ[39] DDR1_DQ[56] DDR1_DQSP[7] DDR_B_DQS7 <19>
    DDR_A_D56 AY27 AW50 DDR_B_D57 AU22 AN43
    DDR_A_D57 AW27 DDR0_DQ[56]/DDR1_DQ[40] DDR0_ALERT# AT52 DDR_B_D58 AU21 DDR1_DQ[57] DDR1_ALERT# AP43 DDR_B_PAR
    DDR0_DQ[57]/DDR1_DQ[41] DDR0_PAR TP@ T22 +0.675V_VREFCA +0.675V_A_VREFDQ +0.675V_B_VREFDQ DDR1_DQ[58] DDR1_PAR TP@ T23
    B DDR_A_D58 AY25 DDR_B_D59 AT21 AT13 DDR_DRAMRST# DDR_DRAMRST# <18,19> B
    DDR_A_D59 AW25 DDR0_DQ[58]/DDR1_DQ[42] DDR CH - A AY67 DDR_B_D60 AN22 DDR1_DQ[59] DDR CH - B DRAM_RESET# AR18
    DDR_A_D60 BB27 DDR0_DQ[59]/DDR1_DQ[43] DDR_VREF_CA AY68 DDR_B_D61 AP22 DDR1_DQ[60] DDR_RCOMP[0] AT18
    DDR_A_D61 BA27 DDR0_DQ[60]/DDR1_DQ[44] DDR0_VREF_DQ BA67 DDR_B_D62 AP21 DDR1_DQ[61] DDR_RCOMP[1] AU18 SM_RCOMP0 RC38 1 2 121_0402_1%
    DDR_A_D62 BA25 DDR0_DQ[61]/DDR1_DQ[45] DDR1_VREF_DQ DDR_B_D63 AN21 DDR1_DQ[62] 3 OF 20 DDR_RCOMP[2] SM_RCOMP1 RC39 1 2 80.6_0402_1%
    DDR_A_D63 BB25 DDR0_DQ[62]/DDR1_DQ[46] 2 OF 20 AW67 Trace width/Spacing >= 20mils DDR1_DQ[63] SM_RCOMP2 RC40 1 2 100_0402_1%
    DDR0_DQ[63]/DDR1_DQ[47] DDR_VTT_CNTL SKL-U_BGA1356
    SKL-U_BGA1356
    Buffer with Open Drain Output

    For VTT power control

    +1.35V_VDDQ +3VALW +3VS

    0.1U_0201_10V6K 2 1 CC57

    1
    UC7 RC123 RC129
    1 5 100K_0402_5% 100K_0402_5%
    NC VCC @
    DDR_VTT_CNTL 2
    2

    2
    A 4
    Y 0.675V_DDR_VTT_ON <37>
    3
    GND
    74AUP1G07GW_TSSOP5

    A A

    Security Classification
    2014/05/19
    Compal Secret Data
    2015/12/31 Title
    Compal Electronics, Inc.
    Issued Date Deciphered Date
    THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
    SKL-U(2/12)DDRIII
    AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&DSize Document Number Rev
    DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS Custom 0.2
    MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC. LA-C071P
    Date: Tuesday, July 28, 2015 Sheet 7 of 55
    5 4 3 2 1
    5 4 3 2 1

    +3VS
    Main Func : CPU
    PCH_SMBCLK RC390 2 1 1K_0402_5%
    From WW48 MOW for PCH SPI0_MOSI Pin SMB_ALERT# SML0_ALERT# SML1_ALERT# PCH_SMBDAT RC391 2 1 1K_0402_5%

    <14> XDP_SPI_SI RC44 2 CMC@ 1 1K_0402_5% PCH_SPI_D0 TLS Confidentiality EC interface EXI BOOT STALL BYPASS
    1 Enable ( for iAMT ) 1 ESPI mode 1 Enable
    <14> XDP_SPI_IO2 RC21 2 CMC@ 1 1K_0402_5% PCH_SPI_D2
    Vinafix.com
    0 Disable ( Default ) 0 LPC mode ( Default ) 0 Disable ( Default ) +3V_PRIM

    D RC21/44 place to within 1100 mil of SPIO_MOSI/SPI0_IO2 pin for CMC +3VS D
    SML0_SMBCLK RC49 1 2 499_0402_1%
    SML0_SMBDATA RC50 1 2 499_0402_1%

    2
    SML1CLK 1 8
    SML1DATA 2 7

    G
    6 1 3 6
    SMBCLK PCH_SMBCLK <18,19>

    S
    QC2B DSX@ 4 5

    5
    +3V_SPI DMN66D0LDW-7_SOT363-6 1K_0804_8P4R_5% RPC7

    G
    3 4 SMBCLK 1 8
    SMBDATA PCH_SMBDAT <18,19>

    S
    1K_0402_1% 2 1 RC47 PCH_SPI_D2 QC2A SMBDATA 2 7
    DMN66D0LDW-7_SOT363-6 3 6
    1K_0402_1% 2 @ 1 RC48 PCH_SPI_D3 4 5
    UC1E @ SKL-U 1K_0804_8P4R_5% RPC18
    Rev_1.0
    SPI - FLASH
    4.7K_0402_5% 2 1 RC53 PCH_SPI_CS#0 SMBUS, SMLINK SUS_STAT# RC110 1 @ 2 8.2K_0402_5%
    PCH_SPI_CLK AV2 R7 SMBCLK
    PCH_SPI_D1 AW3 SPI0_CLK GPP_C0/SMBCLK R8 SMBDATA SMB -> XDP, DDR
    PCH_SPI_D0 AV3 SPI0_MISO GPP_C1/SMBDATA R10 SMB_ALERT#
    1K_0402_1% 2 ES@ 1 RC51 PCH_SPI_D3 PCH_SPI_D2 AW2 SPI0_MOSI
    SPI0_IO2
    GPP_C2/SMBALERT# Strap Pin
    PCH_SPI_D3 AU4 R9 SML0_SMBCLK
    PCH_SPI_CS#0 AU3 SPI0_IO3 GPP_C3/SML0CLK W2 SML0_SMBDATA
    *****ONLY***** AU2 SPI0_CS0# GPP_C4/SML0DATA W1 SML0_ALERT#
    From WW36 MOW for SKL-U ES sample AU1 SPI0_CS1#
    SPI0_CS2#
    GPP_C5/SML0ALERT# Strap Pin
    *** Not Strap Pin *** W3 SML1CLK
    GPP_C6/SML1CLK SML1CLK <8> SML1 -> EC,DGPU
    +3VS High --> 1 DIMM V3 SML1DATA SML1DATA <8>
    Low --> 2 DIMM SPI - TOUCH GPP_C7/SML1DATA AM7 SML1_ALERT#
    10K_0402_5%2 @ 1 RC231 ONE_DIMM# M2
    GPP_D1/SPI1_CLK
    GPP_B23/SML1ALERT#/PCHHOT# Strap Pin +3V_PRIM
    C 10K_0402_5%2 1 RC232 M3 C
    J4 GPP_D2/SPI1_MISO
    V1 GPP_D3/SPI1_MOSI
    V2 GPP_D21/SPI1_IO2 AY13 SML0_ALERT# 4.7K_0402_5% 2 @ 1 RC202
    GPP_D22/SPI1_IO3 GPP_A1/LAD0/ESPI_IO0 LPC_LAD0 <23>
    +1.8VS_3VS_PGPPA M1 LPC BA13
    GPP_D0/SPI1_CS# GPP_A2/LAD1/ESPI_IO1 LPC_LAD1 <23>
    BB13 SMB_ALERT# 10K_0402_5%2 @ 1 RC229
    GPP_A3/LAD2/ESPI_IO2 LPC_LAD2 <23>
    10K_0402_5%2 1 RC225 AY12
    C LINK GPP_A4/LAD3/ESPI_IO3 LPC_LAD3 <23>
    BA12 SML1_ALERT# 4.7K_0402_5% 2 @ 1 RC221
    GPP_A5/LFRAME#/ESPI_CS# LPC_LFRAME# <23>
    10K_0402_5%2 1 RC122 G3 BA11 SUS_STAT#
    G2 CL_CLK GPP_A14/SUS_STAT#/ESPI_RESET#
    G1 CL_DATA RC45 1 EMI@ 2 22_0402_5%
    Follow 543016_SKL_U_Y_PDG_0_9 CL_RST# CLK_PCI_LPC_MEC <23> To EC
    AW9
    GPP_A9/CLKOUT_LPC0/ESPI_CLK AY9 PCI_CLK_LPC1 RC54 1 EMI@ 2 22_0402_5%
    GPP_A10/CLKOUT_LPC1 CLK_PCI_LPDEBUG <23> To Debug
    <23> SIO_RCIN# SIO_RCIN# AW13 AW11 CLKRUN#
    GPP_A0/RCIN# GPP_A8/CLKRUN# CLKRUN# <23>

    <23> SERIRQ SERIRQ AY11


    GPP_A6/SERIRQ 5 OF 20
    +1.8VS_3VS_PGPPA
    SKL-U_BGA1356

    CLKRUN# 1 2
    RC107 8.2K_0402_5%

    +3V_PRIM

    Single SPI ROM_CS0# 16M SPI ROM (Confirmed by BIOS RD)

    5
    B B
    L1 Routing L2 Routing +3V_SPI

    G
    UC2 4
    3
    <8> SML1CLK GPU_THM_SMBCLK <23,30,48>

    D
    PCH_SPI_CS#0 1 8 1 2 QC3A
    /CS VCC

    2
    RC61 PCH_SPI_D1_R 2 7 CC8 0.1U_0201_10V6K DMN66D0LDW-7_SOT363-6
    PCH_SPI_D2 RC52 1 2 33_0402_5% 1 2 PCH_SPI_D2_R 3 IO1 IO3 6 1 2 DSX@

    G
    15_0402_1% 4 IO2 CLK 5 CC9 10P_0402_50V8J 1 6
    GND IO0 <8> SML1DATA GPU_THM_SMBDAT <23,30,48>

    D
    To SPI ROM @EMI@ QC3B DSX@
    RPC5 W25Q128FVSIQ_SO8 DMN66D0LDW-7_SOT363-6
    PCH_SPI_D1 RC57 1 2 33_0402_5% 8 1
    PCH_SPI_D0 RC58 1 2 33_0402_5% 7 2 PCH_SPI_D0_R
    PCH_SPI_CLK RC59 1 2 33_0402_5% 6 3 PCH_SPI_CLK_R 1 NDSX@ 2
    PCH_SPI_D3 RC60 1 2 33_0402_5% 5 4 PCH_SPI_D3_R RC397 0_0402_5%
    1 NDSX@ 2
    15_0804_8P4R_5% RC399 0_0402_5%

    Layout need meet L1 = L2 = L3


    << JC1 colay UC2 >>
    L3 Routing
    +3V_SPI
    EC_MISO_R
    ROM Socket
    <23> EC_MISO_R
    EC_MOSI_R JC1
    <23> EC_MOSI_R
    From EC EC_SPICLK_R PCH_SPI_CS#0 1 8
    (For share ROM) <23> EC_SPICLK_R CS# VCC
    EC_SPICS#_R PCH_SPI_D2_R 3 6 PCH_SPI_CLK_R
    <23> EC_SPICS#_R WP# SCLK
    PCH_SPI_D3_R 7 5 PCH_SPI_D0_R
    4 HOLD# SI/SIO0 2 PCH_SPI_D1_R
    GND SO/SIO1
    ACES_91960-0084N_MX25L3206EM2I
    CONN@
    A A

    Security Classification
    2014/05/19
    Compal Secret Data
    2015/12/31 Title
    Compal Electronics, Inc.
    Issued Date Deciphered Date
    THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
    SKL-U(3/12)SPI,ESPI,SMB,LPC
    AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&DSize Document Number Rev
    DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS Custom 0.2
    MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC. LA-C071P
    Date: Tuesday, July 28, 2015 Sheet 8 of 55
    5 4 3 2 1
    5 4 3 2 1

    Main Func : CPU UC1F @ SKL-U


    Rev_1.0
    LPSS ISH

    AN8 P2 CAM_DETECT
    +3VS GPP_B15/GSPI0_CS# GPP_D9 CAM_DETECT <33>
    SOC_GPIOB16 AP7 P3 DGPU_HOLD_RST#
    GPP_B16/GSPI0_CLK GPP_D10 DGPU_HOLD_RST# <45> +3V_PRIM
    VRAM_ID1 AP8 P4
    RC118 1 @ 2 4.7K_0402_5% NRB_BIT NRB_BIT AR7 GPP_B17/GSPI0_MISO GPP_D11 P1
    GPP_B18/GSPI0_MOSI GPP_D12 RTC_DET# <20>
    RTC_DET# 10K_0402_5% 1 2 RC233

    NRB_BIT <25> Vinafix.com


    DBC_EN
    DBC_EN
    3D_CAM_EN_R
    AM5
    AN7 GPP_B19/GSPI1_CS#
    GPP_B20/GSPI1_CLK
    GPP_D5/ISH_I2C0_SDA
    GPP_D6/ISH_I2C0_SCL
    M4
    N3 KB_DET# 10K_0402_5% 1 2 RC327
    3D Camera FW_UPDATE_R AP5
    AN5 GPP_B21/GSPI1_MISO N1 Reseve PU by NV +3VS
    D NO REBOOT GPP_B22/GSPI1_MOSI GPP_D7/ISH_I2C1_SDA N2
    D

    AB1 GPP_D8/ISH_I2C1_SCL DGPU_PWR_EN 10K_0402_5%1 DIS@ 2 RC230


    1 Reboot Disable BLUETOOTH_EN AB2 GPP_C8/UART0_RXD AD11
    <28> BLUETOOTH_EN GPP_C9/UART0_TXD GPP_F10/I2C5_SDA/ISH_I2C2_SDA
    0 Reboot Enable (Default) SOC_GPIOC10 W4 AD12
    BOARD_ID2 AB3 GPP_C10/UART0_RTS# GPP_F11/I2C5_SCL/ISH_I2C2_SCL
    Enable No Reboot Mode. (PCH will disable the TCO GPP_C11/UART0_CTS#
    Timer system reboot feature). This function is useful Win7 Debug UART_2_CRXD_DTXD AD1 U1 DGPU_PWR_EN
    when running ITP/XDP. GPP_C20/UART2_RXD GPP_D13/ISH_UART0_RXD/SML0BDATA/I2C4B_SDA DGPU_PWR_EN <50>
    UART_2_CTXD_DRXD AD2 U2
    SIO_EXT_WAKE# AD3 GPP_C21/UART2_TXD GPP_D14/ISH_UART0_TXD/SML0BCLK/I2C4B_SCL U3
    <23> SIO_EXT_WAKE# GPP_C22/UART2_RTS# GPP_D15/ISH_UART0_RTS#
    LPSS_UART2_CTS# AD4 U4
    GPP_C23/UART2_CTS# GPP_D16/ISH_UART0_CTS#/SML0BALERT#
    GSPI1_MOSI (AN5) U7 GPP_C12/UART1_RXD/ISH_UART1_RXD
    AC1
    AC2 DGPU_HOLD_RST# 10K_0402_5% 1 DIS@ 2 RC214
    <29> I2C_SDA_TP GPP_C16/I2C0_SDA GPP_C13/UART1_TXD/ISH_UART1_TXD
    BOOT BIOS STRAP (BBS) U6 AC3
    <29> I2C_SCL_TP GPP_C17/I2C0_SCL GPP_C14/UART1_RTS#/ISH_UART1_RTS# AB4 DGPU_PWR_EN 10K_0402_5% 1 @ 2 RC211
    U8 GPP_C15/UART1_CTS#/ISH_UART1_CTS#
    1 LPC mode U9 GPP_C18/I2C1_SDA AY8 PROJECT_ID1
    GPP_C19/I2C1_SCL GPP_A18/ISH_GP0 BA8 PROJECT_ID2
    0 SPI mode (Default) AH9 GPP_A19/ISH_GP1 BB7
    GPP_F4/I2C2_SDA GPP_A20/ISH_GP2 KB_DET# <29>
    AH10 BA7 BOARD_ID3
    GPP_F5/I2C2_SCL GPP_A21/ISH_GP3 AY7
    +3VS AH11 GPP_A22/ISH_GP4 AW7 VRAM_ID2
    AH12 GPP_F6/I2C3_SDA GPP_A23/ISH_GP5 AP13
    RC394 1 2 1K_0402_5% I2C_SDA_TP GPP_F7/I2C3_SCL Sx_EXIT_HOLDOFF# / GPP_A12 / BM_BUSY# / ISH_GP6 Need " PANEL_SIZE_ID " ?
    RC395 1 2 1K_0402_5% I2C_SCL_TP AF11
    RC329 2 1 10K_0402_5% DBC_EN AF12 GPP_F8/I2C4_SDA
    RC322 2 1 10K_0402_5% BLUETOOTH_EN GPP_F9/I2C4_SCL 6 OF 20

    C RC62 2 1 49.9K_0402_1% UART_2_CRXD_DTXD SKL-U_BGA1356 C


    RC63 2 1 49.9K_0402_1% UART_2_CTXD_DRXD

    RC65 2 1 49.9K_0402_1% LPSS_UART2_CTS#

    RC330 2 1 10K_0402_5% CAM_DETECT

    +3V_PRIM

    RC64 2 1 10K_0402_5% SIO_EXT_WAKE# +3VS +3VS


    RC68 2 @ 1 49.9K_0402_1% UART_2_CTXD_DRXD
    TO DGPU PROJECT_ID2 RC318 2 @ 1 10K_0402_5% BOARD_ID2 RC325 2 @ 1 10K_0402_5%
    RC315 1 2 10K_0402_5% RC324 1 2 10K_0402_5%

    SOC_GPIOC10 RC2041 GC6@ 2 0_0402_5% GPU_EVENT#


    GPU_EVENT# <48>
    PROJECT_ID1 RC314 2 @ 1 10K_0402_5% BOARD_ID3 RC323 2 @ 1 10K_0402_5%
    SOC_GPIOB16 RC1951 2 0_0402_5% GC6_FB_EN GC6_FB_EN <48,49> RC319 1 2 10K_0402_5% RC326 1 2 10K_0402_5%

    3D_CAM_EN_R 1 2 PROJECT_ID2 PROJECT_ID1 BOARD_ID3 BOARD_ID2


    DC4 3D_CAM_EN <23,33> PROJECT ID BOARD ID
    RB751S40T1G_SOD523-2
    *BAV00 0 0 *BAV00 0 0
    FW_UPDATE_R 1 2
    DC5
    FW_UPDATE <23,33> Reserved 0 1 Reserved 0 1
    B RB751S40T1G_SOD523-2 B
    Reserved 1 0 Reserved 1 0
    Reserved 1 1 Reserved 1 1

    RC316 UMA@ RC317 UMA@ +3VS

    VRAM_ID2 RC321 1 @ 2 10K_0402_5%


    RC316 1 @ 2 10K_0402_5%

    10K_0402_5% 10K_0402_5%
    *** Pin defintion was defined by Customer *** SD028100280 SD028100280 VRAM_ID1 RC320 1 @ 2 10K_0402_5%
    RC317 1 @ 2 10K_0402_5%
    RC316 2G@ RC320 2G@
    Win7 Debug solution
    +5VALW 6
    JWDB1 VRAM ID VRAM_ID2 VRAM_ID1
    5 GND (PCBA VRAM Size Config.)
    GND 10K_0402_5% 10K_0402_5%
    SD028100280 SD028100280
    4 UMA 0 0
    UART_2_CTXD_DRXD 3 4 RC321 4G@ RC317 4G@
    UART_2_CRXD_DTXD 2 3 2G 0 1
    1 2
    1 4G 1 0
    CVILU_CI1804M1VRA-NH
    A
    CONN@ Reserved 1 1 A

    10K_0402_5% 10K_0402_5%
    SD028100280 SD028100280

    Security Classification
    2014/05/19
    Compal Secret Data
    2015/12/31 Title
    Compal Electronics, Inc.
    Issued Date Deciphered Date
    THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
    SKL-U(6/12)GPIO
    AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&DSize Document Number Rev
    DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS Custom 0.2
    MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC. LA-C071P
    Date: Tuesday, July 28, 2015 Sheet 9 of 55
    5 4 3 2 1
    5 4 3 2 1

    Main Func : CPU UC1H @ SKL-U


    Rev_1.0

    PCIE / USB3 / SATA SSIC / USB3


    H8 USB3_CRX_DTX_N1 <24>
    USB3_1_RXN G8
    USB3_1_RXP USB3_CRX_DTX_P1 <24>
    <45> PCIE_CRX_GTX_N1 PCIE_CRX_GTX_N1 H13 C13 USB3.0 MB_PORT1
    PCIE1_RXN/USB3_5_RXN USB3_1_TXN USB3_CTX_DRX_N1 <24>
    <45> PCIE_CRX_GTX_P1 PCIE_CRX_GTX_P1 G13 D13
    PCIE1_RXP/USB3_5_RXP USB3_1_TXP USB3_CTX_DRX_P1 <24>
    CC17 DIS@ 1 2 0.22U_0402_16V7K PCIE_CTX_GRX_N1 B17
    <45> PCIE_CTX_C_GRX_N1 PCIE1_TXN/USB3_5_TXN
    <45> PCIE_CTX_C_GRX_P1 CC21 DIS@ 1 2 0.22U_0402_16V7K PCIE_CTX_GRX_P1 A17 J6 USB3_CRX_DTX_N2 <24>

    <45> PCIE_CRX_GTX_N2
    Vinafix.com PCIE_CRX_GTX_N2
    PCIE_CRX_GTX_P2
    G11
    F11
    PCIE1_TXP/USB3_5_TXP

    PCIE2_RXN/USB3_6_RXN
    USB3_2_RXN / SSIC_RXN
    USB3_2_RXP / SSIC_RXP
    USB3_2_TXN / SSIC_TXN
    H6
    B13
    A13
    USB3_CRX_DTX_P2
    USB3_CTX_DRX_N2
    <24>
    <24> USB3.0 MB_PORT2
    <45> PCIE_CRX_GTX_P2 PCIE2_RXP/USB3_6_RXP USB3_2_TXP / SSIC_TXP USB3_CTX_DRX_P2 <24>
    CC18 DIS@ 1 2 0.22U_0402_16V7K PCIE_CTX_GRX_N2 D16
    D <45> PCIE_CTX_C_GRX_N2 CC19 DIS@ 1 2 0.22U_0402_16V7K PCIE_CTX_GRX_P2 C16 PCIE2_TXN/USB3_6_TXN J10 D
    <45> PCIE_CTX_C_GRX_P2 PCIE2_TXP/USB3_6_TXP USB3_3_RXN USB3_CRX_DTX_N3 <33>
    H10 USB3_CRX_DTX_P3 <33>
    PCIE_CRX_GTX_N3 H16 USB3_3_RXP B15
    DGPU <45> PCIE_CRX_GTX_N3
    PCIE_CRX_GTX_P3 G16 PCIE3_RXN USB3_3_TXN A15
    USB3_CTX_DRX_N3 <33> 3D CAMERA
    (x4 Lane) <45> PCIE_CRX_GTX_P3 CC20 DIS@ 1 2 0.22U_0402_16V7K PCIE_CTX_GRX_N3 D17 PCIE3_RXP USB3_3_TXP USB3_CTX_DRX_P3 <33>
    <45> PCIE_CTX_C_GRX_N3 PCIE3_TXN
    CC22 DIS@ 1 2 0.22U_0402_16V7K PCIE_CTX_GRX_P3 C17 E10
    <45> PCIE_CTX_C_GRX_P3 PCIE3_TXP USB3_4_RXN F10
    PCIE_CRX_GTX_N4 G15 USB3_4_RXP C15
    <45> PCIE_CRX_GTX_N4 PCIE_CRX_GTX_P4 F15 PCIE4_RXN USB3_4_TXN D15
    <45> PCIE_CRX_GTX_P4 CC23 DIS@ 1 2 0.22U_0402_16V7K PCIE_CTX_GRX_N4 B19 PCIE4_RXP USB3_4_TXP
    <45> PCIE_CTX_C_GRX_N4 PCIE4_TXN
    CC24 DIS@ 1 2 0.22U_0402_16V7K PCIE_CTX_GRX_P4 A19 AB9 USB20_N1
    <45> PCIE_CTX_C_GRX_P4 PCIE4_TXP USB2N_1 USB20_N1 <24>
    AB10 USB20_P1 USB2.0 MB_PORT1
    USB2P_1 USB20_P1 <24>
    PCIE_PRX_WLANTX_N5 F16
    <28> PCIE_PRX_WLANTX_N5 PCIE_PRX_WLANTX_P5 E16 PCIE5_RXN AD6 USB20_N2
    <28> PCIE_PRX_WLANTX_P5 PCIE5_RXP USB2N_2 USB20_N2 <24>
    NGFF WLAN+BT CC25 1 2 0.1U_0402_10V7K PCIE_PTX_WLANRX_N5 C19 AD7 USB20_P2 USB2.0 MB_PORT2
    <28> PCIE_PTX_WLANRX_N5_C PCIE5_TXN USB2P_2 USB20_P2 <24>
    CC26 1 2 0.1U_0402_10V7K PCIE_PTX_WLANRX_P5 D19
    <28> PCIE_PTX_WLANRX_P5_C PCIE5_TXP AH3
    PCIE_PRX_LANTX_N6 G18 USB2N_3 AJ3
    <22> PCIE_PRX_LANTX_N6
    PCIE_PRX_LANTX_P6 F18 PCIE6_RXN USB2P_3 NC
    <22> PCIE_PRX_LANTX_P6 PCIE6_RXP
    LAN CC135 1 2 0.1U_0402_10V7K PCIE_PTX_LANRX_N6 D20 AD9 USB20_N4
    <22> PCIE_PTX_LANRX_N6_C PCIE6_TXN USB2N_4 USB20_N4 <31>
    CC136 1 2 0.1U_0402_10V7K PCIE_PTX_LANRX_P6 C20 AD10 USB20_P4 USB2.0 IO_PORT3
    <22> PCIE_PTX_LANRX_P6_C PCIE6_TXP USB2P_4 USB20_P4 <31>
    F20 AJ1 USB20_N5
    <27> SATA3_PRX_HDDTX_N0 PCIE7_RXN/SATA0_RXN USB2N_5 USB20_N5 <25>
    E20 AJ2 USB20_P5 USB2.0 Camera
    <27> SATA3_PRX_HDDTX_P0 PCIE7_RXP/SATA0_RXP USB2P_5 USB20_P5 <25>
    For selected technology HDD B21 USB2
    please use 100nF for PCIE. <27> SATA3_PTX_HDDRX_N0 A21 PCIE7_TXN/SATA0_TXN AF6 USB20_N6
    please use 10nF for SATA. <27> SATA3_PTX_HDDRX_P0 PCIE7_TXP/SATA0_TXP USB2N_6 USB20_N6 <31>
    AF7 USB20_P6 Card Reader
    USB2P_6 USB20_P6 <31>
    G21
    F21 PCIE8_RXN/SATA1A_RXN AH1 USB20_N7
    PCIE8_RXP/SATA1A_RXP USB2N_7 USB20_N7 <25>
    D21 AH2 USB20_P7 TOUCH SCREEN
    PCIE8_TXN/SATA1A_TXN USB2P_7 USB20_P7 <25>
    C21
    PCIE8_TXP/SATA1A_TXP AF8 USB20_N8
    C USB2N_8 USB20_N8 <28> C
    E22 AF9 USB20_P8 NGFF WLAN+BT
    PCIE9_RXN USB2P_8 USB20_P8 <28>
    E23
    B23 PCIE9_RXP AG1
    A23 PCIE9_TXN USB2N_9 AG2
    PCIE9_TXP USB2P_9 Intel NOW update design :
    F25 AH7 Unused USBID, VBUSSEBSE need PD_1K ohm
    +3VS E25 PCIE10_RXN USB2N_10 AH8
    D23 PCIE10_RXP USB2P_10
    C23 PCIE10_TXN AB6 USB2_COMP RC119 1 2 113_0402_1%
    PCIE10_TXP USB2_COMP AG3 USB2_ID RC10 1 2 1K_0402_5%
    USB2_ID
    2

    RC120 1 2 100_0402_1% PCIE_RCOMPN F5 AG4 USB2_VBUSSENSE RC16 1 2 1K_0402_5% +3V_PRIM


    RC201 PCIE_RCOMPP E5 PCIE_RCOMPN USB2_VBUSSENSE RPC14
    PCIE_RCOMPP A9 USB_OC#0_1 USB_OC#2_3 1 8
    10K_0402_5% GPP_E9/USB2_OC0# USB_OC#0_1 <24>
    XDP_PRDY# D56 C9 USB_OC#2_3 USB_OC#2_3 <31> USB_OC#6_7 2 7
    <14> XDP_PRDY# XDP_PREQ# D61 PROC_PRDY# GPP_E10/USB2_OC1# D9 USB_OC#4_5 USB_OC#0_1 3 6
    <14> XDP_PREQ#
    1

    SOC_GPIOA7 BB11 PROC_PREQ# GPP_E11/USB2_OC2# B9 USB_OC#6_7 USB_OC#4_5 4 5


    GPP_A7/PIRQA# GPP_E12/USB2_OC3#
    Follow 545659_SKL_PCH_LP_EDS_Rev1_0 E28 J1 DEVSLP0 DEVSLP0 <27> 10K_0804_8P4R_5%
    E27 PCIE11_RXN/SATA1B_RXN GPP_E4/DEVSLP0 J2 SIO_EXT_SCI#
    PCIE11_RXP/SATA1B_RXP GPP_E5/DEVSLP1 SIO_EXT_SCI# <23> +3VS
    D24 J3 GC6_THM_DIS# GC6_THM_DIS# <23>
    C24 PCIE11_TXN/SATA1B_TXN GPP_E6/DEVSLP2
    E30 PCIE11_TXP/SATA1B_TXP H2 10K_0402_5% 1 @ 2 RC206
    F30 PCIE12_RXN/SATA2_RXN GPP_E0/SATAXPCIE0/SATAGP0 H3 10K_0402_5% 1 2 RC200
    A25 PCIE12_RXP/SATA2_RXP GPP_E1/SATAXPCIE1/SATAGP1 G4 10K_0402_5% 1 2 RC199
    B25 PCIE12_TXN/SATA2_TXN GPP_E2/SATAXPCIE2/SATAGP2
    PCIE12_TXP/SATA2_TXP H1 SATA_LED#
    GPP_E8/SATALED# SATA_LED# <23,31>
    8 OF 20

    SKL-U_BGA1356

    B B

    Follow 545659_SKL_PCH_LP_EDS_Rev1_0

    A A

    Security Classification
    2014/05/19
    Compal Secret Data
    2015/12/31 Title
    Compal Electronics, Inc.
    Issued Date Deciphered Date
    THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
    SKL-U(7/12)PCIE,USB,SATA
    AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&DSize Document Number Rev
    DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS Custom 0.2
    MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC. LA-C071P
    Date: Tuesday, July 28, 2015 Sheet 10 of 55
    5 4 3 2 1
    5 4 3 2 1

    UC1J @ SKL-U
    Main Func : CPU Rev_1.0
    Closed to CPU
    CLOCK SIGNALS XTAL@
    XTAL24_IN 15P_0402_50V8J CC13
    CLK_PEG_VGA# D42 1
    <45> CLK_PEG_VGA# CLKOUT_PCIE_N0
    DGPU CLK_PEG_VGA C42
    <45> CLK_PEG_VGA CLKOUT_PCIE_P0
    <45> PEG_CLKREQ# PEG_CLKREQ# AR10
    GPP_B5/SRCCLKREQ0# 1
    CLK_PCIE_WLAN_N1 B42 2 YC1 XTAL@
    <28> CLK_PCIE_WLAN_N1 CLKOUT_PCIE_N1 GND

    2
    NGFF WALN+BT CLK_PCIE_WLAN_P1 A42 F43 CLK_CPU_ITP# 24MHZ_12PF_7V24000020
    <28>
    <28> CLK_PCIE_WLAN_P1
    CLK_PCIE_WLAN_REQ# Vinafix.com
    CLK_PCIE_WLAN_REQ# AT7 CLKOUT_PCIE_P1
    GPP_B6/SRCCLKREQ1#
    CLKOUT_ITPXDP_N
    CLKOUT_ITPXDP_P
    E43 CLK_CPU_ITP
    TP@T89
    TP@T90
    SUSCLK <28>
    RC92
    1M_0402_5%
    CLK_PCIE_LAN_N2 D41 BA17 SUSCLK RC105 1 @ 2 1K_0402_5% XTAL@ 4
    <22> CLK_PCIE_LAN_N2 CLKOUT_PCIE_N2 GPD8/SUSCLK GND
    D LAN CLK_PCIE_LAN_P2 C41 D
    <22> CLK_PCIE_LAN_P2

    1
    CLK_PCIE_LAN_REQ# AT8 CLKOUT_PCIE_P2 E37 XTAL24_IN +1.0V_CLK5
    <22> CLK_PCIE_LAN_REQ# GPP_B7/SRCCLKREQ2# XTAL24_IN 3
    E35 XTAL24_OUT
    D40 XTAL24_OUT RC96 1 2 2.7K_0402_1%
    +3VS +3VS C40 CLKOUT_PCIE_N3 E42 XCLK_BIASREF XTAL24_OUT 3
    RC127 1 @ 2 10K_0402_5% AT10 CLKOUT_PCIE_P3 XCLK_BIASREF RC124 1 @ 2 60.4_0402_1% 18P_0402_50V8J CC12
    GPP_B8/SRCCLKREQ3# AM18 PCH_RTCX1 XTAL@
    RPC10 RTCX1
    B40 AM20 PCH_RTCX2
    8 1 CLK_PCIE_WLAN_REQ# A40 CLKOUT_PCIE_N4 RTCX2 Follow 546765_2014WW48_Skylake_MOW_Rev_1_0
    7 2 CLK_PCIE_LAN_REQ# RC126 1 @ 2 10K_0402_5% AU8 CLKOUT_PCIE_P4 AN18 SRTCRST# Stuff 2.7k ohm(RC96) PH for Skylake U
    6 3 GPP_B9/SRCCLKREQ4# SRTCRST# AM16 PCH_RTCRST# Stuff 60.4 ohm(RC124) PD for Cannonlake U Closed to CPU
    5 4 PEG_CLKREQ# E40 RTCRST# XTAL@
    E38 CLKOUT_PCIE_N5 PCH_RTCX2 5.6P_0402_50V8J 1 2 CC16
    10K_0804_8P4R_5% RC125 1 @ 2 10K_0402_5% AU7 CLKOUT_PCIE_P5
    GPP_B10/SRCCLKREQ5# +3VL_RTC

    2
    From 545659_SKL_PCH_U_Y_EDS_R0_7

    2
    10 OF 20 RC98
    SRTCRST# 20K_0402_5% 2 1 RC91 10M_0402_5% YC2 XTAL@
    SKL-U_BGA1356 XTAL@ 32.768KHZ_12.5PF_9H03280012
    1U_0402_6.3V6K 2 1 CC10

    1
    CLR ME SHORT PADS 2 1 CLRP1
    PCH_RTCX1 1 2
    5.6P_0402_50V8J CC15
    +3VS PCH_RTCRST# 20K_0402_5% 2 1 RC93 XTAL@
    PCH PLTRST Buffer CC14

    1
    1 2 1U_0402_6.3V6K 2 1 CC11
    D
    5

    UC3 0.1U_0201_10V6K <23> RTCRST_ON 2 CLR CMOS SHORT PADS 2 1 CLRP2


    C PCH_PLTRST# 1 G QC1 C
    P

    1
    4 S 2N7002K_SOT23-3
    Y PLT_RST# <22,23,25,28,45>
    2 RC121

    3
    A
    G

    10K_0402_5%
    TC7SH08FUF_SSOP5
    3

    For S3 timing issue

    2
    +3VALW
    RC99 1 2 100K_0402_5% Buffer with Open Drain Output For VTT power control
    PCH_PLTRST#_EC <22,23,25,28,45>
    0.1U_0201_10V6K 2 1 CC92
    +3VALW +1.0V_VCCST
    UC13

    1
    1 5 0.1U_0201_10V6K 2 1 CC83
    NC VCC RC113
    SIO_SLP_S3# 1 RC130 2 2 UC12 1K_0402_5%
    10K_0402_5% A 4 1 5
    Y NC VCC

    2
    3

    2
    +3VALW_DSW +3VS CC93 GND ALL_SYS_PWRGD 2
    2.2U_0402_6.3V6M 74AUP1G07GW_TSSOP5 A 4 1 2 VCCST_PWRGD

    1
    RC104 1 @ 2 1K_0402_5% PCH_PCIE_WAKE# 3 Y RC116 60.4_0402_1%
    GND

    2
    +3VS
    From 543016_SKL_PDG_UY_v1.0 DC6 1 2 @ 74AUP1G07GW_TSSOP5
    RPC11 RC388
    8 1 RESET_OUT# Unused for PWR sequence. 1K_0402_5% RB751S40T1G_SOD523-2
    7 2 LAN_WAKE#

    1
    6 3 PCH_RSMRST#_Q 1VS_VCCIO_PWRGD 1 @ 2 ALL_SYS_PWRGD
    ALL_SYS_PWRGD <23> +3VALW_DSW
    5 4 SYS_RESET# RC389 0_0402_5%
    <37> 1.35V_VTT_PWRGD 1 2 1 2
    +3V_PRIM IMVP_VR_ON <40,41>
    10K_0804_8P4R_5% RC392 0_0402_5% RC345 0_0402_5% SIO_PWRBTN# 100K_0402_5% 1 @ 2 RC111
    AC_PRESENT 10K_0402_5% 2 1 RC106
    B PCH_BATLOW# 8.2K_0402_5% 2 1 RC103 B

    RC108 1 @ 2 10K_0402_5% ME_SUS_PWR_ACK


    UC1K @ SKL-U
    CLRP3 2 1 SHORT PADS SYS_RESET# Rev_1.0
    SYSTEM POWER MANAGEMENT
    RC101 2 @ 1 100K_0402_5% PCH_DPWROK AT11 SIO_SLP_S0#
    GPP_B12/SLP_S0# SIO_SLP_S0# <16>
    AP15 SIO_SLP_S3#
    GPD4/SLP_S3# SIO_SLP_S3# <16,23,32,34,41>
    PCH_PLTRST# AN10 BA16 SIO_SLP_S4#
    GPP_B13/PLTRST# GPD5/SLP_S4# SIO_SLP_S4# <16,23,37>
    SYS_RESET# B5 AY16 SIO_SLP_S5#
    SYS_RESET# GPD10/SLP_S5# SIO_SLP_S5# <35>
    Only For Power Sequence Debug PCH_RSMRST#_Q AY17
    RSMRST# AN15 SIO_SLP_SUS#_R 0_0402_5%1 2 RC128
    SLP_SUS# SIO_SLP_SUS# <17,23,38,39>
    RC102 1 @ 2 1K_0402_5% H_CPUPWRGD A68 AW15 SIO_SLP_LAN# TP@ T87
    VCCST_PWRGD B65 PROCPWRGD SLP_LAN# BB17 SIO_SLP_WLAN#
    VCCST_PWRGD GPD9/SLP_WLAN# TP@ T88
    AN16 SIO_SLP_A# TP@ T93
    B6 GPD6/SLP_A#
    <23> SYS_PWROK SYS_PWROK
    <23> RESET_OUT# RESET_OUT# BA20 BA15 SIO_PWRBTN#_R 0_0402_5%1 2 RC109 SIO_PWRBTN# <23>
    RC112 2 DSX@ 1 0_0402_5% PCH_DPWROK BB20 PCH_PWROK GPD3/PWRBTN# AY15 AC_PRESENT 2 1
    <36,38,39> POK DSW_PWROK GPD1/ACPRESENT ACAV_IN <23,35>
    <11,14> PCH_RSMRST#_Q RC396 1 NDSX@ 2 0_0402_5% AU13 PCH_BATLOW# DC2
    ME_SUS_PWR_ACK AR13 GPD0/BATLOW# RB751S40T1G_SOD523-2
    <23> ME_SUS_PWR_ACK GPP_A13/SUSWARN#/SUSPWRDNACK +3VL_RTC
    <23> SUSACK# RC398 2 DSX@ 1 0_0402_5% SUSACK#_R AP11
    GPP_A15/SUSACK# AU11 PME#
    GPP_A11/PME# TP@ T91
    <22,23,28> PCIE_WAKE# RC66 2 1 0_0402_5% PCH_PCIE_WAKE# BB15 AP16 INTRUDER# 1M_0402_5% 2 1 RC94
    RC56 2 @ 1 0_0402_5% LAN_WAKE# AM15 WAKE# INTRUDER#
    <23> EC_WAKE# GPD2/LAN_WAKE# +3VALW
    AW17 AM10 MPHYP_PWR_EN MPHYP_PWR_EN <17>
    AT15 GPD11/LANPHYPC GPP_B11/EXT_PWR_GATE# AM11 VRALERT# 2 1
    GPD7/RSVD 11 OF 20 GPP_B2/VRALERT# 10K_0402_5% RC115
    +3VALW
    A
    REMRST Circuit SKL-U_BGA1356
    A
    5

    UC11
    1
    P

    <23> PCH_RSMRST# B 4 PCH_RSMRST#_Q


    Y PCH_RSMRST#_Q <11,14>
    POK 2
    A
    G

    TC7SH08FUF_SSOP5 Security Classification Compal Secret Data Compal Electronics, Inc.


    3

    Issued Date 2014/05/19 Deciphered Date 2015/12/31 Title


    1M_0402_5% 1 2 RC95
    THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
    SKL-U(5/12)CLK,GPIO
    2 1 RC55 2 @ 1 0_0402_5% AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&DSize Document Number Rev
    1U_0402_6.3V6K CC142 DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS Custom 0.2
    MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC. LA-C071P
    Date: Tuesday, July 28, 2015 Sheet 11 of 55
    5 4 3 2 1
    5 4 3 2 1

    Main Func : CPU


    +1.0V_VCCST

    RC2 1 2 1K_0402_5% H_THERMTRIP#

    +1.0VS_VCCSTG Vinafix.com +1.0V_VCCST UC1D @ SKL-U


    D Rev_1.0 D
    RC3 1 2 1K_0402_5% H_PROCHOT# RC14 2 @ 1 49.9_0402_1% H_CATERR# D63
    PECI_EC A54 CATERR#
    <23> PECI_EC PECI
    <23,34,35,40> H_PROCHOT# RC4 1 2 499_0402_1% H_PROCHOT#_R C65 JTAG
    +3VS H_THERMTRIP# C63 PROCHOT#
    A65 THERMTRIP#
    RC215 1 2 10K_0402_5% TOUCH_SCREEN_PD# SKTOCC# B61 CPU_XDP_TCK0
    CPU MISC PROC_TCK CPU_XDP_TCK0 <14>
    T16 TP@ XDP_OBS0_R C55 D60 SOC_XDP_TDI
    BPM#[0] PROC_TDI SOC_XDP_TDI <14>
    RC216 1 2 10K_0402_5% TOUCHPAD_INTR#_D T19 TP@ XDP_OBS1_R D55 A61 SOC_XDP_TDO
    BPM#[1] PROC_TDO SOC_XDP_TDO <14>
    T10 TP@ XDP_OBS2_R B54 C60 SOC_XDP_TMS
    BPM#[2] PROC_TMS SOC_XDP_TMS <14>
    T11 TP@ XDP_OBS3_R C56 B59 SOC_XDP_TRST#
    BPM#[3] PROC_TRST# SOC_XDP_TRST# <14>
    A6 B56 PCH_JTAG_TCK1 <14>
    RC402 1 @ 2 0_0402_5% A7 GPP_E3/CPU_GP0 PCH_JTAG_TCK D59 SOC_XDP_TDI
    <25> TOUCH_SCREEN_PD# GPP_E7/CPU_GP1 PCH_JTAG_TDI
    1 2 TOUCHPAD_INTR#_D BA5 A56 SOC_XDP_TDO
    <23,29> TOUCHPAD_INTR# GPP_B3/CPU_GP2 PCH_JTAG_TDO
    DC3 RB751S40T1G_SOD523-2 AY5 C59 SOC_XDP_TMS
    GPP_B4/CPU_GP3 PCH_JTAG_TMS C61 SOC_XDP_TRST#
    RC5 2 1 49.9_0402_1% CPU_POPIRCOMP AT16 PCH_TRST# A59 CPU_XDP_TCK0
    RC6 2 1 49.9_0402_1% PCH_OPIRCOMP AU16 PROC_POPIRCOMP JTAGX
    RC7 2 1 49.9_0402_1% EDRAM_OPIO_RCOMP H66 PCH_OPIRCOMP
    RC8 2 1 49.9_0402_1% EOPIO_RCOMP H65 OPCE_RCOMP
    OPC_RCOMP
    4 OF 20
    SKL-U_BGA1356

    C C

    @EMI@
    CA26 1 2 22P_0402_50V8J

    #545659 SKL_PCH_EDS_R0.7 P.84 UC1G @ SKL-U


    Rev_1.0
    HDA for AUDIO
    AUDIO
    RPC9
    <21> HDA_CODEC_BITCLK 1 8 HDA_BIT_CLK HDA_SYNC BA22
    2 7 HDA_SYNC HDA_BIT_CLK AY22 HDA_SYNC/I2S0_SFRM
    <21> HDA_CODEC_SYNC HDA_BLK/I2S0_SCLK
    <21> HDA_CODEC_SDOUT 3 6 HDA_SDOUT HDA_SDOUT BB22 SDIO / SDXC
    4 5 HDA_RST# HDA_SDIN0 BA21 HDA_SDO/I2S0_TXD
    <21> HDA_CODEC_RST# HDA_SDI0/I2S0_RXD
    AY21 AB11
    33_0804_8P4R_5% HDA_RST# AW22 HDA_SDI1/I2S1_RXD GPP_G0/SD_CMD AB13
    J5 HDA_RST#/I2S1_SCLK GPP_G1/SD_DATA0 AB12
    HDA_SDIN0 AY20 GPP_D23/I2S_MCLK GPP_G2/SD_DATA1 W12
    <21> HDA_SDIN0 I2S1_SFRM GPP_G3/SD_DATA2
    AW20 W11
    I2S1_TXD GPP_G4/SD_DATA3 W10
    B AK7 GPP_G5/SD_CD# W8 B
    GPP_F1/I2S2_SFRM GPP_G6/SD_CLK KB_LED_BL_DET <29>
    AK6 W7
    AK9 GPP_F0/I2S2_SCLK GPP_G7/SD_WP
    AK10 GPP_F2/I2S2_TXD BA9
    GPP_F3/I2S2_RXD GPP_A17/SD_PWR_EN#/ISH_GP7 BB9
    GPP_A16/SD_1P8_SEL
    +3VS H5 AB7 SD_RCOMP RC76 2 1 200_0402_1%
    D7 GPP_D19/DMIC_CLK0 SD_RCOMP
    Flash Descriptor Security override RC217 1 2 10K_0402_5% GPP_D20/DMIC_DATA0
    +3VS D8 AF13
    C8 GPP_D17/DMIC_CLK1 GPP_F23
    <43,45,49,50> DGPU_PWROK GPP_D18/DMIC_DATA1
    RC218 1 @ 2 10K_0402_5%
    <21> SPKR AW5
    GPP_B14/SPKR
    7 OF 20
    RC17 1 2 1K_0402_5% HDA_SDOUT +3VS
    <23> ME_FWP_EC
    SKL-U_BGA1356
    RC117 1 @ 2 2.2K_0402_5%
    HDA_SDOUT
    TOP Swap Override
    Flash Descriptor Security override
    1 Disable SPKR
    0 Enable (Default) TOP Swap Override
    1 Enable
    A 0 Disable ( Default ) A

    Security Classification
    2014/05/19
    Compal Secret Data
    2015/12/31 Title
    Compal Electronics, Inc.
    Issued Date Deciphered Date
    THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
    SKL-U(4/12)HDA,EMMC,SDIO,CSI2
    AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&DSize Document Number Rev
    DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS Custom 0.2
    MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC. LA-C071P
    Date: Tuesday, July 28, 2015 Sheet 12 of 55
    5 4 3 2 1
    5 4 3 2 1

    Main Func : CPU

    CFG Configuration Signals


    1 = Normal Operation ; No Stall ( Default )
    Stall reset sequence after PCU
    CFG0 PLL lock until de-asserted
    0 = Stall

    1 = Disable ( Default )
    Vinafix.com
    eDP enable
    D
    CFG4 D
    0 = Enable UC1S @ SKL-U
    ** CFG2 , 5 , 6 , 7 for SKL-H CPU function ** Rev_1.0
    RESERVED SIGNALS-1

    2 1 CFG4 <14> CFG0 CFG0 E68 BB68 T156 TP@


    1K_0402_1% RC193 CFG1 B67 CFG[0] RSVD_TP_BB68 BB69
    <14> CFG1 CFG[1] RSVD_TP_BB69 T157 TP@
    <14> CFG2 CFG2 D65
    CFG3 D67 CFG[2] AK13
    <14> CFG3 CFG[3] RSVD_TP_AK13 T158 TP@
    <14> CFG4 CFG4 E70 AK12 T159 TP@
    CFG5 C68 CFG[4] RSVD_TP_AK12
    <14> CFG5 CFG[5]
    <14> CFG6 CFG6 D68 BB2
    CFG7 C67 CFG[6] RSVD_BB2 BA3
    <14> CFG7 CFG[7] RSVD_BA3
    <14> CFG8 CFG8 F71
    CFG9 G69 CFG[8]
    CFG Signals <14> CFG9 CFG[9]
    <14> CFG10 CFG10 F70 AU5 T162 TP@
    (For Strap & XDP) CFG11 G68 CFG[10] TP5 AT5
    <14> CFG11 CFG[11] TP6 T163 TP@
    <14> CFG12 CFG12 H70
    CFG13 G71 CFG[12]
    <14> CFG13 CFG[13]
    <14> CFG14 CFG14 H69 D5
    CFG15 G70 CFG[14] RSVD_D5 D4
    <14> CFG15 CFG[15] RSVD_D4 B2
    CFG16 E63 RSVD_B2 C2
    <14> CFG16 CFG[16] RSVD_C2
    <14> CFG17 CFG17 F63
    CFG[17] B3
    CFG18 E66 RSVD_B3 A3
    <14> CFG18 CFG[18] RSVD_A3
    <14> CFG19 CFG19 F66
    CFG[19] AW1
    49.9_0402_1% 2 1 RC185 CFG_RCOMP E60 RSVD_AW1
    C
    CFG_RCOMP E1 C
    XDP_ITP_PMODE E8 RSVD_E1 E2
    <14> XDP_ITP_PMODE ITP_PMODE RSVD_E2
    AY2 BA4
    AY1 RSVD_AY2 RSVD_BA4 BB4
    RSVD_AY1 RSVD_BB4
    D1 A4
    D3 RSVD_D1 RSVD_A4 C4
    RSVD_D3 RSVD_C4
    K46 BB5 T199 TP@
    K45 RSVD_K46 TP4
    RSVD_K45 A69
    AL25 RSVD_A69 B69
    AL27 RSVD_AL25 RSVD_B69
    RSVD_AL27 AY3 RC1821 2 0_0402_5%
    C71 RSVD_AY3
    B70 RSVD_C71 D71
    RSVD_B70 RSVD_D71 C70
    F60 RSVD_C70
    RSVD_F60 C54
    A52 RSVD_C54 D54
    RSVD_A52 RSVD_D54
    BA70 AY4
    T213 TP@
    BA68 RSVD_TP_BA70 TP1 BB3
    T214 TP@
    T216 TP@
    For 2+3e Solution
    T215 TP@ RSVD_TP_BA68 TP2
    J71 AY71 RC183 1 2 0_0402_5%
    J68 RSVD_J71 VSS_AY71 AR56 PM_ZVM# T225 TP@
    PM_ZVM#
    RSVD_J68 ZVM#
    Zero Voltage Mode: Control Signal to OPC
    F65 AW71
    B G65 VSS_F65 RSVD_TP AW70
    T221 TP@
    T223 TP@ +1.0V_VCCST VR, when low OPC VR output is 0V. B
    VSS_G65 RSVD_TP
    F61 AP56 PM_MSM#
    E61 RSVD_F61 MSM# C64 SKL_CNL#
    T230 TP@
    RC184 1 @ 2 100K_0402_5% PM_MSM#
    RSVD_E61 PROC_SELECT#
    Minimum Speed Mode: Control signal to
    19 OF 20
    Follow 546765_2014WW48_Skylake_MOW_Rev_1_0 VccEOPIO VR (connected only in 2 VR
    SKL-U_BGA1356 solution for OPC).
    Stuff 100k(RC184) for Cannonlake.
    Un-stuff 100k(RC184) for Skylake

    UC1T @ SKL-U
    Rev_1.0
    SPARE
    PROC_SELECT#
    AW69
    RSVD_AW69 RSVD_F6
    F6 Processor Select: This pin is for
    AW68 E3
    +1.8V_PRIM AU56 RSVD_AW68 RSVD_E3 C11 compatibility with future platforms. It should
    RSVD_AU56 RSVD_C11
    AW48
    RSVD_AW48 RSVD_B11
    B11 NC with Skylake
    C7 A11
    RC3611 @ 2 0_0402_5% U12 RSVD_C7 RSVD_A11 D12
    U11 RSVD_U12 RSVD_D12 C12
    H11 RSVD_U11 RSVD_C12 F52
    Connect U11, U12 to1.8V RSVD_H11 RSVD_F52
    for Cannonlake-U PCH compatibility 20 OF 20

    SKL-U_BGA1356
    A A

    Security Classification
    2014/05/19
    Compal Secret Data
    2015/12/31 Title
    Compal Electronics, Inc.
    Issued Date Deciphered Date
    THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
    SKL-U(12/12)RSVD
    AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&DSize Document Number Rev
    DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS Custom 0.2
    MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC. LA-C071P
    Date: Tuesday, July 28, 2015 Sheet 13 of 55
    5 4 3 2 1
    5 4 3 2 1

    Main Func : CPU

    PRIMARY CMC CONN


    Vinafix.com
    D
    +1.0V_XDP +1.0V_PRIM D

    UC1P @ SKL-U UC1Q @ SKL-U


    0_0402_5% 2 1 RC12 Rev_1.0 Rev_1.0 UC1R @ SKL-U
    GND 1 OF 3 GND 2 OF 3 Rev_1.0
    GND 3 OF 3
    A5 AL65 AT63 BA49 F8 L18
    A67 VSS VSS AL66 AT68 VSS VSS BA53 G10 VSS VSS L2
    <13> CFG0 TP@ T4932 VSS VSS VSS VSS VSS VSS
    TP@ T4933 A70 AM13 AT71 BA57 G22 L20
    <13> CFG1 VSS VSS VSS VSS VSS VSS
    TP@ T4935 AA2 AM21 AU10 BA6 G43 L4
    <13> CFG2 VSS VSS VSS VSS VSS VSS
    TP@ T4934 AA4 AM25 AU15 BA62 G45 L8
    <13,14> CFG3 VSS VSS VSS VSS VSS VSS
    TP@ T4943 AA65 AM27 AU20 BA66 G48 N10
    <13> CFG4 VSS VSS VSS VSS VSS VSS
    TP@ T4944 AA68 AM43 AU32 BA71 G5 N13
    <13> CFG5 VSS VSS VSS VSS VSS VSS
    TP@ T4945 AB15 AM45 AU38 BB18 G52 N19
    <13> CFG6 VSS VSS VSS VSS VSS VSS
    TP@ T4946 AB16 AM46 AV1 BB26 G55 N21
    <13> CFG7 VSS VSS VSS VSS VSS VSS
    TP@ T4938 AB18 AM55 AV68 BB30 G58 N6
    <13> CFG8 VSS VSS VSS VSS VSS VSS
    TP@ T4939 AB21 AM60 AV69 BB34 G6 N65
    <13> CFG9 VSS VSS VSS VSS VSS VSS
    TP@ T4940 AB8 AM61 AV70 BB38 G60 N68
    <13> CFG10 VSS VSS VSS VSS VSS VSS
    TP@ T4941 AD13 AM68 AV71 BB43 G63 P17
    <13> CFG11 VSS VSS VSS VSS VSS VSS
    TP@ T4947 AD16 AM71 AW10 BB55 G66 P19
    <13> CFG12 VSS VSS VSS VSS VSS VSS
    TP@ T4948 AD19 AM8 AW12 BB6 H15 P20
    <13> CFG13 VSS VSS VSS VSS VSS VSS
    TP@ T4949 AD20 AN20 AW14 BB60 H18 P21
    <13> CFG14 VSS VSS VSS VSS VSS VSS
    TP@ T4942 AD21 AN23 AW16 BB64 H71 R13
    <13> CFG15 VSS VSS VSS VSS VSS VSS
    TP@ T4937 AD62 AN28 AW18 BB67 J11 R6
    <13> CFG16 VSS VSS VSS VSS VSS VSS
    TP@ T4936 AD8 AN30 AW21 BB70 J13 T15
    <13> CFG17 VSS VSS VSS VSS VSS VSS
    TP@ T4951 AE64 AN32 AW23 C1 J25 T17
    <13> CFG18 VSS VSS VSS VSS VSS VSS
    TP@ T4950 AE65 AN33 AW26 C25 J28 T18
    <13> CFG19 VSS VSS VSS VSS VSS VSS
    AE66 AN35 AW28 C5 J32 T2
    AE67 VSS VSS AN37 AW30 VSS VSS D10 J35 VSS VSS T21
    C AE68 VSS VSS AN38 AW32 VSS VSS D11 J38 VSS VSS T4 C
    +3VALW AE69 VSS VSS AN40 AW34 VSS VSS D14 J42 VSS VSS U10
    AF1 VSS VSS AN42 AW36 VSS VSS D18 J8 VSS VSS U63
    AF10 VSS VSS AN58 AW38 VSS VSS D22 K16 VSS VSS U64
    RC9 1 2 1K_0402_5% XDP_SPI_SI AF15 VSS VSS AN63 AW41 VSS VSS D25 K18 VSS VSS U66
    XDP_SPI_SI <8> VSS VSS VSS VSS VSS VSS
    AF17 AP10 AW43 D26 K22 U67
    AF2 VSS VSS AP18 AW45 VSS VSS D30 K61 VSS VSS U69
    +1.0VS_VCCSTG AF4 VSS VSS AP20 AW47 VSS VSS D34 K63 VSS VSS U70
    AF63 VSS VSS AP23 AW49 VSS VSS D39 K64 VSS VSS V16
    AG16 VSS VSS AP28 AW51 VSS VSS D44 K65 VSS VSS V17
    Place to CPU side VSS VSS VSS VSS VSS VSS
    AG17 AP32 AW53 D45 K66 V18
    AG18 VSS VSS AP35 AW55 VSS VSS D47 K67 VSS VSS W13
    RC11 2 CMC@ 1 51_0402_5% SOC_XDP_TMS AG19 VSS VSS AP38 AW57 VSS VSS D48 K68 VSS VSS W6
    SOC_XDP_TMS <12> VSS VSS VSS VSS VSS VSS
    AG20 AP42 AW6 D53 K70 W9
    RC13 2 CMC@ 1 51_0402_5% SOC_XDP_TDI AG21 VSS VSS AP58 AW60 VSS VSS D58 K71 VSS VSS Y17
    SOC_XDP_TDI <12> VSS VSS VSS VSS VSS VSS
    AG71 AP63 AW62 D6 L11 Y19
    RC15 2 CMC@ 1 51_0402_5% SOC_XDP_TDO AH13 VSS VSS AP68 AW64 VSS VSS D62 L16 VSS VSS Y20
    SOC_XDP_TDO <12> VSS VSS VSS VSS VSS VSS
    AH6 AP70 AW66 D66 L17 Y21
    AH63 VSS VSS AR11 AW8 VSS VSS D69 VSS VSS
    AH64 VSS VSS AR15 AY66 VSS VSS E11
    AH67 VSS VSS AR16 B10 VSS VSS E15 18 OF 20
    AJ15 VSS VSS AR20 B14 VSS VSS E18
    +1.0V_XDP AJ18 VSS VSS AR23 B18 VSS VSS E21 SKL-U_BGA1356
    AJ20 VSS VSS AR28 B22 VSS VSS E46
    AJ4 VSS VSS AR35 B30 VSS VSS E50
    RC31 1 CMC@ 2 1K_0402_5% XDP_ITP_PMODE AK11 VSS VSS AR42 B34 VSS VSS E53
    XDP_ITP_PMODE <13> VSS VSS VSS VSS
    AK16 AR43 B39 E56
    AK18 VSS VSS AR45 B44 VSS VSS E6
    AK21 VSS VSS AR46 B48 VSS VSS E65
    B CFG3 <13,14> VSS VSS VSS VSS B
    RC43 2 @ 1 0_0402_5% XDP_PRSENT_CPU AK22 AR48 B53 E71
    AK27 VSS VSS AR5 B58 VSS VSS F1
    AK63 VSS VSS AR50 B62 VSS VSS F13
    XDP_SPI_IO2 <8> VSS VSS VSS VSS
    RC46 2 @ 1 0_0402_5% XDP_PRSENT_PCH AK68 AR52 B66 F2
    AK69 VSS VSS AR53 B71 VSS VSS F22
    CMC@ AK8 VSS VSS AR55 BA1 VSS VSS F23
    RC35 2 1 51_0402_1% CPU_XDP_TCK0 AL2 VSS VSS AR58 BA10 VSS VSS F27
    CPU_XDP_TCK0 <12> VSS VSS VSS VSS
    AL28 AR63 BA14 F28
    RC37 2 @ 1 51_0402_5% PCH_JTAG_TCK1 AL32 VSS VSS AR8 BA18 VSS VSS F32
    PCH_JTAG_TCK1 <12> VSS VSS VSS VSS
    AL35 AT2 BA2 F33
    AL38 VSS VSS AT20 BA23 VSS VSS F35
    AL4 VSS VSS AT23 BA28 VSS VSS F37
    Place to CPU side VSS VSS VSS VSS
    AL45 AT28 BA32 F38
    AL48 VSS VSS AT35 BA36 VSS VSS F4
    AL52 VSS VSS AT4 F68 VSS VSS F40
    AL55 VSS VSS AT42 BA45 VSS VSS F42
    SOC_XDP_TRST# AL58 VSS VSS AT56 VSS VSS BA41
    T4956 TP@ SOC_XDP_TRST# <12> VSS VSS VSS
    AL64 AT58
    PCH_RSMRST#_Q VSS VSS
    T4962 TP@ PCH_RSMRST#_Q <11>
    16 OF 20 17 OF 20
    T4963 TP@ XDP_PREQ# XDP_PREQ# <10>
    SKL-U_BGA1356 SKL-U_BGA1356
    T4964 TP@ XDP_PRDY#
    XDP_PRDY# <10>

    A A

    Security Classification
    2014/05/19
    Compal Secret Data
    2015/12/31 Title
    Compal Electronics, Inc.
    Issued Date Deciphered Date
    THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
    SKL-U(11/12)GND
    AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&DSize Document Number Rev
    DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS Custom 0.2
    MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC. LA-C071P
    Date: Tuesday, July 28, 2015 Sheet 14 of 55
    5 4 3 2 1
    5 4 3 2 1

    Main Func : CPU


    +VCC_GT +VCC_GT
    +VCC_CORE +VCC_CORE UC1M @ SKL-U
    Rev_1.0
    UC1L @ SKL-U CPU POWER 2 OF 4
    Rev_1.0 N70

    A30 Vinafix.com
    VCC_A30
    CPU POWER 1 OF 4

    VCC_G32
    G32
    A48
    A53 VCCGT
    VCCGT
    VCCGT
    VCCGT
    VCCGT
    N71
    R63
    A34 G33 A58 R64
    A39 VCC_A34 VCC_G33 G35 A62 VCCGT VCCGT R65
    D D
    A44 VCC_A39 VCC_G35 G37 A66 VCCGT VCCGT R66
    AK33 VCC_A44 VCC_G37 G38 AA63 VCCGT VCCGT R67
    AK35 VCC_AK33 VCC_G38 G40 AA64 VCCGT VCCGT R68
    AK37 VCC_AK35 VCC_G40 G42 AA66 VCCGT VCCGT R69
    AK38 VCC_AK37 VCC_G42 J30 AA67 VCCGT VCCGT R70
    AK40 VCC_AK38 VCC_J30 J33 AA69 VCCGT VCCGT R71
    AL33 VCC_AK40 VCC_J33 J37 AA70 VCCGT VCCGT T62
    AL37 VCC_AL33 VCC_J37 J40 AA71 VCCGT VCCGT U65
    AL40 VCC_AL37 VCC_J40 K33 +VCC_CORE AC64 VCCGT VCCGT U68
    AM32 VCC_AL40 VCC_K33 K35 AC65 VCCGT VCCGT U71
    AM33 VCC_AM32 VCC_K35 K37 RC203 1 2 100_0402_1% AC66 VCCGT VCCGT W63
    AM35 VCC_AM33 VCC_K37 K38 AC67 VCCGT VCCGT W64
    AM37 VCC_AM35 VCC_K38 K40 RC205 1 2 100_0402_1% AC68 VCCGT VCCGT W65
    AM38 VCC_AM37 VCC_K40 K42 AC69 VCCGT VCCGT W66
    G30 VCC_AM38 VCC_K42 K43 AC70 VCCGT VCCGT W67
    VCC_G30 VCC_K43 AC71 VCCGT VCCGT W68
    K32 E32 J43 VCCGT VCCGT W69
    T123 TP@ RSVD VCC_SENSE VCCSENSE <40> VCCGT VCCGT
    E33 J45 W70
    VSS_SENSE VSSSENSE <40> VCCGT VCCGT
    T121 TP@ AK32 J46 W71
    RSVD B63 H_CPU_SVIDALRT# J48 VCCGT VCCGT Y62
    AB62 VIDALERT# A63 VIDSCLK +1.0VS_VCCSTG J50 VCCGT VCCGT
    VCCOPC_AB62 VIDSCK VIDSCLK <40> VCCGT
    P62 D64 VIDSOUT J52
    V62 VCCOPC_P62 VIDSOUT J53 VCCGT AK42
    VCCOPC_V62 G20 J55 VCCGT VCCGTX_AK42 AK43
    For CPU2+3e SKU VCCSTG_G20 VCCGT VCCGTX_AK43
    H63 J56 AK45
    VCC_OPC_1P8_H63 J58 VCCGT VCCGTX_AK45 AK46
    G61 J60 VCCGT VCCGTX_AK46 AK48
    VCC_OPC_1P8_G61 K48 VCCGT VCCGTX_AK48 AK50
    C VCCOPC_SENSE AC63 K50 VCCGT VCCGTX_AK50 AK52 C
    T132 TP@ VCCOPC_SENSE VCCGT VCCGTX_AK52
    T133 TP@ VSSOPC_SENSE AE63 K52 AK53
    VSSOPC_SENSE K53 VCCGT VCCGTX_AK53 AK55
    AE62 K55 VCCGT VCCGTX_AK55 AK56
    AG62 VCCEOPIO K56 VCCGT VCCGTX_AK56 AK58
    VCCEOPIO K58 VCCGT VCCGTX_AK58 AK60
    VCCEOPIO_SENSE AL63 K60 VCCGT VCCGTX_AK60 AK70
    T137 TP@ VCCEOPIO_SENSE VCCGT VCCGTX_AK70
    T139 TP@ VSSEOPIO_SENSE AJ62 L62 AL43
    VSSEOPIO_SENSE 12 OF 20 L63 VCCGT VCCGTX_AL43 AL46
    L64 VCCGT VCCGTX_AL46 AL50
    For CPU2+3e SKU
    SKL-U_BGA1356 L65 VCCGT VCCGTX_AL50 AL53
    L66 VCCGT VCCGTX_AL53 AL56
    L67 VCCGT VCCGTX_AL56 AL60
    L68 VCCGT VCCGTX_AL60 AM48
    L69 VCCGT VCCGTX_AM48 AM50
    +VCC_GT L70 VCCGT VCCGTX_AM50 AM52
    L71 VCCGT VCCGTX_AM52 AM53
    100_0402_1% 2 1 RC219 M62 VCCGT VCCGTX_AM53 AM56
    N63 VCCGT VCCGTX_AM56 AM58
    100_0402_1% 2 1 RC226 N64 VCCGT VCCGTX_AM58 AU58
    N66 VCCGT VCCGTX_AU58 AU63
    N67 VCCGT VCCGTX_AU63 BB57
    N69 VCCGT VCCGTX_BB57 BB66
    VCCGT VCCGTX_BB66
    VCC_GT_SENSE J70 AK62 VCCGTX_SENSE T155 TP@
    <40> VCC_GT_SENSE VCCGT_SENSE VCCGTX_SENSE
    VSS_GT_SENSE J69 AL61 VSSGTX_SENSE T219 TP@
    <40> VSS_GT_SENSE VSSGT_SENSE VSSGTX_SENSE
    13 OF 20

    SKL-U_BGA1356
    B B

    SVID ALERT +1.0V_VCCST


    1

    RC179 Place the PU


    56_0402_5% resistors close to CPU
    2

    H_CPU_SVIDALRT# 1 2 (To VR)


    VIDALERT_N <40>
    RC180 220_0402_5%

    +1.0V_VCCST

    SVID DATA
    1

    RC181 Place the PU


    A 100_0402_1% resistors close to CPU A
    2

    VIDSOUT
    VIDSOUT <40> (To VR) Security Classification
    2014/05/19
    Compal Secret Data
    2015/12/31 Title
    Compal Electronics, Inc.
    Issued Date Deciphered Date
    THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
    SKL-U(10/12)Power,SVID
    AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&DSize Document Number Rev
    DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS Custom 0.2
    MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC. LA-C071P
    Date: Tuesday, July 28, 2015 Sheet 15 of 55
    5 4 3 2 1
    5 4 3 2 1

    Main Func : CPU +1.35V_VDDQ


    PSC Side BSC Side
    1 1 1 1 1 1 1 1 1 1
    CC37 CC38 CC39 CC40 CC41 CC42 CC43 CC44 CC45 CC46

    10U_0603_6.3V6M

    10U_0603_6.3V6M

    10U_0603_6.3V6M

    10U_0603_6.3V6M

    10U_0603_6.3V6M

    10U_0603_6.3V6M

    1U_0402_6.3V6K

    1U_0201_6.3V6K

    1U_0402_6.3V6K

    1U_0402_6.3V6K
    2 2 2 2 2 2 2 2 2 2

    Vinafix.com
    +1.0VS_VCCIO
    D D
    PSC Side BSC Side
    1 1 1 1 1 1 1 1 1 1
    CC36 CC35 CC34 CC33 CC32 CC31 CC30 CC29 CC28 CC27
    +1.35V_VDDQ : 10UF/6.3V/0603 *6 + 1UF/6.3V/0402 * 4

    1U_0402_6.3V6K

    1U_0402_6.3V6K

    1U_0402_6.3V6K

    1U_0402_6.3V6K

    1U_0201_6.3V6K

    1U_0201_6.3V6K

    1U_0201_6.3V6K

    1U_0201_6.3V6K

    10U_0402_6.3V6M

    10U_0402_6.3V6M
    2 2 2 2 2 2 2 2 2 2

    +1.35V_VDDQC UC1N @ SKL-U


    Rev_1.0
    RC208 1 @ 2 0_0603_5% BSC Side CPU POWER 3 OF 4
    CC47 1 2 1U_0402_6.3V6K AU23 AK28
    AU28 VDDQ_AU23 VCCIO AK30
    AU35 VDDQ_AU28 VCCIO AL30
    PSC Side VDDQ_AU35 VCCIO
    CC1411 2 10U_0402_6.3V6M AU42 AL42
    +1.0V_VCCSTU +1.0V_VCCST BB23 VDDQ_AU42 VCCIO AM28
    BB32 VDDQ_BB23 VCCIO AM30
    PSC Side VDDQ_BB32 VCCIO
    RC140 1 2 0_0402_5% BB41 AM42 +VCC_SA
    CC48 1 2 1U_0402_6.3V6K BB47 VDDQ_BB41 VCCIO
    BB51 VDDQ_BB47 AK23
    VDDQ_BB51 VCCSA AK25
    +1.0VS_VCCSTG VCCSA G23
    AM40 VCCSA G25
    BSC Side VDDQC VCCSA G27
    CC56 1 2 1U_0201_6.3V6K A18 VCCSA G28
    VCCST VCCSA J22
    A22 VCCSA J23
    VCCSTG_A22 VCCSA J27
    C +1.35V_VCCSFR_OC AL23 VCCSA K23 +VCC_SA C
    VCCPLL_OC VCCSA K25
    BSC Side VCCSA
    RC141 1 2 0_0402_5% K20 K27 RC227 1 2 100_0402_1%
    CC49 1 2 0.1U_0201_10V6K K21 VCCPLL_K20 VCCSA K28
    VCCPLL_K21 VCCSA K30 RC228 1 2 100_0402_1%
    VCCSA
    AM23 VCCIO_SENSE T124 TP@
    +1.0V_VCCSFR VCCIO_SENSE AM22 VSSIO_SENSE
    VSSIO_SENSE T125 TP@
    PSC Side
    RC143 1 2 0_0402_5% H21 VSA_SEN-
    VSSSA_SENSE VSA_SEN- <40>
    CC55 1 2 1U_0402_6.3V6K H20 VSA_SEN+
    VCCSA_SENSE VSA_SEN+ <40>
    14 OF 20

    SKL-U_BGA1356

    +1.0V_PRIM TO +1.0V_VCCSTU
    I (Max) : 0.04 A(+1.0V_VCCSTU)
    RON(Max) : 25 mohm
    to +1.0VS_VCCSTG/ +1.0VS_VCCIO
    +1.0V_PRIM_JP ＜-------- +1.0V_PRIM +5VALW V drop : 0.001 V +1.0V_VCCSTU
    @ JP14
    1
    1 2
    2 Imax : 2.77 A +1.0V_PRIM TO +1.0VS_VCCSTG / +1.0VS_VCCIO
    B
    1 1 B
    JUMP_43X79 1 CC98 CC96
    CC97 1U_0402_6.3V6K 0.1U_0402_25V6
    1U_0402_6.3V6K
    @ 2 2 +5VALW +1.0V_PRIM_JP
    2
    I (Max) : 3 A(+1.0VS_VCCIO)
    UC5 RON(Max) : 6.2 mohm
    1 14 Follow 543977_SKL_PDDG_Rev0_91 Imax : 0.04 A +1.0VS_VCCSTG
    2 VIN1 VOUT1 13 V drop : 0.019 V
    VIN1 VOUT1 CC95 10PF ->22us(Spec:<= 65us) 1 1
    CC88 CC117 RC188 1 2 0_0402_5%
    RC144 1 2 0_0402_5% EN_1.0V_VCCSTU 3 12 CC95 1 2 10P_0402_50V8J 0.1U_0402_25V6 1U_0402_6.3V6K UC6
    <11,23,37> SIO_SLP_S4# ON1 CT1
    @ 1 2 @ 1 1
    CC104 1U_0402_6.3V6K 4 11 2 2 2 VIN1 CC89
    VBIAS GND VIN2
    0.1U_0402_25V6
    RC194 1 2 0_0402_5% EN_1.8VS 5 10 CC94 1 2 1000P_0402_50V7K 7 6 +1.0VS_VCCSTG_IO @
    11,16,23,32,34,41> SIO_SLP_S3# ON2 CT2 VIN thermal VOUT 2
    6 9 +1.8VS 3
    +1.8V_PRIM +1.8V_PRIM_VS 7 VIN2 VOUT2 8 VBIAS Imax : 3 A
    VIN2 VOUT2 4 5 +1.0VS_VCCIO
    @ ON GND
    RC3931 2 0_0603_5% 15 1 @ JP15
    GPAD CC100 1 2
    1 1 2

    VCCSTG_EN_R
    CC99 EM5209VF_DFN14_2X3 0.1U_0402_25V6 TPS22961DNYR_WSON8
    For Power consumption 1U_0402_6.3V6K RZ75 1 @ 2 0_0402_5% JUMP_43X79 1
    @ 2 CC90
    Measurement 2 +3VALW
    I (Max) : 0.536 A(+1.8VS) 1 2 DC7 0.1U_0402_25V6
    RON(Max) : 25 mohm @
    RB751S40T1G_SOD523-2 2
    V drop : 0.013 V
    5

    1 RC67
    P

    <11,16,23,32,34,41> SIO_SLP_S3# B 4 VCCSTG_EN 2 1


    A
    +1.8V_PRIM TO +1.8VS <11> SIO_SLP_S0#
    2
    A
    O 49.9K_0402_1% 1
    A
    G

    UC15 CC101
    TC7SH08FU_SSOP5~D 0.1U_0402_25V6
    3

    Security Classification
    2014/05/19
    Compal Secret Data
    2015/12/31 Title
    Compal Electronics, Inc.
    Issued Date Deciphered Date
    THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
    SKL-U(8/12)Power
    AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&DSize Document Number Rev
    DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS Custom 0.2
    MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC. LA-C071P
    Date: Tuesday, July 28, 2015 Sheet 16 of 55
    5 4 3 2 1
    5 4 3 2 1

    Main Func : CPU +1.0V_PRIM


    +1.8V_PRIM +3V_PRIM
    Follow 543016_SKL_U_Y_PDG_0_9 +3V_1.8V_PGPPA 0_0402_5% 2 @ 1 RC196
    0_0402_5% 2 1 RC197
    +1.0V_PRIM +3V_PRIM +3V_PRIM
    +1.0V_PRIM +3V_PGPPB +3V_PRIM
    0_0402_5% 2 1 RC161
    Imax : 2.57A 1 1 1 1 1 1 @
    @ @ @ @ @ @ @ 1U_0402_6.3V6K 2 1 CC102

    Vinafix.com
    +1.0VO_DSW CC76 1 2 1U_0402_6.3V6K CC111 CC112 CC113 CC114 CC115 CC116

    22U_0603_6.3V6M

    22U_0603_6.3V6M

    22U_0603_6.3V6M

    22U_0603_6.3V6M

    22U_0603_6.3V6M

    22U_0603_6.3V6M
    2 2 2 2 2 2 +3V_PGPPC +3V_PRIM
    0_0402_5% 2 1 RC163
    CC85 1 2 1U_0402_6.3V6K @
    D D
    1U_0402_6.3V6K 2 1 CC73
    +1.0V_PRIM

    +3V_PRIM
    +3V_PGPPD
    CC87 1 2 1U_0402_6.3V6K 0_0402_5% 2 1 RC172

    +1.0V_MPHYPLL 1U_0402_6.3V6K 2 1 CC103


    UC1O @ SKL-U
    Rev_1.0
    @ CPU POWER 4 OF 4 +3V_PGPPE +3V_PRIM
    CC81 1 2 22U_0603_6.3V6M AB19 0_0402_5% 2 1 RC167
    @ AB20 VCCPRIM_1P0 AK15 @
    CC82 1 2 22U_0603_6.3V6M P18 VCCPRIM_1P0 VCCPGPPA AG15 1U_0402_6.3V6K 2 1 CC74
    VCCPRIM_1P0 VCCPGPPB Y16 +1.8V_PRIM
    CC80 1 2 1U_0201_6.3V6K AF18 VCCPGPPC Y15
    AF19 VCCPRIM_CORE VCCPGPPD T16
    V20 VCCPRIM_CORE VCCPGPPE AF16 1U_0402_6.3V6K 2 1 CC72
    V21 VCCPRIM_CORE VCCPGPPF AD15 +3V_PRIM
    VCCPRIM_CORE VCCPGPPG For SD CARD
    @ AL1 V19
    CC118 1 2 22U_0603_6.3V6M DCPDSW_1P0 VCCPRIM_3P3_V19 +3V_PRIM
    @ K17 T1
    CC119 1 2 22U_0603_6.3V6M L1 VCCMPHYAON_1P0 VCCPRIM_1P0_T1 @
    @ VCCMPHYAON_1P0 AA1 1U_0402_6.3V6K 2 1 CC67
    +1.0V_APLL CC61 1 2 1U_0402_6.3V6K N15 VCCATS_1P8
    N16 VCCMPHYGT_1P0_N15 AK17
    VCCMPHYGT_1P0_N16 VCCRTCPRIM_3P3 +1.0V_PRIM
    N17 +1.0V_DTS
    @ P15 VCCMPHYGT_1P0_N17 AK19 0_0402_5% 2 1 RC162
    CC124 1 2 22U_0603_6.3V6M P16 VCCMPHYGT_1P0_P15 VCCRTC_AK19 BB14
    VCCMPHYGT_1P0_P16 VCCRTC_BB14 +1.8V_PRIM
    CC64 1 2 0.1U_0402_10V7K K15 BB10 1 2
    RF@ L15 VCCAMPHYPLL_1P0 DCPRTC 0.1U_0402_10V7K CC71
    +1.0V_PRIM Intel SR_V1.5 : 44638000 VCCAMPHYPLL_1P0 A14
    V15 VCCCLK1
    C VCCAPLL_1P0 K19 C
    AB17 VCCCLK2 +3V_PRIM_RTC +3V_PRIM
    +3VALW Y18 VCCPRIM_1P0_AB17 L21 0_0402_5% 2 1 RC171
    +3VALW_DSW VCCPRIM_1P0_Y18 VCCCLK3
    RC209 1 @ 2 0_0603_5% AD17 N20 1U_0402_6.3V6K 2 1 CC77
    AD18 VCCDSW_3P3_AD17 VCCCLK4
    Follow 543016_SKL_U_Y_PDG_0_9 VCCDSW_3P3_AD18
    +3V_PRIM AJ17 L19 0.1U_0201_10V6K 2 1 CC78 +3VL_RTC
    VCCDSW_3P3_AJ17 VCCCLK5
    AJ19 A10
    VCCHDA VCCCLK6
    T130
    CC63 1 2 10P_0402_50V8J AJ16 AN11 PRIMCORE_VID0
    VCCSPI GPP_B0/CORE_VID0 +1.0V_PRIM
    RF@ AN13 TP@ +1.0V_CLK6_24TBT @
    Intel SR_V1.5 : 44638000 AF20 GPP_B1/CORE_VID1 0_0603_5% 2 1 RC169
    VCCSRAM_1P0 T131
    +3V_PRIM AF21 PRIMCORE_VID1 @
    +3V_SPI T19 VCCSRAM_1P0 TP@ 22U_0603_6.3V6M2 1 CC125
    VCCSRAM_1P0
    Follow 543016_SKL_U_Y_PDG_1_0
    RC154 1 2 0_0402_5% T20 @
    VCCSRAM_1P0 1U_0402_6.3V6K 2 1 CC75
    +1.0V_MPHYPLL AJ21
    VCCPRIM_3P3_AJ21
    AK20
    @ VCCPRIM_1P0_AK20
    +3V_PRIM CC1221 2 1U_0402_6.3V6K N18
    VCCAPLLEBB_1P0 15 OF 20
    +1.0V_APLL +1.0V_PRIM
    @
    SKL-U_BGA1356 0_0603_5% 2 1 RC148
    +1.0V_PRIM @
    22U_0603_6.3V6M2 1 CC123 Follow 543016_SKL_U_Y_PDG_1_0
    @
    +1.0V_PRIM
    CC91 1 2 1U_0402_6.3V6K +1.0V_CLK4_F100OC @
    0_0603_5% 2 1 RC190
    +1.0V_MPHYPLL @
    22U_0603_6.3V6M2 1 CC127 Follow 543016_SKL_U_Y_PDG_1_0
    @
    22U_0603_6.3V6M2 1 CC128
    B CC68 1 2 1U_0201_6.3V6K B

    +1.0V_PRIM
    +1.0V_CLK5 @
    0_0603_5% 2 1 RC152
    @
    22U_0603_6.3V6M2 1 CC129 Follow 543016_SKL_U_Y_PDG_1_0
    @
    22U_0603_6.3V6M2 1 CC130 +1.0V_CLK6_24TBT

    @
    +1.8VS +1.8VS_3VS_PGPPA 22U_0603_6.3V6M2 1 CC126
    @
    RC177 1 @ 2 0_0402_5% 1U_0402_6.3V6K 2 1 CC86

    +3VS

    RC178 1 2 0_0402_5%
    +3VALW TO +3V_PRIM
    +3VALW Short Jump JP16 +3V_PRIM
    For NON-DS3
    @
    Intel_2015MOW_WW17 : JP16 1 2 JUMP_43X79
    1 2
    +1.0V_PRIM TO +1.0V_MPHYPLL LPM mode is no support for SKL platform.
    >>> Please short JP17 <<< For DS3 1
    CC51
    Short Jump JP17 1 @ JP18 4.7U_0603_6.3V6K
    +1.0V_PRIM For Volume +1.0V_MPHYPLL CC50 +3V_PRIMJP 1 2
    @ 1U_0402_6.3V6K UC8 DSX@ 1 2 2
    JP17 1 2 JUMP_43X79 Imax : 2.766A DSX@ 5 1 JUMP_43X79
    1 2 2 IN OUT
    For Premium 2 +3VALW
    1 GND
    CC58 RC191 1 DSX@ 2 0_0402_5%
    +5VALW <23> PCH_ALW_ON
    1 0.1U_0402_25V6 RC174 1 @ 2 0_0402_5% EN_3V_PRIM 4 3 3V_PRIM_OC 1 @ 2
    <11,23,38,39> SIO_SLP_SUS# EN OC
    A CC59 UC4 LPM@ @ 10K_0402_5% RC166 A
    1U_0402_6.3V6K 1 2 SY6288C20AAC_SOT23-5
    1 VIN1
    CC52 LPM@ 2 I (Max) : 0.46 A(+3V_PRIM)
    0.1U_0402_25V6 2 VIN2 @ JP19
    LPM@ 7 6 +1.0V_MPHYJP1 2
    Note : Stuff DSX@ for meet energy star power RDS(Typ) : 65 mohm
    2 VIN thermal VOUT 1 2 consumption under AC S5 mode V drop : 0.03 V
    3 JUMP_43X79
    VBIAS
    LPM@
    1 2 EXT_PWR_GATE#_R 4 5
    <11> MPHYP_PWR_EN ON GND
    RC210 0_0402_5%

    TPS22961DNYR_WSON8
    Security Classification
    2014/05/19
    Compal Secret Data
    2015/12/31 Title
    Compal Electronics, Inc.
    Issued Date Deciphered Date
    I (Max) : 2.766 A(+1.0V_MPHYPLL)
    RON(Max) : 6.2 mohm THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
    SKL-U(9/12)Power
    AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&DSize Document Number Rev
    V drop : 0.017 V DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS Custom 0.2
    MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC. LA-C071P
    Date: Tuesday, July 28, 2015 Sheet 17 of 55
    5 4 3 2 1
    A B C D E

    Main Func : SO-DIMM A +0.675V_DDRA_VREFDQ


    10mils JDIMM1
    Reverse Type
    1 2
    3 VREF_DQ VSS 4 DDR_A_D5
    VSS DQ4 2-3A to 1 DIMMs/channel

    0.1U_0402_25V6K
    2.2U_0402_6.3V6M
    DDR_A_D0 5 6 DDR_A_D4
    <7> DDR_A_DQS#[0..7] DQ0 DQ5
    1 DDR_A_D1 7 8
    DQ1 VSS

    1
    +1.35V_VDDQ

    CD2
    9 10 DDR_A_DQS#0
    <7> DDR_A_D[0..63] VSS DQS0#

    CD1
    D/DQ Signals link to CPU 11 12 DDR_A_DQS0
    13 DM0 DQS0 14

    Vinafix.com
    <7> DDR_A_DQS[0..7]

    2
    2 DDR_A_D6 15 VSS VSS 16 DDR_A_D3
    DQ2 DQ6

    1
    @ @ DDR_A_D2 17 18 DDR_A_D7
    19 DQ3 DQ7 20 RD1
    <7> DDR_A_MA[0..15] VSS VSS
    DDR_A_D12 21 22 DDR_A_D9 470_0402_5%
    1 DDR_A_BS0 DDR_A_D11 23 DQ8 DQ12 24 DDR_A_D8 1
    <7> DDR_A_BS0 DQ9 DQ13
    DDR_A_BS1 25 26
    <7> DDR_A_BS1

    2
    DDR_A_BS2 CMD Signals from CPU DDR_A_DQS#1 27 VSS VSS 28
    <7> DDR_A_BS2 DQS1# DM1
    DDR_A_WE# DDR_A_DQS1 29 30 DDR_DRAMRST#
    <7> DDR_A_WE# DQS1 RESET# DDR_DRAMRST# <7,19>
    From CPU to CHB

    0.1U_0402_25V6K
    DDR_A_CAS# 31 32
    <7> DDR_A_CAS# VSS VSS
    DDR_A_RAS# DDR_A_D14 33 34 DDR_A_D10 @1
    <7> DDR_A_RAS# DQ10 DQ14

    CD3
    DDR_A_D15 35 36 DDR_A_D13
    37 DQ11 DQ15 38
    DDR_A_CLK0 DDR_A_D20 39 VSS VSS 40 DDR_A_D16
    <7> DDR_A_CLK0 DQ16 DQ20 2
    CAD NOTE
    DDR_A_CLK#0 Clock Signals from CPU DDR_A_D17 41 42 DDR_A_D21 PLACE THE CAP NEAR TO
    <7> DDR_A_CLK#0 DQ17 DQ21
    DDR_A_CLK1 43 44
    <7> DDR_A_CLK1
    DDR_A_CLK#1 DDR_A_DQS#2 45 VSS VSS 46 DIMM RESET PIN
    <7> DDR_A_CLK#1 DQS2# DM2
    DDR_A_DQS2 47 48
    49 DQS2 VSS 50 DDR_A_D19
    DDR_A_CKE0 DDR_A_D18 51 VSS DQ22 52 DDR_A_D23
    <7> DDR_A_CKE0 DQ18 DQ23
    DDR_A_CKE1 CTL Signals from CPU DDR_A_D22 53 54
    <7> DDR_A_CKE1 DQ19 VSS
    DDR_A_CS#0 55 56 DDR_A_D25
    <7> DDR_A_CS#0 VSS DQ28
    DDR_A_CS#1 DDR_A_D24 57 58 DDR_A_D29
    <7> DDR_A_CS#1 DQ24 DQ29
    DDR_A_D28 59 60
    61 DQ25 VSS 62 DDR_A_DQS#3
    PCH_SMBCLK SMBUS Signals link to CPU 63 VSS DQS3# 64 DDR_A_DQS3
    <8,19> PCH_SMBCLK DM3 DQS3
    PCH_SMBDAT 65 66
    <8,19> PCH_SMBDAT VSS VSS
    DDR_A_D30 67 68 DDR_A_D27
    DDR_A_D31 69 DQ26 DQ30 70 DDR_A_D26
    DDR_A_ODT0 71 DQ27 DQ31 72
    <7> DDR_A_ODT0 +1.35V_VDDQ VSS VSS +1.35V_VDDQ
    DDR_A_ODT1 From SOC ODT Signals to CH A
    <7> DDR_A_ODT1
    DDR_A_CKE0 73 74 DDR_A_CKE1
    75 CKE0 CKE1 76
    Note: VDD VDD
    Layout Note: 77 78 DDR_A_MA15
    Check voltage tolerance of DDR_A_BS2 79 NC A15 80 DDR_A_MA14
    Place near JDIMM1 VREF_DQ at the DIMM socket 81 BA2 A14 82
    2 DDR_A_MA12 83 VDD VDD 84 DDR_A_MA11 2
    DDR_A_MA9 85 A12/BC# A11 86 DDR_A_MA7
    87 A9 A7 88
    DDR_A_MA8 89 VDD VDD 90 DDR_A_MA6
    DDR_A_MA5 91 A8 A6 92 DDR_A_MA4
    +1.35V_VDDQ 93 A5 A4 94
    DDR_A_MA3 95 VDD VDD 96 DDR_A_MA2
    DDR_A_MA1 97 A3 A2 98 DDR_A_MA0
    99 A1 A0 100
    VDD VDD
    1U_0402_6.3V6K

    1U_0402_6.3V6K

    1U_0402_6.3V6K

    1U_0402_6.3V6K

    1U_0402_6.3V6K

    1U_0402_6.3V6K

    DDR_A_CLK0 101 102 DDR_A_CLK1


    DDR_A_CLK#0 103 CK0 CK1 104 DDR_A_CLK#1
    1 1 1 1 1 1 CK0# CK1#
    @ @ @ @ 105 106
    VDD VDD
    CD4

    CD5

    CD6

    CD7

    CD8

    CD9

    DDR_A_MA10 107 108 DDR_A_BS1


    DDR_A_BS0 109 A10/AP BA1 110 DDR_A_RAS#
    2 2 2 2 2 2 111 BA0 RAS# 112
    DDR_A_WE# 113 VDD VDD 114 DDR_A_CS#0
    DDR_A_CAS# 115 WE# S0# 116 DDR_A_ODT0
    117 CAS# ODT0 118
    DDR_A_MA13 119 VDD VDD 120 DDR_A_ODT1 +0.675V_DDRA_VREFCA +0.675V_DDR_VREFCA
    DDR_A_CS#1 121 A13 ODT1 122
    123 S1# NC 124
    VDD VDD 10mils
    125 126 1 2
    +1.35V_VDDQ TEST VREF_CA

    0.1U_0402_25V6K
    127 128
    VSS VSS

    2.2U_0402_6.3V6M
    DDR_A_D37 129 130 DDR_A_D33 RD8
    DDR_A_D32 131 DQ32 DQ36 132 DDR_A_D36 0_0402_5%
    DQ33 DQ37 1

    1
    10U_0603_6.3V6M

    10U_0603_6.3V6M

    10U_0603_6.3V6M

    10U_0603_6.3V6M

    10U_0603_6.3V6M

    10U_0603_6.3V6M

    10U_0603_6.3V6M

    10U_0603_6.3V6M

    CD18
    133 134
    VSS VSS

    CD17
    DDR_A_DQS#4 135 136
    DQS4# DM4
    330U_D3_2.5VY_R6M

    @ @ 1 DDR_A_DQS4 137 138 @

    2
    139 DQS4 VSS 140 DDR_A_D35 2
    1 1 1 1 1 1 1 1 VSS DQ38
    CD10

    CD11

    CD12

    CD13

    CD14

    CD19

    CD15

    CD20

    CD16

    + DDR_A_D38 141 142 DDR_A_D34


    DDR_A_D39 143 DQ34 DQ39 144
    145 DQ35 VSS 146 DDR_A_D41
    3 2 2 2 2 2 2 2 2 2 DDR_A_D45 147 VSS DQ44 148 DDR_A_D40 3
    DDR_A_D44 149 DQ40 DQ45 150
    151 DQ41 VSS 152 DDR_A_DQS#5
    153 VSS DQS5# 154 DDR_A_DQS5
    155 DM5 DQS5 156 +1.35V_VDDQ
    DDR_A_D46 157 VSS VSS 158 DDR_A_D42
    DDR_A_D47 159 DQ42 DQ46 160 DDR_A_D43
    DQ43 DQ47

    1
    1.8K_0402_1%
    161 162
    VSS VSS

    RD9
    DDR_A_D48 163 164 DDR_A_D52
    DDR_A_D53 165 DQ48 DQ52 166 DDR_A_D49
    Layout Note: Layout Note: DQ49 DQ53 +0.675V_DDRA_VREFDQ +0.675V_A_VREFDQ
    167 168
    Place near JDIMM1.203,204 Place near JDIMM1.199 DDR_A_DQS#6 169 VSS VSS 170

    2
    DDR_A_DQS6 171 DQS6# DM6 172
    173 DQS6 VSS 174 DDR_A_D54 RD10 1 2
    DDR_A_D51 175 VSS DQ54 176 DDR_A_D50 2_0402_1%
    DQ50 DQ55 1
    DDR_A_D55 177 178
    179 DQ51 VSS 180 DDR_A_D59 CD21
    VSS DQ60

    1
    +3VS

    1.8K_0402_1%
    +0.675VS_VTT DDR_A_D58 181 182 DDR_A_D57 0.022U_0402_16V7K
    DQ56 DQ61 2

    RD11
    DDR_A_D56 183 184
    185 DQ57 VSS 186 DDR_A_DQS#7
    VSS DQS7#

    1
    187 188 DDR_A_DQS7
    DM7 DQS7
    0.1U_0402_25V6K

    0.1U_0402_25V6K

    1U_0402_6.3V6K

    1U_0402_6.3V6K

    2.2U_0402_6.3V6M

    189 190 RD12

    2
    @1 @1 DDR_A_D60 191 VSS VSS 192 DDR_A_D62
    1 1 1 DQ58 DQ62 24.9_0402_1%
    1
    CD22

    CD23

    0.1U_0402_25V6K

    DDR_A_D61 193 194 DDR_A_D63


    +0.675VS_VTT +3VS DQ59 DQ63 +0.675VS_VTT
    CD24

    CD25

    CD26

    195 196

    2
    VSS VSS
    CD27

    @ DDR_A_SA0 197 198


    2

    2 2 2 2 2 199 SA0 EVENT# 200 PCH_SMBDAT


    DDR_A_SA1 201 VDDSPD SDA 202 PCH_SMBCLK
    +0.675VS_VTT 203 SA1 SCL 204 +0.675VS_VTT
    VTT VTT Place near to SO-DIMM connector.
    205 206
    207 GND1 GND2 208
    4 BOSS1 BOSS2 4

    BELLW_80001-1021

    Address : 00
    DDR_A_SA0
    SP07000P700
    CONN@
    Interleaved Memory
    DDR_A_SA1 Security Classification
    2014/05/19
    Compal Secret Data
    2015/12/31 Title
    Compal Electronics, Inc.
    Issued Date Deciphered Date
    THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
    DDR3L_DIMMA
    AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&DSize Document Number Rev
    DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS Custom 0.2
    MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC. LA-C071P
    Date: Tuesday, July 28, 2015 Sheet 18 of 55
    A B C D E
    A B C D E

    Main Func : SO-DIMM B +0.675V_DDRB_VREFDQ Reverse Type


    10mils JDIMM2
    1 2
    3 VREF_DQ VSS1 4 DDR_B_D10
    2-3A to 1 DIMMs/channel
    VSS2 DQ4

    0.1U_0402_25V6K
    2.2U_0402_6.3V6M
    DDR_B_D14 5 6 DDR_B_D9
    <7> DDR_B_DQS#[0..7] DQ0 DQ5
    1 DDR_B_D15 7 8
    DQ1 VSS3

    1
    9 10 DDR_B_DQS#1
    <7> DDR_B_D[0..63] VSS4 DQS#0

    CD29
    CD28
    D/DQ Signals link to CPU 11 12 DDR_B_DQS1
    @ @ 13 DM0 DQS0 14

    Vinafix.com
    <7> DDR_B_DQS[0..7]

    2
    2 DDR_B_D13 15 VSS5 VSS6 16 DDR_B_D8
    DDR_B_D11 17 DQ2 DQ6 18 DDR_B_D12
    19 DQ3 DQ7 20
    <7> DDR_B_MA[0..15] VSS7 VSS8
    DDR_B_D5 21 22 DDR_B_D4
    1 DDR_B_BS0 DDR_B_D1 23 DQ8 DQ12 24 DDR_B_D0 1
    <7> DDR_B_BS0 DQ9 DQ13
    DDR_B_BS1 CMD Signals from CPU 25 26
    <7> DDR_B_BS1 VSS9 VSS10
    DDR_B_BS2 DDR_B_DQS#0 27 28
    <7> DDR_B_BS2 DQS#1 DM1
    DDR_B_WE# DDR_B_DQS0 29 30 DDR_DRAMRST#
    <7> DDR_B_WE# DQS1 RESET# DDR_DRAMRST# <7,18>
    From CPU
    DDR_B_CAS# 31 32
    <7> DDR_B_CAS# VSS11 VSS12

    0.1U_0402_25V6K
    DDR_B_RAS# DDR_B_D3 33 34 DDR_B_D2 1
    <7> DDR_B_RAS# DQ10 DQ14

    CD30
    DDR_B_D6 35 36 DDR_B_D7 @
    37 DQ11 DQ15 38
    DDR_B_CLK0 DDR_B_D17 39 VSS13 VSS14 40 DDR_B_D21
    <7> DDR_B_CLK0 DQ16 DQ20 2
    DDR_B_CLK#0 Clock Signals from CPU DDR_B_D16 41 42 DDR_B_D20
    <7> DDR_B_CLK#0 DQ17 DQ21
    DDR_B_CLK1 43 44
    <7> DDR_B_CLK1 VSS15 VSS16
    DDR_B_CLK#1 DDR_B_DQS#2 45 46
    <7> DDR_B_CLK#1 DDR_B_DQS2 47 DQS#2 DM2 48
    49 DQS2 VSS17 50 DDR_B_D19
    DDR_B_CKE0 DDR_B_D18 51 VSS18 DQ22 52 DDR_B_D23
    <7> DDR_B_CKE0 DQ18 DQ23 CAD NOTE
    DDR_B_CKE1 CTL Signals from CPU DDR_B_D22 53 54 PLACE THE CAP NEAR TO
    <7> DDR_B_CKE1 DQ19 VSS19
    DDR_B_CS#0 55 56 DDR_B_D25
    <7> DDR_B_CS#0
    DDR_B_CS#1 DDR_B_D24 57 VSS20 DQ28 58 DDR_B_D28 DIMM RESET PIN
    <7> DDR_B_CS#1 DQ24 DQ29
    DDR_B_D29 59 60
    61 DQ25 VSS21 62 DDR_B_DQS#3
    PCH_SMBCLK SMBUS Signals link to CPU 63 VSS22 DQS#3 64 DDR_B_DQS3
    <8,18> PCH_SMBCLK DM3 DQS3
    PCH_SMBDAT 65 66
    <8,18> PCH_SMBDAT VSS23 VSS24
    DDR_B_D27 67 68 DDR_B_D30
    DDR_B_D26 69 DQ26 DQ30 70 DDR_B_D31
    DDR_B_ODT0 71 DQ27 DQ31 72 +1.35V_VDDQ
    <7> DDR_B_ODT0 VSS25 VSS26
    DDR_B_ODT1 From SOC ODT Signals to CH B
    <7> DDR_B_ODT1 +1.35V_VDDQ +1.35V_VDDQ

    1
    1.8K_0402_1%
    RD13
    DDR_B_CKE0 73 74 DDR_B_CKE1
    75 CKE0 CKE1 76
    Layout Note: VDD1 VDD2 +0.675V_DDRB_VREFDQ +0.675V_B_VREFDQ
    77 78 DDR_B_MA15
    Place near JDIMM2 DDR_B_BS2 79 NC1 A15 80 DDR_B_MA14

    2
    2 81 BA2 A14 82 2
    DDR_B_MA12 83 VDD3 VDD4 84 DDR_B_MA11 RD14 1 2
    DDR_B_MA9 85 A12/BC# A11 86 DDR_B_MA7 2_0402_1%
    A9 A7 1
    87 88
    DDR_B_MA8 89 VDD5 VDD6 90 DDR_B_MA6 CD31
    A8 A6

    1
    +1.35V_VDDQ

    1.8K_0402_1%
    DDR_B_MA5 91 92 DDR_B_MA4 0.022U_0402_16V7K
    A5 A4 2

    RD15
    93 94
    DDR_B_MA3 95 VDD7 VDD8 96 DDR_B_MA2
    A3 A2

    1
    1U_0402_6.3V6K

    1U_0402_6.3V6K

    1U_0402_6.3V6K

    1U_0402_6.3V6K

    1U_0402_6.3V6K

    1U_0402_6.3V6K

    DDR_B_MA1 97 98 DDR_B_MA0
    @1 @1 @1 @1 99 A1 A0 100 RD16
    1 1

    2
    DDR_B_CLK0 101 VDD9 VDD10 102 DDR_B_CLK1
    CK0 CK1 24.9_0402_1%
    CD32

    CD33

    CD34

    CD35

    CD36

    CD37

    DDR_B_CLK#0 103 104 DDR_B_CLK#1


    105 CK0# CK1# 106

    2
    2 2 2 2 2 2 DDR_B_MA10 107 VDD11 VDD12 108 DDR_B_BS1
    DDR_B_BS0 109 A10/AP BA1 110 DDR_B_RAS#
    111 BA0 RAS# 112
    DDR_B_WE# 113 VDD13 VDD14 114 DDR_B_CS#0
    DDR_B_CAS# 115 WE# S0# 116 DDR_B_ODT0
    Place near to SO-DIMM connector.
    117 CAS# ODT0 118
    DDR_B_MA13 119 VDD15 VDD16 120 DDR_B_ODT1
    DDR_B_CS#1 121 A13 ODT1 122 +0.675V_DDRB_VREFCA +0.675V_DDR_VREFCA
    +1.35V_VDDQ 123 S1# NC2 124
    VDD17 VDD18 10mils
    125 126 RD17 1 2 0_0402_5%
    127 NCTEST VREF_CA 128
    VSS27 VSS28
    10U_0603_6.3V6M

    10U_0603_6.3V6M

    10U_0603_6.3V6M

    10U_0603_6.3V6M

    10U_0603_6.3V6M

    10U_0603_6.3V6M

    10U_0603_6.3V6M

    10U_0603_6.3V6M

    0.1U_0402_25V6K
    DDR_B_D36 129 130 DDR_B_D37
    DQ32 DQ36

    2.2U_0402_6.3V6M
    DDR_B_D33 131 132 DDR_B_D32
    DQ33 DQ37
    330U_D3_2.5VY_R6M

    1 133 134 1
    VSS29 VSS30

    CD48
    1 1 @1 1 1 @1 1 1 @ DDR_B_DQS#4 135 136
    DQS#4 DM4
    CD38

    CD39

    CD40

    CD41

    CD42

    CD43

    CD44

    CD45

    CD46

    CD47
    DDR_B_DQS4 137 138
    139 DQS4 VSS31 140 DDR_B_D35 @

    2
    DDR_B_D39 141 VSS32 DQ38 142 DDR_B_D38 2
    2 2 2 2 2 2 2 2 2 DDR_B_D34 143 DQ34 DQ39 144
    3 145 DQ35 VSS33 146 DDR_B_D45 3
    DDR_B_D41 147 VSS34 DQ44 148 DDR_B_D40
    DDR_B_D44 149 DQ40 DQ45 150
    151 DQ41 VSS35 152 DDR_B_DQS#5
    153 VSS36 DQS#5 154 DDR_B_DQS5
    155 DM5 DQS5 156
    DDR_B_D43 157 VSS37 VSS38 158 DDR_B_D47 +1.35V_VDDQ
    DDR_B_D42 159 DQ42 DQ46 160 DDR_B_D46
    161 DQ43 DQ47 162
    VSS39 VSS40

    1
    1.8K_0402_1%
    Layout Note: Layout Note: DDR_B_D49 163 164 DDR_B_D52
    DQ48 DQ52

    RD18
    DDR_B_D48 165 166 DDR_B_D53
    Place near JDIMM2.203,204 Place near JDIMM2.199 167 DQ49 DQ53 168
    DDR_B_DQS#6 169 VSS41 VSS42 170 +0.675V_DDR_VREFCA +0.675V_VREFCA
    DDR_B_DQS6 171 DQS#6 DM6 172

    2
    173 DQS6 VSS43 174 DDR_B_D54
    DDR_B_D55 175 VSS44 DQ54 176 DDR_B_D51 RD19 1 2
    DDR_B_D50 177 DQ50 DQ55 178 2_0402_1%
    DQ51 VSS45 1
    +0.675VS_VTT +3VS 179 180 DDR_B_D61
    DDR_B_D56 181 VSS46 DQ60 182 DDR_B_D60 CD49
    DQ56 DQ61

    1
    1.8K_0402_1%
    DDR_B_D57 183 184 0.022U_0402_16V7K
    DQ57 VSS47 2

    RD20
    185 186 DDR_B_DQS#7
    VSS48 DQS#7
    0.1U_0402_25V6K

    0.1U_0402_25V6K

    1U_0402_6.3V6K

    1U_0402_6.3V6K

    0.1U_0402_25V6K

    2.2U_0402_6.3V6M

    187 188 DDR_B_DQS7


    DM7 DQS7

    1
    @1 @1 1 1 1 189 190
    VSS49 VSS50
    1
    CD50

    CD51

    CD54

    DDR_B_D59 191 192 DDR_B_D63 RD21

    2
    DQ58 DQ62
    CD52

    CD53

    CD55

    DDR_B_D58 193 194 DDR_B_D62 24.9_0402_1%


    @ +0.675VS_VTT +3VS 195 DQ59 DQ63 196 +0.675VS_VTT
    2

    2 2 2 2 2 DDR_B_SA0 197 VSS51 VSS52 198

    2
    199 SA0 EVENT# 200 PCH_SMBDAT
    DDR_B_SA1 201 VDDSPD SDA 202 PCH_SMBCLK
    +0.675VS_VTT 203 SA1 SCL 204 +0.675VS_VTT
    VTT1 VTT2
    205 206
    4 G1 G2 Place near to SO-DIMM connector. 4
    FOX_AS0A626-U4SN-7F
    CONN@

    +3VS
    Address : 01
    SP07000H800
    Interleaved Memory
    DDR_B_SA1 Security Classification
    2014/05/19
    Compal Secret Data
    2015/12/31 Title
    Compal Electronics, Inc.
    DDR_B_SA0
    Issued Date Deciphered Date
    THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
    DDR3L_DIMMB
    AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&DSize Document Number Rev
    DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS Custom 0.2
    MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC. LA-C071P
    Date: Tuesday, July 28, 2015 Sheet 19 of 55
    A B C D E
    5 4 3 2 1

    Main Func : Screw

    Screw Hole
    H1 H20 H21 H22 Vinafix.com
    H23
    H_2P8N H_2P8N H_2P8N H_2P8X3P3N H_2P8X4P8N
    D @ @ @ @ @ D
    1

    1
    H2 H3 H4 H5 H6 H7 H8 H9
    H_2P8 H_2P8 H_2P8 H_2P8 H_2P8 H_2P8 H_2P8-G H_2P8
    @ @ @ @ @ @ @ @
    1

    1
    H10 Delete.
    Layout informed PCB vendor to do PTH solution.
    ( Function is same as beofre.)

    H11 H12
    H_2P8 H_2P8
    @ @
    1

    H13 H14 H15 H16


    H_3P6-G H_3P6-G H_3P6-G H_3P6-G

    C
    @ @ @ @ CPU bracket C
    1

    H17 H18
    H_3P3-G H_3P3-G
    @ @ VGA stand-off
    1

    H19
    H_3P3
    @ NGFF stand-off
    1

    FD1 FD2 FD3 FD4


    @ FIDUCAL @ FIDUCIAL @ FIDUCAL @ FIDUCIAL
    1

    B B

    Main Func : RTC RTC_DET# <9>

    1
    D
    2 QC4
    G 2N7002K_SOT23-3

    1
    S
    RC400

    3
    10M_0402_5%

    RTC Battery

    2
    +3VALW +3VL_RTC

    W=20mils MAX. 8000mil 2 1


    +RTCBATT DC1 DC8 RB551V-30_SOD323-2
    1 2 2
    RC192 1K_0402_5% W=20mils
    1
    +3VLP
    W=20mils 3

    BAT54C-7-F_SOT23-3 1 1
    CC84 CC79
    1U_0402_6.3V6K 0.1U_0201_10V6K
    2 2
    A A
    CC79.CC84 Close UC1.AK19.

    Security Classification Compal Secret Data Compal Electronics, Inc.


    Issued Date 2014/04/01 Deciphered Date 2015/04/30 Title

    THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
    Screw Hole
    Size
    AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D Document Number Rev
    DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS 0.1
    MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC. LA-B015P
    Date: Tuesday, July 28, 2015 Sheet 20 of 55
    5 4 3 2 1
    5 4 3 2 1

    Main Func : Audio


    +3VS +3VS +5VS +5VA Reserve for HDA issue
    +CODEC_AVDD2 +1.8VS
    CPVDD RA1111 2 @ 1 0_0805_5%
    1 1 1 1 1 1 0_0402_5% 2 1 RA8
    1
    CA59 CA60 CA58
    Vinafix.com
    CA57 CA51 CA71

    4.7U_0603_6.3V6K

    0.1U_0402_16V7K

    0.1U_0402_16V7K

    4.7U_0603_6.3V6K

    0.1U_0402_16V7K

    4.7U_0603_6.3V6K
    CA61
    2 2 2 2 2 2

    4.7U_0603_6.3V6K
    2 +5V_PVDD +5VS
    D D
    1 @ 2
    1 1 1 1 RA1110 0_0805_5%

    CA54 CA53 CA56 CA55

    0.1U_0402_16V7K

    4.7U_0603_6.3V6K

    0.1U_0402_16V7K

    4.7U_0603_6.3V6K
    2 2 2 2
    For Pin9 , Pin36 For Pin1 For Pin26

    UA1
    1 26
    DVDD AVDD1 40
    9 AVDD2
    DVDD-IO
    1 @EMI@ 2 1 2 @EMI@ 36 CPVDD For Pin41 For Pin46
    RA1112 0_0402_5% CA21 22P_0402_50V8J CPVDD 41
    6 PVDD1 46
    <12> HDA_CODEC_BITCLK BCLK PVDD2 +3VS
    5
    <12> HDA_CODEC_SDOUT SDATA-OUT
    HP/LINE1 JD(JD1)
    13 JACK_SENSE# RA13 1 2 100K_0402_5% Trace width for SPK-L+/SPK-L-/SPK-R+/SPK-R-
    10 14
    <12> HDA_CODEC_SYNC SYNC MIC2/LINE2 JD(JD2)
    SPDIFO/FRONT JD(JD3)/GPIO3
    15 RA4 2 1 200K_0402_5% JACK_PLUG# Speaker 4 ohm : 40mil
    1 2 HDA_CODEC_SDIN0 8
    <12> HDA_SDIN0
    RA130 33_0402_5% SDATA-IN Speaker 8 ohm : 20mil
    <12> HDA_CODEC_RST# 11 JSPK
    RESETB 32 HPOUT-L INT-SPK-R- LA3 1 EMI@ 2 BLM15PD800SN1D SPK_R1-_CONN 1
    HPOUT-L(PORT-I-L) 33 HPOUT-R INT-SPK-R+ LA4 1 EMI@ 2 BLM15PD800SN1D SPK_R2+_CONN 2 1
    LINE1-R 21 HPOUT-R(PORT-I-R) INT-SPK-L- LA5 1 EMI@ 2 BLM15PD800SN1D SPK_L1-_CONN 3 2
    LINE1-L 22 LINE1-R(PORT-C-R) INT-SPK-L+ LA6 1 EMI@ 2 BLM15PD800SN1D SPK_L2+_CONN 4 3
    Line1-VREFO-R 30 LINE1-L(PORT-C-L) 5 4
    LINE1-VREFO-R G1

    3
    CA29 1000P_0402_50V7K

    CA30 1000P_0402_50V7K

    CA31 1000P_0402_50V7K

    CA32 1000P_0402_50V7K
    Line1-VREFO-L 31 42 INT-SPK-L+ 6
    LINE1-VREFO-L SPK-OUT-L+ Close to UA1 1 1 1 1 G2

    AZ5125-02S.R7G_SOT23-3
    DA13

    AZ5125-02S.R7G_SOT23-3
    DA14
    23 43 INT-SPK-L-
    LINE2-R(PORT-E-R) SPK-OUT-L-
    C
    +3VL_RTC +3VALW +MIC2-VREFO
    24
    LINE2-L(PORT-E-L) SPK-OUT-R+
    45
    44
    INT-SPK-R+
    INT-SPK-R-
    Pin11,13,14,16 ACES_50278-00401-001
    CONN@
    C

    SPK-OUT-R- 2 2 2 2

    ESD@

    ESD@
    AUD_PC_BEEP 1 3246@ 2MONO_PC_BEEP_R 16
    MONO-OUT
    1

    EMI@

    EMI@

    EMI@

    EMI@
    0_0402_5% RA1114
    RA11 RA10 2 A_MIC_DATA <25>
    0_0402_5% 29 GPIO0/DMIC-DATA 3 MIC_CLK_C LA1 1 2 EMI@ A_MIC_CLK
    0_0402_5% A_MIC_CLK <25>

    1
    AGND was requested RING2 17 MIC2-VREFO GPIO1/DMIC-CLK 48 BLM15PX221SN1D_2P
    @ MIC2-L(PORT-F-L)/RING SPDIF-OUT/GPIO2 1
    by Realtek SLEEVE 18 CA22
    2

    2 1 MIC1-L 19 MIC2-R(PORT-F-R)/SLEEVE 22P_0402_50V8J


    +A_VCC CA74 10U_0603_6.3V6M MIC_CAP 37 @EMI@
    CBP 35 2 1 2
    20 CBN CA24 1U_0402_6.3V6K
    NC DA8
    EC_MUTE# 47 CA23 2 1 2.2U_0603_6.3V6K 2
    <23> EC_MUTE# PDB 28 RA79
    BEEP <23> EC Beep
    +3VS RA12 1 2 100K_0402_5% VREF 12 AUD_PC_BEEP_R 1 3234@
    @ 2 AUD_PC_BEEP 1 2 1 2 PC_BEEP 1
    CA62 1 2 10U_0603_6.3V6M 27 PCBEEP 34 0_0402_1% RA1115 CA65 0.1U_0402_16V7K
    1 @ 2 CA63 1 2 10U_0603_6.3V6M 39 LDO1-CAP CPVEE 1K_0402_1% 3
    100K_0402_5% RA14 CA64 1 2 10U_0603_6.3V6M 7 LDO2-CAP SPKR <12> MCU Beep
    LDO3-CAP CA25 2 1 1U_0402_6.3V6K BAT54C-7-F_SOT23-3

    1
    1
    1 3234@
    @ 2 4 25 RA81 CA69 RA19
    0_0402_1% RA1113 DVSS AVSS1 38 10K_0402_5%
    AVSS2 1K_0402_1% 100P_0402_50V8J
    49 @
    GND 2@

    2
    ALC3234-CG_MQFN48_6X6

    B B

    +MIC2-VREFO
    2

    Line1-VREFO-R RA166 1 2 4.7K_0402_5%


    Line1-VREFO-L RA165 1 2 4.7K_0402_5% RA1109 RA53
    2.2K_0402_5% 2.2K_0402_5%

    LINE1-L 1 2 RA80 1 2 1K_0402_1%


    1

    CA67 4.7U_0603_6.3V6K
    LINE1-R 1 2 RA82 1 2 1K_0402_1% JHP
    CA68 4.7U_0603_6.3V6K EMI@ RING2_R 3
    SLEEVE LA7 2 1 BLM15PX330SN1D 0402 40mil MIC_IN_R AUD_HP_OUT_L_CN 1
    EMI@
    RA55 RING2 LA10 2 1 BLM15PX330SN1D 0402 40mil RING2_R
    10_0402_1% EMI@ JACK_PLUG# 5
    HPOUT-L 1 2 Line-IN-L LA8 2 1 BLM15PD800SN1D AUD_HP_OUT_L_CN
    EMI@ 6
    HPOUT-R 1 2 Line-IN-R LA9 2 1 BLM15PD800SN1D AUD_HP_OUT_R_CN
    10_0402_1% AUD_HP_OUT_R_CN 2
    CA33

    CA39

    CA38

    CA40

    RA56
    1

    1 1 1 1 MIC_IN_R 4
    AZ5125-02S.R7G_SOT23-3
    DA10

    AZ5123-02S.R7G_SOT23-3
    DA12

    RA84 RA83 7
    10K_0402_5% 10K_0402_5%
    100P_0402_50V8J

    100P_0402_50V8J

    1000P_0402_50V7K

    1000P_0402_50V7K

    @ @ SINGA_2SJ3080-001111F
    2 2 2 2 CONN@
    2

    EMI@

    EMI@

    EMI@

    EMI@

    ESD@

    ESD@

    RA29 1 @ 2 0_0402_1%
    iPhone and Nokia type Combo Jack
    1

    A RA30 1 @ 2 0_0402_1% A

    RA31 1 @ 2 0_0402_1%

    RA32 1 @ 2 0_0402_1%

    GNDA GND
    Security Classification Compal Secret Data Compal Electronics, Inc.
    Issued Date 2014/04/01 Deciphered Date 2015/04/30 Title
    Place on the moat between GND & GNDA. Audio Codec ALC3234
    THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
    AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&DSize Document Number Rev
    DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS 0.1
    MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC. LA-B015P
    Date: Tuesday, July 28, 2015 Sheet 21 of 55
    5 4 3 2 1
    1 2 3 4 5

    Main Func : 10/100 LAN


    60mils_3via 40mils_2via
    +LAN_VDD33 rising time : >1ms and <100ms +LAN_REGOUT
    RL1 2
    LAN_L@
    1 0_0603_5%
    +LAN_VDD10

    LAN_SW@
    +3VALW +LAN_VDD33 LL1 1 2
    W=40mils W=40mils
    Vinafix.com2
    JP3 @
    1
    1.5A 1 2.2UH_LQM2MPN2R2NG0L_30% 1
    CL4 CL5
    1
    CL6
    1
    CL7
    1
    CL8
    1
    CL9
    1

    1 1 1 CL3

    LAN_SW@
    4.7U_0603_6.3V6K

    0.1U_0402_25V6

    0.1U_0402_25V6

    0.1U_0402_25V6

    0.1U_0402_25V6

    1U_0402_6.3V4Z
    A 2MM 0.1U_0402_25V6 A
    CL39 CL15 CL19 LAN_L@ 2 2 2 2 2 2 2
    1U_0402_6.3V6K UL3 0.1U_0402_10V7K 0.1U_0402_10V7K
    2 5 1 2 2
    IN OUT +3VALW
    2
    GND RL40
    4 3 2 1
    <23> LAN_EN EN OC

    2
    10K_0402_5%
    RL27 SY6288C20AAC_SOT23-5 RTL8111G(LDO mode) RTL8111GS(SWR mode) Place close to each VDD10 pin
    100K_0402_5%

    1
    +LAN_VDD33 +LAN_VDDREG
    @
    RL6 1 2 0_0603_5%
    1 1 1 2 1
    @ @
    CL12 CL13 CL14 CL16 CL17

    0.1U_0402_16V7K

    4.7U_0603_6.3V6K

    10U_0603_6.3V6M

    0.1U_0402_16V7K

    4.7U_0603_6.3V6K
    2 2 2 1 2

    B B
    These caps close to UL1: Pin 11,32
    +LAN_VDD33 Rising time (10%~90%)要>1mS and <100mS
    +LAN_VDD10
    CL30, CL31 close to UL1 Pin 17, 18 UL1

    <10> PCIE_PRX_LANTX_P6 CL30 1 2 0.1U_0402_10V7K PCIE_PRX_LANTX_P3_C 17 3


    CL31 1 2 0.1U_0402_10V7K PCIE_PRX_LANTX_N3_C 18 HSOP AVDD10 8 +LAN_VDD33
    <10> PCIE_PRX_LANTX_N6 HSON AVDD10 30 TL2 @
    AVDD10 22
    DVDD10 +LAN_VDDREG MDI1- 1 16 MDO1-
    MDI1+ 2 RD+ RX+ 15 MDO1+
    11 3 RD- RX- 14 MCT0
    AVDD33 32 +LAN_REGOUT 4 CT CT 13
    PCIE_PTX_LANRX_P6_C 13 AVDD33 5 NC NC 12
    <10> PCIE_PTX_LANRX_P6_C HSIP 2 NC NC
    PCIE_PTX_LANRX_N6_C 14 23 6 11 MCT1
    <10> PCIE_PTX_LANRX_N6_C HSIN VDDREG CT CT
    24 CL41 MDI0- 7 10 MDO0-
    REGOUT TD+ TX+

    1
    0.01U_0402_16V7K MDI0+ 8 9 MDO0+
    1 MDI0+ 1 TD- TX- RL20 RL19
    MDIP0 2 MDI0- 75_0603_5% 75_0603_5%
    MDIN0 4 MDI1+ 350UH_LF-H1201P-2
    +3VS 19 MDIP1 5 MDI1- TL2
    <11,23,25,28,45> PLT_RST#

    2
    PERSTB MDIN1
    RL33 1 2 1K_0402_5% ISOLATEB 20 15 1
    ISOLATEB REFCLK_P CLK_PCIE_LAN_P2 <11>
    RL35 1 2 15K_0402_5% 16 CL33
    REFCLK_N CLK_PCIE_LAN_N2 <11>
    100P_1206_2KV8J
    <11,23,28> PCIE_WAKE# 21 12 EMI@
    LANWAKEB CLKREQB CLK_PCIE_LAN_REQ# <11> 2
    28 S X'FORM_ NS0015 LF LAN
    C +LAN_VDD33 26 CKXTAL1 29 C
    LED1/GPO CKXTAL2 XTLO XTAL@ 2 1 SP050005Y00

    6 LED2
    25
    27
    CL37 12P_0402_50V8J Place close to TCT pin
    RL39 1 @ 2 10K_0402_5% 7 NC LED0 YL2 XTAL@
    9 NC 31 3 4
    10 NC RSET OSC GND
    NC
    2

    33 1 2
    GND RL31 OSC GND

    RTL8106E-CG QFN 32P E-LAN CTRL 2.49K_0402_1% 25MHZ_10PF_7V25000014 JLAN CONN@

    XTLI XTAL@ 2 1 8
    1

    CL36 12P_0402_50V8J PR4-


    7
    PR4+
    MDO1- 6
    PR2-
    5
    PR3-
    4
    PR3+
    MDO1+ 3
    PR2+
    MDO0- 2
    PR1-
    MDO0+ 1
    PR1+
    9
    GND
    D D
    10
    GND

    Security Classification Compal Secret Data Compal Electronics, Inc.


    Title
    Issued Date 2014/04/01 Deciphered Date 2015/04/30
    THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
    Size Document Number
    10/100 LAN Rev
    AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
    DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS Custom 0.1
    MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.
    Date:
    LA-B015P
    Tuesday, July 28, 2015 Sheet 22 of 55
    1 2 3 4 5
    5 4 3 2 1

    Main Func : EC +3VALW +3VALW_EC


    RE343 EC@
    SD034100280
    SD034137280
    10K_0402_1%
    13.7K_0402_1%
    +3VALW_EC +3VALW_EC

    @ SD034178280 17.8K_0402_1% Model ID Board ID

    1
    2 1 SD034221280 22.1K_0402_1%
    RE342 0_0603_5% SD034270280 27K_0402_1% R2452

    10U_0603_6.3V6M

    0.1U_0402_10V7K

    1000P_0402_50V7K
    @EMI@

    1000P_0402_50V7K
    @EMI@

    0.1U_0402_25V6

    0.1U_0402_25V6

    0.1U_0402_25V6

    0.1U_0402_25V6

    0.1U_0402_25V6
    1 1 2 2 SD034324280 32.4K_0402_1% Rc 10K_0402_5% Ra RE343

    1
    SD034374280 37.4K_0402_1% DIS@ 27K_0402_1%
    +3VALW

    CE62

    CE63

    CE66

    CE67

    CE68

    CE69

    CE70
    27K_0402_1% SD034499280 49.9K_0402_1% @

    2
    SD034576280 57.6K_0402_1% MODEL_ID BOARD_ID

    2
    2 2 1 1 SD034649280 64.9K_0402_1%
    SD034270280

    CE64

    CE65
    5 4 KSI0 SD00000B180 73.2K_0402_1% 1 1

    2
    0.1U_0402_10V7K
    C5230

    0.1U_0402_10V7K
    CE71
    6 3 KSI1 SD000002780 82.5K_0402_1%
    7
    8
    RPE1
    2
    1
    KSI2
    KSI3
    10K_8P4R_5%
    Vinafix.com RE343 For
    SD034931280

    Board ID Select SD034107380


    93.1K_0402_1%

    107K_0402_1% 2
    Rd
    R2453
    100K_0402_1% 2
    Rb
    RE344
    100K_0402_1%
    SD034120380 120K_0402_1% UMA@

    1
    D 5 4 KSI4 +3VL_RTC +3VALW_EC SD034137380 137K_0402_1% D
    6 3 KSI5 @ SD034154380 154K_0402_1%
    7 2 KSI6 2 1 +3VL_RTC_VBAT 2 1 SD034200380 200K_0402_1%
    8 1 KSI7 RE345 0_0603_5% 1 RE346 0_0402_5% EC_AGND EC_AGND
    SD034232380 232K_0402_1%
    RPE2 10K_8P4R_5% CE72
    0.1U_0402_10V7K
    1 8 KSO0 RE350 NDSX@ RE351 NDSX@
    2 7 KSO1 2

    122

    103
    3 6 KSO2

    43
    82

    19
    65
    5
    4 5 KSO3 UE5
    RPE3 100K_8P4R_5% 54 1 2

    VBAT

    VTR
    VTR
    VTR
    VTR
    VTR
    VTR
    VTR_33_18 CE73 0.1U_0402_25V6
    1 8 KSO4 PECI_EC 1K_0402_5% 1K_0402_5% +3VALW_EC
    PECI_EC <12>
    2 7 KSO5 KSO0 2 SD028100180 SD028100180
    GPIO027/KSO00/PVT_IO1

    1
    3 6 KSO6 KSO1 14 8 PBAT_CHG_SMBDAT
    GPIO015/KSO01/PVT_nCS GPIO007/SMB01_DATA/SMB01_DATA18 PBAT_CHG_SMBDAT <34,35>
    4 5 KSO7 KSO2 15 9 PBAT_CHG_SMBCLK PBAT_CHG_SMBDAT 4.7K_0402_5% 1 2 RE347
    GPIO016/KSO02/PVT_SCLK GPIO010/SMB01_CLK/SMB01_CLK18 PBAT_CHG_SMBCLK <34,35>
    RPE4 100K_8P4R_5% KSO3 16 11 GPU_THM_SMBDAT PBAT_CHG_SMBCLK 4.7K_0402_5% 1 2 RE349
    GPIO017/KSO03/PVT_IO0 GPIO012/SMB02_DATA/SMB02_DATA18 GPU_THM_SMBDAT <8,30,48>
    KSO4 37 12 GPU_THM_SMBCLK DE3 GPU_THM_SMBDAT 2.2K_0402_5% 1 DSX@ 2 RE350
    GPIO045/BCM_nINT1/KSO04 GPIO013/SMB02_CLK/SMB02_CLK18 GPU_THM_SMBCLK <8,30,48>
    1 8 KSO10 KSO5 38 89 AZ5125-01H.R7G_SOD523-2 GPU_THM_SMBCLK 2.2K_0402_5% 1 DSX@ 2 RE351
    GPIO046/BCM_DAT1/KSO05 GPIO130/SMB03_DATA/SMB03_DATA18 SYS_PWROK <11>
    2 7 KSO11 <29> KSI[0..7] KSO6 39 91 L_BKLT_EN_EC <6> @ PCIE_WAKE# 10K_0402_5% 2 1 RE352
    3 6 KSO12 KSO7 50 GPIO047/BCM_CLK1/KSO06 GPIO131/SMB03_CLK/SMB03_CLK18 96 TOUCHPAD_INTR# 100K_0402_5% 1 2 RE354
    GPIO025/KSO07/PVT_IO2 GPIO141/SMB04_DATA/SMB04_DATA18 SIO_SLP_SUS# <11,17,38,39>
    4 5 KSO13 KSO8 46 97 PBAT_PRES#
    <29> KSO[0..16] PBAT_PRES# <34,35>

    2
    RPE5 100K_8P4R_5% KSO9 68 GPIO055/PWM2/KSO08/PVT_IO3 GPIO142/SMB04_CLK/SMB04_CLK18 RE353 1 2 10K_0402_5% RESET_OUT# 10K_0402_5% 1 @ 2 RE355
    GPIO102/KSO09/CR_STRAP +3VS 1
    KSO10 72 40 FAN1_TACH FAN1_TACH <30> ME_FWP_EC 1K_0402_5% 1 @ 2 RE357
    1 8 KSO8 KSO11 74 GPIO106/KSO10 GPIO050/TACH0 41 LID_CL_SIO# CE74 PCH_RSMRST# 10K_0402_5% 1 2 RE359
    2 7 KSO15 KSO12 75 GPIO110/KSO11 GPIO051/TACH1
    GPIO111/KSO12 100P_0402_50V8J
    3 6 KSO14 KSO13 76 44 2
    4 5 KSO16 KSO14 77 GPIO112/PS2_CLK1A/KSO13 MEC1404 GPIO053/PWM0 45
    KB_LED_PWM <29>
    GPIO113/PS2_DAT1A/KSO14 GPIO054/PWM1 BEEP <21>
    RPE6 100K_8P4R_5% KSO15 86 Reserve to Control 3D Camera
    KSO16 92 GPIO125/KSO15 47
    GPIO132/KSO16 GPIO056/PWM3 GC6_THM_DIS# <10>
    RE348 2 1 100K_0402_5% KSO9 93 34 3D_CAM_EN_EC 1 2 3D_CAM_EN <9,33>
    <29> CAP_LED# GPIO140/KSO17 GPIO030/BCM_nINT0/PWM4 SUSACK# <11> RB551V-30_SOD323-2
    RE356 2 1 100K_0402_5% USB_EN# 35 DX7
    GPIO031/BCM_DAT0/PWM5 EC_WAKE# <11>
    RE358 2 1 100K_0402_5% BAT1_LED# KSI0 98 36 PS_ID <34>
    RE360 2 1 100K_0402_5% BAT2_LED# KSI1 99 GPIO143/KSI0/nDTR GPIO032/BCM_CLK0/PWM6 4 PCIE_WAKE# FW_UPDATE_EC 1 2
    GPIO144/KSI1/nDCD GPIO002/PWM7 PCIE_WAKE# <11,22,28> FW_UPDATE <9,33>
    RE361 2 1 100K_0402_5% PCH_ALW_ON KSI2 6 RB551V-30_SOD323-2 DX8
    KSI3 7 GPIO005/SMB00_DATA/SMB00_DATA18/KSI2 1 BAT1_LED#
    GPIO006/SMB00_CLK/SMB00_CLK18/KSI3 GPIO157/LED0/TST_CLK_OUT BAT1_LED# <31>
    KSI4 104 106 BAT2_LED#
    GPIO147/KSI4/nDSR GPIO156/LED1 BAT2_LED# <31> +1.0V_PRIM
    C KSI5 105 70 SIO_SLP_S3# SIO_SLP_S3# <11,16,32,34,41> C
    KSI6 107 GPIO150/KSI5/nRI GPIO104/LED2
    KSI7 108 GPIO151/KSI6/nRTS 80 ME_FWP_EC VREF_CPU +3VALW
    GPIO152/KSI7/nCTS GPIO116/TFDP_DATA/UART_RX ME_FWP_EC <12>
    81 HOST_DEBUG_TX
    GPIO117/TFDP_CLK/UART_TX HOST_DEBUG_TX <28>

    1
    78 CE75
    <29> CLK_TP_SIO GPIO114/PS2_CLK0

    1
    <29> DAT_TP_SIO 79 90 PTP_DIS#_R RE362 2 1 0_0402_5% PTP_DIS# 0.1U_0402_25V6
    GPIO115/PS2_DAT0 GPIO035/SB-TSI_CLK PTP_DIS# <29>
    52 94 PECI_MEC1404 RE364 1 2 43_0402_1% PECI_EC
    <11> SIO_PWRBTN#

    2
    PCH_RSMRST# 88 GPIO026/PS2_CLK1B GPIO033/PECI_DAT/SB_TSI_DAT RE363
    <11> PCH_RSMRST# GPIO127/PS2_DAT1B 95 VREF_CPU 10K_0402_5%
    LPC_LAD0 59 VREF_CPU
    <8> LPC_LAD0

    2
    LPC_LAD1 60 GPIO040/LAD0 101 ICSP_CLK RE365 2 @ 1 0_0402_5% EC_MUTE# LID_CL_SIO# 2 1
    <8> LPC_LAD1 GPIO041/LAD1 GPIO145/ICSP_CLOCK LID_CLOSE# <25,31>
    LPC_LAD2 61 102 ICSP_DAT RE367 2 @ 1 0_0402_5% PTP_DIS# RE366 10_0402_5%
    <8> LPC_LAD2 GPIO042/LAD2 GPIO146/ICSP_DATA +3VLP
    LPC_LAD3 62 87 ICSP_CLR
    <8> LPC_LAD3 GPIO043/LAD3 ICSP_MCLR

    1
    <8> LPC_LFRAME# LPC_LFRAME# 58 CE77
    PCH_PLTRST#_EC 56 GPIO044/nLFRAME 119 EC_MUTE#_R RE368 2 1 0_0402_5% EC_MUTE# 1K_0402_5% 1 2 RE369 0.047U_0402_16V4Z
    <11,22,23,25,28,45> PCH_PLTRST#_EC GPIO064/nLRESET BGPO/GPIO004 EC_MUTE# <21>
    <8> CLK_PCI_LPC_MEC 57 120 100K_0402_5% 1 2 RE371 @

    2
    63 GPIO034/PCI_CLK SYSPWR_PRES/GPIO003 121
    <8> CLKRUN# GPIO067/nCLKRUN VCI_OUT/GPIO036 ALWON <36>
    @EMI@ 2 1 1 @EMI@ 2 55 126 VCI_IN1
    <8> SERIRQ GPIO063/SER_IRQ nVCI_IN1/GPIO162
    0.1U_0402_10V7K CE76 0_0402_5% R2454 10 127 POWER_SW_IN#
    <6> SIO_EXT_SMI# GPIO011/nSMI/nEMI_INT nVCI_IN0/GPIO163 +3VL_RTC
    49 128 ACAV_IN <11,35>
    <29> TP_PW_EN# GPIO060/KBRST VCI_OVRD_IN/GPIO164
    53
    <8> SIO_RCIN# GPIO061/nLPCPD +3VALW_EC
    66 23 3D_CAM_EN_EC VCI_IN1 1 2
    <10> SIO_EXT_SCI# GPIO100/nEC_SCI GPIO160/DAC_0 24 RE370 100K_0402_5%
    GPIO161/DAC_1 FAN1_DAC_1 <30>
    <8> EC_SPICLK_R RE372 1 2 15_0402_1% EC_SPI_CLK 32 22 +3VL_RTC
    RE373 1 2 15_0402_1% EC_SPI_MOSI 28 GPIO126/SHD_SCLK DAC_VREF
    <8> EC_MOSI_R GPIO133/SHD_IO0

    1
    <8> EC_MISO_R RE374 1 2 15_0402_1% EC_SPI_MISO 29 85 CMP_VOUT0 CE78
    GPIO134/SHD_IO1 GPIO124/CMP_VOUT0 CMP_VOUT0 <36,48>

    1
    <10,31> SATA_LED# R2455 1 @ 2 0_0402_5% SATA_LED#_R 30 20 CMP_VIN0 1 2 VCIN0_PH <30> 0.1U_0402_25V6
    R2460 1 @ 2 0_0402_5% 31 GPIO135/SHD_IO2 GPIO020/CMP_VIN0 25 VCREF0 RE375 0_0402_5%
    <39> EN_1.8VALW <11> RTCRST_ON

    2
    RE377 2 1 0_0402_5% EC_SPI_CS0# 27 GPIO136/SHD_IO3 GPIO165/CMP_VREF0 RE376
    <8> EC_SPICS#_R GPIO123/SHD_nCS 83 H_PROCHOT_EC 100K_0402_5%
    67 GPIO120/CMP_VOUT1 21
    <11,16,37> SIO_SLP_S4# GPU_PWR_LEVEL <48>

    2
    69 GPIO101/SPI_CLK GPIO021/CMP_VIN1 26 +3VALW POWER_SW_IN# 1 2
    <35> AC_DIS GPIO103/SPI_IO0 GPIO166/CMP_VREF1/UART_CLK LCD_TST <25> +3VALW POWER_SW#_MB <29>
    PCH_ALW_ON 71 RE378 10K_0402_5%
    <17> PCH_ALW_ON GPIO105/SPI_IO1
    <11> ME_SUS_PWR_ACK 42 118 CMP_STRAP0 RE3791 2 10K_0402_5%
    GPIO052/SPI_IO2 GPIO024/CMP_STRAP0

    1
    <12,29> TOUCHPAD_INTR# TOUCHPAD_INTR# 33 117
    GPIO062/SPI_IO3 GPIO023/ADC6/A20M PANEL_BKEN_EC <25>

    1
    3 116 CE79
    <22> LAN_EN GPIO001/SPI_nCS/32KHZ_OUT GPIO022/ADC5 SIO_EXT_WAKE# <9>
    109 MODEL_ID 1U_0402_6.3V6K

    2
    13 GPIO153/ADC4 110 I_ADP_R FW_UPDATE_EC RE380
    B <24,31> USB_EN# nRESET_IN/GPIO014 GPIO154/ADC3 B
    <11> ALL_SYS_PWRGD ALL_SYS_PWRGD RE381 2 1 0_0402_5% RUNPWROK 48 111 BOARD_ID 10K_0402_1%
    GPIO057/VCC_PWRGD GPIO155/ADC2
    VSS_VBAT

    RESET_OUT# 73 113 2 @ 1 I_SYS <35,40>


    <11> RESET_OUT#

    2
    GPIO107/nRESET_OUT GPIO122/ADC1
    VR_CAP
    114 I_BATT_R 0_0402_5% RE403 VCREF0
    GPIO121/ADC0
    AVSS

    MEC_XTAL2 125 115

    0.1U_0402_25V6
    VSS
    VSS
    VSS
    VSS
    VSS

    XTAL2 ADC_VREF

    1
    MEC_XTAL1 2 1 MEC_XTAL1_R 123 +3VALW_EC
    XTAL1

    1
    RE382 0_0402_5%
    +3VALW

    CE81
    MEC1404-NU-D0_VTQFP128_14X14 RE383

    0.1U_0402_25V6
    124

    84
    51
    17
    64
    100

    112

    18

    10K_0402_1%
    32 KHz Clock

    2
    1
    +3VS
    Close UE5

    1
    CE80
    VR_CAP 1 2
    EC_AGND

    1 MEC_XTAL1 1 2 MEC_XTAL2 C5231 1U_0603_16V7 RE384

    2
    1 1 ESR <100m ohms 100K_0402_5%
    CE82 Y1 Close UE2 EC_AGND
    0.1U_0402_10V7K C5232 32.768KHZ_9PF_CM315D32768DZCT C5233 RE385

    2
    2 10P_0402_50V8J 10P_0402_50V8J 2 1 @
    5

    UE6 2 2 I_ADP_R 1 2 CMP_VIN0 1 @ 2 CMP_VOUT0


    I_ADP <35>
    SN74LVC1G06DCKR_SC70-5 0_0603_5% 1 RE386 300_0402_5% RE387 100K_0402_5%
    P

    4 2 H_PROCHOT_EC EC_AGND
    <12,34,35,40> H_PROCHOT# Y A CE83
    NC

    1
    G

    2200P_0402_25V7K
    CE84 RE388 2
    1

    47P_0402_50V8J 100K_0402_5%
    2 PCH_PLTRST#_EC CE85 1 2 0.047U_0402_16V4Z
    EC_AGND ESD@
    1

    FAN1_TACH CE86 1 2 220P_0402_50V8J

    SIO_SLP_S3# CE87 1 2 0.1U_0402_10V7K


    ESD@
    RESET_OUT# CE88 1 2 1000P_0402_50V7K
    ESD@
    ACAV_IN CE89 2 1 100P_0402_50V8J
    I_BATT_R 1 2 I_BATT <35>
    Close UE5 RE389 300_0402_5%
    Debug Connector +3VALW
    1 Close to UE5 each pin
    +3VS CE90 2200P_0402_25V7K
    1

    A A
    DB1 CONN@ RE390 2
    49.9_0402_1%
    12 10 pin6,7 need assign GPIO for multi function???
    11 GND 10 9 JDEG1 CONN@ EC_AGND
    2

    GND 9 8 LPC_LAD0 1
    8 7 LPC_LAD1 1 2 JTAG_TDI RE395 2 1 0_0402_5% ICSP_CLK
    7 6 LPC_LAD2 2 3 JTAG_TMS RE396 2 1 0_0402_5% ICSP_CLR
    6 5 LPC_LAD3 3 4 JTAG_CLK RE397 2 1 0_0402_5% @ T4931 +3VALW
    5 4 LPC_LFRAME# 4 5 JTAG_TDO RE398 2 1 0_0402_5% ICSP_DAT
    4 3 5 6 MSCLK RE391 2 1 10K_0402_5%
    3
    2
    2
    1
    PCH_PLTRST#_EC <11,22,23,25,28,45> 6
    7
    7
    8
    MSDATA
    HOST_DEBUG_TX
    RE394
    RE392
    2
    2
    @ 1
    1
    100K_0402_5%
    10K_0402_5%
    Security Classification Compal Secret Data Compal Electronics, Inc.
    1 CLK_PCI_LPDEBUG <8> 8 Issued Date 2014/11/05 Deciphered Date 2014/12/15 Title
    11 9 RE393 2 @ 1 10K_0402_5%
    ACES_51522-01001-001 12 GND
    GND
    9
    10
    10
    THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
    EC MEC1404
    Pin8 5085_TXD for EC Debug Size
    AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D Document Number Rev
    pin9 5048_TXD for SBIOS X00(0.1)
    ACES_51522-01001-001 debug
    DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
    MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC. LA-C761P
    Date: Tuesday, July 28, 2015 Sheet 23 of 55
    5 4 3 2 1
    5 4 3 2 1

    Main Func : USB 3.0 Port


    +5V_USB_PWR1
    +5VALW UI5
    1 80mil
    5 OUT
    IN 2
    1 1 1 GND
    CI18 CI12 CI14 4
    EN 3 +5V_USB_PWR1

    47U_0805_6.3V4Z
    Vinafix.com
    OCB USB_OC#0_1 <10,24>

    4.7U_0805_10V4Z

    0.1U_0402_16V7K
    2 2 2 1
    SY6288D20AAC_SOT23-5
    CI15 1
    D 0.1U_0402_16V7K 1 1 D
    2 CI1 + CI40 CI2
    2.0A

    10U_0603_6.3V6M

    0.1U_0402_16V7K
    RI95 1 @EMI@ 2 0_0402_5% 220U_6.3V_M
    2 2 2
    LI2 EMI@
    1 2 USB20_JUSB1_N0_R
    <10> USB20_N1

    <23,24,31> USB_EN# USB_EN#


    1 4 3 USB20_JUSB1_P0_R
    <10> USB20_P1

    3
    CI13 MCM1012B900F06BP_4P
    0.1U_0402_16V7K RI96 1 @EMI@ 2 0_0402_5%
    2
    DI2
    L30ESDL5V0C3-2_SOT23-3 JUSB1
    RI97 1 EMI@ 2 0_0402_5% ESD@ 1
    2 VBUS
    3 D-
    USB3RN1_JUSB1_R 4 D+
    <10> USB3_CRX_DTX_N1

    1
    5 GND
    6 StdA-SSRX- 10
    USB3RP1_JUSB1_R DI1 ESD@ 7 StdA-SSRX+ GND 11
    <10> USB3_CRX_DTX_P1 GND-DRAIN GND
    1 10 USB3RN1_JUSB1_R 8 12
    9 StdA-SSTX- GND 13
    RI98 1 EMI@ 2 0_0402_5% 2 9 USB3RP1_JUSB1_R StdA-SSTX+ GND
    TAITW_PUBAU6-09FLBS1NN4H0
    RI99 1 EMI@ 2 0_0402_5% 4 7 USB3TN1_JUSB1_R CONN@

    C
    <10> USB3_CTX_DRX_N1 2 1 USB3TN1_JUSB1_C USB3TN1_JUSB1_R 5 6 USB3TP1_JUSB1_R C
    CI3 0.1U_0402_10V7K

    2 1 USB3TP1_JUSB1_C USB3TP1_JUSB1_R
    3 USB connector1
    <10> USB3_CTX_DRX_P1
    CI4 0.1U_0402_10V7K 8 USB20 port0
    RI100 1 EMI@ 2 0_0402_5% IP4292CZ10-TBR_XSON10_2.5X1~D USB30 port1

    Main Func : USB 3.0 Port +5V_USB_PWR1 +5V_USB_PWR2


    +5V_USB_PWR2
    +5VALW UI6 @
    1 80mil 1 @ 2
    5 OUT RI111 0_0805_5%
    IN 2
    1 1 GND
    CI6 CI7 4 RI111 placed to close UI5 / UI6
    @ @ EN 3 +5V_USB_PWR2
    OCB USB_OC#0_1 <10,24>
    4.7U_0805_10V4Z

    0.1U_0402_16V7K

    2 2 SY6288D20AAC_SOT23-5
    1
    1 1
    CI8 + CI43 CI9

    10U_0603_6.3V6M

    0.1U_0402_16V7K
    RI101 1 @EMI@ 2 0_0402_5% 220U_6.3V_M
    @2 2 2
    LI5 EMI@
    B 1 2 USB20_JUSB2_N1_R B
    <10> USB20_N2

    <23,24,31> USB_EN# USB_EN#


    1 4 3 USB20_JUSB2_P1_R
    <10> USB20_P2

    3
    CI26 @ MCM1012B900F06BP_4P
    0.1U_0402_16V7K RI102 1 @EMI@ 2 0_0402_5%
    2
    DI5
    RI103 1 EMI@ 2 0_0402_5% L30ESDL5V0C3-2_SOT23-3 JUSB2
    ESD@ 1
    2 VBUS
    USB3RN2_JUSB2_R 3 D-
    <10> USB3_CRX_DTX_N2 D+
    4

    1
    5 GND
    USB3RP2_JUSB2_R 6 StdA-SSRX- 10
    <10> USB3_CRX_DTX_P2 StdA-SSRX+ GND
    DI4 ESD@ 7 11
    1 10 USB3RN2_JUSB2_R 8 GND-DRAIN GND 12
    RI104 1 EMI@ 2 0_0402_5% 9 StdA-SSTX- GND 13
    2 9 USB3RP2_JUSB2_R StdA-SSTX+ GND
    TAITW_PUBAU6-09FLBS1NN4H0
    RI106 1 EMI@ 2 0_0402_5% 4 7 USB3TN2_JUSB2_R CONN@

    5 6 USB3TP2_JUSB2_R
    2 1 USB3TN2_JUSB2_C USB3TN2_JUSB2_R
    <10> USB3_CTX_DRX_N2
    CI10 0.1U_0402_10V7K 3 USB connector2
    <10> USB3_CTX_DRX_P2
    CI11
    2 1 USB3TP2_JUSB2_C
    0.1U_0402_10V7K
    USB3TP2_JUSB2_R 8 USB20 port0
    A

    RI105 1 EMI@ 2 0_0402_5%


    IP4292CZ10-TBR_XSON10_2.5X1~D USB30 port1 A

    Security Classification Compal Secret Data Compal Electronics, Inc.


    Issued Date 2014/04/01 Deciphered Date 2015/04/30 Title

    THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
    USB3.0
    Size
    AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D Document Number Rev
    DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS 0.1
    MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC. LA-B015P
    Date: Tuesday, July 28, 2015 Sheet 24 of 55
    5 4 3 2 1
    5 4 3 2 1

    Main Func : LCD USB20_N7


    <10> USB20_N7
    LCD PWR CTRL <10> USB20_P7
    USB20_P7

    3
    +3VS +LCDVDD +LCDVDD_CONN eDP Connector
    1
    Vinafix.com LX1 1 @ 2
    W=60mils
    0_0805_5%
    DX2
    PESD5V0U2BT_SOT23-3 JEDP
    CX7 W=60mils @ESD@ 0.1U_0402_16V7K 2 1 C4312 EDP_TX0_C 1
    <6> EDP_TX0_DP 1
    D 4.7U_0805_10V4Z UX4 1 1 0.1U_0402_16V7K 2 1 C4311 EDP_TX0#_C 2 41 D
    <6> EDP_TX0_DN 2 G1
    5 1 CX11 CX8 3 42

    1
    DX5 2 IN OUT 0.1U_0402_16V7K 2 1 C4314 EDP_TX1_C 4 3 G2 43
    +3VS <6> EDP_TX1_DP 4 G3

    0.1U_0402_10V7K

    4.7U_0805_10V4Z
    2 2 0.1U_0402_16V7K 2 1 C4313 EDP_TX1#_C 5 44
    <6> EDP_VDD_EN GND 2 2 <6> EDP_TX1_DN 5 G4
    6 45
    1 ENVDD_R 4 3 2 1 0.1U_0402_16V7K 2 1 C4321 EDP_AUX_C 7 6 G5 46
    EN OC <6> EDP_AUX_DP 7 G6
    10K_0402_5% RX10 <6> EDP_AUX_DN 0.1U_0402_16V7K 2 1 C4322 EDP_AUX#_C 8
    3 SY6288C20AAC_SOT23-5 9 8
    <23,25> LCD_TST 9

    1
    +VDD_TOUCH 10
    <6> EDP_HPD 10
    BAT54C-7-F_SOT23-3 RX48 11
    100K_0402_5% 12 11
    @EMI@ 12
    1 2 USB20_N7 13
    RX22 0_0402_5% USB20_P7 14 13

    2
    15 14
    MCM1012B900F06BP_4P 16 15
    4 3 USB20_P5_L 17 16
    <10> USB20_P5 17
    18
    TS_RST# 19 18
    1 2 USB20_N5_L 20 19
    <10> USB20_N5 20
    TS_INT# 21
    LX6 EMI@ TS_EN_R 22 21
    DBC_EN_R 23 22
    @EMI@ +VDD_TOUCH +LCDVDD_CONN 23
    1 2 24
    24
    RX21 0_0402_5% W=60mils 25
    25
    26
    +3VS +3VS_CAM USB20_P5_L 27 26
    USB20_N5_L 28 27
    1 @ 2 29 28
    Web Cam PWR RX27 0_0603_1% A_MIC_CLK 30 29
    <21> A_MIC_CLK 30
    C 31 C
    A_MIC_DATA 32 31
    Array MIC<21> A_MIC_DATA 32
    +3VS 1 @ 2 LCD_TEST 33
    <23,25> LCD_TST 33
    RX32 0_0402_1% 34
    35 34
    1 @ 2 LCD_BRIGHTNESS 36 35
    RX33 0_0402_5% BLON_OUT_C 37 36
    38 37
    38

    1
    DX6 W=60mils 39
    39
    2 RX26 40
    <6> L_BKLT_CTRL 40
    100K_0402_5%
    +3VS +5VS 1 STARC_107K40-000001-G2
    * Touch Screen Panel CONN@

    2
    <23,25> LCD_TST 3
    1

    RX30 RX29 +V_TS BAT54C-7-F_SOT23-3


    0_0603_5% 0_0603_5% +19VB
    @ +VDD_TOUCH +INV_PWR_SRC
    2

    0_0805_5% 2 1 RX4
    RX28 2 1 0_0603_5% 1 1
    1 1 CX5 CX6 FX3
    CX50 CX49 1 @ 2 DBC_EN_R <23> PANEL_BKEN_EC 1 2 @ 2 @ 1
    <9> DBC_EN

    0.1U_0603_25V7K

    1U_0603_25V7K
    FX2 1 2 @ @ @ RX23 0_0402_1% RX31 100_0402_5%

    1
    2 2
    0.1U_0402_10V7K

    4.7U_0805_10V4Z

    1 SMD1812P150TF/24 1.5A UL/CSA/TUV


    CX51 1.1A_24V_SMD1812P110TF-24 2 2 RX49 RX9
    4.7U_0805_10V4Z 0_0402_5% 100K_0402_5%
    @ co-lay @ co-lay
    2

    2
    B B

    DX9 2 1 RB551V-30_SOD323-2
    LID_CLOSE# <23,31>

    RX25 1 @ 2 0_0402_1% TS_EN_R


    <12> TOUCH_SCREEN_PD#
    1
    CX9 +3VS +LCDVDD_CONN
    0.1U_0402_10V7K
    @
    2

    0.1U_0402_10V7K

    0.1U_0402_10V7K

    10U_0805_10V6K
    1 1 1

    CX1
    CX2

    CX3
    +VDD_TOUCH
    2 2 2
    RX47 1 2 100K_0402_5% TS_INT#

    RX24 1 @ 2 0_0402_5% TS_RST# Place close to JEDP


    <11,22,23,28,45> PLT_RST#
    1
    CX4
    0.1U_0402_10V7K
    @
    A 2 A

    Security Classification Compal Secret Data Compal Electronics, Inc.


    Issued Date 2014/04/01 Deciphered Date 2015/04/30 Title

    THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
    eDP / webcam / TouchScreen
    Size
    AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D Document Number Rev
    DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS 0.1
    MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC. LA-B015P
    Date: Tuesday, July 28, 2015 Sheet 25 of 55
    5 4 3 2 1
    5 4 3 2 1

    Main Func : HDMI


    Place close to JHDMI
    +5VS

    2
    RX35 1 EMI@ 2 5.6_0402_1% TMDS_L_TXCN
    DX3
    +VDISPLAY_VCC
    Vinafix.com
    RB551V-30_SOD323-2
    W=40mils

    1
    RX36 2 1

    10U_0603_6.3V6M
    0.1U_0402_16V7K
    D 150_0402_1% 1 1 D

    CX21
    EMI@ FX1
    1.5A_6V_1206L150PR~D CX22

    2
    +3VS 2 2
    RX37 1 EMI@ 2 5.6_0402_1% TMDS_L_TXCP

    RX38 1 EMI@ 2 5.6_0402_1% TMDS_L_TX0N

    1
    RX12

    1
    10K_0402_5%
    RX39
    150_0402_1%

    2
    CX12 2 1 0.1U_0402_10V7K TMDS_TXCN EMI@ JHDMI
    <6> HDMI_CLK#
    CX13 2 1 0.1U_0402_10V7K TMDS_TXCP HDMI_HPLUG 19
    <6> HDMI_CLK

    2
    18 HP_DET
    CX14 2 1 0.1U_0402_10V7K TMDS_TX0N 17 +5V
    <6> HDMI_DATA0# DDC/CEC_GND
    CX15 2 1 0.1U_0402_10V7K TMDS_TX0P RX40 1 EMI@ 2 5.6_0402_1% TMDS_L_TX0P CPU_DPB_CTRLDAT_R 16
    <6> HDMI_DATA0 SDA
    CPU_DPB_CTRLCLK_R 15
    CX16 2 1 0.1U_0402_10V7K TMDS_TX1N RX41 1 EMI@ 2 5.6_0402_1% TMDS_L_TX1N 14 SCL
    <6> HDMI_DATA1# Reserved
    CX17 2 1 0.1U_0402_10V7K TMDS_TX1P 13
    <6> HDMI_DATA1 CEC
    TMDS_L_TXCN 12 20
    CX18 2 1 0.1U_0402_10V7K TMDS_TX2N 11 CK- GND 21
    <6> HDMI_DATA2# CK_shield GND

    1
    CX19 2 1 0.1U_0402_10V7K TMDS_TX2P TMDS_L_TXCP 10 22
    <6> HDMI_DATA2 CK+ GND
    RX42 TMDS_L_TX0N 9 23
    150_0402_1% 8 D0- GND
    EMI@ TMDS_L_TX0P 7 D0_shield
    TMDS_L_TX1N 6 D0+

    2
    1 D1-
    2
    3
    4

    4
    3
    2
    1
    C 5 C
    RP59 RP58 TMDS_L_TX1P 4 D1_shield
    RX43 1 EMI@ 2 5.6_0402_1% TMDS_L_TX1P TMDS_L_TX2N 3 D1+
    470_8P4R_5% 470_8P4R_5% D2-
    2
    TMDS_L_TX2P 1 D2_shield
    8
    7
    6
    5

    5
    6
    7
    8
    RX44 1 EMI@ 2 5.6_0402_1% TMDS_L_TX2N D2+
    CONCR_099ATAC19NBLCNF
    CONN@

    1
    RX45 46@ ROYALTY HDMI W/LOGO
    150_0402_1% Part Number Description
    +3VS EMI@
    1

    RO0000002HM HDMI W/Logo:RO0000002HM

    2
    D
    2 QX3
    G 2N7002K_SOT23-3 RX46 1 EMI@ 2 5.6_0402_1% TMDS_L_TX2P
    1

    S +3VS
    RX13
    3

    100K_0402_5%
    @

    1
    C RX15
    2

    QX5 2 1 2 HDMI_HPLUG
    MMBT3904_NL_SOT23-3 B 150K_0402_5%
    E

    1
    <6> HDMI_DET
    RX34

    1
    @ 20K_0402_5%
    B RX14 B

    2
    100K_0402_5%

    2
    +5VS

    1
    DX4
    BAW56W_SOT323-3
    +3VS

    2 3

    2 2
    RX16 RX17
    2.2K_0402_5% 2.2K_0402_5%

    2
    G

    1
    1 6 CPU_DPB_CTRLCLK_R
    <6> PCH_HDMI_CLK

    D
    QX4B
    DMN66D0LDW-7_SOT363-6

    5
    G
    <6> PCH_HDMI_DATA 4 3 CPU_DPB_CTRLDAT_R
    A A

    D
    QX4A
    DMN66D0LDW-7_SOT363-6

    Security Classification Compal Secret Data Compal Electronics, Inc.


    Issued Date 2014/04/01 Deciphered Date 2015/04/30 Title

    THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
    HDMI
    Size
    AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D Document Number Rev
    DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS 0.1
    MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC. LA-B015P
    Date: Tuesday, July 28, 2015 Sheet 26 of 55
    5 4 3 2 1
    A B C D E F G H

    Main Func : HDD

    Vinafix.com
    1 1

    US2 US2 @ US2 @


    +3VS

    SN75LVCP601RTJR PI3EQX6741STZDEX PS8520CTQFN20GTR2-A1 1 1

    1
    CS42 CS27
    SA00003ZX00 SA00004H100 SA00005U300

    0.01U_0402_16V7K

    0.1U_0402_25V6K
    RS25
    0_0402_5% 2 2
    +3VS

    2
    US2 @
    RS19 1 2 0_0402_5% 7 6 DEW2
    EN VDD 16 DEW1
    CS37 1 2 0.01U_0402_16V7K SATA_PTX_DRX_P0_R 1 VDD
    <10> SATA3_PTX_HDDRX_P0 A_INp
    <10> SATA3_PTX_HDDRX_N0 CS36 1 2 0.01U_0402_16V7K SATA_PTX_DRX_N0_R 2 10
    A_INn NC 20 HDD_REXT_SATA0
    CS35 1 2 0.01U_0402_16V7K SATA_PRX_DTX_P0_RC 5 REXT
    <10> SATA3_PRX_HDDTX_P0 B_OUTp
    CS33 1 2 0.01U_0402_16V7K SATA_PRX_DTX_N0_RC 4 9 HDD_A0_PRE0
    <10> SATA3_PRX_HDDTX_N0 B_OUTn A_PRE0 8 HDD_B0_PRE0

    +3VS
    HDD_B0_PRE1
    HDD_A0_PRE1
    17
    19 B_PRE1
    A_PRE1
    B_PRE0

    A_OUTp
    15 SATA_PTX_DRX_P0_RC CS30 1 2 0.01U_0402_16V7K SATA_PTX_DRX_P0 SATA HDD Connector
    14 SATA_PTX_DRX_N0_RC CS32 1 2 0.01U_0402_16V7K SATA_PTX_DRX_N0
    RS20 1 @ 2 0_0402_5% 18 A_OUTn JHDD
    2 3 TEST 11 SATA_PRX_DTX_P0_R CS34 1 2 0.01U_0402_16V7K SATA_PRX_DTX_P0 SATA_PRX_DTX_P0 1 2
    RS22 1 @ 2 0_0402_5% HDD_B0_EQ 13 GND B_INp 12 SATA_PRX_DTX_N0_R CS31 1 2 0.01U_0402_16V7K SATA_PRX_DTX_N0 SATA_PRX_DTX_N0 2 1
    21 GND B_INn 3 2
    EPAD SATA_PTX_DRX_N0 4 3
    PS8520BTQFN20GTR2_TQFN20_4X4 SATA_PTX_DRX_P0 5 4
    6 5
    1 @ 2 JHDD_P10 7 6
    +3VS <10> DEVSLP0 7
    RS8 0_0402_1% 8
    9 8
    10 9
    RS29 1 @ 2 0_0402_5% 11 10
    RS18 2 @ 1 0_0402_5% HDD_B0_PRE1 +5VS +5V_HDD 12 GND
    JP13 @ GND
    RS30 1 @ 2 0_0402_5% 2 1 E&T_4260K-F10N-00L
    RS23 2 @ 1 0_0402_5% HDD_A0_PRE1 2 1 CONN@
    1 1 1
    JUMP_43X79
    RS38 2 @ 1 0_0402_5% CS5 CS6 CS7

    1000P_0402_50V7K

    0.1U_0402_25V6K

    10U_0805_10V6K
    RS37 2 1 0_0402_5% HDD_B0_EQ

    RS33 2 @ 1 4.7K_0402_5%
    SHORT 2 2 2

    RS35 2 1 4.7K_0402_5% DEW2


    For Skylake
    RS34 2 @ 1 4.7K_0402_5%
    RS36 2 1 4.7K_0402_5% DEW1

    RS26 1 2 0_0402_5%
    RS31 2 @ 1 5.1K_0402_1% HDD_REXT_SATA0

    RS27 1 @ 2 0_0402_5%
    3 RS24 2 @ 1 2K_0402_5% HDD_A0_PRE0 3

    RS28 1 2 0_0402_5%
    RS21 2 @ 1 0_0402_5% HDD_B0_PRE0

    4 4

    Security Classification Compal Secret Data Compal Electronics, Inc.


    Issued Date 2014/04/01 Deciphered Date 2015/04/30 Title

    THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
    HDD / Free Fall Sensor
    Size
    AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D Document Number Rev
    DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS 0.1
    MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC. LA-B015P
    Date: Tuesday, July 28, 2015 Sheet 27 of 55
    A B C D E F G H
    5 4 3 2 1

    Main Func : WiFi/BT


    +3S TO +3VS_WLAN_NGFF
    +3VS +3VS_WLAN_NGFF
    @
    RM7 1 2 0_0603_5%
    Vinafix.com 1 2 RM10 1
    @
    2 0_0603_5% 1
    CM10
    D CM9 CM8 10P_0402_50V8J D
    10P_0402_50V8J 1U_0402_6.3V6K @RF@
    2 1 2
    @RF@

    closed to pin 2, 4 closed to pin 64, 66


    +3VS_WLAN_NGFF +3VS_WLAN_NGFF
    NGFF WL Con (E Key)
    1 1 1 1
    CM4 CM6
    10U_0603_6.3V6M CM5 CM7
    @ 0.1U_0402_10V7K 10U_0603_6.3V6M 0.1U_0402_10V7K
    +3VS_WLAN_NGFF 2 2 2 2

    JNGFF
    1 2
    C 3 GND 3.3VAUX 4 C
    <10> USB20_P8 USB_D+ 3.3VAUX
    5 6
    <10> USB20_N8 USB_D- LED1#
    7 8
    9 GND PCM_CLK 10
    11 SIDO_CLK PCM_SYNC 12
    13 SDIO_CMD PCM_IN 14
    15 SDO_DAT0 PCM_OUT 16
    17 SDO_DAT1 LED2# 18
    19 SDO_DAT2 GND 20
    21 SDO_DAT3 UART_WAKE# 22
    23 SDIO_WAKE# UART_RX
    SDIO_RESET#

    24
    25 UART_TX 26
    27 GND UART_CTS 28
    <10> PCIE_PTX_WLANRX_P5_C PETP0 UART_RTS
    <10> PCIE_PTX_WLANRX_N5_C 29 30 E51_TX2
    31 PETN0 RESERVED 32
    33 GND RESERVED 34
    <10> PCIE_PRX_WLANTX_P5 PERP0 RESERVED
    35 36 E51_TX1
    <10> PCIE_PRX_WLANTX_N5 PERN0 COEX3
    37 38 E51_RX1
    GND COEX2 @ T4928 PAD~D
    <11> CLK_PCIE_WLAN_P1 39 40
    41 REFCLKP0 COEX1 42 SUSCLK_R RM5 1 @ 2 0_0402_1%
    <11> CLK_PCIE_WLAN_N1 REFCLKN0 SUSCLK SUSCLK <11>
    43 44 PLT_RST#_R RM6 1 @ 2 0_0402_1%
    GND PERST0# PLT_RST# <11,22,23,25,45>
    45 46 BLUETOOTH_EN
    <11> CLK_PCIE_WLAN_REQ# CLKEQ0# W_DISABLE2# BLUETOOTH_EN <9>
    1 @ 2 47 48 WL_OFF#_R
    <11,22,23> PCIE_WAKE# PEWAKE0# W_DISABLE1#
    RM14 0_0402_5% 49 50
    51 GND I2C_DATA 52
    B 53 RSRVD/PETP1 I2C_CLK 54 B
    55 RSRVD/PETN1 ALERT 56
    57 GND RESERVED 58
    59 RSRVD/PERP1 RESERVED 60
    61 RSRVD/PERN1 RESERVED 62 +3VS_WLAN_NGFF
    63 GND RESERVED 64
    65 RESERVED 3.3VAUX 66
    RESERVED 3.3VAUX

    1
    67
    GND RM8
    10K_0402_5%
    69 68
    MTG77 MTG76 DM1

    2
    2 1 WLAN_RADIO_DIS# <6>
    LOTES_APCI0019-P009A
    CONN@ RB551V-30_SOD323-2

    Reserved for NGFF Debug Card


    +3VALW +3VS_WLAN_NGFF

    RM11 1 @ 2 0_0402_5%

    A A
    E51_TX1 RM12 1 @ 2 0_0402_5% HOST_DEBUG_TX <23>
    E51_TX2 RM13 1 @ 2 0_0402_1%
    1

    RM9
    100K_0402_5%
    Security Classification Compal Secret Data Compal Electronics, Inc.
    @ 2014/04/01 2015/04/30 Title
    Issued Date Deciphered Date
    NGFF WLAN
    2

    THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
    Size
    AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D Document Number Rev
    DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS 0.1
    MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC. LA-B015P
    Date: Tuesday, July 28, 2015 Sheet 28 of 55
    5 4 3 2 1
    5 4 3 2 1

    Main Func : PWR SW Main Func : Keyboard Main Func : KBBL

    Power ON Circuit Vinafix.com INT_KBD Connector Key Board Back Light


    D JKB D
    <9> KB_DET# 30 32
    KSI7 29 30 GND 31
    KSI6 28 29 GND +5VS +5VS_KBL
    ON/OFF switch KSI4
    KSI2
    27
    26
    28
    27
    26 20mil KBBL@
    KSI5 25 FE1 2 1
    KSI1 24 25 20mil
    TOP Side KSI3 23 24
    23 1 0.5A_13.2V_NANOSMDC050F-13.2-2 1
    KSI0 22 CE56 CE57
    SW1 KSO5 21 22 1U_0603_10V6K 10U_0603_6.3V6M
    SMT1-05-A_4P KSO4 20 21 KBBL@ @
    1 3 KSO7 19 20 Tulip 設設，要要CPU 電電電電SPEC 2 2
    POWER_SW#_MB <23> 19 建建建 56K_5% ( SD028560200 )
    1 KSO6 18
    2 4 KSI[0..7] KSO8 17 18 JKBBL
    <23> KSI[0..7] 17
    3

    CE20 KSO3 16 1
    0.1U_0402_16V7K KSO[0..16] KSO1 15 16 RE61 1 KBBL@ 2 51K_0402_5% 2 1
    <23> KSO[0..16] <12> KB_LED_BL_DET
    6
    5

    2 KSO2 14 15 3 2
    14 3

    1
    KSO0 13 KB_BL_PWM 4
    KSO12 12 13 RE58 5 4
    DE2 KSO16 11 12 100K_0402_5% 6 GND
    L03ESDL5V0CC3-2_SOT23-3 KSO15 10 11 KBBL@
    20mil GND
    @ESD@ KSO13 9 10 ACES_50524-00401-P01

    2
    KSO14 8 9 CONN@
    1

    1
    2
    5
    6
    KSO9 7
    KSO11 6 7 D QE5
    KSO10 5 6 G AP2606AGY-HF 1N SOT26-6
    CAP_LED 4 5 3
    4 <23> KB_LED_PWM
    3 S KBBL@
    C 2 3 C

    4
    1 2
    1
    +3VS HB_A823020-SBHR21
    CONN@

    1
    +5VS
    RE330
    QE10

    2
    G
    100K_0402_5% R2
    3
    2

    3 1 CAP_LED_R#2
    <23> CAP_LED# R1
    S 1 CAP_LED_Q 1 2 CAP_LED

    D
    RE401 1K_0402_5%
    QE11 DDTA144VCA-7-F-GP
    LN2306LT1G_SOT23-3

    Main Func : TouchPAD


    +3VS +3VS_TOUCH
    TP/PTP
    Touch PAD

    1
    +3VS_TOUCH +3VS_TOUCH
    B RE335 RE334 B
    4.7K_0402_5% 4.7K_0402_5% 1
    PTP@ PTP@

    2
    +3VS +3VS_TOUCH CE58

    2
    RC78 1U_0402_6.3V6K~D
    G 2
    1 @ 2 1 6 I2C_SDA_TP_R RE329 100K_0402_5%
    <9> I2C_SDA_TP
    S

    D
    RE399 0_0402_5% 10K_0402_5% PTP@
    QE6B JTP

    1
    5

    QE9 @ DMN66D0LDW-7_SOT363-6 8
    +3VALW NTK3139PT1G_SOT723-3 PTP@ I2C_SDA_TP_R 7 8 10
    G

    4 3 I2C_SCL_TP_R I2C_SCL_TP_R 6 7 G2 9
    <9> I2C_SCL_TP 6 G1
    S

    RE400 1 2 0_0402_5% 3 1 5
    QE6A INT_TP# 4 5
    4
    1

    2 DMN66D0LDW-7_SOT363-6 1 2 TP_LOCK# 3
    <23> PTP_DIS# 3
    CE61 RE402 PTP@ DE4 RB551V-30_SOD323-2 2
    G

    <23> DAT_TP_SIO
    2

    1U_0402_6.3V6K 100_0402_1% 1 2
    <23> CLK_TP_SIO 1
    @ RE336 1 @ 2 0_0402_5%
    1 ACES_51524-0080N-001
    1 2

    RE337 1 @ 2 0_0402_5% CONN@


    D +3VS_TOUCH
    2 +3VS_TOUCH
    <23> TP_PW_EN# G QE8
    S 2N7002KW 1N SOT323-3
    3

    1
    G
    RE339 RE338
    QE9 1 3 INT_TP# 4.7K_0402_5% 4.7K_0402_5%
    <12,23> TOUCHPAD_INTR#

    S
    QE7 @EMI@

    2
    2N7002KW 1N SOT323-3 CE91 2 1 680P_0402_50V7K
    A A
    DAT_TP_SIO
    CLK_TP_SIO CE92 2 1 680P_0402_50V7K
    S TR PJV1701 1P SOT723-3
    @EMI@
    SB000017J00
    Security Classification Compal Secret Data Compal Electronics, Inc.
    Issued Date 2014/04/01 Deciphered Date 2015/04/30 Title

    THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
    FAN / TP / PWR SW / KBBL
    Size
    AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D Document Number Rev
    DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS 0.1
    MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC. LA-B015P
    Date: Tuesday, July 28, 2015 Sheet 29 of 55
    5 4 3 2 1
    5 4 3 2 1

    Main Func : Fan/Thermal

    CPU Bottom side


    Vinafix.com +FAN_POWER FAN Control circuit
    +3VS
    D 40mil 40mil 9/16. +3VALW +3VLP
    D

    SA000050J00 & SA00003S000 are EOL.


    1 1

    1
    CE22 CE23 Change to SA00005CA00 for 1st Source (approved by HSW)

    2
    RE50

    2.2U_0603_6.3V6K

    1000P_0402_50V7K
    10K_0402_5% RE332 RE333
    @ JFAN 2 2 7.15K_0402_1% 10K_0402_1%
    1 @

    2
    2 1 4
    <23> FAN1_TACH

    1
    3 2 GND 5 +5VS CE25
    1 3 GND
    CE24 2.2U_0603_6.3V6K
    <23> VCIN0_PH
    0.01U_0402_16V7K 1 2
    ACES_88231-03041

    1
    2 CONN@ 1
    UE3 CE26
    1 8 HE1 0.01U_0402_16V7K
    2 VEN GND 7 100K_0402_1%_TSM0B104F4251RZ
    3 VIN GND 6 2

    2
    FAN1_DAC_1 4 VO GND 5
    <23> FAN1_DAC_1 VSET GND
    NCT3942S SOP 8P

    +3VS +3VS
    C C

    1
    1
    R2456 R2457
    10K_0402_5% 10K_0402_5%

    2
    G
    2
    2
    THM_SML1_DATA 1 6
    GPU_THM_SMBDAT <8,23,48>

    D
    Fintek thermal sensor Q2409B

    5
    DMN66D0LDW-7_SOT363-6
    placed near by TOP DDR3

    G
    +3VS THM_SML1_CLK 4 3 GPU_THM_SMBCLK <8,23,48>

    D
    Q2409A
    1 DMN66D0LDW-7_SOT363-6
    C2498 +3VS
    0.1U_0402_10V6K
    R2458 1 @ 2 0_0402_5%

    1
    2
    R2448 R2459 1 @ 2 0_0402_5%
    10K_0402_5%
    BOTTOM DDR3 REMOTE1+ Close U2407 U2407 @

    2
    1
    1

    C C2500 1 10 THM_SML1_CLK
    Q2407 2 2200P_0402_25V7K C2502 VDD SMCLK
    MMBT3904WH_SOT323-3 B @ 2200P_0402_25V7K REMOTE1+ 2 9 THM_SML1_DATA
    2

    B E 2 DP1 SMDATA B
    3

    REMOTE1- REMOTE1- 3 8
    DN1 ALERT#
    REMOTE2+ REMOTE2+ 4 7 MAINPWON
    BOTTOM CPU DP2/DN3 THERM#
    1 REMOTE2- 5 6
    DN2/DP3 GND
    1

    C C2505
    Q2408 2 2200P_0402_25V7K C2504
    MMBT3904WH_SOT323-3 B @ 2200P_0402_25V7K F75303M_MSOP10
    2

    E 2
    Address 1001_101xb
    3

    REMOTE2-

    2nd source
    REMOTE1,2 (+/-) : SA000029210-->EMC1403-2-AIZL-TR
    Trace width/space:10/10 mil
    Trace length:<8"

    A A

    Security Classification Compal Secret Data Compal Electronics, Inc.


    Issued Date 2014/04/01 Deciphered Date 2015/04/30 Title

    THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
    Thermal Sensor
    Size
    AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D Document Number Rev
    DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS 0.1
    MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC. LA-B015P
    Date: Tuesday, July 28, 2015 Sheet 30 of 55
    5 4 3 2 1
    5 4 3 2 1

    Main Func : DB CONN.

    +5VALW

    CI44
    1
    CI45
    1 Vinafix.com +5V_USB_PWR3
    D UI7 D
    80mil
    4.7U_0805_10V4Z

    0.1U_0402_16V7K 1
    2 2 80mil 5 OUT
    IN 2
    4 GND
    EN 3
    OCB USB_OC#2_3 <10>
    1
    SY6288D20AAC_SOT23-5
    CI47
    0.1U_0402_16V7K
    2
    <23,24> USB_EN#
    USB_EN# 2.0A IO to MB CONN
    CI46
    1
    Substitute:SP01001FS00
    0.1U_0402_16V7K
    2 +3VS +5V_USB_PWR3
    JIO
    1
    2 1
    RI109 1 @EMI@ 2 0_0402_5% 3 2
    4 3
    LI8 EMI@ 5 4
    4 3 6 5
    C <10> USB20_P6 6 C
    7
    8 7
    1 2 9 8
    <10> USB20_N6 9
    10
    MCM1012B900F06BP_4P USB20_CR_P6_R 11 10
    RI110 1 @EMI@ 2 0_0402_5% USB20_CR_N6_R 12 11
    13 12
    RI107 1 @EMI@ 2 0_0402_5% USB20_JUSB3_P4_R 14 13
    USB20_JUSB3_N4_R 15 14
    LI11 EMI@ 16 15
    4 3 16
    <10> USB20_P4
    17
    18 GND
    1 2 GND
    <10> USB20_N4
    ACES_51524-0160N-001
    MCM1012B900F06BP_4P CONN@
    RI108 1 @EMI@ 2 0_0402_5%

    LED/B TO M/B
    B
    +3VALW_EC +5VS +5VALW
    SP01001A900 B

    JLED
    +3VALW_EC 1
    2 1
    3 2
    3
    2

    LID_CLOSE# 4
    <23,25> LID_CLOSE# 4
    RI93 5
    100K_0402_5% 6 5 9
    7 6 G1 10
    7 G2
    6

    8
    1

    2 G
    D
    +3VALW_EC 8
    S QI1B +3VS ACES_51524-0080N-001
    3

    DMN66D0LDW-7_SOT363-6 CONN@
    1

    2
    D

    <23> BAT1_LED# 5 G

    2
    S RI94
    QI1A 100K_0402_5% RI91
    4

    DMN66D0LDW-7_SOT363-6 100K_0402_5%

    3
    1

    3
    D
    5 G RI1A

    1
    D
    S DMN66D0LDW-7_SOT363-6 5 G
    6

    S QI2A
    4

    6
    D

    <23> BAT2_LED# 2 G DMN66D0LDW-7_SOT363-6

    4
    D
    S
    <10,23> SATA_LED# 2 G

    A RI1B S QI2B A
    1

    DMN66D0LDW-7_SOT363-6 DMN66D0LDW-7_SOT363-6

    1
    Security Classification Compal Secret Data
    Issued Date 2014/04/01 Deciphered Date 2015/04/30 Title

    THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
    IO/B, LED/B
    AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&DSize Document Number Rev
    DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS B 0.1
    MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC. LA-B015P
    Date: Tuesday, July 28, 2015 Sheet 31 of 55
    5 4 3 2 1
    A B C D E

    Main Func : DC/DC

    +5VS and +3VS switch


    Vinafix.com +5VALW

    1 1
    1 1 1
    C5222 C2306 C2305
    @RF@ @

    10P_0402_50V8J

    10U_0603_6.3V6M

    10U_0603_6.3V6M
    2 2 2

    SHORT +5VS
    U2301 @ J510 @
    1 14 5VS 2 1
    2 VIN1 VOUT1 13 2 1
    VIN1 VOUT1 1 1 1
    JUMP_43X79 C2307 C2308 C5223
    R2313 1 2 0_0402_5% 5VS_GATE 3 12 1 2 @ @RF@
    <11,16,23,34,41> SIO_SLP_S3# ON1 CT1

    10U_0805_10V4Z

    10U_0603_6.3V6M

    10P_0402_50V8J
    C5216 1000P_0402_50V7K
    4 11 2 2 2
    VBIAS GND
    R2318 1 2 0_0402_5% 3VS_GATE 5 10 C5217 1 2 1000P_0402_50V7K
    10mil ON2 CT2
    6 9 3VS
    VIN2 VOUT2

    1
    C2322 C2309 +3VALW 7 8
    @ @ VIN2 VOUT2

    0.01U_0603_25V7K

    0.01U_0603_25V7K
    15
    SHORT
    2

    2
    GPAD
    TPS22966DPUR_SON14_2X3 +3VS
    1 1 1 J511 @
    C5224 C2316 C2318 2 1
    @RF@ @ 2 1

    10P_0402_50V8J

    10U_0603_6.3V6M

    10U_0603_6.3V6M
    2 U2301 JUMP_43X79 2
    2 2 2
    1 1 1
    C2324 C2323 C5225
    @RF@

    10U_0603_6.3V6M

    10U_0603_6.3V6M

    10P_0402_50V8J
    @
    2 2 2
    S IC EM5209VF DFN 14P DUAL LOAD SW

    SA00007PM00

    3 3

    4 4

    Security Classification Compal Secret Data Compal Electronics, Inc.


    Issued Date 2014/04/01 Deciphered Date 2015/04/30 Title

    THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
    DC/DC Interface
    Size
    AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D Document Number Rev
    DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS 0.1
    MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC. LA-B015P
    Date: Tuesday, July 28, 2015 Sheet 32 of 55
    A B C D E
    5 4 3 2 1

    Main Func : 3D Camera


    +5VALW TO +5V_3DCAM
    +5VALW +5V_CAM

    Vinafix.com 1
    OPEN
    2
    J521 @
    D C5221 1 2 C94 D
    0.1U_0402_10V6K 1 2 1U_0402_6.3V6K
    2 JUMP_43X39 1
    +3VS
    RI88 1 @ 2 10K_0402_5% U2409

    +3V_PRIM 1 7
    RI54 1 2 10K_0402_5% 2 VIN VOUT 8
    VIN VOUT
    3 6
    <9,23> 3D_CAM_EN ON CT
    1

    1
    RI90 4 C5220
    100K_0402_5% VBIAS 5 2200P_0402_25V7K
    GND 9 2
    GND

    2
    CT pin use 2200pf for
    TPS22967DSGR_SON8_2X2
    soft start tuning
    For Test,
    APE8937(SA000070L00)
    AOZ1336(SA00006U600)
    RI3 1 @EMI@ 2 0_0402_5% TPS22967(SA000070S00)

    +3VS
    EMI@ LI10
    2 1
    0.01U_0402_16V7K 1 2 CI23
    UI8
    C 0.1U_0402_10V6K 1 2 CI20 1 7 RI56 1 2 4.99K_0402_1% 3 4 +5V_CAM C
    13 VCC NC 24 RI57 1 @ 2 0_0402_5%
    VCC NC S COM FI_ CHILISIN CMMI21T-670Y-N
    CI22 1 2 0.1U_0402_10V6K USB3_CRX_C_RD_DTX_N3 11 20 USB3_CRX_RD_DTX_N3 JCAM3D
    <10> USB3_CRX_DTX_N3 TX2- RX2-
    CI19 1 2 0.1U_0402_10V6K USB3_CRX_C_RD_DTX_P3 12 19 USB3_CRX_RD_DTX_P3 RI4 1 @EMI@ 2 0_0402_5% 10 12
    <10> USB3_CRX_DTX_P3 TX2+ RX2+ 10 GND
    USB3_CRX_L_DTX_N3 USB3_CRX_L_DTX_N3 9 11
    USB3_OS2_P0 15 USB3_CRX_L_DTX_P3 USB3_CRX_L_DTX_P3 8 9 GND
    USB3_DE2_P0 16 OS2 5 USB3_ERD_P0 USB3_CTX_L_DRX_N3 7 8
    USB3_EQ2_P0 17 DE2 EN_RXD 14 USB3_CM_P0 USB3_CTX_L_DRX_P3 USB3_CTX_L_DRX_N3 6 7
    EQ2 CM USB3_CTX_L_DRX_P3 5 6
    CI16 1 2 0.1U_0402_10V6K USB3_CTX_C_RD_DRX_N3 8 23 USB3_CTX_RD_DRX_N3 CI21 1 2 0.1U_0402_10V6K 4 5
    <10> USB3_CTX_DRX_N3 RX1- TX1- 4
    CI5 1 2 0.1U_0402_10V6K USB3_CTX_C_RD_DRX_P3 9 22 USB3_CTX_RD_DRX_P3 CI24 1 2 0.1U_0402_10V6K RI5 1 @EMI@ 2 0_0402_5% 3
    <10> USB3_CTX_DRX_P3 RX1+ TX1+ 3
    2
    USB3_OS1_P0 4 LI9 EMI@ 1 2
    USB3_DE1_P0 3 OS1 6 USB3_P0_PIN6 USB3_CTX_C_DRX_N3 2 1 1
    USB3_EQ1_P0 2 DE1 GND 10 STARC_111D10-000000-G4-R
    EQ1 GND 18 USB3_P0_PIN18 CONN@
    25 GND 21 USB3_CTX_C_DRX_P3 3 4
    PGND GND
    S COM FI_ CHILISIN CMMI21T-670Y-N
    CAM_DETECT
    <9> CAM_DETECT
    PS8713BTQFN24GTR2-A0_TQFN24_4X4 RI6 1 @EMI@ 2 0_0402_5%

    +3VS +3VS
    RI89 1 @ 2 10K_0402_5%

    RI53 1 @ 2 3.3K_0402_5% +3V_PRIM


    B RI49 1 @ 2 0_0402_5% USB3_P0_PIN6 RI55 1 2 10K_0402_5% B

    Layout request to swap pin ! FW_UPDATE


    <9,23> FW_UPDATE
    RI52 1 @ 2 3.3K_0402_5%
    RI50 1 @ 2 0_0402_5% USB3_P0_PIN18

    DI3 @ESD@
    RI42 1 @ 2 4.7K_0402_5% USB3_CRX_L_DTX_P3 1 10 USB3_CRX_L_DTX_P3
    RI46 1 @ 2 4.7K_0402_5% USB3_CM_P0
    USB3_CRX_L_DTX_N3 2 9 USB3_CRX_L_DTX_N3

    RI44 1 @ 2 4.7K_0402_5% USB3_CTX_L_DRX_P3 4 7 USB3_CTX_L_DRX_P3


    RI48 1 @ 2 4.7K_0402_5% USB3_ERD_P0
    USB3_CTX_L_DRX_N3 5 6 USB3_CTX_L_DRX_N3

    RI19 1 @ 2 4.7K_0402_5% 3
    RI87 1 @ 2 4.7K_0402_5% USB3_OS2_P0
    8

    RI20 1 @ 2 4.7K_0402_5% S DIO(BR) TVWDF1004AD0 DFN ESD


    RI31 1 @ 2 4.7K_0402_5% USB3_DE2_P0

    RI21 1 @ 2 4.7K_0402_5%
    RI36 1 @ 2 4.7K_0402_5% USB3_EQ2_P0

    RI22 1 @ 2 4.7K_0402_5%
    RI40 1 @ 2 4.7K_0402_5% USB3_OS1_P0
    A A

    RI26 1 @ 2 4.7K_0402_5%
    RI35 1 @ 2 4.7K_0402_5% USB3_DE1_P0

    RI23 1 @ 2 4.7K_0402_5% Security Classification Compal Secret Data Compal Electronics, Inc.
    RI32 1 @ 2 4.7K_0402_5% USB3_EQ1_P0 2014/04/01 2015/04/30 Title
    Issued Date Deciphered Date
    THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
    3D CAMERA
    Size
    AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D Document Number Rev
    DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS 0.1
    MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC. LA-B015P
    Date: Tuesday, July 28, 2015 Sheet 33 of 55
    5 4 3 2 1
    A B C D

    @ PJP1
    2 1
    2 1
    JUMP_43X79

    EMI@ PL1
    +19V_VIN PR4 PSID@
    FBMJ4516HS720NT_2P 33_0402_5%
    +19V_ADPIN 1 2 1 3 PSID-3 1 2 PS_ID <23>

    S
    PQ6 PSID@
    FDV301N_G 1N SOT23-3

    1000P_0402_50V7K

    1000P_0402_50V7K
    PJPDC

    G
    2

    1
    100K_0402_1%
    0.1U_0402_25V7K

    0.1U_0402_25V7K
    1
    1 PR8

    2
    2 1 2 PSID@ PR3 PSID@
    2

    Vinafix.com

    EMI@ PC1

    EMI@ PC2

    EMI@ PC3

    EMI@ PC4

    PR6
    PSID@
    3 EMI@ PL4 PSID-2 2 1 +5VALW 2.2K_0402_5%
    3 4 FBMJ4516HS720NT_2P

    2
    4 5 @ PJP2

    2
    5 2 1 10K_0402_1%
    +3VALW

    1
    2 1

    1
    1 6 C 1
    GND 7 JUMP_43X79 PSID-1 2 PQ5 PSID@
    GND

    15K_0402_1%
    B MMST3904-7-F_SOT323

    2
    ACES_50299-00501-003 E

    3
    PR9
    PSID@
    CONN@

    PL2
    BLM15AG102SN1D_2P

    1
    PSID 2 1
    EMI@

    +17.4V_BATT+ @ PJP3
    2 1 +17.4V_BATT++
    +17.4V_BATT+

    2 1
    JUMP_43X79

    EMI@ PL3
    FBMJ4516HS720NT_2P
    1 2 +17.4V_BATT++
    1

    1000P_0402_50V7K
    0.01U_0402_25V7K
    1

    PC8

    1
    EMI@ PC7

    PD2 PD3
    2

    TVNST52302AB0_SOT523-3 TVNST52302AB0_SOT523-3
    EMI@

    EMI@ EMI@

    3
    SMART
    Battery:
    01.GND1 PBAT_PRES# <23,35>
    02.GND2 PBATT
    03.BAT_ALERT 1
    2
    1 2

    04.SYS_PRES 2
    2
    3 PR15 PR16
    05.BATT_PRS 3 4 SYS_PRES PR20 200_0402_5% 10K_0402_1%
    06.DAT_SMB 4 5 100_0402_5% 1 2 1 2
    07.CLK_SMB 5 6 DAT_SMB 1 2 +3VALW
    6 7 CLK_SMB 1 2
    08.BATT1+ 7 8
    09.BATT2+ 8 9 PR18
    9 10 100_0402_5% PBAT_CHG_SMBCLK <23,35>
    GND 11
    GND
    LLTOP_ALLTOP C144LS-109A9-L 9P BATT P2
    CONN@
    PBAT_CHG_SMBDAT <23,35>

    Other component (37.1)

    3 3

    JRTC CONN@
    Adapter protection: Battery protection: Erp lot6 Circuit +19V_VIN 1
    +RTCBATT 2 1
    if battery removed, adaptor only, asserts H_PROCHOT# when adaptor is 2
    then trigger the H_PROCHOT#, unplugged, keep low for 10ms

    3.3K_1206_5%
    3
    keep @ in BOM since battery can not till SW PROCHOT# is issued by EC 4 GND
    GND

    1
    be removed by end user <11,16,23,32,41> SIO_SLP_S3#

    PR5
    ACES_50271-0020N-001
    H_PROCHOT#
    H_PROCHOT# +19V_VIN
    <12,23,35,40>
    +3VALW @ PR7 @
    2
    10K_0402_1%

    3 2
    1

    1M_0402_1%
    +3VALW
    PR28

    6
    10K_0402_1%

    L2N7002DW1T1G_SC88-6
    PR31 PC16
    1

    PQ1B
    L2N7002DW1T1G_SC88-6

    .1U_0402_16V7K
    1
    PQ2A
    PR37

    1M_0402_1% 5
    3 2
    3

    PC14 1 2 2
    6

    2
    L2N7002DW1T1G_SC88-6

    L2N7002DW1T1G_SC88-6

    .1U_0402_16V7K @
    4
    100K_0402_1%
    PQ3B

    PQ2B
    L2N7002DW1T1G_SC88-6

    @
    2

    1
    1

    PQ1A

    PBAT_PRES# 1 2 5 PR10
    PR29

    5 2
    100K_0402_1%

    10K_0402_1%

    PR33 1M_0402_1%
    4

    1
    1

    PR2 1

    @
    4

    1
    PR32

    1M_0402_1%
    2

    4 @ 4
    2

    DELL CONFIDENTIAL/PROPRIETARY
    Security Classification Compal Secret Data Compal Electronics, Inc.
    Issued Date 2014/11/05 Deciphered Date 2014/12/15 Title

    THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
    PWR_DCIN/BATT CONN/OTP
    Size
    AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D Document Number Rev
    DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS X00(0.1)
    MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.
    Date: Tuesday, July 28, 2015 Sheet 34 of 55
    A B C D
    A B C D

    2 1 2 1

    @ PR739 @ PR746 Iada=0~3.33A(65W)


    1M_0402_1% 1M_0402_1%
    Iada=0~2.30A(45W)

    5
    2 1 3 4 ADP_I = 32*Iadapter*Rsense
    @ PR744 @
    1M_0402_1% PQ709B

    Vinafix.com
    L2N7002DW1T1G_SC88-6

    @
    PD706
    1 1

    PQ709A
    ACIN_CHG 2 1 +19VB

    L2N7002DW1T1G_SC88-6
    SDMK0340L-7-F_SOD323-2
    2

    1
    2 1 2 1

    PR738 PR737
    1M_0402_1% 3M_0402_5%
    PR703
    PQ740 PQ718 0.01_1206_1%
    AON7426_DFN3X3EP8-5 MDU1512RH_POWERDFN56-8-5 @EMI@ PL704
    1 1 1 4 1 2
    2 2

    2200P_0402_25V7K
    0.1U_0402_25V7K
    5 3 3 5 2 3 1UH_PCMB053T-1R0MS_7A_20%
    +19V_VIN

    EMI@

    EMI@
    10U_0805_25V6K

    10U_0805_25V6K

    10U_0805_25V6K

    10U_0805_25V6K
    PC764
    @ PJP701

    1
    3.3K_1206_5%

    PC760

    PC762

    PC763
    1 2
    1 2

    PC765

    PC705
    1

    1
    0_0402_5%

    2_0402_5%
    JUMP_43X118

    2
    PR720

    PR772

    PR740
    2

    2
    @
    @
    PQ707A

    L2N7002DW1T1G_SC88-6

    @
    PC747
    0.1U_0402_25V6
    2 2 1
    <23,35> AC_DIS
    1

    4.02K_0402_1%

    4.02K_0402_1%
    2 2

    For DT Mode
    1

    1
    PR745
    392K_0402_1%

    100_0402_1%
    2

    2
    1

    5
    PR762

    PR763

    MDU1512RH_POWERDFN56-8-5
    +17.4V_BATT+
    PR729

    PC750 0.22U_0603_25V7K
    1 2

    @ PR773 0_0603_5%
    2
    L2N7002DW1T1G_SC88-6

    1 2 4
    PQ707B

    PQ717
    0.01UF_0402_25V7K
    3

    @
    1
    49.9K_0402_1%

    1
    PR732

    0.1U_0402_25V7K

    3
    2
    1
    PC711

    5
    <23,35> AC_DIS

    2
    PC779
    CMSRC
    1

    2
    1 VDD_CHG
    4

    ASGATE

    1
    5
    @

    AON7408L_DFN8-5
    100K_0402_1%

    32

    31

    30

    29

    28

    27

    26

    25
    PU703 ISL95521HRZ-T_QFN32_4X4 2S2P : CV = 8.4V CC = 3.9A

    PQ704
    3S1P : CV = 12.6V CC = 2A
    PR741

    For Learn Mode

    CSIP

    CSIN

    ASGATE

    CMSRC

    OPCN

    QPCP

    VBAT

    BGATE
    PC721 4
    @ PR771 0_0603_5% 0.22U_0603_25V7K
    ACIN_CHG 1 24 1 2 1 2
    2

    ACIN BOOT PR765


    PL700
    ACIN 2 23 UGATE_CHG 0.01_1206_1%

    3
    2
    1
    <11,23> ACAV_IN 0_0402_5% @ PR769 ACOK UGATE 4.7UH_5.5A_20%_7X7X3_M +17.4V_BATT+
    1
    158K_0402_1%

    1 2 3 22 PHASE_CHG 1 2 1 4
    <23,34> PBAT_CHG_SMBDAT SDA PHASE
    PR731

    @ PR770 0_0402_5%

    680P_0603_50V7K 4.7_1206_5%
    1 2 4 21 LGATE_CHG 2 3
    <23,34> PBAT_CHG_SMBCLK SCL LGATE

    10U_0805_25V6K

    10U_0805_25V6K

    10U_0805_25V6K

    10U_0805_25V6K
    EMI@ PR766

    0.1U_0402_25V7K
    @ PR777 0_0402_5%

    AON7506_DFN33-8-5
    3
    1 2 5 20 VDDP_CHG 3
    2

    <12,23,34,40> H_PROCHOT# @ PR774 0_0402_5% PROCHOT# VDOP

    1
    PC775

    PC776

    PC777

    PC761

    PC766
    1 2 6 19 VDD_CHG 1 2
    <23> I_ADP AMON VDO

    PQ708
    @ PR775 0_0402_5%

    2
    1 2 7 18 PR760 4.7_0402_5%

    2
    <23> I_BATT BMON DCIN

    1U_0402_16V6K

    1U_0402_16V6K
    4

    2
    BATGONE
    8 17
    <23,40> I_SYS PSYS NTC

    1
    100K_0402_1%

    EMI@ PC767
    CCLIM

    ACLIM
    COMP
    PROG
    AGND

    CSON
    2200P_0402_25V7K

    2200P_0402_25V7K

    CSOP

    PC768

    PC769
    FSET

    1
    2
    10.5K_0402_1%

    3
    2
    1

    2
    1

    PR757
    1

    2
    PC748

    PC749

    PR727

    33

    10

    11

    12

    13

    14

    15

    16

    3
    PQ710
    2

    0_0603_5%
    LMUN5113T1G_SOT323-3
    2

    PR780
    2

    0_0402_5%

    1U_0603_25V6
    1 2
    +19V_VIN

    2
    VDD_CHG PR743 10_1206_5%

    1
    PR779
    1 2 PD704 SDMK0340L-7-F_SOD323-2 @

    1
    2
    PC757
    1 2 BA

    1
    200K_0402_1%

    200K_0402_1%

    @
    1

    1
    PD705 SDMK0340L-7-F_SOD323-2 <11> SIO_SLP_S5# 2
    CCLIM
    2

    2
    PR749

    PR750

    PQ711

    BA
    10K_0402_1%

    ACLIM

    3
    PROG 1 2 LTC015EUBFS8TL_UMT3F
    1

    COMP PR742 2_0402_5%

    2
    PC708
    182K_0402_1%

    102K_0402_1%
    0.015U_0402_25V7K 499_0402_1%

    0.1U_0402_25V6
    2

    1
    560P_0402_50V7K

    PR764
    1
    2
    PR753

    PR754

    PR755

    1 2
    2
    127K_0402_1%
    76.8K_0402_1%

    PC751

    @ PR776 0_0402_5%
    1

    4 4
    1
    2

    2
    PR751

    PR752

    PBAT_PRES# <23,34>
    2

    10P_0402_50V8J
    PC752

    PC753
    1

    DELL CONFIDENTIAL/PROPRIETARY
    Security Classification Compal Secret Data Compal Electronics, Inc.
    Issued Date 2014/11/05 Deciphered Date 2014/12/15 Title

    THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
    PWR_CHARGER
    Size
    AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D Document Number Rev
    DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS X00(0.1)
    MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.
    Date: Tuesday, July 28, 2015 Sheet 35 of 55
    A B C D
    A B C D E

    Vinafix.com
    1 1

    @EMI@ PL102
    FBMJ4516HS720NT_2P PR102
    1 2 499K_0402_1%
    ENLDO_3V5V 1 2
    @ PR100 +19VB
    @ PJP105 0_0603_5% PC102

    1
    499K_0402_1%
    1 2 3V_VIN BST_3V1 2 1 2
    +19VB 1 2

    PR103
    JUMP_43X79 0.1U_0603_25V7K

    2200P_0402_50V7K

    1
    PU100

    2
    @EMC@ PC100

    EMC@ PC103

    10U_0805_25V6K

    10U_0805_25V6K
    0.1U_0402_25V6

    IN

    IN

    IN

    IN

    BS
    1

    1
    PC105

    @ PC104
    LX_3V 6 20 PL100
    LX LX 1.5UH_PCMC063T-1R5MN_9A_20%

    2
    7 19 LX_3V 1 2
    GND LX +3VALWP

    EMC@ PR106
    8 SY8286BRAC_QFN20_3X3 18
    GND GND

    4.7_1206_5%

    22U_0805_6.3V6M

    22U_0805_6.3V6M

    22U_0805_6.3V6M

    22U_0805_6.3V6M

    22U_0805_6.3V6M
    9 17
    PG LDO +3VLP

    1
    PC106

    PC107

    PC108

    PC109

    @ PC110
    10 16
    NC NC
    3VALWP

    OUT

    2
    EN2

    EN1

    1
    21

    NC
    FF
    GND PC111 TDC 7.087 A

    13V_SN 2
    PR107 4.7U_0603_6.3V6M
    Peak Current 8.504 A

    11

    12

    13

    14

    15

    680P_0603_50V7K
    10K_0402_5%

    EMC@ PC112
    1 2
    +3VALWP 3.3V LDO 150mA~300mA OCP Current 9 A fix by IC

    ENLDO_3V5V
    2 2
    Vout is 3.234V~3.366V
    POK <11,38,39>

    2
    POK

    @ PJP102

    150K_0402_1%
    PC113 PR108 +3VALWP 1 2 +3VALW
    1 2

    1
    @ PR109
    1000P_0402_25V8J 1K_0402_5%
    EN_3V 3V_FB 1 2 1 2 JUMP_43X118

    @EMI@ PL103

    2
    FBMJ4516HS720NT_2P
    1 2

    1
    150K_0402_1%
    @ PJP103

    @ PR110
    @ PR111 +5VALWP 1 2 +5VALW
    @ PJP106 0_0603_5% PC114 1 2
    1 2 5V_VIN BST_5V 1 2 1 2 JUMP_43X118
    +19VB 1 2

    2
    JUMP_43X79 0.1U_0603_25V7K
    2200P_0402_50V7K

    1
    @EMC@ PC115

    EMC@ PC116

    10U_0805_25V6K

    10U_0805_25V6K
    0.1U_0402_25V6

    PU102
    1

    IN

    IN

    IN

    IN

    BS
    PC117

    PC118

    LX_5V 6 20 PL101
    2

    LX LX 2.2UH +-20% 7.8A 7X7X3 MOLDING


    7 19 LX_5V 1 2 +5VALWP
    GND LX
    8 SY8286CRAC_QFN20_3X3 18
    GND GND

    1
    PR112

    680P_0603_50V7K 4.7_1206_5%

    22U_0805_6.3V6M

    22U_0805_6.3V6M

    22U_0805_6.3V6M

    22U_0805_6.3V6M

    22U_0805_6.3V6M
    3 PC119 3

    1
    EMC@
    9 17 1 2

    PC120

    PC121

    PC122

    PC123

    @ PC124
    PG VCC
    10 16

    2
    NC NC 4.7U_0603_6.3V6M

    15V_SN
    OUT

    LDO

    2
    EN2

    EN1

    @ PR121 0_0402_5% 21
    FF

    EN_3V 1 2 GND
    11

    12

    13

    14

    15

    PC125
    PR113
    +3VALWP VL

    EMC@
    @ PR120 0_0402_5% 10K_0402_5%

    2
    EN_5V 1 2 1 2
    ENLDO_3V5V

    5V LDO 150mA~300mA
    1
    EN_5V

    PC126
    4.7U_0603_6.3V6M

    POK
    PR114
    2.2K_0402_5%
    5VALWP
    2

    150K_0402_1%
    1 2
    <23> ALWON

    1
    TDC 4.5 A

    @ PR115
    PD102
    @ PR116 0_0402_5% SDMK0340L-7-F_SOD323-2 Peak Current 6.3 A
    <23,48> CMP_VOUT0
    1 2 1 2 OCP Current 9 A fix by IC

    2
    4.7U_0402_6.3V6M
    1

    1
    150K_0402_1%
    PC128

    PC127 PR117

    @ PR118
    EN_3V 1000P_0402_25V8J 1K_0402_5%
    5V_FB 1 2 1 2
    2

    EN_5V

    2
    EN1 and EN2 dont't floating
    4 4
    3

    @EMI@

    PD101
    DELL CONFIDENTIAL/PROPRIETARY
    TVNST52302AB0_SOT523-3
    1

    Compal Electronics, Inc.


    Title

    Place PD101 close to PU100 THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL PWR_3.3VALWP/5VALWP
    AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D Size Document Number Rev
    DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS X00(0.1)
    MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC. LA-C761P
    Date: Tuesday, July 28, 2015 Sheet 36 of 55
    A B C D E
    5 4 3 2 1

    @ PR200
    0_0603_5%
    BST_1.35V_R 1 2 BST_1.35V
    0.675Volt +/- 5%
    +1.35VP TDC 0.7A
    Vinafix.com Peak Current 1A

    1
    PC200
    D 0.1U_0603_25V7K D

    2
    @ PJP206
    +19VB 2 1 +19VB_1.35V UG_1.35V
    2 1 +0.675VSP

    2200P_0402_50V7K

    10U_0805_25V6K

    10U_0805_25V6K
    0.1U_0402_25V6
    JUMP_43X79

    10U_0805_6.3V6K

    10U_0805_6.3V6K
    LX_1.35V

    EMI@ PC208

    EMI@ PC201

    PC206

    PC212

    1
    PC205

    PC211
    2

    16

    17

    18

    19

    20
    PU200

    2
    PHASE

    UGATE

    BOOT

    VLDOIN

    VTT
    21
    PAD
    LG_1.35V 15 1
    LGATE VTTGND

    14 2
    PGND VTTSNS

    1
    PR205
    PQ201 10.2K_0402_1%

    D1

    D1

    D1

    G1
    AON7934_DFN3X3A8-10 1 2 CS_1.35V 13 3
    +1.35V_VDDQ PC204 CS RT8207PGQW_WQFN20_3X3 GND
    TDC 6 A 10
    D1 D2/S1
    9 1U_0603_10V6K
    1 2 12 4 VTTREF_1.35V
    Peak Current 9 A PR206 VDDP VTTREF
    5.1_0603_5%
    OCP Current 11 A

    G2
    S2

    S2

    S2
    1 2 VDD_1.35V 11 5
    VDD VDDQ +1.35VP

    1
    PGOOD
    5

    1
    PC210

    TON
    +5VALW

    1
    C PR210 0.033U_0402_16V7K C

    FB
    S5

    S3

    2
    PC209 2.2_0603_5%
    1U_0603_10V6K @ PC214

    10

    6
    220P_0402_25V8J

    2
    1 2
    +5VALW

    FB_1.35V
    TON_1.35V

    EN_0.675VSP
    EN_1.35V
    PR207
    54.9K_0402_1%
    PL200 <11> 1.35V_VTT_PWRGD 1 2 +1.35VP
    1UH_11A_20%_7X7X3_M PR208
    +1.35VP 1 2 @ PR209 +19VB_1.35V1 2
    10K_0402_1%
    453K_0402_1%

    1
    1 2
    +3VALW

    1
    @ PC213
    For RT8207P
    @ PR201 PR204
    .1U_0402_16V7K
    22U_0603_6.3V6M

    22U_0603_6.3V6M

    22U_0603_6.3V6M

    22U_0603_6.3V6M

    22U_0603_6.3V6M

    22U_0603_6.3V6M

    0_0402_5% 68.1K_0402_1%

    2
    1 2
    <11,16,23> SIO_SLP_S4#

    2
    1
    1

    1
    PC220

    PC218

    PC217

    PC216

    PC215

    PC219

    EMI@ PC207 @ PC202


    680P_0402_50V7K 0.1U_0402_10V7K
    2
    2

    2
    1

    @ PR202
    0_0402_5%
    EMI@ PR203 1 2
    <7> 0.675V_DDR_VTT_ON
    4.7_1206_5%
    2

    1
    B B
    @ PC203
    0.1U_0402_10V7K
    Mode S3 S5 +1.35VP +V_DDR_REF +0.675V_P

    2
    S5 L L off off off
    S3 L H on on off
    S0 H H on on on

    @ PJP200
    +1.35VP 1 2 +1.35V_VDDQ
    1 2
    JUMP_43X118
    @ PJP202
    1 2
    1 2
    JUMP_43X118

    @ PJP203
    2 1
    +0.675VSP 2 1 +0.675VS_VTT
    JUMP_43X79

    A A

    DELL CONFIDENTIAL/PROPRIETARY
    Security Classification Compal Secret Data
    Issued Date 2014/11/05 Deciphered Date 2014/12/15 Title
    PWR_+1.35V_VDDQ/+0.675VS_VTT
    THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
    AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&DSize Document Number Rev
    DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS Custom X00(0.1)
    MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.
    Date: Tuesday, July 28, 2015 Sheet 37 of 55
    5 4 3 2 1
    5 4 3 2 1

    +3V_PRIM
    PR314
    10K_0402_5%
    2 1

    @ PR315
    0_0402_5%
    Vinafix.com 2 1
    POK <11,36,39>

    D D
    @ PR313
    0_0402_5%
    2 1
    SIO_SLP_SUS# <11,17,23,39>

    @ PR312
    0_0402_5%
    EN_+1VALWP 1 2
    +1.8V_PG <39>

    1
    0.1U_0402_25V6
    1
    @ PC405
    1M_0402_1%
    PR302 @ PJP302

    2
    +1VALWP 1 2 +1.0V_PRIM

    2
    1 2
    JUMP_43X118

    EMC@ PR303 EMC@ PC302


    4.7_1206_5% 680P_0603_50V7K
    1 2 SNB_+1VALWP 1 2
    @ PJP301 PU301
    +19VB 2200P_0402_50V7K
    0.1U_0402_25V6

    2 1 +19VB_+1VALWP 8 1 @ PR304 PC304


    2 1 IN EN

    10U_0805_25V6K

    10U_0805_25V6K
    0_0603_5% 0.1U_0603_25V7K
    JUMP_43X79 6 BS_+1VALWP 1 2 1 2 PL301
    BS
    1

    1
    PC305

    PC306
    0.68UH +-20% 7.9A
    +1VALWP
    @EMC@ PC301

    @EMC@ PC303

    C 9 10 SW_+1VALWP 1 2 C
    GND LX
    2

    330P_0402_50V7K

    47U_0805_6.3V6M

    47U_0805_6.3V6M

    22U_0805_6.3VAM

    22U_0805_6.3VAM
    1

    1
    6.65K_0402_1%

    PC307
    4 FB_+1VALWP
    FB

    PC308

    PC309

    PC310

    PC311
    2
    PR306
    ILMT_+1VALWP 3 7
    +3VALW

    2
    ILMT BYP

    4.7U_0603_6.3V6K
    +3VALW

    1
    1K_0402_5%
    4.7U_0603_6.3V6K
    2 5
    PG LDO

    PC312

    PR308
    2
    1

    PC313
    SYX196DQNC_QFN10_3X3
    1

    2
    2

    2
    PR307
    0_0402_5%
    2

    1
    ILMT_+1VALWP
    PR311
    1

    10K_0402_1%

    @ PR310

    2
    0_0402_5%
    2

    The current limit is set to 6A, 9A or 12A when this pin


    is pull low, floating or pull high

    B B

    +1.0V_PRIM
    TDC 6.5 A
    Peak Current 9.3 A
    OCP Current 12 A Fix by IC
    TYP MAX
    Choke DCR 11.0mohm , 12.0mohm

    A A

    DELL CONFIDENTIAL/PROPRIETARY
    Security Classification Compal Secret Data
    Issued Date 2014/11/05 Deciphered Date 2014/12/15 Title
    PWR_+1VALWP
    THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
    AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&DSize Document Number Rev
    DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS Custom X00(0.1)
    MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.
    Date: Tuesday, July 28, 2015 Sheet 38 of 55
    5 4 3 2 1
    5 4 3 2 1

    TDC = 0.76A
    Prak current : 1.096A
    OCP : 3A
    FB=0.6V
    Vinafix.com @ PJP502
    JUMP_43X79
    D D
    1 2
    +1.8VALWP 1 2 +1.8V_PRIM

    PC502
    22U_0603_6.3V6M

    1 2 PU501
    SY8032ABC_SOT23-6
    @ PJP501 PL501
    JUMP_43X79 1UH_PHT25201B-1R0MS_2.45A_20%
    1 2 VIN_1.8VALW 4 3 LX_1.8VALW 1 2
    +3VALW 1 2 IN LX +1.8VALWP
    <38> +1.8V_PG 5 2
    PG GND

    22U_0603_6.3V6M

    22U_0603_6.3V6M
    1

    68P_0402_50V8J
    6 1
    FB EN

    1
    PC501

    PC504
    EMC@ PR502

    1
    PC503
    PR501
    @ PR504 4.7_0603_5%

    2
    0_0402_5% 20K_0402_1%

    SNUB_1.8VALW 2

    2
    1 2 EN_1.8VALW
    <11,17,23,38> SIO_SLP_SUS#

    2
    @ PR507
    Rup

    1
    0_0402_5%

    1
    1 2 PR505 @ PC505 FB_1.8VALW
    <11,36,38> POK
    1M_0402_1% 0.1U_0402_16V7K

    1
    2
    PR506
    <23> EN_1.8VALW

    1
    EMC@ PC506
    10K_0402_1%
    Rdown
    680P_0402_50V7K

    2
    C
    Note: C
    When design Vin=5V, please stuff snubber +1.8V_PRIM
    to prevent Vin damage TDC 0.66 A
    Vout=0.6V* (1+Rup/Rdown) Peak Current 0.95 A
    OCP Current 3.5A fix by IC

    B B

    A A

    DELL CONFIDENTIAL/PROPRIETARY
    Security Classification Compal Secret Data
    Title
    Compal Electronics, Inc.
    Issued Date 2014/11/05 Deciphered Date 2014/12/15
    THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
    PWR_+1.8V_PRIM
    Size
    AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D Document Number Rev
    DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS C X00(0.1)
    MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.
    Date: Tuesday, July 28, 2015 Sheet 39 of 55
    5 4 3 2 1
    5 4 3 2 1

    VCC_SA
    +1.0V_VCCST Loadline : 10.3m-ohm
    PJP603
    @ PR602
    TDC 4A 1 2
    Peak Current 4.5A VCCSA_B+ CPU_B+

    0.1U_0402_25V6
    0_0402_5%

    PC602
    45.3_0402_1%

    75_0402_1%

    100_0402_1%
    1 2
    +5VALW OCP current 7A PAD-OPEN1x1m

    PR605
    PR601

    PR604
    Local sense put on HW site Vinafix.com @ PR603 Choke DCR 12 +-5%m ohm

    2
    0_0402_5%

    0.22U_0603_25V7K
    @ 1 2 CPU_B+

    1U_0603_10V6K
    D 1 2 1 2 VR_SCLK D
    <15> VIDSCLK

    1
    @ 0_0402_5% PR606 49.9_0402_1% PR618

    PC603

    PC604
    <15> VIDALERT_N 1 2 1 2 VR_ALERT#
    @ 0_0402_5% PR607 @ 0_0402_5% PR625

    2
    <15> VIDSOUT 1 2 1 2 VR_SDA
    @ 0_0402_5% PR609 10_0402_1% PR626
    <12,23,34,35> H_PROCHOT# PR678 VCCSA_B+
    100_0402_1%
    1 2 1 2
    1 2
    PC605 47P_0402_50V8J~D
    U22@ PR608

    10U_0805_25V6K

    10U_0805_25V6K
    PH601 PR610 78.7K_0402_1%
    470K_0402_5%_ TSM0B474J4702RE 10K_0402_1% 1 2
    1 2 1 2 U22@ PR613 1.91K_0402_1% PR612

    1
    PC612

    PC608
    86.6K_0402_1% 1 2 PR611
    1 2 1 2 +3VS 48.7K_0402_1%
    PR631 PC613

    2
    27.4K_0402_1% 330P_0402_50V8J
    1 2 1 2
    <11,41> IMVP_VR_ON
    PC614 PR617
    2200P_0402_50V7K 3.6K_0402_1% @ 0_0402_5% PR616
    1 2 1 2

    40
    39
    38
    37
    36
    35
    34
    33
    32
    31
    PU602
    PC616 @ PR619 PC611

    VR_ENABLE
    VR_READY
    VR_HOT#
    SCLK
    ALERT#
    SDA

    PROG1
    PROG2
    VCC
    VIN
    33P_0402_50V8J 1 2 1 2
    1 2 PC617 PR621 @ 0_0402_5% PR620 0.22U_0603_16V7K
    220P_0402_50V7K 1K_0402_1% 1 2 1 30 PWM_VSA 0_0603_5% PU606 AON7934_DFN3X3A-8-10
    <23,35> I_SYS PSYS PWM_C

    1
    1 2 1 2 2 29 FCCM_VSA ISL95808HRZ-TS2378_DFN8_2X2 PQ501
    <15> VCC_GT_SENSE IMON_B FCCM_C
    U22@ PR622 3 28

    D1

    D1

    D1

    G1
    @ PC618 1.96K_0402_1% 4 NTC_B ISUMN_C 27 1 8 PL601
    COMP_B ISUMP_C UGATE PHASE
    0.082U_0402_16V7K

    1 2 1 2 5 26 0.68UH +-20% 7.9A


    FB_B RTN_C
    PC620

    6 25 FB_VSA 2 7 10 9 SA_SW 1 2
    RTN_B FB_C BOOT FCCM D1 D2/S1 +VCC_SA
    1

    PR627 EMC@
    330P_0402_50V7K 7 24 COMP_VSA
    PC621 PR623 8 ISUMP_B COMP_C 23 IMON_VSA PWM_VSA 3 6
    C ISUMN_B IMON_C PWM VCC C

    4.7_1206_5%
    PC619 680P_0402_50V7K 2K_0402_1% 9 22

    G2
    S2

    S2

    S2
    2

    ISEN1_B PWM_A PWM_IA <41>

    1
    1 2 @ 1 2 1 2 10 21 4 5
    ISEN2_B FCCM_A FCCM_IA <41> GND LGATE

    1
    TP
    ISUMN_A
    ISUMP_A
    PR624

    COMP_A
    PWM1_B
    PWM2_B

    8
    FCCM_B

    IMON_A
    0.01U_0402_50V7K 41

    NTC_A

    RTN_A
    AGND 3.65K_0603_1%

    1
    FB_A
    <15> VSS_GT_SENSE

    2
    0_0402_5%
    PR679
    +5VALW

    ISUMP_VSA 2
    PR637 need close to PU602

    SA_SNUB
    11
    12
    13
    14
    15
    16
    17
    18
    19
    20
    ISL95859HRTZ-T_TQFN40_5X5

    +VCC_SA
    2
    1
    1U_0402_10V6K
    @
    <41> ISUMP_GT

    IMON_IA

    FCCM_VSA
    FB_IA
    <41> FCCM_GT

    NTC_IA
    COMP_IA
    4.42K_0402_1%

    PC685
    <41> PWM1_GT

    2
    1

    @ PR637 PWM2_GT

    680P_0603_50V7K
    PR628

    PC625
    20M_0402_5%

    1
    330P_0402_50V7K
    10K_0402_5%_ERTJ0ER103J

    EMC@ PC622
    1 2
    0.047U_0402_25V7K

    U22@
    PR629
    2

    2
    0.047U_0402_25V7K

    84.5K_0402_1% @ PR654 PR654 need close to PU602

    2
    1

    1
    PC624

    PC626

    10P_0402_50V8J

    4.02K_0402_1%
    1 2

    2
    PR630
    PC627 PH603 20M_0402_5%
    1

    1
    11K_0402_1%

    1200P_0402_50V7K
    PR632 470K_0402_5%_ TSM0B474J4702RE
    2

    2
    1

    2200P_0402_50V7K

    2200P_0402_50V7K
    PH602

    PR633

    PC628
    1K_0402_1% 1 2 1 2
    1 2 1 2 ISUMP_VSA

    2
    255_0402_1%
    PR647 27.4K_0402_1% PR635

    1
    U22@ PR638 1 2 10K_0402_1% 1 2 1 2

    2.61K_0402_1%
    2

    1
    PR640
    274_0402_1%
    2

    1
    PC629

    PC630

    PC631
    1 2 PC632 PR641

    PR642
    41> +VCC_GT_L PR639
    2200P_0402_50V7K 3K_0402_1% 2200P_0402_25V7K 1K_0402_1%

    10KB_0402_5%_ERTJ0ER103J
    1 2 1 2 1 2

    U22@

    0.033U_0402_16V7K

    2
    2

    11K_0402_1%
    PC636 PR636 1.24K_0402_1%
    +5VALW 33P_0402_50V8J

    1K_0402_1%

    6800P_0402_25V7K

    PR643
    1

    PC633
    1 2

    PC637
    1
    PR644

    1
    B PC639 PR645 PR646 PC640 B

    1
    2200P_0402_25V7K 316_0402_1% 1 2 1 2 @

    330P_0402_50V7K
    .1U_0402_16V7K

    1 2 1 2
    1

    PH604
    316_0402_1% 2200P_0402_25V7K

    2
    PC641

    U22@ PR648

    2
    1 2 U22@ PR649
    2

    1
    140K_0402_1%
    U22@ PR651
    1 2

    1
    1.37K_0402_1% PC642 +VCC_SA
    680P_0402_50V7K 2K_0402_1%

    PC643
    0.047U_0402_25V7K 1.69K_0402_1% PC644
    1

    2K_0402_1%
    1 2 .1U_0402_16V7K

    PR652
    .1U_0402_16V7K
    1 2

    2
    1
    PR650

    PC645
    2

    1 2
    PC646

    680P_0402_50V7K
    0.047U_0402_25V7K
    2

    VSA_SEN- <16>
    PC647

    PC601
    1 2

    2
    1

    PC649
    0.01U_0402_50V7K

    0.082U_0402_16V7K
    1 2
    PR656
    11K_0402_1%
    <15> VCCSENSE

    2
    PC650
    1 2
    @ PC652
    PR657

    1
    @ PC651 PH605 @ 330P_0402_50V7K
    1 2 4.42K_0402_1% 10KB_0402_5%_ERTJ0ER103J 1 2
    0.082U_0402_16V7K

    1 2 1 2
    PC653

    330P_0402_50V7K
    1

    VSA_SEN+ <16>
    +VCC_CORE_L <41>
    2

    PC654 @
    A A
    1 2
    ISUMP_IA <41>
    1

    0.01U_0402_50V7K

    @ PR655 PR655 need close to PU602


    <15> VSSSENSE
    DELL CONFIDENTIAL/PROPRIETARY
    2

    20M_0402_5%
    Local sense put on HW site
    Security Classification Compal Secret Data Compal Electronics, Inc.
    2014/11/05 2014/12/15 Title
    Issued Date Deciphered Date PWR_+VCC_SA
    THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
    Size
    AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D Document Number Rev
    DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS X00(0.1)
    MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.
    Date: Tuesday, July 28, 2015 Sheet 40 of 55
    5 4 3 2 1
    5 4 3 2 1

    VCC_core VCC_GT
    Loadline : 2.4m-ohm Loadline : 3.1m-ohm
    TDC 21A TDC 18A
    Peak Current 29A Peak Current 31A
    OCP current 35A OCP current 40A
    Vinafix.com Choke DCR 0.66 +-7%m ohm Choke DCR 0.66 +-7%m ohm

    D D

    +19VB
    @ PJP601
    1 2
    CPU_B+ PAD-OPEN 4x4m

    @EMC@ PL602
    1 2
    PC659 @EMC@

    PC660 @EMC@

    FBMA-L11-453215800LMA90T_2P
    2200P_0402_50V7K
    10U_0805_25V6K

    10U_0805_25V6K

    10U_0805_25V6K

    0.1U_0402_25V6K~D

    33U_25V_M
    1

    1
    PC656

    PC657

    PC658

    + PC606
    2

    2
    PWM_IA <40>

    @ PR664 0_0402_5%
    +5VALW 2 1
    IMVP_VR_ON <11,40,41>
    1U_0402_10V6K

    2 1 DRMOS
    1

    PR658 0_0402_5% @
    PC661

    @ PR662 2 1
    SIO_SLP_S3# <11,16,23,32,34,41>
    0_0402_5% PU603
    2

    AOZ5019QI_QFN23_5X3P5
    @ PR659 CPU_B+
    0_0402_5% 13
    <40> FCCM_IA 2 1 1 PWM 12
    @ 0_0603_5% 2 SMOD EN 11 PL603
    1 PR660 2 3 VCC VIN 10
    C
    4 BOOT CGND 9 .15UH +-20% 29A 7X7X4 MOLDING C
    0.22U_0603_16V7K GH GL
    1 2 5 8 CORE_SW 1 2

    PC655
    6 VSWH
    VIN
    VSWH
    PGND
    7 PR663 EMC@ +VCC_CORE
    10P_0402_25V8J

    4.7_1206_5%
    1

    1
    PC686

    PC680 @

    1
    1000P_0402_50V7K PR661 PR673
    2

    0_0402_5%
    2

    3.65K_0603_1%
    2

    <40>
    +VCC_CORE_L
    2
    CORE_SNUB

    <40>
    ISUMP_IA
    680P_0603_50V7K
    1

    EMC@ PC662

    GPU_B+ CPU_B+
    2

    @ PJP602
    1 2

    PAD-OPEN 4x4m
    PC666 @EMC@

    PC667 @EMC@
    2200P_0402_50V7K
    10U_0805_25V6K

    10U_0805_25V6K

    0.1U_0402_25V6K~D

    B B
    1

    1
    PC672

    PC673
    2

    PWM1_GT <40>
    DRMOS

    @ PR683 0_0402_5%
    @ PR671 2 1
    IMVP_VR_ON <11,40,41>
    0_0402_5%
    <40> FCCM_GT PR682 0_0402_5% @
    2 1 2 1
    SIO_SLP_S3# <11,16,23,32,34,41>
    PU605
    1U_0402_10V6K

    AOZ5019QI_QFN23_5X3P5
    GPU_B+
    1
    PC677

    13
    1 PWM 12
    2

    @ 0_0603_5% 2 SMOD EN 11 PL605


    1 PR672 2 3 VCC VIN 10
    4 BOOT CGND 9 .15UH +-20% 29A 7X7X4 MOLDING
    0.22U_0603_16V7K GH GL
    1 2 5 8 GT_SW1 1 2
    VSWH VSWH +VCC_GT
    PR676 EMC@

    6 7
    PC671 VIN PGND
    10P_0402_25V8J

    4.7_1206_5%
    1

    1
    PC688

    PC679
    1

    1000P_0402_50V7K @
    2

    PR674 PR675
    2

    3.65K_0603_1% 0_0402_5%
    1 2
    2

    <40>
    +VCC_GT_L

    A A
    GT_SNUB1

    <40>
    ISUMP_GT

    DELL CONFIDENTIAL/PROPRIETARY
    680P_0603_50V7K
    1

    EMC@ PC678

    Security Classification Compal Secret Data Compal Electronics, Inc.


    Issued Date 2014/11/05 Deciphered Date 2014/12/15 Title
    2

    THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
    PWR_+VCC_core and +VCC_GT
    Size
    AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D Document Number Rev
    DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS X00(0.1)
    MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.
    Date: Tuesday, July 28, 2015 Sheet 41 of 55
    5 4 3 2 1
    4

    +VCC_CORE
    Vinafix.com

    +VCC_GT
    A

    A
    22U_0603 * 20 pcs+330u_D2*2 pcs
    Primary Side.
    22U_0603 * 13 pcs +1U_0201*35 pcs
    Back Side.
    VCC_CORE Place on CPU
    2 1 2 1

    1
    +
    220U 2V Y D2
    PC1099 PC1083 PC1076
    PC1127
    1U_0201_6.3V6M 1U_0201_6.3V6M 22U_0603_6.3V6M
    2 1 2 1

    1
    +
    220U 2V Y D2
    PC1095 PC1030 PC1081 PC1078
    PC1062
    1U_0201_6.3V6M 1U_0201_6.3V6M 22U_0603_6.3V6M 22U_0603_6.3V6M
    2

    1
    PC1221 2 1
    22U_0603_6.3V6M

    1
    PC1094 PC1080 PC1077
    1U_0201_6.3V6M 22U_0603_6.3V6M 22U_0603_6.3V6M
    2

    1
    @

    PC1222 2 1
    22U_0603_6.3V6M

    1
    PC1096 PC1082 PC1079
    1U_0201_6.3V6M 22U_0603_6.3V6M 22U_0603_6.3V6M
    2

    1
    @

    PC1223 2 1 2 1
    22U_0603_6.3V6M

    1
    @
    PC1090 PC1033 PC1001
    1U_0201_6.3V6M 1U_0201_6.3V6M 22U_0603_6.3V6M
    2

    PC1224 2 1 2 1 2 1
    22U_0603_6.3V6M

    1
    @

    @
    PC1173 PC1093 PC1034 PC1072 PC1002
    22U_0603_6.3V6M 1U_0201_6.3V6M 1U_0201_6.3V6M 22U_0603_6.3V6M 22U_0603_6.3V6M
    2

    1
    @

    PC1158 2 1
    22U_0603_6.3V6M

    1
    @
    @ PC1174 PC1069 PC1003
    22U_0603_6.3V6M 22U_0603_6.3V6M 22U_0603_6.3V6M
    2

    PC1162 2 1 2 1
    22U_0603_6.3V6M

    1
    @
    PC1097 PC1036 PC1074 PC1004
    1U_0201_6.3V6M 1U_0201_6.3V6M 22U_0603_6.3V6M 22U_0603_6.3V6M
    2

    PC1159 2 1 2 1
    B

    B
    22U_0603_6.3V6M

    1
    PC1092 PC1037 PC1070 PC1005
    1U_0201_6.3V6M 1U_0201_6.3V6M 22U_0603_6.3V6M 22U_0603_6.3V6M
    2

    1
    @

    PC1154 2 1 2 1
    22U_0603_6.3V6M

    1
    PC1098 PC1038 PC1061 PC1006
    1U_0201_6.3V6M 1U_0201_6.3V6M 22U_0603_6.3V6M 22U_0603_6.3V6M
    2

    PC1161 2 1 2 1
    22U_0603_6.3V6M

    1
    @

    @
    PC1050 PC1039 PC1071 PC1007
    1U_0201_6.3V6M 1U_0201_6.3V6M 22U_0603_6.3V6M 22U_0603_6.3V6M
    2

    PC1163 2 1
    22U_0603_6.3V6M

    1
    @
    PC1084 PC1066 PC1008
    1U_0201_6.3V6M 22U_0603_6.3V6M 22U_0603_6.3V6M
    2

    1
    @

    PC1155 2 1 2 1
    22U_0603_6.3V6M

    1
    For GTX

    @
    PC1052 PC1086 PC1073 PC1009
    1U_0201_6.3V6M 1U_0201_6.3V6M 22U_0603_6.3V6M 22U_0603_6.3V6M
    2

    1
    @

    PC1156 2 1 2 1
    22U_0603 * 8 pcs
    Primary Side.
    22U_0603 * 4 pcs + 1U_0201*7 pcs
    Back Side.
    VCC_SA Place on CPU

    22U_0603_6.3V6M

    1
    @
    PC1053 PC1085 PC1010
    1U_0201_6.3V6M 1U_0201_6.3V6M 22U_0603_6.3V6M
    2 1

    1
    @
    PC1088 PC1075 PC1011
    Security Classification
    MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.
    DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
    AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
    THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL

    1U_0201_6.3V6M 22U_0603_6.3V6M 22U_0603_6.3V6M


    2 1 2 1
    Issued Date

    1
    @
    PC1126 PC1087 PC1064 PC1012
    1U_0201_6.3V6M 1U_0201_6.3V6M 22U_0603_6.3V6M 22U_0603_6.3V6M
    2 1 2 1

    1
    @
    PC1164 PC1089 PC1065 PC1013
    1U_0201_6.3V6M 1U_0201_6.3V6M 22U_0603_6.3V6M 22U_0603_6.3V6M
    C

    C
    2 1

    PC1125
    1U_0201_6.3V6M
    2014/11/05

    +VCC_GT
    Compal Secret Data

    +VCC_SA
    Deciphered Date

    2 1
    2

    1
    +

    330U_D2_2V_Y
    PC1040 PC1133 PC1014

    22U_0603 * 13 pcs +330u_D2*2 pcs


    Primary Side.
    22U_0603 * 13 pcs +1U_0201*12 pcs
    Back Side.
    VCC_GT Place on CPU
    PC1063
    1U_0201_6.3V6M 22U_0603_6.3V6M 22U_0603_6.3V6M
    2 1
    2

    PC1041 PC1137 PC1015


    1U_0201_6.3V6M 22U_0603_6.3V6M 22U_0603_6.3V6M
    2 1
    2

    1
    @

    2 1 PC1042 PC1129 PC1016


    1U_0201_6.3V6M 22U_0603_6.3V6M 22U_0603_6.3V6M
    2

    1
    D

    D
    PC1153 PC1057 2 1 2 1
    2014/12/15

    1U_0201_6.3V6M 22U_0603_6.3V6M
    2

    1
    @

    2 1 @ PC1181 PC1043 PC1132 PC1017


    22U_0603_6.3V6M 1U_0201_6.3V6M 22U_0603_6.3V6M 22U_0603_6.3V6M
    2

    PC1147 PC1058 2 1 2 1
    1U_0201_6.3V6M 22U_0603_6.3V6M
    2

    1
    @

    2 1 @ PC1180 PC1044 PC1136 PC1018


    22U_0603_6.3V6M 1U_0201_6.3V6M 22U_0603_6.3V6M 22U_0603_6.3V6M
    2

    PC1148 PC1059 2 1 2 1
    1U_0201_6.3V6M 22U_0603_6.3V6M
    2

    2 1 @ PC1177 PC1045 PC1134 PC1019


    22U_0603_6.3V6M 1U_0201_6.3V6M 22U_0603_6.3V6M 22U_0603_6.3V6M
    2

    1
    DELL CONFIDENTIAL/PROPRIETARY

    PC1149 PC1060 2 1 2 1
    1U_0201_6.3V6M 22U_0603_6.3V6M
    2

    2 1 PC1179 PC1046 PC1135 PC1020


    22U_0603_6.3V6M 1U_0201_6.3V6M 22U_0603_6.3V6M 22U_0603_6.3V6M
    2

    1
    @

    PC1150 PC1139 2 1 2 1
    Date:

    Size

    Title

    1U_0201_6.3V6M 22U_0603_6.3V6M
    2

    1
    @

    2 1 @ PC1176 PC1047 PC1138 PC1021


    22U_0603_6.3V6M 1U_0201_6.3V6M 22U_0603_6.3V6M 22U_0603_6.3V6M
    2

    1
    Document Number

    PC1151 PC1140 2 1 2 1
    Tuesday, July 28, 2015

    PWR_CPU&VGA bulk and MLCC

    1U_0201_6.3V6M 22U_0603_6.3V6M
    2

    1
    @

    2 1 @ PC1178 PC1048 PC1027 PC1022


    22U_0603_6.3V6M 1U_0201_6.3V6M 22U_0603_6.3V6M 22U_0603_6.3V6M
    2

    PC1152 PC1141 2 1 2 1
    Compal Electronics, Inc.

    1U_0201_6.3V6M 22U_0603_6.3V6M
    2

    1
    @

    @ PC1175 PC1049 PC1028 PC1023


    22U_0603_6.3V6M 1U_0201_6.3V6M 22U_0603_6.3V6M 22U_0603_6.3V6M
    2

    PC1142 2 1 2 1
    22U_0603_6.3V6M
    2

    1
    @

    @ PC1182 PC1055 PC1130 PC1024


    22U_0603_6.3V6M 1U_0201_6.3V6M 22U_0603_6.3V6M 22U_0603_6.3V6M
    2

    PC1143 2 1 2 1
    22U_0603_6.3V6M
    2

    @ PC1184 PC1056 PC1029 PC1025


    E

    22U_0603_6.3V6M 1U_0201_6.3V6M 22U_0603_6.3V6M 22U_0603_6.3V6M


    2

    PC1144 2 1
    Sheet

    22U_0603_6.3V6M
    2

    @ PC1183 PC1131 PC1026


    22U_0603_6.3V6M 22U_0603_6.3V6M 22U_0603_6.3V6M
    2

    PC1145
    42

    22U_0603_6.3V6M
    2

    1
    of

    PC1146
    22U_0603_6.3V6M
    55

    Rev
    X00(0.1)

    1
    5 4 3 2 1

    unmount PRV5 for 2 phase select


    +3VS_DGPU
    @VGA@ PR801
    DGPU_PSI <48>
    10K_0402_1%
    1 2

    .1U_0402_16V7K
    VGA_EN

    1M_0402_1%
    1
    @VGA@
    1

    VGA@
    PC801

    PR825
    @VGA@ PR823 +19VB_VGA PL801
    PSI :
    Vinafix.com 0_0402_5% @EMI@_VGA@

    2
    1 2 HCB2012KF-121T50_0805
    1 phase with DEM 0V to 0.8V DGPU_MAIN_EN <48,50>

    2
    2 1
    1 phase with CCM 1.2V to 1.8V +3VS +19VB_VGA
    +19VB

    <48>
    DGPU_VID

    10U_0805_25V6K

    10U_0805_25V6K

    10U_0805_25V6K

    10U_0805_25V6K
    2 phase with CCM 2.4V to 5.5V

    68P_0402_50V8J
    RF@_VGA@ PC813

    @RF@_VGA@ PC814
    0.1U_0402_25V6
    D @ PJP801 D

    1
    VGA@ PC2118

    VGA@ PC2119

    VGA@ PC2120

    VGA@ PC2121
    2 1
    2 1

    10K_0402_5%

    10K_0402_5%
    2

    2
    0_0402_5%
    JUMP_43X79

    2
    @VGA@ PR804

    @VGA@ PR803

    @VGA@ PR802
    EN High Threshold = 1.6V

    1
    VGA@ PC802 @VGA@ PR819
    2700P_0402_50V7K 0_0603_5%
    Config B 2 1 1
    BST1_VGA 2BST1_VGA_R

    1
    Vboot=0.9V
    PL802

    D1

    G1
    VGA@ PR806 VGA@ PR805 VGA@
    20K_0402_1% 20K_0402_1% 0.36UH_PDME064T-R36MS1R405_24A_20% +GPU_CORE
    VREF_VGA 2 1 2 1REFADJ VGA@ 7 LX1_VGA 1 2
    PU801 D2/S1

    1
    VGA@ PC808 VGA@
    VGA@ PR824 VGA@ PR808 VGA@ PR807 PQ800

    G2
    S2

    S2

    S2
    VID

    PSI

    EN

    UGATE1

    BOOT1

    EMI@_VGA@
    680P_0402_50V7K 4.7_1206_5%
    0_0402_5% 18K_0402_1% 2K_0402_1% 0.1U_0603_25V7K AON6992_DFN5X6D-8-7

    2
    2 1 2 1 2 1

    330U_D2_2V_Y

    330U_D2_2V_Y
    1 1

    PR821

    VGA@ PC816

    VGA@ PC817
    6 20 LX1_VGA
    REFADJ PHASE1 + +

    1SNUB_VGA1 1
    REFIN_VGA 7 19 LG1_VGA
    VGA@ PC803 REFIN LGATE1 @VGA@ PR817 2 2

    7.5K_0402_1%
    .1U_0603_25V7K 0_0402_5%

    EMI@_VGA@
    1 2 VREF_VGA 8 18 PVCC_VGA 1 2
    VREF PVCC +5VS

    VGA@ PR818
    1

    PC819
    RT8812AGQW_WQFN20_3X3 VGA@ PC807
    VGA@ PR809 TON_VGA 9 17 LG2_VGA PR818 : OCP setting
    620K_0402_1% TON LGATE2 1U_0603_10V6K

    2
    +19VB_VGA 2 1
    +19VB_VGA

    2
    10 16 LX2_VGA
    RGND PHASE2 +19VB_VGA

    UGATE2
    PGOOD

    BOOT2
    VSNS
    GND

    SS
    VGA@ PR810
    100_0402_1% +19VB_VGA

    21

    11

    12

    13

    14

    15
    1 2

    1
    VGA@ PC806 UG2_VGA
    C C
    @VGA@ PR811 0.1U_0603_25V7K

    2
    0_0402_5% @VGA@ PR816
    <45> NVVDD_GND_SENSE 1 2 NVVDD_GND_SENSE_R 0_0603_5%

    1
    BST2_VGA1 2 BST2_VGA_R

    1
    @VGA@ PC805 PL803

    D1

    G1
    1

    @VGA@ PC804 VGA@


    .1U_0402_16V7K 0.36UH_PDME064T-R36MS1R405_24A_20% +GPU_CORE

    2
    @VGA@ PR812 1000P_0402_50V7K UG2_VGA 7 LX2_VGA 1 2
    2

    D2/S1

    EMI@_VGA@
    4.7_1206_5%
    0_0402_5%

    2
    <45> NVVDD_SENSE 1 2 NVVDD_SENSE_R VGA@

    PR822
    PQ801

    G2
    S2

    S2

    S2
    DGPU_PWROK <12,23,45,49,50>
    AON6992_DFN5X6D-8-7
    VGA@ PR813

    6
    100_0402_1% VGA@ PR814

    1SNUB_VGA2 1
    1 2 10K_0402_5%
    +GPU_CORE 2 1 +3VS

    680P_0402_50V7K
    EMI@_VGA@
    LG2_VGA

    PC820
    2
    +GPU_CORE Under GPU Core +GPU_CORE
    GB4-128 package
    4.7U_0603_6.3V6M

    4.7U_0603_6.3V6M

    4.7U_0603_6.3V6M

    4.7U_0603_6.3V6M

    4.7U_0603_6.3V6M

    4.7U_0603_6.3V6M

    4.7U_0603_6.3V6M

    4.7U_0603_6.3V6M

    4.7U_0603_6.3V6M

    4.7U_0603_6.3V6M
    VGA@ PC821

    VGA@ PC822

    VGA@ PC823

    VGA@ PC824

    VGA@ PC825

    VGA@ PC826

    VGA@ PC827

    VGA@ PC828

    VGA@ PC829

    VGA@ PC830

    Remove GPU OTP circuit for HW request

    @RF@_VGA@ PC858

    @RF@_VGA@ PC859

    @RF@_VGA@ PC860

    @RF@_VGA@ PC861
    0.1U_0402_25V6

    0.1U_0402_25V6

    0.1U_0402_25V6

    0.1U_0402_25V6
    1

    1
    2

    2
    1U_0402_16V6K

    1U_0402_16V6K

    1U_0402_16V6K

    1U_0402_16V6K

    VGA_core
    VGA@ PC835

    VGA@ PC841

    VGA@ PC847

    VGA@ PC844

    N16S-GM
    1

    TDC 20A
    B Peak Current 32A B
    2

    OCP current 40A


    Choke DCR 1.4 +-5%m ohm
    +GPU_CORE Near GPU Core
    22U_0805_6.3V6M

    47U_0805_6.3V6M

    4.7U_0603_6.3V6M

    4.7U_0603_6.3V6M

    4.7U_0603_6.3V6M

    4.7U_0603_6.3V6M

    4.7U_0603_6.3V6M

    4.7U_0603_6.3V6M
    VGA@ PC849

    VGA@ PC840

    VGA@ PC850

    VGA@ PC842

    VGA@ PC843

    VGA@ PC848

    VGA@ PC845

    VGA@ PC846

    1
    1

    1
    2

    A A

    DELL CONFIDENTIAL/PROPRIETARY
    Security Classification Compal Secret Data Compal Electronics, Inc.
    Issued Date 2014/11/05 Deciphered Date 2014/12/15 Title
    PWR_VGA_CORE
    THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
    AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&DSize Document Number Rev
    DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS Custom X00(0.1)
    MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.
    Date: Tuesday, July 28, 2015 Sheet 43 of 55
    5 4 3 2 1
    5 4 3 2 1

    Version Change List ( P. I. R. List )


    Request Issue Solution
    Item Page# Title Date Owner Description Description Rev.
    Vinafix.com
    D D
    1 38 PWR 2015/04/27 COMPAL reserve from EE request add PR315 and net to POK 0.2

    2 39 PWR 2015/04/27 COMPAL reserve from EE request add PR507 and net to POK 0.2

    3 40 PWR 2015/04/27 COMPAL add from RF request pop PR627 and PC622 0.2

    4 40 PWR 2015/04/27 COMPAL abnormal shutdown when enter S3 change PU606.12 from +5VS to +5VALW 0.2

    5 41 PWR 2015/04/27 COMPAL abnormal shutdown when enter S3 change PU603.2 and PU605.2 net from +5VS to +5VALW 0.2
    change PU603.12 and PU605.12 net from +5VS to IMVP_VR_ON

    6 39 PWR 2015/06/09 COMPAL change from EE request swap resister from PR504 to PR507 0.3

    7 35 PWR 2015/06/09 COMPAL change from EMI request change PC2,PC4 from 100p to 0.1u 0.3

    8 36 PWR 2015/06/09 COMPAL change from EMI request add PC765 0.3
    C C

    9 34 PWR 2015/07/14 COMPAL revise S5 power consumption issue delete PQ1,PR2,PR5,PR7,PR10

    10 COMPAL

    B B

    A A

    DELL CONFIDENTIAL/PROPRIETARY
    Security Classification Compal Secret Data Compal Electronics, Inc.
    Issued Date 2014/11/05 Deciphered Date 2014/12/15 Title

    THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
    PWR_Change list
    AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&DSize Document Number Rev
    DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS X00(0.1)
    MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.
    Date: Tuesday, July 28, 2015 Sheet 44 of 55
    5 4 3 2 1
    5 4 3 2 1

    UV1A
    Main Func : dGPU COMMON @
    1/14 PCI_EXPRESS
    Place near balls Place near BGA
    1.0V
    +1.0VS_DGPU

    1 1 1 1 1 1 1
    AB6 PEX_WAKE#
    CV23 CV22 CV2 CV21 CV24 CV9 CV7

    1U_0402_6.3V6K

    1U_0402_6.3V6K

    10U_0603_6.3V6M

    10U_0603_6.3V6M

    22U_0603_6.3V6M

    22U_0603_6.3V6M
    AA22 @ @ DIS@ @ DIS@ @ @

    4.7U_0603_6.3V6K
    PEX_IOVDD
    PLT_RST_VGA_MON# RV9 1 @ 2 0_0402_5% PLT_RST_VGA# AC7 PEX_IOVDD AB23 2 2 2 2 2 2 2
    PEX_RST#
    PEX_IOVDD AC24
    CLKREQ_PCIE#0_R AC6 PEX_CLKREQ# PEX_IOVDD AD25

    PCIE CLK
    <11> CLK_PEG_VGA
    Vinafix.com AE8
    AD8
    PEX_REFCLK
    PEX_REFCLK#
    PEX_IOVDD
    PEX_IOVDD
    AE26
    AE27
    <11> CLK_PEG_VGA#
    DIS@
    D (From PCH CLKOUT0) PCIE_CRX_GTX_P1 CV11 1 2 0.22U_0402_16V7K PCIE_CRX_C_GTX_P1 AC9 D
    <10> PCIE_CRX_GTX_P1 PEX_TX0
    PCIE_CRX_GTX_N1 CV12 1 2 0.22U_0402_16V7K PCIE_CRX_C_GTX_N1 AB9 PEX_TX0#
    <10> PCIE_CRX_GTX_N1 +1.0VS_DGPU
    Place near balls Place near BGA
    PCIE_CTX_C_GRX_P1 DIS@ AG6 PEX_RX0 1.0V
    <10> PCIE_CTX_C_GRX_P1
    PCIE_CTX_C_GRX_N1 AG7 PEX_RX0# PEX_IOVDDQ AA10
    <10> PCIE_CTX_C_GRX_N1
    DIS@ PEX_IOVDDQ AA12 1 1 1 1 1 1 1
    PCIE_CRX_GTX_P2 CV13 1 2 0.22U_0402_16V7K PCIE_CRX_C_GTX_P2 AB10 PEX_TX1 PEX_IOVDDQ AA13
    <10> PCIE_CRX_GTX_P2
    PCIE_CRX_GTX_N2 CV14 1 2 0.22U_0402_16V7K PCIE_CRX_C_GTX_N2 AC10 PEX_TX1# PEX_IOVDDQ AA16 CV27 CV26 CV3 CV25 CV28 CV10 CV8
    <10> PCIE_CRX_GTX_N2

    1U_0402_6.3V6K

    1U_0402_6.3V6K

    10U_0603_6.3V6M

    10U_0603_6.3V6M

    22U_0603_6.3V6M

    22U_0603_6.3V6M
    AA18 DIS@ @ @ @ @ @ DIS@

    4.7U_0603_6.3V6K
    PEX_IOVDDQ
    PCIE_CTX_C_GRX_P2 DIS@ AF7 PEX_IOVDDQ AA19 2 2 2 2 2 2 2
    <10> PCIE_CTX_C_GRX_P2 PEX_RX1
    PCIE_CTX_C_GRX_N2 AE7 PEX_RX1# PEX_IOVDDQ AA20
    <10> PCIE_CTX_C_GRX_N2
    DIS@ PEX_IOVDDQ AA21
    PCIE X4 Bus PCIE_CRX_GTX_P3 CV15 1 2 0.22U_0402_16V7K PCIE_CRX_C_GTX_P3 AD11 PEX_TX2 PEX_IOVDDQ AB22
    <10> PCIE_CRX_GTX_P3
    PCIE_CRX_GTX_N3 CV16 1 2 0.22U_0402_16V7K PCIE_CRX_C_GTX_N3 AC11 PEX_TX2# PEX_IOVDDQ AC23
    <10> PCIE_CRX_GTX_N3
    (Link to CPU Port 1~4) PEX_IOVDDQ AD24
    PCIE_CTX_C_GRX_P3 DIS@ AE9 PEX_RX2 PEX_IOVDDQ AE25
    <10> PCIE_CTX_C_GRX_P3
    PCIE_CTX_C_GRX_N3 AF9 PEX_RX2# PEX_IOVDDQ AF26
    <10> PCIE_CTX_C_GRX_N3
    DIS@ PEX_IOVDDQ AF27
    PCIE_CRX_GTX_P4 CV17 1 2 0.22U_0402_16V7K PCIE_CRX_C_GTX_P4 AC12 PEX_TX3
    <10> PCIE_CRX_GTX_P4
    PCIE_CRX_GTX_N4 CV18 1 2 0.22U_0402_16V7K PCIE_CRX_C_GTX_N4 AB12 PEX_TX3#
    <10> PCIE_CRX_GTX_N4
    PCIE_CTX_C_GRX_P4 DIS@ AG9 PEX_RX3
    <10> PCIE_CTX_C_GRX_P4
    PCIE_CTX_C_GRX_N4 AG10 PEX_RX3#
    <10> PCIE_CTX_C_GRX_N4
    AB13 PEX_TX4
    AC13 PEX_TX4#

    AF10 PEX_RX4
    AE10 PEX_RX4#

    AD14 NC FOR GF119


    PEX_TX5
    AC14 PEX_TX5# PEX_PLL_HVDD AA8
    C PEX_PLL_HVDD AA9 C

    NC FOR GM108
    AE12 +3VS_DGPU_AON
    PEX_RX5 Place near BGA
    AF12 PEX_RX5#
    PEX_SVDD_3V3 AB8
    AC15 PEX_TX6 1 1 1
    +3VS_DGPU_AON AB15
    Reset Control PEX_TX6#
    CV19 CV5 CV4

    0.1U_0201_10V6K
    AG12 DIS@ DIS@ DIS@

    4.7U_0603_6.3V6K

    4.7U_0603_6.3V6K
    PEX_RX6
    5

    AG13 2 2 2
    PEX_RX6#
    1
    P

    <11,22,23,25,28> PLT_RST# B 4 AB16 PEX_TX7


    Y PLT_RST_VGA_MON# <48>
    2 AC16 PEX_TX7#
    <9> DGPU_HOLD_RST# A
    G

    (From PCH)
    UV12 +3VS_DGPU_AON AF13 PEX_RX7
    3

    TC7SH08FUF_SSOP5 AE13 PEX_RX7#


    DIS@
    5

    AD17 PEX_TX8
    1 AC17 PEX_TX8#
    P

    B 4
    Y PLT_RST_VGA# <48>
    2 AE15 PEX_RX8
    <48> PLT_RST_VGA_HOLD# A
    G

    (From GPU) AF15 PEX_RX8#


    UV13 RV66
    3

    TC7SH08FUF_SSOP5 10K_0402_5% AC18 F2 NVVDD_SENSE


    DIS@ DIS@ AB18
    PEX_TX9
    PEX_TX9#
    VDD_SENSE NVVDD_SENSE <43> To POWER
    trace width: 16mils
    2

    AG15 PEX_RX9 GND_SENSE F1 NVVDD_GND_SENSE differential voltage sensing.


    NVVDD_GND_SENSE <43>
    AG16 PEX_RX9# differential signal routing.
    AB19 PEX_TX10
    AC19 PEX_TX10#

    AF16 PEX_RX10
    B AE16 B
    PEX_RX10#

    NC FOR GF117/GK208/GM108
    AD20 PEX_TX11
    AC20 PEX_TX11#

    AE18 PEX_RX11
    AF18
    DGPU_PWROK CLK_REQ
    <12,43,49,50> PEX_RX11#

    AC21 PEX_TX12
    AB21 PEX_TX12#
    +3VS_DGPU_AON AG18 PEX_RX12 PEX_TSTCLK_OUT AF22 PEX_PLL_CLK_OUT RV4 2 @ 1 200_0402_1%
    AG19 PEX_RX12# PEX_TSTCLK_OUT# AE22 PEX_PLL_CLK_OUT#
    +1.0VS_DGPU
    1

    AD23 PEX_TX13 Place near BALL Place near BGA


    RV68 AE23 PEX_TX13# 1.0V
    10K_0402_5%
    2

    @ AF19 AA14 PEX_PLLVDD_GPU 0_0402_5% 2 1 RV12


    G

    PEX_RX13 PEX_PLLVDD
    AE19 PEX_RX13# PEX_PLLVDD AA15 1 1 1
    2

    1 3 CLKREQ_PCIE#0_R
    <11> PEG_CLKREQ#
    AF24 CV20 CV29 CV6
    D

    PEX_TX14

    0.1U_0201_10V6K

    1U_0402_6.3V6K

    4.7U_0603_6.3V6K
    (To SOC) AE24 PEX_TX14# DIS@ DIS@ DIS@
    QV3 2 2 2
    2N7002E_SOT23-3 AE21 PEX_RX14
    @ AF21 PEX_RX14#
    TESTMODE AD9 GPU_TESTMODE
    AG24 PEX_TX15
    0_0402_5%2 1 RV5 AG25 PEX_TX15#

    AG21 PEX_RX15
    AG22 PEX_RX15#

    A A
    GPU_TESTMODE <48>
    PEX_TERMP AF25

    UV1 DIS@ PEX_TERMP RV6 1 DIS@ 2 2.49K_0402_1%


    N16S-GT-S-A2_BGA595

    S IC N16S-GM-S-A2 BGA 595P GPU A31 !


    Security Classification
    2014/05/19
    Compal Secret Data
    2015/12/31 Title
    Compal Electronics, Inc.
    Issued Date Deciphered Date
    SA00008R81L
    THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
    NV(1/5)-PCIE
    AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&DSize Document Number Rev
    DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS Custom 0.2
    MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC. LA-C071P
    Date: Tuesday, July 28, 2015 Sheet 45 of 55
    5 4 3 2 1
    5 4 3 2 1

    Main Func : dGPU UV1G


    COMMON @ IFPA/B
    UV1H
    COMMON @ IFPC
    5/14 IFPC
    UV1J
    COMMON @ IFPE/F 4/14 IFPAB

    T6
    IFPC

    7/14 IFPEF IFPC_RSET GF119/GK208


    IFPA_TXC# AC4
    GF119/GK208 IFPA_TXC AC3 DVI/HDMI DP
    DVI-DL DVI-SL/HDMI DP

    NC FOR GF117/GM108
    AA6 IFPAB_RSET M7 IFPC_PLLVDD I2CW_SDA IFPC_AUX# N5
    I2CY_SDA I2CY_SDA
    Vinafix.com
    IFPE_AUX# J3 IFPA_TXD0# Y3 N7 IFPC_PLLVDD I2CW_SCL IFPC_AUX N4

    NC FOR GF117/GM108
    I2CY_SCL I2CY_SCL IFPE_AUX J2 IFPA_TXD0 Y4
    J7 IFPEF_PLLVDD
    V7 IFPAB_PLLVDD TXC IFPC_L3# N3
    D IFPE_L3# J1 IFPA_TXD1# AA2 N2 D
    TXC TXC TXC IFPC_L3
    K1 W7 AA3

    NC FOR GF117/GM108
    IFPE_L3 IFPAB_PLLVDD IFPA_TXD1
    TXC TXC
    K7 R3

    NC FOR GF117/GM108
    IFPEF_PLLVDD NC FOR GF117/GK208/GM108 TXD0 IFPC_L2#
    IFPE_L2# K3 TXD0 IFPC_L2 R2
    TXD0 TXD0 K2 AA1
    IFPE_L2 IFPA_TXD2#
    TXD0 TXD0 AB1 R1
    IFPA_TXD2 TXD1 IFPC_L1#
    K6 IFPEF_RSET IFPE_L1# M3 TXD1 IFPC_L1 T1
    TXD1 TXD1
    M2

    NC FOR GF117/GM108
    IFPE_L1
    TXD1 TXD1
    IFPA_TXD3# AA5 IFPC_L0# T3
    TXD2
    IFPE_L0# M1 IFPA_TXD3 AA4 TXD2 IFPC_L0 T2
    TXD2 TXD2 N1
    IFPE_L0
    TXD2 TXD2
    IFPB_TXC# AB4 GF117
    IFPE NC FOR GK208
    IFPB_TXC AB5 P6 IFPC_IOVDD GPIO15 C3
    NC

    HPD_E GPIO18 C2 W6 IFPA_IOVDD IFPB_TXD4# AB2


    HPD_E
    IFPB_TXD4 AB3 N16S-GT-S-A2_BGA595
    Y6 IFPB_IOVDD
    NC FOR GF117

    H6 IFPE_IOVDD
    IFPB_TXD5#
    IFPB_TXD5
    AD2
    AD3
    UV1I
    COMMON @ IFPD
    GF119/GK208 6/14 IFPD
    J6 IFPF_IOVDD DVI-DL DVI-SL/HDMI DP AD1
    IFPB_TXD6#
    IFPF_AUX# H4 IFPB_TXD6 AE1 U6 GF119/GK208
    I2CZ_SDA IFPD_RSET
    I2CZ_SCL IFPF_AUX H3
    DVI/HDMI DP
    IFPB_TXD7# AD5
    TXC IFPF_L3# J5 IFPB_TXD7 AD4 T7 IFPD_PLLVDD I2CX_SDA IFPD_AUX# P4
    NC FOR GF117/GM108

    IFPF_L3 J4 IFPD_AUX P3

    NC FOR GF117/GM108
    TXC I2CX_SCL
    R7 IFPD_PLLVDD
    C IFPF_L2# K5 C

    NC FOR GF117/GM108
    TXD3 TXD0
    TXD3 TXD0 IFPF_L2 K4 GF117 TXC IFPD_L3# R5
    TXC IFPD_L3 R4
    TXD4 TXD1 IFPF_L1# L4 NC GPIO14 B3
    IFPF TXD4 TXD1 IFPF_L1 L3
    IFPAB TXD0
    IFPD_L2# T5
    TXD0 IFPD_L2 T4
    TXD5 TXD2 IFPF_L0# M5 N16S-GT-S-A2_BGA595
    TXD5 TXD2 IFPF_L0 M4 TXD1 IFPD_L1# U4
    IFPD TXD1 IFPD_L1 U3
    NC FOR GK208 V4
    IFPD_L0#
    TXD2
    TXD2 IFPD_L0 V3
    HPD_F GPIO19 F7

    GF117
    NC FOR GF117 R6 D4
    IFPD_IOVDD GPIO17
    NC
    +1.0VS_DGPU 1.0V
    N16S-GT-S-A2_BGA595 Place near balls
    DIS@

    UV1K
    COMMON @
    DAC_A LV5 1 2 MPZ1608S300AT_2P

    CV32
    1
    CV31
    1
    GPU_PLLVDD

    N16S-GT-S-A2_BGA595
    3/14 DACA 22U_0603_6.3V6M 0.1U_0402_10V7K
    DIS@ DIS@
    GF117/GM108 GF117 GM108/GK208 2 2
    W5 DACA_VDD NC NC I2CA_SCL B7 I2CA_SCL
    I2CA_SCL <48>
    NC I2CA_SDA A7 I2CA_SDA
    AE2

    AF2
    DACA_VREF

    DACA_RSET
    TSEN_VREF

    NC NC DACA_HSYNC AE3
    I2CA_SDA <48>

    +1.0VS_DGPU 1.0V Place near BGA Place near balls


    UV1M
    COMMON @
    9/14 XTAL_PLL
    X'TAL
    NC DACA_VSYNC AE4
    B DIS@ L6 B
    PLLVDD
    LV3 1 2 TDK MPZ1608S331AT _2P VID_PLLVDD M6 SP_PLLVDD
    DACA_RED AG3 1 1 1 1 1
    NC
    N6 VID_PLLVDD NC
    DACA_GREEN AF4 CV61 CV35 CV30 CV34 CV60 +3VS_DGPU_AON
    NC
    22U_0603_6.3V6M

    22U_0603_6.3V6M

    10U_0603_6.3V6M

    0.1U_0402_10V7K

    0.1U_0402_10V7K
    DIS@ DIS@ DIS@ DIS@ DIS@ GF117/GM108
    2 2 2 2 2 GF119/GK208
    NC DACA_BLUE AF3
    XTAL_OUTBUFF 1 @ 2
    GM108 10K_0402_1% RV23
    GK208 2 DIS@ 1 A10 XTALOUTBUFF C10 1 DIS@ 2
    GF117 XTALSSIN
    RV21 10K_0402_1% 10K_0402_1% RV20
    N16S-GT-S-A2_BGA595
    C11 XTALIN XTALOUT B10 XTAL_OUT

    N16S-GT-S-A2_BGA595

    1
    90-OHM DIFF Impedance for XTALIN & XTALOUT. RV24
    1K_0402_1%
    DIS_XTAL@
    YV1 DIS_XTAL@

    2
    Crystal
    4 3 XTAL_OUT_R
    GND OUT
    1
    XTALIN 1 2 CV36
    IN GND 15P_0402_50V8J
    1
    DIS_XTAL@
    CV37 27MHZ_10PF_7V27000023 2
    15P_0402_50V8J
    2 DIS_XTAL@
    A A

    Place near balls

    Security Classification
    2014/05/19
    Compal Secret Data
    2015/12/31 Title
    Compal Electronics, Inc.
    Issued Date Deciphered Date
    THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
    NV(2/5)-IFP_ABCDEF_DAC_XTAL
    AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&DSize Document Number Rev
    DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS Custom 0.2
    MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC. LA-C071P
    Date: Tuesday, July 28, 2015 Sheet 46 of 55
    5 4 3 2 1
    5 4 3 2 1

    UV1D
    Main Func : dGPU COMMON
    12/14 FBVDDQ
    @

    B26 FBVDDQ
    C25 FBVDDQ
    E23 FBVDDQ UV1F
    +1.35VS_VRAM E26 FBVDDQ COMMON @
    F14 +GPU_CORE UV1E
    Place under GPU FBVDDQ 13/14 GND
    F21 COMMON @ A2 M13
    Vinafix.com
    FBVDDQ GND GND
    G13 FBVDDQ Voltage by GPU SKU 11/14 NVVDD AB17 GND GND M15
    1 1 1 1 1 1 G14 FBVDDQ K10 VDD AB20 GND GND M17
    G15 FBVDDQ K12 VDD AB24 GND GND N10
    D CV40 CV38 CV41 CV42 CV39 CV43 G16 FBVDDQ K14 VDD AC2 GND GND N12 D
    4.7U_0603_6.3V6K

    4.7U_0603_6.3V6K

    1U_0402_6.3V6K

    1U_0402_6.3V6K

    0.1U_0201_10V6K

    0.1U_0201_10V6K
    DIS@ DIS@ DIS@ DIS@ DIS@ DIS@ G18 FBVDDQ K16 VDD AC22 GND GND N14
    2 2 2 2 2 2 G19 K18 AC26 N16
    FBVDDQ VDD GND GND
    G20 FBVDDQ L11 VDD AC5 GND GND N18
    G21
    L22
    L24
    FBVDDQ
    FBVDDQ
    FBVDDQ
    GPU_Decoupling L13
    L15
    L17
    VDD
    VDD
    VDD
    AC8
    AD12
    AD13
    GND
    GND
    GND
    GND
    GND
    GND
    P11
    P13
    P15
    L26
    M21
    N21
    FBVDDQ
    FBVDDQ
    FBVDDQ
    CAPs @ Power M10
    M12
    M14
    VDD
    VDD
    VDD
    A26
    AD15
    AD16
    GND
    GND
    GND
    GND
    GND
    GND
    P17
    P2
    P23
    R21
    T21
    V21
    FBVDDQ
    FBVDDQ
    FBVDDQ
    Page M16
    M18
    N11
    VDD
    VDD
    VDD
    AD18
    AD19
    AD21
    GND
    GND
    GND
    GND
    GND
    GND
    P26
    P5
    R10
    W21 FBVDDQ N13 VDD AD22 GND GND R12
    N15 VDD AE11 GND GND R14
    N17 VDD AE14 GND GND R16
    GF117 P10 AE17 R18
    VDD GND GND
    GF119 P12 AE20 T11
    Place near GPU GK208
    VDD GND GND
    P14 VDD AB11 GND GND T13
    H24 FBVDDQ_AON FBVDDQ
    P16 VDD AF1 GND GND T15
    1 1 H26 FBVDDQ_AON FBVDDQ
    P18 VDD AF11 GND GND T17
    J21 FBVDDQ_AON FBVDDQ
    R11 VDD AF14 GND GND U10
    CV45 CV44 K21 FBVDDQ_AON FBVDDQ
    R13 VDD AF17 GND GND U12
    22U_0603_6.3V6M

    DIS@ 10U_0603_6.3V6M DIS@ R15 AF20 U14


    VDD GND GND
    2 2 R17 AF23 U16
    VDD GND GND
    T10 VDD AF5 GND GND U18
    T12 VDD AF8 GND GND U2
    T14 VDD AG2 GND GND U23
    T16 VDD AG26 GND GND U26
    C T18 VDD AB14 GND GND U5 C
    U11 VDD B1 GND GND V11
    U13 VDD B11 GND GND V13
    U15 VDD B14 GND GND V15
    U17 VDD B17 GND GND V17
    V10 VDD B20 GND GND Y2
    V12 VDD B23 GND GND Y23
    V14 VDD B27 GND GND Y26
    V16 VDD B5 GND GND Y5
    +1.35VS_VRAM V18 VDD B8 GND
    E11 GND
    Near Ball E14 GND
    N16S-GT-S-A2_BGA595 E17 GND
    E2 GND
    FB_CAL_PD_VDDQ D22 40.2_0402_1% 1 DIS@ 2 RV41 E20 GND
    E22 GND
    E25 GND
    FB_CAL_PU_GND C24 42.2_0402_1% 2 DIS@ 1 RV42 E5 GND
    E8 GND
    H2 GND
    FB_CALTERM_GND B25 51.1_0402_1% 2 DIS@ 1 RV43 H23 GND
    H25 GND
    H5 GND
    N16S-GT-S-A2_BGA595 K11 GND
    K13 GND
    K15 GND
    UV1C K17 GND
    COMMON @ L10 GND
    14/14 XVDD/VDD33 Under GPU Near GPU +3VS_DGPU L12 GND
    B L14 B
    GND
    AD10 NC VDD33 G8 0_0402_5% 2 1 RV40 L16 GND
    AD7 NC GM108 VDD33 G9 1 1 1 1 L18 GND
    3V3_AON VDD33 G10 L2 GND
    3V3_AON VDD33 G12 CV69 CV50 CV49 CV48 L23 GND
    0.1U_0201_10V6K

    0.1U_0201_10V6K

    1U_0402_6.3V6K

    4.7U_0603_6.3V6K
    DIS@ DIS@ DIS@ DIS@ L25 GND
    F11 3V3AUX_NC
    2 2 2 2 L5 AA7
    GND GND
    M11 GND GND AB7
    V5 FERMI_RSVD1_NC
    V6 FERMI_RSVD2_NC

    N16S-GT-S-A2_BGA595

    CONFIGURABLE
    POWER CHANNELS
    * nc on substrate Under GPU Near GPU +3VS_DGPU_AON

    G1 XPWR_G1 0_0402_5% 2 1 RV58


    G2 XPWR_G2 1 1 1
    G3 XPWR_G3
    ** XPWR pins are configurable. G4 XPWR_G4 CV46 CV47 CV54
    0.1U_0201_10V6K

    1U_0402_6.3V6K

    4.7U_0603_6.3V6K

    G5 XPWR_G5 DIS@ DIS@ DIS@


    G6 2 2 2
    These pins are not connected on the substrate. XPWR_G6
    G7 XPWR_G7
    Therefore, XPWR pins can be assigned as needed,

    to improve Top layer routing, power delivery. V1 XPWR_V1


    V2 XPWR_V2
    A A

    W1 XPWR_W1
    W2 XPWR_W2
    W3
    W4
    XPWR_W3
    XPWR_W4
    Security Classification
    2014/05/19
    Compal Secret Data
    2015/12/31 Title
    Compal Electronics, Inc.
    Issued Date Deciphered Date
    THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
    NV(3/5)-POWER
    N16S-GT-S-A2_BGA595 AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&DSize Document Number Rev
    DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS Custom 0.2
    MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC. LA-C071P
    Date: Tuesday, July 28, 2015 Sheet 47 of 55
    5 4 3 2 1
    5 4 3 2 1

    Main Func : dGPU UV1L


    COMMON
    10/14 MISC2
    @ +3VS_DGPU
    STRAP
    STRAP0 : PU 49.9K (50K) STRAP

    1
    +3VS_DGPU_AON
    STRAP[1:5] : Reserved E10 VMON_IN0_NC RV80 RV81 RV84
    F10 VMON_IN1_NC ROM_CS# D12 4.99K_0402_1% 4.99K_0402_1% 4.99K_0402_1%
    @ @ @
    ROM_SI B12 ROM_SI

    2
    ROM_SO A12 ROM_SO ROM_SI

    1
    RV47
    49.9K_0402_1%
    RV51
    4.99K_0402_1%
    RV46
    4.99K_0402_1%
    RV45
    4.99K_0402_1% Vinafix.com
    RV61
    10K_0402_1%
    STRAP0
    STRAP1
    STRAP2
    D1
    D2
    E4
    STRAP0
    STRAP1
    STRAP2
    NC FOR
    ROM_SCLK C12 ROM_SCLK ROM_SO
    ROM_SCLK

    1
    DIS@ @ @ @ @ STRAP3 E3 GM108
    STRAP3
    STRAP4 D3 STRAP4 [ROM_SI] : 0x30(PD 20K) RV63 RV64 RV65
    2

    2
    D D
    4.99K_0402_1% 4.99K_0402_1% 24.9K_0402_1%
    STRAP0 H5TC4G63AFR-11C(1.35V) DIS@ DIS@ @
    STRAP1

    2
    STRAP2 C1 STRAP5_NC [ROM_SO] : 0x00(PD 5K)
    STRAP3 BUFRST# D11 GPU_BUFRST
    STRAP4
    Bit3(DEVID_SEL)=0,default.
    Bit2(PCIE_CFG)=0, default.

    1
    STRAPREF0 F6 MULTISTRAP_REF0_GND NC PGOOD D10
    1

    1
    GF117 RV67 Bit1(SMB_ALT_ADDR)=0,I2CS ADR 0x9E. RV65 @ RV65 @

    1
    RV52 RV48 RV50 RV49 RV62 GK208 GF117 GF119 10K_0402_5%
    4.99K_0402_1% 45.3K_0402_1% 15K_0402_1% 4.99K_0402_1% 45.3K_0402_1% RV44 @
    Bit0(VGA_DEVICE)=0,2nd Display.
    GM108 GK208
    @ @ @ @ @ 40.2K_0402_1% F4 MULTISTRAP_REF1_GND NC GM108

    2
    DIS@ [ROM_SCLK] : 0x00(PD 4.99K)
    2

    2
    F5 MULTISTRAP_REF2_GND NC No display output

    2
    10K_0402_1% 15K_0402_1%
    SD034100280 SD034150280
    N16S-GT-S-A2_BGA595

    RAM_CFG[3:0]
    (ROM_SI) BAV00

    C C

    0x4(PD 24.9K)
    V (SSI)

    0x1(PD 10K)

    0x2(PD 15K)
    Internal Thermal Sensor
    <45,48> PLT_RST_VGA# Link to PCH SML1
    PU @ PCH SIDE

    5
    QV2B DIS@
    DMN65D8LDW-7_SOT363-6
    I2CS_SCL 4 3
    GPU_THM_SMBCLK <8,23,30>
    RV74 1 @ 2 0_0402_5%

    2
    QV2A DIS@
    DMN65D8LDW-7_SOT363-6
    I2CS_SDA 1 6
    GPU_THM_SMBDAT <8,23,30>
    RV75 1 @ 2 0_0402_5%

    UV1N
    COMMON
    8/14 MISC1
    @ GPIO +3VS_DGPU_AON

    B I2CS_SCL D9 I2CS_SCL 2.2K_0402_5% 1 DIS@ 2 RV203 I2CS SMBUS: B


    D8 I2CS_SDA 2.2K_0402_5% 1 DIS@ 2 RV204
    I2CS_SDA 0x96 and 0x9E(Default) +3VS_DGPU_AON
    I2CC_SCL A9 I2CC_SCL 2.2K_0402_5% 1 @ 2 RV205
    I2CC_SDA B9 I2CC_SDA 2.2K_0402_5% 1 @ 2 RV206 RPV5 DIS@
    DGPU_MAIN_EN 1 8
    DGPU_PSI 2 7
    E12 GF117 GPU_PWR_LEVEL 3 6
    THERMDN
    NC I2CB_SCL C9 I2CB_SCL 4 5
    F12 THERMDP NC I2CB_SDA C8 I2CB_SDA
    10K_0804_8P4R_5%

    T231 TP@ GPU_JTAG_TCK AE5 JTAG_TCK GPIO8_OVERT# 1 DIS@ 2


    GPU_JTAG_TMS AD6 100K_0402_5% RV69
    T232
    T242
    TP@
    TP@ GPU_JTAG_TDI AE6
    AF6
    JTAG_TMS
    JTAG_TDI For GC6 2.0
    T243 TP@ GPU_JTAG_TDO JTAG_TDO RPV7 DIS@
    GPU_JTAG_TRST# AG4 C6 GPIO0_GC6_FB_EN 0_0402_5%1 GC6@ 2 RV202 PLT_RST_VGA_MON# 1 8
    JTAG_TRST# GPIO0 GC6_FB_EN <9,49>
    GPIO1 B2 PLT_RST_VGA_HOLD# 2 7
    GPIO2 D6 GPU_EVENT#_D 3 6
    GPIO3 C7 FB_CLAMP 4 5
    <49> FB_CLAMP
    GPIO4 F9
    GPIO5 A3 DGPU_MAIN_EN DIS@ 10K_0804_8P4R_5%
    DGPU_MAIN_EN <43,50>
    GK208 GPIO6 A4 GPU_EVENT#_D 2 1
    GPU_EVENT# <9>
    GM108 GPIO7 B6 RB751S40T1G_SOD523-2 DV1
    OVERT GPIO8 A6 GPIO8_OVERT# RPV6 DIS@
    GPIO9 F8 GPIO9_ALERT# GPIO9_ALERT# 1 8
    GPIO10 C5 GPU_JTAG_TRST# 2 7
    GPIO11 E7 DGPU_VID GPU_TESTMODE 3 6
    D7 GPU_PWR_LEVEL
    DGPU_VID <43> To DGPU VR <45> GPU_TESTMODE
    4 5
    GPIO12 GPU_PWR_LEVEL <23> From EC
    GPIO13 B4 DGPU_PSI Shutdown System when GPU over Temp.
    DGPU_PSI <43> To DGPU VR 10K_0804_8P4R_5%
    GM108 GK208 GF117 GF119 <45,48> PLT_RST_VGA#
    RPV3 @
    GPIO16 GPIO16 NC GPIO16 D5 I2CA_SCL 1 8
    <46> I2CA_SCL
    GPIO20 GPIO20 NC GPIO20 E6 I2CA_SDA 2 7
    <46> I2CA_SDA
    A GPIO21 GPIO8 NC GPIO21 C4 PLT_RST_VGA_HOLD# I2CB_SCL 3 6 A
    PLT_RST_VGA_HOLD# <45>
    2
    G

    I2CB_SDA 4 5
    GPIO8 NC NC NC E9 PLT_RST_VGA_MON# DIS@
    PLT_RST_VGA_MON# <45>
    GPIO8_OVERT# 3 1 2.2K_0804_8P4R_5%
    CMP_VOUT0 <23,36>
    S

    QV4
    N16S-GT-S-A2_BGA595 2N7002KW 1N SOT323-3

    VGA_THERMDN and VGA_THERMDP:


    1. 5mil track width and spacing
    Security Classification
    2014/05/19
    Compal Secret Data
    2015/12/31 Title
    Compal Electronics, Inc.
    2. 5mil grounded gurad tracks width and spacing Issued Date Deciphered Date
    3. ground referenced
    THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
    NV(4/5)-GPIO/Strap
    4. Connect guard tracks to pin5 AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&DSize Document Number Rev
    DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS Custom LA-C071P 0.2
    MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.
    Date: Tuesday, July 28, 2015 Sheet 48 of 55
    5 4 3 2 1
    5 4 3 2 1

    Main Func : dGPU


    +3VS_DGPU_AON +3VS
    For GC6 0_0402_5%1 @ 2 RV208
    0_0402_5%1 2 RV211
    1
    From DG-07158-001_v03_secured(NVDIA Spec)
    CV200
    0.1U_0402_10V7K
    GC6@ 2
    UV23
    MC74VHC1G32DFT2G SC70-5

    Vinafix.com

    5
    GC6@
    GC6_FB_EN 2

    G Vcc
    <9,48> GC6_FB_EN B 4
    Y 1.35V_PWR_EN <50>
    1
    <12,43,45,50> DGPU_PWROK A

    2
    D D

    3
    RV88
    UV1B 10K_0402_5%
    COMMON @ GC6@
    2/14 FBA 1 @ 2
    <51,53> FB_A_D[0..31]

    1
    FB_A_D0 E18 FBA_D0 NC FB_CLAMP F3 FB_CLAMP RV201 0_0402_5%
    FB_CLAMP <48>
    FB_A_D1 F18 FBA_D1
    FB_A_D2 E16 FBA_D2 GF119
    FB_A_D3 F17 FBA_D3 Stuff RV201 if not support GC6
    FB_A_D4 D20 FBA_D4
    FB_A_D5 D21 FBA_D5
    FB_A_D6 F20 FBA_D6
    FB_A_D7 E21 FBA_D7
    FB_A_D8 E15 FBA_D8
    FB_A_D9 D15 FBA_D9
    FB_A_D10 F15 FBA_D10
    FB_A_D11 F13 FBA_D11
    FB_A_D12 C13 FBA_D12
    FB_A_D13 B13 FBA_D13
    FB_A_D14 E13 FBA_D14 +1.35VS_VRAM
    FB_A_D15 D13 FBA_D15
    FB_A_D16 B15 FBA_D16
    FB_A_D17 C16 FBA_D17
    FB_A_D18 A13 FBA_D18 RPV8 DIS@ 2
    FB_A_D19 A15 FBA_D19 FB_A_CMD26 1 8 CV81
    FB_A_D20 B18 FBA_D20 2 7 0.1U_0201_10V6K
    FB_A_D21 A18 FBA_D21 FB_A_CMD13 3 6 DIS@
    FB_A_D22 A19 4 5 1
    FBA_D22
    FB_A_D23 C19 FBA_D23
    FB_A_D24 B24 FBA_D24 100_0804_8P4R_5%
    FB_A_D25 C23 FBA_D25
    FB_A_D26 A25 FBA_D26
    FB_A_D27 A24 FBA_D27 RPV9 DIS@ 2
    FB_A_D28 A21 FBA_D28 FB_A_CMD15 1 8 CV82
    FB_A_D29 B21 FBA_D29 2 7 0.1U_0201_10V6K
    FB_A_CMD[0..30] <51,52,53,54>
    FB_A_D30 C20 FBA_D30 FB_A_CMD11 3 6 DIS@
    FB_A_D31 C21 4 5 1
    <52,54> FB_A_D[32..63] FBA_D31
    FB_A_D32 R22 FBA_D32
    FB_A_D33 R24 FBA_D33 FBA_CMD0 C27 FB_A_CMD0 100_0804_8P4R_5%
    FB_A_D34 T22 FBA_D34 FBA_CMD1 C26 FB_A_CMD1
    FB_A_D35 R23 FBA_D35 FBA_CMD2 E24 FB_A_CMD2
    FB_A_D36 N25 FBA_D36 FBA_CMD3 F24 FB_A_CMD3 RPV10 DIS@ 2
    C C
    FB_A_D37 N26 FBA_D37 FBA_CMD4 D27 FB_A_CMD4 FB_A_CMD21 1 8 CV72
    FB_A_D38 N23 FBA_D38 FBA_CMD5 D26 FB_A_CMD5 2 7 0.1U_0201_10V6K
    FB_A_D39 N24 FBA_D39 FBA_CMD6 F25 FB_A_CMD6 FB_A_CMD8 3 6 DIS@
    FB_A_D40 V23 FBA_CMD7 F26 FB_A_CMD7 4 5 1
    FBA_D40
    FB_A_D41 V22 FBA_D41 FBA_CMD8 F23 FB_A_CMD8 FBA_RST FB_A_CMD20
    FB_A_D42 T23 FBA_D42 FBA_CMD9 G22 FB_A_CMD9 100_0804_8P4R_5%
    FB_A_D43 U22 FBA_D43 FBA_CMD10 G23 FB_A_CMD10 FBA_ODT_L FB_A_CMD0
    FB_A_D44 Y24 FBA_D44 FBA_CMD11 G24 FB_A_CMD11
    FB_A_D45 AA24 FBA_D45 FBA_CMD12 F27 FB_A_CMD12 FBA_ODT_H FB_A_CMD16 RPV11 DIS@ 2
    FB_A_D46 Y22 FBA_D46 FBA_CMD13 G25 FB_A_CMD13 FB_A_CMD30 1 8 CV73
    FB_A_D47 AA23 FBA_D47 FBA_CMD14 G27 FB_A_CMD14 FBA_CKE_L FB_A_CMD3 2 7 0.1U_0201_10V6K
    FB_A_D48 AD27 FBA_D48 FBA_CMD15 G26 FB_A_CMD15 FB_A_CMD24 3 6 DIS@
    FB_A_D49 AB25 FBA_CMD16 M24 FB_A_CMD16 FBA_CKE_H FB_A_CMD19 4 5 1
    FBA_D49
    FB_A_D50 AD26 FBA_D50 FBA_CMD17 M23 FB_A_CMD17
    FB_A_D51 AC25 FBA_D51 FBA_CMD18 K24 FB_A_CMD18 100_0804_8P4R_5%

    2
    FB_A_D52 AA27 FBA_D52 FBA_CMD19 K23 FB_A_CMD19
    FB_A_D53 AA26 FBA_D53 FBA_CMD20 M27 FB_A_CMD20
    FB_A_D54 W26 FBA_D54 FBA_CMD21 M26 FB_A_CMD21 RV2437 RV2438 RV2439 RV2440 RV2447 RPV12 DIS@ 2
    FB_A_D55 Y25 FBA_D55 FBA_CMD22 M25 FB_A_CMD22 DIS@ DIS@ DIS@ DIS@ DIS@ FB_A_CMD25 1 8 CV74

    10K_0402_5%

    10K_0402_5%

    10K_0402_5%

    10K_0402_5%

    10K_0402_5%
    FB_A_D56 R26 FBA_D56 FBA_CMD23 K26 FB_A_CMD23 2 7 0.1U_0201_10V6K

    1
    FB_A_D57 T25 FBA_D57 FBA_CMD24 K22 FB_A_CMD24 FB_A_CMD28 3 6 DIS@
    FB_A_D58 N27 FBA_CMD25 J23 FB_A_CMD25 4 5 1
    FBA_D58
    FB_A_D59 R27 FBA_D59 FBA_CMD26 J25 FB_A_CMD26
    FB_A_D60 V26 FBA_D60 FBA_CMD27 J24 FB_A_CMD27 100_0804_8P4R_5%
    FB_A_D61 V27 FBA_D61 FBA_CMD28 K27 FB_A_CMD28
    FB_A_D62 W27 FBA_D62 FBA_CMD29 K25 FB_A_CMD29
    FB_A_D63 W25 FBA_D63 FBA_CMD30 J27 FB_A_CMD30 RPV13 DIS@ 2
    FBA_CMD31 J26 FB_A_CMD10 1 8 CV75
    2 7 0.1U_0201_10V6K
    <51,53> FB_A_DQM[3..0]
    FB_A_DQM0 D19 FBA_DQM0 FB_A_CMD6 3 6 DIS@
    FB_A_DQM1 D14 4 5 1
    FBA_DQM1 FBVDDQ_GPU
    FB_A_DQM2 C17 FBA_DQM2 GF117/GF119
    FB_A_DQM3 C22 FBA_DQM3 GK208
    100_0804_8P4R_5%
    <52,54> FB_A_DQM[7..4]
    FB_A_DQM4 P24 FBA_DQM4 +1.35VS_VRAM
    FB_A_DQM5 W24 FBA_DQM5 NC
    FBA_CMD32 B19 1.35V
    FB_A_DQM6 AA25 FBA_DQM6 RPV14 DIS@ 2
    FB_A_DQM7 U25 FBA_DQM7 FBA_DEBUG0
    FBA_CMD34 F22 60.4_0402_1% 1 @ 2 RV82 FB_A_CMD27 1 8 CV77
    FBA_DEBUG1
    FBA_CMD35 J22 60.4_0402_1% 1 @ 2 RV83 2 7 0.1U_0201_10V6K
    FB_A_CMD29 3 6 DIS@
    <51,53> FB_A_DQS[3..0] 1
    FB_A_DQS0 E19 FBA_DQS_WP0 4 5
    FB_A_DQS1 C15 FBA_DQS_WP1
    B FB_A_DQS2 B16 FBA_DQS_WP2 FBA_CLK0 D24 FB_A_CLK0 100_0804_8P4R_5% B
    FB_A_CLK0 <51,53>
    FB_A_DQS3 B22 FBA_DQS_WP3 FBA_CLK0# D25 FB_A_CLK#0
    <52,54> FB_A_DQS[7..4] FB_A_CLK#0 <51,53>
    FB_A_DQS4 R25 FBA_DQS_WP4 FBA_CLK1 N22 FB_A_CLK1
    FB_A_CLK1 <52,54>
    FB_A_DQS5 W23 FBA_DQS_WP5 FBA_CLK1# M22 FB_A_CLK#1 RPV15 DIS@ 2
    FB_A_CLK#1 <52,54>
    FB_A_DQS6 AB26 FBA_DQS_WP6 FB_A_CMD4 1 8 CV76
    FB_A_DQS7 T26 FBA_DQS_WP7 2 7 0.1U_0201_10V6K
    FB_A_CMD5 3 6 DIS@
    4 5 1
    <51,53> FB_A_DQS#[3..0]
    FB_A_DQS#0 F19 FBA_DQS_RN0 FBA_WCK01 D18
    FB_A_DQS#1 C14 FBA_DQS_RN1 FBA_WCK01# C18 100_0804_8P4R_5%
    FB_A_DQS#2 A16 FBA_DQS_RN2 FBA_WCK23 D17
    FB_A_DQS#3 A22 FBA_DQS_RN3 FBA_WCK23# D16
    <52,54> FB_A_DQS#[7..4]
    FB_A_DQS#4 P25 FBA_DQS_RN4 FBA_WCK45 T24 RPV16 DIS@ 2
    FB_A_DQS#5 W22 FBA_DQS_RN5 FBA_WCK45# U24 FB_A_CMD7 1 8 CV78
    FB_A_DQS#6 AB27 FBA_DQS_RN6 FBA_WCK67 V24 2 7 0.1U_0201_10V6K
    FB_A_DQS#7 T27 FBA_DQS_RN7 FBA_WCK67# V25 FB_A_CMD9 3 6 DIS@
    Close to P22 Close to F16 +1.0VS_PLLAVDD +1.0VS_DGPU 4 5 1
    1.0V
    Close to H22 Near GPU
    GF119 DIS@ 100_0804_8P4R_5%
    FB_PLLAVDD F16 1 2
    NC 1 2 1 1 MPZ1608S300AT_2P LV4
    FB_PLLAVDD P22 RPV17 DIS@ 2
    CV55 CV52 CV53 CV51 FB_A_CMD12 1 8 CV79
    0.1U_0402_10V7K

    0.1U_0402_10V7K

    0.1U_0402_10V7K

    22U_0603_6.3V6M

    FB_PLLAVDD FB_DLLAVDD H22 DIS@ DIS@ DIS@ DIS@ 2 7 0.1U_0201_10V6K


    2 1 2 2 FB_A_CMD14 3 6 DIS@
    4 5 1
    GF117

    100_0804_8P4R_5%

    RPV18 DIS@
    For VRAM DEBUG using FB_A_CMD22 1 8
    2
    CV80
    T2401 TP@ FB_VREF D23 FB_VREF_PROBE 2 7 0.1U_0201_10V6K
    FB_A_CMD23 3 6 DIS@
    4 5 1
    N16S-GT-S-A2_BGA595
    100_0804_8P4R_5%

    A A

    Security Classification
    2014/05/19
    Compal Secret Data
    2015/12/31 Title
    Compal Electronics, Inc.
    Issued Date Deciphered Date
    THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
    NV(5/5)-MEMORY FBA
    AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&DSize Document Number Rev
    DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS Custom LA-C071P 0.2
    MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.
    Date: Tuesday, July 28, 2015 Sheet 49 of 55
    5 4 3 2 1
    5 4 3 2 1

    Main Func : dGPU +3VS to +3VS_DGPU +3VS to +3VS_DGPU_AON +1.35V_VDDQ to +1.35VS_VRAM


    I_Continuous(Max) : 0.06 A(+3VS_DGPU_AON)
    +3VS +3VS_D I_Continuous(Max) : VRAM*8 -> 2.2A + GPU FBtotal -> 2.15 A = 4.35A(+1.35VS_VRAM)
    RV207 1 @ 2 0_0603_5% I_Continuous(Max) : 0.06 A(+3VS_DGPU)
    1 1 RON(Max) : 25 mohm
    CV289 CV58 DIS@
    10P_0402_50V8J 1U_0402_6.3V6K V drop : 0.002 V +3VS_D QV6
    @RF@ DIS@ DMG2301U-7 1P SOT23-3 +3VS_DGPU_AON QV7 DIS@ +1.35VS_VRAM
    2 2 +3VS_DGPU AON6552_DFN5X6-8-5
    +1.35V_VDDQ

    D
    UV10 DIS@ 3 1 1
    1 14 1 1 2
    2 VIN1 VOUT1 13 CV64 CV295 5 3
    VIN1 VOUT1 1 1 1 1
    +5VALW CV56 CV291 0.1U_0402_25V6 10P_0402_50V8J CV57 CV292

    G
    1 1

    2
    DGPU_MAIN_EN 3 12 1 2 CV83 0.1U_0402_25V6 10P_0402_50V8J DIS@ @RF@ CV290 0.1U_0402_25V6 10P_0402_50V8J

    Vinafix.com
    <43,48> DGPU_MAIN_EN ON1 CT1 2 2 CV117
    DIS@ 470P_0402_50V7K DIS@ @RF@ +5VALW @ 10P_0402_50V8J DIS@ @RF@
    1U_0402_6.3V6K

    4
    4 11 2 2 RV2718 @RF@ +5VALW +5VALW 2 2
    VBIAS GND 2 DIS@ 2
    2 DIS@ 1 RV129 1 DIS@ 2 47K_0402_5% 470_0603_5%
    1 1 1 2 EN_1.0VS 5 10 1 2 CV67 RV212 100K_0402_5% 2
    <12,43,45,49> DGPU_PWROK

    1
    ON2 CT2

    1
    CV293 CV63 RV210 0_0402_5% @ 3300P_0402_50V7K +1.0VS_DGPU CV66
    D 10P_0402_50V8J 1U_0402_6.3V6K 6 9 470P_0402_50V7K RV2719 RV2720 D
    VIN2 VOUT2

    6
    @RF@ DIS@ 7 8 DIS@ 100K_0402_5% 10K_0402_5% +1.35VS_VRAM
    VIN2 VOUT2

    3
    2 2 1 DIS@ DIS@
    1 1
    +1.0V_PRIM +1.0V_PRIM_D 15 CV65 CV296

    2
    GPAD 0.1U_0402_25V6 10P_0402_50V8J 2
    <9> DGPU_PWR_EN

    2
    RV209 1 @ 2 0_0805_5% EM5209VF_DFN14_2X3 DIS@ @RF@ 5
    2 2 QV8A 1

    1
    DMN65D8LDW-7_SOT363-6 QV8B CV59 RV2721 @

    3
    DIS@ DMN65D8LDW-7_SOT363-6 0.1U_0402_25V6 470_0603_5%
    I_Continuous(Max) : 0.79 A(+1.0VS_DGPU) DIS@ DIS@

    11
    2
    RON(Max) : 25 mohm 2 5
    1.35V_PWR_EN D
    <49> 1.35V_PWR_EN
    QV5B 2 @
    QV5A DMN65D8LDW-7_SOT363-6 G QV74

    4
    DMN65D8LDW-7_SOT363-6 DIS@ S 2N7002LT1G_SOT23-3
    +1.0V_PRIM to +1.0VS_DGPU DIS@

    3
    Reserve for Power's coat mode noise
    Capacitor's value need fine tune by EMI test result

    +VCC_CORE +VCC_GT
    DIS@
    CV297 1 2 10P_0402_50V8J

    DIS@
    CV298 1 2 10P_0402_50V8J

    +VCC_CORE +VCC_SA
    DIS@
    CV300 1 2 10P_0402_50V8J

    DIS@
    CV299 1 2 10P_0402_50V8J

    +VCC_GT
    DIS@
    CV302 1 2 10P_0402_50V8J

    DIS@
    C CV301 1 2 10P_0402_50V8J C

    B B

    A A

    Security Classification
    2014/05/19
    Compal Secret Data
    2015/12/31 Title
    Compal Electronics, Inc.
    Issued Date Deciphered Date
    THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
    DGPU_DC/DC Interface
    AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&DSize Document Number Rev
    DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS 0.2
    MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.
    Date: Tuesday, July 28, 2015 Sheet 50 of 55
    5 4 3 2 1
    5 4 3 2 1

    Main Func : VRAM Memory Partition A - Lower 32 bits [31..0]

    Rank 0 <49,53> FB_A_D[0..31]

    Vinafix.com +1.35VS_VRAM +1.35VS_VRAM


    <49,53> FB_A_DQM[3..0]

    1
    D D
    RV108 RV115
    <49,53> FB_A_DQS[3..0]
    1.33K_0402_1% 1.33K_0402_1%
    DIS_SIN@ +0.675VS_VREF_CA0 DIS_SIN@ +0.675VS_VREF_DQ0
    <49,53> FB_A_DQS#[3..0]

    2
    1

    1
    <49,52,53,54> FB_A_CMD[0..30] 1 1
    RV107 CV70 RV113 CV71
    1.33K_0402_1% 0.01U_0402_25V7K 1.33K_0402_1% 0.01U_0402_25V7K
    DIS_SIN@ DIS_SIN@ DIS_SIN@ DIS_SIN@
    2 2

    2
    +0.675VS_VREF_DQ0 +0.675VS_VREF_CA0 +0.675VS_VREF_DQ0 +0.675VS_VREF_CA0

    UV5 @ UV4 @

    M8 E3 FB_A_D13 M8 E3 FB_A_D5
    H1 VREFCA DQ0 F7 FB_A_D11 H1 VREFCA DQ0 F7 FB_A_D1
    VREFDQ DQ1 F2 FB_A_D15 VREFDQ DQ1 F2 FB_A_D7
    FB_A_CMD7 N3 DQ2 F8 FB_A_D8 FB_A_CMD7 N3 DQ2 F8 FB_A_D0
    FB_A_CMD10 P7 A0 DQ3 H3 FB_A_D12 FB_A_CMD10 P7 A0 DQ3 H3 FB_A_D4
    FB_A_CMD24 P3 A1 DQ4 H8 FB_A_D9 FB_A_CMD24 P3 A1 DQ4 H8 FB_A_D3
    FB_A_CMD6 N2 A2 DQ5 G2 FB_A_D14 FB_A_CMD6 N2 A2 DQ5 G2 FB_A_D6
    FB_A_CMD22 P8 A3 DQ6 H7 FB_A_D10 FB_A_CMD22 P8 A3 DQ6 H7 FB_A_D2
    FB_A_CMD26 P2 A4 DQ7 FB_A_CMD26 P2 A4 DQ7
    FB_A_CMD5 R8 A5 FB_A_CMD5 R8 A5
    FB_A_CMD21 R2 A6 D7 FB_A_D22 FB_A_CMD21 R2 A6 D7 FB_A_D31
    FB_A_CMD8 T8 A7 DQ8 C3 FB_A_D17 FB_A_CMD8 T8 A7 DQ8 C3 FB_A_D25
    C
    FB_A_CMD4 R3 A8 DQ9 C8 FB_A_D23
    PLACE 0.1uF CAPS CLOSEST FB_A_CMD4 R3 A8 DQ9 C8 FB_A_D30
    C

    FB_A_CMD25 L7 A9 DQ10 C2 FB_A_D16 TO THE MEMORY DEVICES FB_A_CMD25 L7 A9 DQ10 C2 FB_A_D24


    PLACE 0.1uF CAPS CLOSEST
    FB_A_CMD23 R7 A10/AP DQ11 A7 FB_A_D20 FB_A_CMD23 R7 A10/AP DQ11 A7 FB_A_D29 TO THE MEMORY DEVICES
    FB_A_CMD9 N7 A11 DQ12 A2 FB_A_D18 FB_A_CMD9 N7 A11 DQ12 A2 FB_A_D27
    FB_A_CMD12 T3 A12/BC# DQ13 B8 FB_A_D21
    PLACE LARGER CAPACITORS FB_A_CMD12 T3 A12/BC# DQ13 B8 FB_A_D28
    FB_A_CMD14 T7 A13 DQ14 A3 FB_A_D19 SLIGHTLY FARTHER AWAY FB_A_CMD14 T7 A13 DQ14 A3 FB_A_D26
    PLACE LARGER CAPACITORS
    M7 A14 DQ15 M7 A14 DQ15 SLIGHTLY FARTHER AWAY
    A15/NC A15/NC
    1.35V +1.35VS_VRAM 1.35V +1.35VS_VRAM
    FB_A_CMD29 M2 B2 FB_A_CMD29 M2 B2
    FB_A_CMD13 N8 BA0 VDD D9 FB_A_CMD13 N8 BA0 VDD D9
    BA1 VDD 1 1 1 1 BA1 VDD 1 1 1 1
    FB_A_CMD27 M3 G7 FB_A_CMD27 M3 G7
    BA2 VDD K2 CV164 CV162 CV166 CV163 BA2 VDD K2 CV235 CV236 CV237 CV238
    VDD VDD
    0.1U_0201_10V6K

    1U_0402_6.3V6K

    1U_0402_6.3V6K

    10U_0603_6.3V6M

    0.1U_0201_10V6K

    1U_0402_6.3V6K

    1U_0402_6.3V6K

    10U_0603_6.3V6M
    K8 DIS_SIN@ DIS_SIN@ DIS_SIN@ DIS_SIN@ K8 DIS_SIN@ DIS_SIN@ DIS_SIN@ DIS_SIN@
    VDD N1 2 2 2 2 VDD N1 2 2 2 2
    FB_A_CLK0 J7 VDD N9 FB_A_CLK0 J7 VDD N9
    <49,53> FB_A_CLK0 CK VDD CK VDD
    <49,53> FB_A_CLK#0 FB_A_CLK#0 K7 R1 FB_A_CLK#0 K7 R1
    CK# VDD R9 CK# VDD R9
    VDD VDD
    FB_A_CMD3 K9 FB_A_CMD3 K9
    J9 CKE0 A1 J9 CKE0 A1
    FB_A_CMD0 K1 CKE1/NC VDDQ A8 FB_A_CMD0 K1 CKE1/NC VDDQ A8
    J1 ODT0 VDDQ C1 J1 ODT0 VDDQ C1
    FB_A_CMD2 L2 ODT1/NC VDDQ C9 FB_A_CMD2 L2 ODT1/NC VDDQ C9
    L1 CS0# VDDQ D2 L1 CS0# VDDQ D2
    CS1#/NC VDDQ E9 CS1#/NC VDDQ E9
    VDDQ F1 +1.35VS_VRAM VDDQ F1 +1.35VS_VRAM
    Place close to Vram FB_A_CMD11 J3 VDDQ H2 FB_A_CMD11 J3 VDDQ H2
    B RAS# VDDQ 1.35V RAS# VDDQ 1.35V B
    FB_A_CLK0 FB_A_CMD15 K3 H9 FB_A_CMD15 K3 H9
    FB_A_CMD28 L3 CAS# VDDQ FB_A_CMD28 L3 CAS# VDDQ
    WE# 1 1 1 1 1 WE# 1 1 1 1 1
    1

    RV2706 A9 CV198 CV199 CV204 CV205 CV203 A9 CV239 CV240 CV241 CV242 CV243
    VSS VSS
    0.1U_0201_10V6K

    0.1U_0201_10V6K

    1U_0402_6.3V6K

    1U_0402_6.3V6K

    10U_0603_6.3V6M

    0.1U_0201_10V6K

    0.1U_0201_10V6K

    1U_0402_6.3V6K

    1U_0402_6.3V6K

    10U_0603_6.3V6M
    162_0402_1% FB_A_DQS1 F3 B3 DIS_SIN@ DIS_SIN@ DIS_SIN@ DIS_SIN@ DIS_SIN@ FB_A_DQS0 F3 B3 DIS_SIN@ DIS_SIN@ DIS_SIN@ DIS_SIN@ DIS_SIN@
    DIS_SIN@ FB_A_DQS2 C7 LDQS VSS E1 2 2 2 2 2 FB_A_DQS3 C7 LDQS VSS E1 2 2 2 2 2
    UDQS VSS G8 UDQS VSS G8
    2

    FB_A_CLK#0 VSS J2 VSS J2


    FB_A_DQS#1 G3 VSS J8 FB_A_DQS#0 G3 VSS J8
    FB_A_DQS#2 B7 LDQS# VSS M1 FB_A_DQS#3 B7 LDQS# VSS M1
    UDQS# VSS M9 UDQS# VSS M9
    VSS P1 VSS P1
    FB_A_DQM1 E7 VSS P9 FB_A_DQM0 E7 VSS P9
    FB_A_DQM2 D3 LDM VSS T1 FB_A_DQM3 D3 LDM VSS T1
    UDM VSS T9 UDM VSS T9
    VSS VSS

    FB_A_CMD20 T2 B1 FB_A_CMD20 T2 B1
    RESET# VSSQ B9 RESET# VSSQ B9
    VSSQ D1 VSSQ D1
    DIS_SIN@ VSSQ D8 DIS_SIN@ VSSQ D8
    RV111 1 2 243_0402_1% L8 VSSQ E2
    A15 is not required for any x16 RV112 1 2 243_0402_1% L8 VSSQ E2
    ZQ0 VSSQ E8 device, even up to 4Gb density. ZQ0 VSSQ E8
    L9 VSSQ F9 L9 VSSQ F9
    ZQ1/NC VSSQ G1 ZQ1/NC VSSQ G1
    VSSQ G9 A15 is only needed if we support VSSQ G9
    VSSQ VSSQ
    96-BALL
    x8 configurations, and only at 96-BALL
    A
    SDRAM DDR3L 4Gb. SDRAM DDR3L
    A
    H5TC4G63AFR-11C_FBGA96 H5TC4G63AFR-11C_FBGA96

    UV5 @ UV4 @

    Security Classification
    2014/05/19
    Compal Secret Data
    2015/12/31 Title
    Compal Electronics, Inc.
    Issued Date Deciphered Date
    Micron_MT41J256M16HA-093G:E Micron_MT41J256M16HA-093G:E
    THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
    VRAM_DDR3_A Lower
    SA000077K0L SA000077K0L AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&DSize Document Number Rev
    DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS Custom LA-C071P 0.2
    MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.
    Date: Tuesday, July 28, 2015 Sheet 51 of 55
    5 4 3 2 1
    5 4 3 2 1

    Main Func : VRAM Memory Partition A - Upper 32 bits [63..32]


    Rank 0 <49,54> FB_A_D[32..63]

    <49,54> FB_A_DQM[7..4]
    Vinafix.com +1.35VS_VRAM +1.35VS_VRAM

    1
    D D
    RV100 RV95
    <49,54> FB_A_DQS[7..4]
    1.33K_0402_1% 1.33K_0402_1%
    DIS_SIN@ +0.675VS_VREF_CA1 DIS_SIN@ +0.675VS_VREF_DQ1
    <49,54> FB_A_DQS#[7..4]

    2
    1

    1
    <49,51,53,54> FB_A_CMD[0..30] 1 1
    RV94 CV105 RV96 CV106
    1.33K_0402_1% 0.01U_0402_25V7K 1.33K_0402_1% 0.01U_0402_25V7K
    DIS_SIN@ DIS_SIN@ DIS_SIN@ DIS_SIN@
    2 2

    2
    +0.675VS_VREF_DQ1 +0.675VS_VREF_CA1 +0.675VS_VREF_DQ1 +0.675VS_VREF_CA1

    UV7 @ UV6 @

    M8 E3 FB_A_D38 M8 E3 FB_A_D41
    H1 VREFCA DQ0 F7 FB_A_D34 H1 VREFCA DQ0 F7 FB_A_D45
    VREFDQ DQ1 F2 FB_A_D37 VREFDQ DQ1 F2 FB_A_D42
    FB_A_CMD7 N3 DQ2 F8 FB_A_D32 FB_A_CMD7 N3 DQ2 F8 FB_A_D47
    FB_A_CMD10 P7 A0 DQ3 H3 FB_A_D39 FB_A_CMD10 P7 A0 DQ3 H3 FB_A_D43
    FB_A_CMD24 P3 A1 DQ4 H8 FB_A_D33 FB_A_CMD24 P3 A1 DQ4 H8 FB_A_D46
    FB_A_CMD6 N2 A2 DQ5 G2 FB_A_D36 FB_A_CMD6 N2 A2 DQ5 G2 FB_A_D40
    FB_A_CMD22 P8 A3 DQ6 H7 FB_A_D35 FB_A_CMD22 P8 A3 DQ6 H7 FB_A_D44
    FB_A_CMD26 P2 A4 DQ7 FB_A_CMD26 P2 A4 DQ7
    FB_A_CMD5 R8 A5 FB_A_CMD5 R8 A5
    FB_A_CMD21 R2 A6 D7 FB_A_D63 FB_A_CMD21 R2 A6 D7 FB_A_D49
    FB_A_CMD8 T8 A7 DQ8 C3 FB_A_D59 FB_A_CMD8 T8 A7 DQ8 C3 FB_A_D54
    C
    FB_A_CMD4 R3 A8 DQ9 C8 FB_A_D62
    PLACE 0.1uF CAPS CLOSEST FB_A_CMD4 R3 A8 DQ9 C8 FB_A_D50
    C

    FB_A_CMD25 L7 A9 DQ10 C2 FB_A_D58 TO THE MEMORY DEVICES FB_A_CMD25 L7 A9 DQ10 C2 FB_A_D55


    PLACE 0.1uF CAPS CLOSEST
    FB_A_CMD23 R7 A10/AP DQ11 A7 FB_A_D61 FB_A_CMD23 R7 A10/AP DQ11 A7 FB_A_D48 TO THE MEMORY DEVICES
    FB_A_CMD9 N7 A11 DQ12 A2 FB_A_D56 FB_A_CMD9 N7 A11 DQ12 A2 FB_A_D53
    FB_A_CMD12 T3 A12/BC# DQ13 B8 FB_A_D60
    PLACE LARGER CAPACITORS FB_A_CMD12 T3 A12/BC# DQ13 B8 FB_A_D51
    FB_A_CMD14 T7 A13 DQ14 A3 FB_A_D57 SLIGHTLY FARTHER AWAY FB_A_CMD14 T7 A13 DQ14 A3 FB_A_D52
    PLACE LARGER CAPACITORS
    M7 A14 DQ15 M7 A14 DQ15 SLIGHTLY FARTHER AWAY
    A15/NC A15/NC
    1.35V +1.35VS_VRAM 1.35V +1.35VS_VRAM
    FB_A_CMD29 M2 B2 FB_A_CMD29 M2 B2
    FB_A_CMD13 N8 BA0 VDD D9 FB_A_CMD13 N8 BA0 VDD D9
    BA1 VDD 1 1 1 1 BA1 VDD 1 1 1 1
    FB_A_CMD27 M3 G7 FB_A_CMD27 M3 G7
    BA2 VDD K2 CV253 CV254 CV255 CV256 BA2 VDD K2 CV263 CV262 CV264 CV265
    VDD VDD
    0.1U_0201_10V6K

    1U_0402_6.3V6K

    1U_0402_6.3V6K

    10U_0603_6.3V6M

    0.1U_0201_10V6K

    1U_0402_6.3V6K

    1U_0402_6.3V6K

    10U_0603_6.3V6M
    K8 DIS_SIN@ DIS_SIN@ DIS_SIN@ DIS_SIN@ K8 DIS_SIN@ DIS_SIN@ DIS_SIN@ DIS_SIN@
    VDD N1 2 2 2 2 VDD N1 2 2 2 2
    FB_A_CLK1 J7 VDD N9 FB_A_CLK1 J7 VDD N9
    <49,54> FB_A_CLK1 CK VDD CK VDD
    <49,54> FB_A_CLK#1 FB_A_CLK#1 K7 R1 FB_A_CLK#1 K7 R1
    CK# VDD R9 CK# VDD R9
    VDD VDD
    FB_A_CMD19 K9 FB_A_CMD19 K9
    J9 CKE0 A1 J9 CKE0 A1
    FB_A_CMD16 K1 CKE1/NC VDDQ A8 FB_A_CMD16 K1 CKE1/NC VDDQ A8
    J1 ODT0 VDDQ C1 J1 ODT0 VDDQ C1
    FB_A_CMD18 L2 ODT1/NC VDDQ C9 FB_A_CMD18 L2 ODT1/NC VDDQ C9
    L1 CS0# VDDQ D2 L1 CS0# VDDQ D2
    CS1#/NC VDDQ E9 CS1#/NC VDDQ E9
    VDDQ F1 +1.35VS_VRAM VDDQ F1 +1.35VS_VRAM
    Place close to Vram FB_A_CMD11 J3 VDDQ H2 FB_A_CMD11 J3 VDDQ H2
    B RAS# VDDQ 1.35V RAS# VDDQ 1.35V B
    FB_A_CLK1 FB_A_CMD15 K3 H9 FB_A_CMD15 K3 H9
    FB_A_CMD28 L3 CAS# VDDQ FB_A_CMD28 L3 CAS# VDDQ
    WE# 1 1 1 1 1 WE# 1 1 1 1 1
    1

    RV2717 A9 CV257 CV258 CV259 CV260 CV261 A9 CV266 CV267 CV268 CV269 CV270
    VSS VSS
    0.1U_0201_10V6K

    0.1U_0201_10V6K

    1U_0402_6.3V6K

    1U_0402_6.3V6K

    10U_0603_6.3V6M

    0.1U_0201_10V6K

    0.1U_0201_10V6K

    1U_0402_6.3V6K

    1U_0402_6.3V6K

    10U_0603_6.3V6M
    162_0402_1% FB_A_DQS4 F3 B3 DIS_SIN@ DIS_SIN@ DIS_SIN@ DIS_SIN@ DIS_SIN@ FB_A_DQS5 F3 B3 DIS_SIN@ DIS_SIN@ DIS_SIN@ DIS_SIN@ DIS_SIN@
    DIS_SIN@ FB_A_DQS7 C7 LDQS VSS E1 2 2 2 2 2 FB_A_DQS6 C7 LDQS VSS E1 2 2 2 2 2
    UDQS VSS G8 UDQS VSS G8
    2

    FB_A_CLK#1 VSS J2 VSS J2


    FB_A_DQS#4 G3 VSS J8 FB_A_DQS#5 G3 VSS J8
    FB_A_DQS#7 B7 LDQS# VSS M1 FB_A_DQS#6 B7 LDQS# VSS M1
    UDQS# VSS M9 UDQS# VSS M9
    VSS P1 VSS P1
    FB_A_DQM4 E7 VSS P9 FB_A_DQM5 E7 VSS P9
    FB_A_DQM7 D3 LDM VSS T1 FB_A_DQM6 D3 LDM VSS T1
    UDM VSS T9 UDM VSS T9
    VSS VSS

    FB_A_CMD20 T2 B1 FB_A_CMD20 T2 B1
    RESET# VSSQ B9 RESET# VSSQ B9
    VSSQ D1 VSSQ D1
    DIS_SIN@ VSSQ D8 DIS_SIN@ VSSQ D8
    RV97 1 2 243_0402_1% L8 VSSQ E2
    A15 is not required for any x16 RV98 1 2 243_0402_1% L8 VSSQ E2
    ZQ0 VSSQ E8 device, even up to 4Gb density. ZQ0 VSSQ E8
    L9 VSSQ F9 L9 VSSQ F9
    ZQ1/NC VSSQ G1 ZQ1/NC VSSQ G1
    VSSQ G9 A15 is only needed if we support VSSQ G9
    VSSQ VSSQ
    96-BALL
    x8 configurations, and only at 96-BALL
    A
    SDRAM DDR3L 4Gb. SDRAM DDR3L
    A
    H5TC4G63AFR-11C_FBGA96 H5TC4G63AFR-11C_FBGA96

    UV6 @ UV7 @

    Security Classification
    2014/05/19
    Compal Secret Data
    2015/12/31 Title
    Compal Electronics, Inc.
    Issued Date Deciphered Date
    Micron_MT41J256M16HA-093G:E Micron_MT41J256M16HA-093G:E
    THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
    VRAM_DDR3_A Lower
    SA000077K0L SA000077K0L AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&DSize Document Number Rev
    DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS Custom LA-C071P 0.2
    MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.
    Date: Tuesday, July 28, 2015 Sheet 52 of 55
    5 4 3 2 1
    5 4 3 2 1

    Main Func : VRAM Memory Partition A - Lower 32 bits [31..0]


    Rank 1 <49,51> FB_A_D[0..31]

    <49,51> FB_A_DQM[3..0]
    Vinafix.com
    D D
    <49,51> FB_A_DQS[3..0]

    <49,51> FB_A_DQS#[3..0]

    <49,51,52,54> FB_A_CMD[0..30]

    +0.675VS_VREF_DQ0 +0.675VS_VREF_CA0 +0.675VS_VREF_DQ0 +0.675VS_VREF_CA0

    UV8 @ UV9 @

    M8 E3 FB_A_D11 M8 E3 FB_A_D1
    H1 VREFCA DQ0 F7 FB_A_D13 H1 VREFCA DQ0 F7 FB_A_D5
    VREFDQ DQ1 F2 FB_A_D8 VREFDQ DQ1 F2 FB_A_D0
    FB_A_CMD9 N3 DQ2 F8 FB_A_D15 FB_A_CMD9 N3 DQ2 F8 FB_A_D7
    FB_A_CMD24 P7 A0 DQ3 H3 FB_A_D10 FB_A_CMD24 P7 A0 DQ3 H3 FB_A_D2
    FB_A_CMD10 P3 A1 DQ4 H8 FB_A_D14 FB_A_CMD10 P3 A1 DQ4 H8 FB_A_D6
    FB_A_CMD13 N2 A2 DQ5 G2 FB_A_D9 FB_A_CMD13 N2 A2 DQ5 G2 FB_A_D3
    FB_A_CMD26 P8 A3 DQ6 H7 FB_A_D12 FB_A_CMD26 P8 A3 DQ6 H7 FB_A_D4
    FB_A_CMD22 P2 A4 DQ7 FB_A_CMD22 P2 A4 DQ7
    FB_A_CMD21 R8 A5 FB_A_CMD21 R8 A5
    FB_A_CMD5 R2 A6 D7 FB_A_D17 FB_A_CMD5 R2 A6 D7 FB_A_D25
    FB_A_CMD8 T8 A7 DQ8 C3 FB_A_D22 FB_A_CMD8 T8 A7 DQ8 C3 FB_A_D31
    C
    FB_A_CMD23 R3 A8 DQ9 C8 FB_A_D16
    PLACE 0.1uF CAPS CLOSEST FB_A_CMD23 R3 A8 DQ9 C8 FB_A_D24
    C

    FB_A_CMD28 L7 A9 DQ10 C2 FB_A_D23 TO THE MEMORY DEVICES FB_A_CMD28 L7 A9 DQ10 C2 FB_A_D30


    PLACE 0.1uF CAPS CLOSEST
    FB_A_CMD4 R7 A10/AP DQ11 A7 FB_A_D19 FB_A_CMD4 R7 A10/AP DQ11 A7 FB_A_D26 TO THE MEMORY DEVICES
    FB_A_CMD7 N7 A11 DQ12 A2 FB_A_D21 FB_A_CMD7 N7 A11 DQ12 A2 FB_A_D28
    FB_A_CMD14 T3 A12/BC# DQ13 B8 FB_A_D18
    PLACE LARGER CAPACITORS FB_A_CMD14 T3 A12/BC# DQ13 B8 FB_A_D27
    FB_A_CMD12 T7 A13 DQ14 A3 FB_A_D20 SLIGHTLY FARTHER AWAY FB_A_CMD12 T7 A13 DQ14 A3 FB_A_D29
    PLACE LARGER CAPACITORS
    M7 A14 DQ15 M7 A14 DQ15 SLIGHTLY FARTHER AWAY
    A15/NC A15/NC
    1.35V +1.35VS_VRAM 1.35V +1.35VS_VRAM
    FB_A_CMD29 M2 B2 FB_A_CMD29 M2 B2
    FB_A_CMD6 N8 BA0 VDD D9 FB_A_CMD6 N8 BA0 VDD D9
    BA1 VDD 1 1 1 1 1 BA1 VDD 1 1 1 1 1
    FB_A_CMD30 M3 G7 FB_A_CMD30 M3 G7
    BA2 VDD K2 CV165 CV167 CV168 CV169 CV170 BA2 VDD K2 CV250 CV251 CV252 CV245 CV244
    VDD VDD
    0.1U_0201_10V6K

    1U_0402_6.3V6K

    1U_0402_6.3V6K

    10U_0603_6.3V6M

    10U_0603_6.3V6M

    0.1U_0201_10V6K

    1U_0402_6.3V6K

    1U_0402_6.3V6K

    10U_0603_6.3V6M

    10U_0603_6.3V6M
    K8 DIS_DUAL@ DIS_DUAL@ DIS_DUAL@ DIS_DUAL@ DIS_DUAL@ K8 DIS_DUAL@ DIS_DUAL@ DIS_DUAL@ DIS_DUAL@ DIS_DUAL@
    VDD N1 2 2 2 2 2 VDD N1 2 2 2 2 2
    FB_A_CLK0 J7 VDD N9 FB_A_CLK0 J7 VDD N9
    <49,51> FB_A_CLK0 CK VDD CK VDD
    <49,51> FB_A_CLK#0 FB_A_CLK#0 K7 R1 FB_A_CLK#0 K7 R1
    CK# VDD R9 CK# VDD R9
    VDD VDD
    FB_A_CMD3 K9 FB_A_CMD3 K9
    J9 CKE0 A1 J9 CKE0 A1
    FB_A_CMD0 K1 CKE1/NC VDDQ A8 FB_A_CMD0 K1 CKE1/NC VDDQ A8
    J1 ODT0 VDDQ C1 J1 ODT0 VDDQ C1
    FB_A_CMD1 L2 ODT1/NC VDDQ C9 FB_A_CMD1 L2 ODT1/NC VDDQ C9
    L1 CS0# VDDQ D2 L1 CS0# VDDQ D2
    CS1#/NC VDDQ E9 CS1#/NC VDDQ E9
    VDDQ F1 +1.35VS_VRAM VDDQ F1 +1.35VS_VRAM
    FB_A_CMD11 J3 VDDQ H2 FB_A_CMD11 J3 VDDQ H2
    B RAS# VDDQ 1.35V RAS# VDDQ 1.35V B
    FB_A_CMD15 K3 H9 FB_A_CMD15 K3 H9
    FB_A_CMD25 L3 CAS# VDDQ FB_A_CMD25 L3 CAS# VDDQ
    WE# 1 1 1 1 WE# 1 1 1 1
    A9 CV201 CV202 CV206 CV207 A9 CV246 CV247 CV248 CV249
    VSS VSS
    0.1U_0201_10V6K

    0.1U_0201_10V6K

    1U_0402_6.3V6K

    1U_0402_6.3V6K

    0.1U_0201_10V6K

    0.1U_0201_10V6K

    1U_0402_6.3V6K

    1U_0402_6.3V6K
    FB_A_DQS1 F3 B3 DIS_DUAL@ DIS_DUAL@ DIS_DUAL@ DIS_DUAL@ FB_A_DQS0 F3 B3 DIS_DUAL@ DIS_DUAL@ DIS_DUAL@ DIS_DUAL@
    FB_A_DQS2 C7 LDQS VSS E1 2 2 2 2 FB_A_DQS3 C7 LDQS VSS E1 2 2 2 2
    UDQS VSS G8 UDQS VSS G8
    VSS J2 VSS J2
    FB_A_DQS#1 G3 VSS J8 FB_A_DQS#0 G3 VSS J8
    FB_A_DQS#2 B7 LDQS# VSS M1 FB_A_DQS#3 B7 LDQS# VSS M1
    UDQS# VSS M9 UDQS# VSS M9
    VSS P1 VSS P1
    FB_A_DQM1 E7 VSS P9 FB_A_DQM0 E7 VSS P9
    FB_A_DQM2 D3 LDM VSS T1 FB_A_DQM3 D3 LDM VSS T1
    UDM VSS T9 UDM VSS T9
    VSS VSS

    FB_A_CMD20 T2 B1 FB_A_CMD20 T2 B1
    RESET# VSSQ B9 RESET# VSSQ B9
    VSSQ D1 VSSQ D1
    DIS_DUAL@ VSSQ D8 DIS_DUAL@ VSSQ D8
    RV114 1 2 243_0402_1% L8 VSSQ E2
    A15 is not required for any x16 RV116 1 2 243_0402_1% L8 VSSQ E2
    ZQ0 VSSQ E8 device, even up to 4Gb density. ZQ0 VSSQ E8
    L9 VSSQ F9 L9 VSSQ F9
    ZQ1/NC VSSQ G1 ZQ1/NC VSSQ G1
    VSSQ G9 A15 is only needed if we support VSSQ G9
    VSSQ VSSQ
    96-BALL
    x8 configurations, and only at 96-BALL
    A
    SDRAM DDR3L 4Gb. SDRAM DDR3L
    A
    H5TC4G63AFR-11C_FBGA96 H5TC4G63AFR-11C_FBGA96

    UV8 @ UV9 @

    Security Classification
    2014/05/19
    Compal Secret Data
    2015/12/31 Title
    Compal Electronics, Inc.
    Issued Date Deciphered Date
    Micron_MT41J256M16HA-093G:E Micron_MT41J256M16HA-093G:E THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
    VRAM_DDR3_A Lower
    AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&DSize Document Number Rev
    SA000077K0L SA000077K0L DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS Custom LA-C071P 0.2
    MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.
    Date: Tuesday, July 28, 2015 Sheet 53 of 55
    5 4 3 2 1
    5 4 3 2 1

    Main Func : VRAM Memory Partition A - Upper 32 bits [63..32]


    Rank 1 <49,52> FB_A_D[32..63]

    <49,52> FB_A_DQM[7..4]
    Vinafix.com
    D D
    <49,52> FB_A_DQS[7..4]

    <49,52> FB_A_DQS#[7..4]

    <49,51,52,53> FB_A_CMD[0..30]

    +0.675VS_VREF_DQ1 +0.675VS_VREF_CA1 +0.675VS_VREF_DQ1 +0.675VS_VREF_CA1

    UV15 @ UV14 @

    M8 E3 FB_A_D34 M8 E3 FB_A_D45
    H1 VREFCA DQ0 F7 FB_A_D38 H1 VREFCA DQ0 F7 FB_A_D41
    VREFDQ DQ1 F2 FB_A_D32 VREFDQ DQ1 F2 FB_A_D47
    FB_A_CMD9 N3 DQ2 F8 FB_A_D37 FB_A_CMD9 N3 DQ2 F8 FB_A_D42
    FB_A_CMD24 P7 A0 DQ3 H3 FB_A_D35 FB_A_CMD24 P7 A0 DQ3 H3 FB_A_D44
    FB_A_CMD10 P3 A1 DQ4 H8 FB_A_D36 FB_A_CMD10 P3 A1 DQ4 H8 FB_A_D40
    FB_A_CMD13 N2 A2 DQ5 G2 FB_A_D33 FB_A_CMD13 N2 A2 DQ5 G2 FB_A_D46
    FB_A_CMD26 P8 A3 DQ6 H7 FB_A_D39 FB_A_CMD26 P8 A3 DQ6 H7 FB_A_D43
    FB_A_CMD22 P2 A4 DQ7 FB_A_CMD22 P2 A4 DQ7
    FB_A_CMD21 R8 A5 FB_A_CMD21 R8 A5
    FB_A_CMD5 R2 A6 D7 FB_A_D59 FB_A_CMD5 R2 A6 D7 FB_A_D54
    FB_A_CMD8 T8 A7 DQ8 C3 FB_A_D63 FB_A_CMD8 T8 A7 DQ8 C3 FB_A_D49
    C
    FB_A_CMD23 R3 A8 DQ9 C8 FB_A_D58
    PLACE 0.1uF CAPS CLOSEST FB_A_CMD23 R3 A8 DQ9 C8 FB_A_D55
    C

    FB_A_CMD28 L7 A9 DQ10 C2 FB_A_D62 TO THE MEMORY DEVICES FB_A_CMD28 L7 A9 DQ10 C2 FB_A_D50


    PLACE 0.1uF CAPS CLOSEST
    FB_A_CMD4 R7 A10/AP DQ11 A7 FB_A_D57 FB_A_CMD4 R7 A10/AP DQ11 A7 FB_A_D52 TO THE MEMORY DEVICES
    FB_A_CMD7 N7 A11 DQ12 A2 FB_A_D60 FB_A_CMD7 N7 A11 DQ12 A2 FB_A_D51
    FB_A_CMD14 T3 A12/BC# DQ13 B8 FB_A_D56
    PLACE LARGER CAPACITORS FB_A_CMD14 T3 A12/BC# DQ13 B8 FB_A_D53
    FB_A_CMD12 T7 A13 DQ14 A3 FB_A_D61 SLIGHTLY FARTHER AWAY FB_A_CMD12 T7 A13 DQ14 A3 FB_A_D48
    PLACE LARGER CAPACITORS
    M7 A14 DQ15 M7 A14 DQ15 SLIGHTLY FARTHER AWAY
    A15/NC A15/NC
    1.35V +1.35VS_VRAM 1.35V +1.35VS_VRAM
    FB_A_CMD29 M2 B2 FB_A_CMD29 M2 B2
    FB_A_CMD6 N8 BA0 VDD D9 FB_A_CMD6 N8 BA0 VDD D9
    BA1 VDD 1 1 1 1 1 BA1 VDD 1 1 1 1 1
    FB_A_CMD30 M3 G7 FB_A_CMD30 M3 G7
    BA2 VDD K2 CV277 CV278 CV279 CV272 CV271 BA2 VDD K2 CV286 CV287 CV288 CV281 CV280
    VDD VDD
    0.1U_0201_10V6K

    1U_0402_6.3V6K

    1U_0402_6.3V6K

    10U_0603_6.3V6M

    10U_0603_6.3V6M

    0.1U_0201_10V6K

    1U_0402_6.3V6K

    1U_0402_6.3V6K

    10U_0603_6.3V6M

    10U_0603_6.3V6M
    K8 DIS_DUAL@ DIS_DUAL@ DIS_DUAL@ DIS_DUAL@ DIS_DUAL@ K8 DIS_DUAL@ DIS_DUAL@ DIS_DUAL@ DIS_DUAL@ DIS_DUAL@
    VDD N1 2 2 2 2 2 VDD N1 2 2 2 2 2
    FB_A_CLK1 J7 VDD N9 FB_A_CLK1 J7 VDD N9
    <49,52> FB_A_CLK1 CK VDD CK VDD
    <49,52> FB_A_CLK#1 FB_A_CLK#1 K7 R1 FB_A_CLK#1 K7 R1
    CK# VDD R9 CK# VDD R9
    VDD VDD
    FB_A_CMD19 K9 FB_A_CMD19 K9
    J9 CKE0 A1 J9 CKE0 A1
    FB_A_CMD16 K1 CKE1/NC VDDQ A8 FB_A_CMD16 K1 CKE1/NC VDDQ A8
    J1 ODT0 VDDQ C1 J1 ODT0 VDDQ C1
    FB_A_CMD17 L2 ODT1/NC VDDQ C9 FB_A_CMD17 L2 ODT1/NC VDDQ C9
    L1 CS0# VDDQ D2 L1 CS0# VDDQ D2
    CS1#/NC VDDQ E9 CS1#/NC VDDQ E9
    VDDQ F1 +1.35VS_VRAM VDDQ F1 +1.35VS_VRAM
    FB_A_CMD11 J3 VDDQ H2 FB_A_CMD11 J3 VDDQ H2
    B RAS# VDDQ 1.35V RAS# VDDQ 1.35V B
    FB_A_CMD15 K3 H9 FB_A_CMD15 K3 H9
    FB_A_CMD25 L3 CAS# VDDQ FB_A_CMD25 L3 CAS# VDDQ
    WE# 1 1 1 1 WE# 1 1 1 1
    A9 CV273 CV274 CV275 CV276 A9 CV283 CV282 CV284 CV285
    VSS VSS
    0.1U_0201_10V6K

    0.1U_0201_10V6K

    1U_0402_6.3V6K

    1U_0402_6.3V6K

    0.1U_0201_10V6K

    0.1U_0201_10V6K

    1U_0402_6.3V6K

    1U_0402_6.3V6K
    FB_A_DQS4 F3 B3 DIS_DUAL@ DIS_DUAL@ DIS_DUAL@ DIS_DUAL@ FB_A_DQS5 F3 B3 DIS_DUAL@ DIS_DUAL@ DIS_DUAL@ DIS_DUAL@
    FB_A_DQS7 C7 LDQS VSS E1 2 2 2 2 FB_A_DQS6 C7 LDQS VSS E1 2 2 2 2
    UDQS VSS G8 UDQS VSS G8
    VSS J2 VSS J2
    FB_A_DQS#4 G3 VSS J8 FB_A_DQS#5 G3 VSS J8
    FB_A_DQS#7 B7 LDQS# VSS M1 FB_A_DQS#6 B7 LDQS# VSS M1
    UDQS# VSS M9 UDQS# VSS M9
    VSS P1 VSS P1
    FB_A_DQM4 E7 VSS P9 FB_A_DQM5 E7 VSS P9
    FB_A_DQM7 D3 LDM VSS T1 FB_A_DQM6 D3 LDM VSS T1
    UDM VSS T9 UDM VSS T9
    VSS VSS

    FB_A_CMD20 T2 B1 FB_A_CMD20 T2 B1
    RESET# VSSQ B9 RESET# VSSQ B9
    VSSQ D1 VSSQ D1
    DIS_DUAL@ VSSQ D8 DIS_DUAL@ VSSQ D8
    RV101 1 2 243_0402_1% L8 VSSQ E2
    A15 is not required for any x16 RV99 1 2 243_0402_1% L8 VSSQ E2
    ZQ0 VSSQ E8 device, even up to 4Gb density. ZQ0 VSSQ E8
    L9 VSSQ F9 L9 VSSQ F9
    ZQ1/NC VSSQ G1 ZQ1/NC VSSQ G1
    VSSQ G9 A15 is only needed if we support VSSQ G9
    VSSQ VSSQ
    96-BALL
    x8 configurations, and only at 96-BALL
    A
    SDRAM DDR3L 4Gb. SDRAM DDR3L
    A
    H5TC4G63AFR-11C_FBGA96 H5TC4G63AFR-11C_FBGA96

    UV14 @ UV15 @

    Security Classification
    2014/05/19
    Compal Secret Data
    2015/12/31 Title
    Compal Electronics, Inc.
    Issued Date Deciphered Date
    Micron_MT41J256M16HA-093G:E Micron_MT41J256M16HA-093G:E THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
    VRAM_DDR3_A Lower
    AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&DSize Document Number Rev
    SA000077K0L SA000077K0L DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS Custom LA-C071P 0.2
    MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.
    Date: Tuesday, July 28, 2015 Sheet 54 of 55
    5 4 3 2 1

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