General Specifications: Model VP6E5800 Turbomachinery I/O Module Logic Builder Package
General Specifications: Model VP6E5800 Turbomachinery I/O Module Logic Builder Package
General Specifications: Model VP6E5800 Turbomachinery I/O Module Logic Builder Package
[Release 6]
General
Turbomachinery I/O modules are the modules that built-in with the high-speed interlock blocks, PID control blocks
and many other control function blocks, and applied in CENTUM VP system.
The main interfaces for turbine control such as speed pulse signal input, LVDT(Linear Variable Differential
Transformer)input and servo output interfaces are supported by theses modules. The Turbomachinery I/O Module
Logic Builder Package (VP6E5800) is the specific application package for configuring and engineering the
Turbomachinery I/O modules.
More information regarding the Turbomachinery I/O modules can be found in the General Specification of
Turbomachinery I/O Modules (GS 33J50F60-01EN). Please read it together with this document.
Main Controller
(FCS)
Communication I/O
DATA DATA
Turbine Gen
LVDT
Gas or steam
IOM Model(Name) I/O Channels Per IOM Redundancy(*1) Built-In Logics IOM Scan-Period SOE
Position Feedback: 4 Channels
Built-In PID
AGS813 DI: 2 Channels
Control-Period —
(Servo Module) AO: 2 Channels
5 msec
POWER OUT: 4 Channels
Scan-Period
5 msec 10 msec
AGP813 Built-In Logic
AI: 4 Chs AI: 6 Chs
(High Speed Protection Control-Period
PI: 0 Chs PI: 4 Chs (DI Only) (*2)
Module) 5 msec,10 msec
DI: 4 Chs DI: 8 Chs
DO: 4 Chs DO: 8 Chs
*1: Install the two modules of same model in the adjacent slots(An odd number slot and the odd number + 1 slot) for dual
redundancy.
*2: The SOE (sequence of events) capability is supported in the same way as the SOE capability of FIO. For more information
about SOE capabilities, see GS 33J30D10-01EN or GS 33J30D20-01EN of Sequence of Events Manager.
All Rights Reserved. Copyright © 2015, Yokogawa Electric Corporation GS 33J10U10-01EN Nov. 27, 2015-00
<<Contents>> <<Index>> 3
System Specifications
The Turbomachinery I/O modules and the control unit exchange the input and output data through the FCS
communication I/O areas. The Turbomachinery I/O modules use the same communication areas with other modules.
Therefore, the number of Turbomachinery I/O modules to be installed subjects to the following restrictions:
Regarding the restrictions on the number of installed modules caused by the power capacity, see the following
documents:
GS 33J60A10-01EN FIO System Overview
GS 33J62A10-01EN N-IO System Overview
Item
Field
Control Function Communication
Control Unit Maximum number of modules can be installed
I/O size
Control Function for Field Control Up to 8 modules (4 sets for dual-redundant use) combined
AFV30S, Station (VP6F1700-V11C01) with the ALR111, ALR121, ALE111 and ALP121 modules
AFV30D, Control Function for Field Control Up to 16 modules (8 sets for dual-redundant use) combined
8000 words/FCS
AFV40S, Station (VP6F1700-V11C02) with the ALR111, ALR121, ALE111 and ALP121 modules
AFV40D Control Function for Field Control Up to 32 modules (16 sets for dual-redundant use) combined
Station (VP6F1700-V11C03) with the ALR111, ALR121, ALE111 and ALP121 modules
All Rights Reserved. Copyright © 2015, Yokogawa Electric Corporation GS 33J10U10-01EN Nov. 27, 2015-00
<<Contents>> <<Index>> 4
l Logic Control Capability
The logics created on the Logic Builder of CENTUM VP, i.e., the Logic for Turbomachinery I/O Module, can be
executed in the high speed protection module as the application logics.
The application logics (hereinafter referred to as APL) performs the logic calculations using the pulse signals (turbine
revolution signals) and other field data. It also uses the parameters set by FCS and returns the calculation results to
the FCS. Accordingly, it can send the trip signals through DO and shutdown commands to servo module. In an APL,
the built-in logic blocks which are previously built with may types of logic functionalities can be used for various logic
controls.
The control period of the logic blocks is 5 msec or 10 msec user-definable.
Table Application Logic Specifications
Up to 100 blocks can be used as long as the logic calculation can complete within the limit of APL
Application logic (APL)
processing time.
Control Period of I/O Module and Limit of APL Processing Time
AGP813:
Limit of APL Processing Time
5 ms Fast Scan Mode: 1.5 ms
10 ms Basic Scan Mode: 3.0 ms
Number of APL Buffer for External Interface: 113
Number of APL Buffers
Number of APL Buffer For Internal Use in I/O Module: 928
The logic blocks built-in the High Speed Protection Module for creating the application logics are shown below:
Table Internal Blocks Built-In AGP813 (1/2)
Category Block Name Block Model Processing Time (μs)
15-0 Bits Coder CODE15-0 57.3
15-0 Bits Decoder DECO15-0 54.4
15-8 Bits Coder CODE15-8 37.6
7-0 Bits Coder CODE7-0 37.6
Typecasting Blocks 15-12 Bits Coder CODE15-12 27.6
11-8 Bits Coder CODE11-8 27.6
7-4 Bits Coder CODE7-4 27.6
3-0 Bits Coder CODE3-0 27.6
Size Converter SIZE 28.3
Sign Change SIGN 13.6
Numeric Blocks
Absolute Value ABS 14.7
16Bit Adder ADD16 32.0
32Bit Adder ADD32 30.5
32&16Bit Adder ADD32&16 31.3
16Bit Subtractor SUB16 32.0
32Bit Subtractor SUB32 30.6
32&16Bit Subtractor SUB32&16 30.1
16Bit Multiplier MUL16 31.6
Arithmetic Blocks 32Bit Multiplier MUL32 31.8
Fixed-Point 32Bit Multiplier MUL32F 33.9
32&16Bit Multiplier MUL32&16 31.3
16Bit Divider DIV16 39.1
32Bit Divider DIV32 40.8
Fixed-Point 32Bit Divider DIV32F 43.6
64&32Bit Divider DIV64&32 42.4
64&16 Bit Divider DIV64&16 42.7
When shifting 64-bit data: Number of shift x1.4 + 32.7
Right Shifter SHIFT-R When shifting 32-bit data: 28.9
When shifting 16-bit data: 25.6
Bit Shift Blocks
When shifting 64-bit data: Number of shift x 1.4 + 31.3
Left Shifter SHIFT-L When shifting 32-bit data: 26.5
When shifting 16-bit data: 24.3
All Rights Reserved. Copyright © 2015, Yokogawa Electric Corporation GS 33J10U10-01EN Feb. 1, 2015-00
<<Contents>> <<Index>> 5
Table Internal Blocks Built-In AGP813 (2/2)
Category Block Name Block Model Processing Time (μs)
AND AND 32.8
OR OR 32.7
NOT NOT 15.0
Bitwise Blocks
16Bit Buffer BUFF16 14.7
2 out of 3 Voter VOTE2&3 18.0
2 out of 4 Voter VOTE2&4 22.0
2 to 1 Selector SEL2&1 18.2
Redundant 2 to 1 Selector RSEL2&1 32.4
Dual 2 to 1 Selector DSEL2&1 20.5
Data Selector SEL Number of data x 1.9 + 23.3
3 to 1 Max Selector MAX3&1 28.4
Max Selector MAX (Number of data -2) x 9.9 + 55.1
Selection Blocks
3 to 1 Min Selector MIN3&1 28.4
Min Selector MIN (Number of data -2) x 9.7 + 61.3
3 to 1 Mid Selector MID3&1 36.1
Mid Selector MID (Number of data -2) x 43.8 + 88.4
3-Input Average Calculator AVG3&1 66.3
Average Calculator AVG (Number of data -2) x 14.4 + 89.8
Comparator Blocks Comparator COMP 24.6
Bistable Blocks SR Flip-Flop SR-FF 17.9
Edge Detection Blocks D Flip-Flop D-FF 21.1
On-Delay Timer OND 16.6
Off-Delay Timer OFFD 16.6
Timer Blocks
One Shot Timer 1 TON1 18.0
One Shot Timer 2 TON2 18.0
High Value Holder HOLD-H 18.9
Low Value Holder HOLD-L 18.9
32Bit Buffer BUFF32 11.8
Advanced Blocks Line Segment FUNC Number of data x 2.8 + 99.2
Scaling SCALE 88.5
First-Order LAG LAG 100.7
Velocity Calculator VEL 84.9
END END 5.6
Auxiliary Blocks
NOP NOP 11.1
All Rights Reserved. Copyright © 2015, Yokogawa Electric Corporation GS 33J10U10-01EN Feb. 1, 2015-00
<<Contents>> <<Index>> 6
Engineering Functions
Computer
Import
Logic
definition file
download
Vnet/IP Bus1
Bus2
FCS
AGP813 F02E.ai
Feature Description
Simulates the logics created on the logic builder. The simulation test can be performed in Step mode or
Break Point mode.
Logic Simulation
User can enter the values to simulate the input signals for testing. The simulation signals can also be
prepared beforehand and saved chronologically in a file for testing.
Sets and displays the follows:
• Modify application logics
• Set line segment tables
• Set simulated input signal
• Set output value to the APL buffers
Set and Display
• Clear set data areas
• Display block details
• Display specified variable values
• Display internal variable values
• Display Logic definitions
Saves the following data used during the logic simulation test into files:
• Application logics
• Line segment data
Save Simulation Data
• Constants
• Simulated inputs
• Simulated outputs
Import Simulation Data Imports the simulation data saved in a file for simulation test.
Display Logic Processing Time Displays the processing times of application logics.
Imports the information file of the application logics created on the Turbomachinery I/O module logic
Import Logic File Information
builder.
All Rights Reserved. Copyright © 2015, Yokogawa Electric Corporation GS 33J10U10-01EN Feb. 1, 2015-00
<<Contents>> <<Index>> 7
Operating Environment
l Hardware Requirement
Conforms to the operating environment of VP6E5100 Standard Engineering Function.
l Software Requirement
Conforms to the operating environment of VP6E5100 Standard Engineering Function.
Necessary software:
VP6E5100 Standard Engineering Function
VP6E5800 Turbomachinery I/O Module Logic Builder Package
Microsoft Excel
For the supported software versions of Microsoft Excel, refer to General Specifications of VP6E5100 Standard
Engineering Function (GS 33J10D10-01EN).
Description
Model VP6E5800 Turbomachinery I/O Module Logic Builder Package
-V Software license
Suffix Code 1 Always 1
1 English version
Ordering Information
Specify the model and suffix code when ordering.
Trademarks
• CENTUM is a registered trademark of Yokogawa Electric Corporation.
• Other company and product names appearing in this document are trademarks or registered trademarks of their
respective holders.
All Rights Reserved. Copyright © 2015, Yokogawa Electric Corporation GS 33J10U10-01EN Mar. 17, 2015-00
Subject to change without notice.