mcp3911 3.3v Two Channel Analog Front End ds20002286d

MCP3911
3.3V Two-Channel Analog Front End

Features Description
• Two Synchronous Sampling 16/24-bit Resolution The MCP3911 is a 2.7V to 3.6V dual channel Analog
Delta-Sigma A/D Converters Front End (AFE) containing two synchronous sampling
• 94.5 dB SINAD, -106.5 dBc Total Harmonic Delta-Sigma Analog-to-Digital Converters (ADC), two
Distortion (THD) (up to 35th harmonic), 111 dB PGAs, phase delay compensation block, low-drift
SFDR for Each Channel internal voltage reference, modulator output block,
Digital Offset and Gain Error Calibration registers and
• 2.7V-3.6V AVDD, DVDD
high-speed 20 MHz SPI compatible serial interface.
• Programmable Data Rate Up to 125 ksps:
The MCP3911 ADCs are fully configurable with
- 4 MHz Maximum Sampling Frequency
features, such as: 16/24-bit resolution, Oversampling
• Oversampling Ratio Up to 4096 Ratio (OSR) from 32 to 4096, gain from 1x to 32x,
• Ultra Low-Power Shutdown Mode with <2 µA independent shutdown and Reset, dithering and auto-
• -122 dB Crosstalk Between the Two Channels zeroing. The communication is largely simplified with the
• Low-Drift 1.2V Internal Voltage Reference: one-byte long commands, including various continuous
7 ppm/°C Read/Write modes that can be accessed by the Direct
Memory Access (DMA) of an MCU with a separate Data
• Differential Voltage Reference Input Pins
Ready pin that can be directly connected to an Interrupt
• High-Gain Programmable Gain Amplifier (PGA) Request (IRQ) input of an MCU.
on Each Channel (up to 32V/V)
The MCP3911 is capable of interfacing a large variety
• Phase Delay Compensation with 1 µs Time
of voltage and current sensors, including shunts,
Resolution
current transformers, Rogowski coils and Hall effect
• Separate Modulator Output Pins for Each sensors.
Channel
• Separate Data Ready Pin for Easy Package Type
Synchronization 20-Lead RESET 1 20 SDI
• Individual 24-Bit Digital Offset and Gain Error SSOP DVDD 2 19 SDO
Correction for Each Channel AVDD 3 18 SCK
• High-Speed 20 MHz SPI Interface with Mode 0,0 CH0+ 4 17 CS
CH0- 5 16 OSC2
and 1,1 Compatibility
CH1- 6 15 OSC1/CLKI
• Continuous Read/Write Modes for Minimum CH1+ 7 14 DR
Communication AGND 8 13 MDAT0
• Low-Power Consumption (8.9 mW at 3.3V, REFIN+/OUT 9 12 MDAT1
5.6 mW at 3.3V in Low-Power mode, typical) REFIN- 10 11 DGND
• Available in Small 20-Lead QFN and SSOP

RESET
DVDD
Packages, Pin-to-Pin Compatible with MCP3901

AVDD
20-Lead
SDO
SDI
• Extended Temperature Range: -40°C to +125°C 4x4 QFN*

20 19 18 17 16
Applications CH0+ 1 15 SCK

CH0- 2 14 CS
• Energy Metering and Power Measurement EP
CH1- 3 21 13 OSC2
• Automotive
CH1+ 4 12 OSC1/CLKI
• Portable Instrumentation
AGND 5 11 DR
• Medical and Power Monitoring
6 7 8 9 10
• Audio/Voice Recognition
REFIN+/OUT
REFIN-
DGND
MDAT1
MDAT0
*Includes Exposed Thermal Pad (EP); see Table 3-1.
 2012-2020 Microchip Technology Inc. DS20002286D-page 1

MCP3911
Functional Block Diagram
AVDD DVDD
REFIN/OUT
Voltage VREFEXT AMCLK Xtal Oscillator
Reference OSC1
Clock MCLK
+
VREF Generation OSC2
– DMCLK/DRCLK
REFIN-
VREF- VREF+ ANALOG DIGITAL

DMCLK OSR[2:0]
PR[1:0]
SINC3 + OFFCAL_CH0 GAINCAL_CH0
SINC1 [23:0] [23:0]
CH0+ + MOD[3:0]
CH0- –
+ X DATA_CH0
[23:0] DR
PGA '6 SDO
Modulator
Phase PHASE[11:0]
) Shifter Digital SPI
Interface RESET
OFFCAL_CH1 GAINCAL_CH1
SDI
[23:0] [23:0]
CH1+ + MOD[7:4] SCK
CH1- –
+ X DATA_CH1 CS
[23:0]
PGA '6 SINC3 +
Modulator SINC1
MODOUT[1:0]
DUAL '6 ADC
Modulator MDAT0
MOD[7:0] Output Block MDAT1
POR POR
AVDD DVDD
Monitoring Monitoring
AGND DGND
DS20002286D-page 2  2012-2020 Microchip Technology Inc.

MCP3911
1.0 ELECTRICAL † Notice: Stresses above those listed under “Absolute
Maximum Ratings” may cause permanent damage to
CHARACTERISTICS
the device. This is a stress rating only and functional
operation of the device at those or any other
Absolute Maximum Ratings† conditions, above those indicated in the operational
VDD ..................................................................... -0.3V to 4.0V listings of this specification, is not implied. Exposure to
Digital inputs and outputs w.r.t. AGND ................. -0.3V to 4.0V maximum rating conditions for extended periods may
Analog input w.r.t. AGND ..................................... ....-2V to +2V affect device reliability.
VREF input w.r.t. AGND .............................. -0.6V to VDD + 0.6V
Storage temperature .....................................-65°C to +150°C
Ambient temp. with power applied ................-65°C to +125°C
Soldering temperature of leads (10 seconds) ............. +300°C
ESD on the analog inputs (HBM,MM) ................. 4.0 kV, 300V
ESD on all other pins (HBM,MM) ........................ 4.0 kV, 300V
1.1 Electrical Specifications

TABLE 1-1: ANALOG SPECIFICATIONS TARGET
Electrical Specifications: Unless otherwise indicated, all parameters apply at AVDD = DVDD = 2.7V to 3.6V; MCLK = 4 MHz;
PRE[1:0] = 00; OSR = 256; GAIN = 1; VREFEXT = 0; CLKEXT = 1; AZ_FREQ = 0; DITHER[1:0] = 11; BOOST[1:0] = 10;
VCM = 0V; TA = -40°C to +125°C; VIN = 1.2 VPP = 424 mVRMS at 50/60 Hz on both channels.
Characteristic Sym Min Typ Max Units Conditions
ADC Performance
Resolution (No Missing 24 — — bits OSR = 256 or greater
Codes)
Sampling Frequency fS(DMCLK) — 1 4 MHz For maximum condition,
BOOST[1:0] = 11
Output Data Rate fD(DRCLK) — 4 125 ksps For maximum condition,
BOOST[1:0] = 11, OSR = 32
Analog Input Absolute CH0+/- -1 — +1 V All analog input channels,
Voltage on CH0+, CH0-, measured to AGND
CH1+, CH1- Pins
Analog Input IIN — ±1 — nA RESET[1:0] = 11,
Leakage Current MCLK running continuously
Differential Input (CHn+ – CHn-) -600/GAIN — +600/GAIN mV VREF = 1.2V,
Voltage Range proportional to VREF
Offset Error VOS -2 0.2 +2 mV Note 4
Offset Error Drift — 0.5 — µV/°C
Gain Error GE -6 — +6 % Note 4
Note 1: This specification implies that the ADC output is valid over this entire differential range and that there is no
distortion or instability across this input range. Dynamic performance specified at -0.5 dB below the maximum
signal range, VIN = 1.2 VPP = 424 mVRMS, VREF = 1.2V at 50/60 Hz. See Section 4.0, Terminologies and
Formulas for definition. This parameter is established by characterization and is not 100% tested. See
performance graphs for other than default settings provided here.
2: For these operating currents, the following Configuration bit settings apply: SHUTDOWN[1:0] = 00,
RESET[1:0] = 00, VREFEXT = 0, CLKEXT = 0.
VREFEXT = 1, CLKEXT = 1.
4: Applies to all gains. Offset and gain errors depend on PGA gain setting; see Section 2.0, Typical Performance
Curves for typical performance.
5: Outside of this range, the ADC accuracy is not specified. An extended input range of ±2V can be applied
continuously to the part with no damage.
6: For proper operation and optimizing ADC accuracy, AMCLK should be limited to the maximum frequency defined
in Table 5-2 as a function of the BOOST and PGA settings chosen. MCLK can take larger values as long as the
prescaler settings (PRE[1:0]) limit AMCLK = MCLK/PRESCALE in the defined range in Table 5-2.

MCP3911
TABLE 1-1: ANALOG SPECIFICATIONS TARGET (CONTINUED)
Gain Error Drift — 1 — ppm/°C
Integral Nonlinearity INL — 5 — ppm
Differential Input ZIN 232 — — k G = 1, proportional to 1/AMCLK
Impedance 142 — — k G = 2, proportional to 1/AMCLK
72 — — k G = 4, proportional to 1/AMCLK
Signal-to-Noise and SINAD 92 94.5 — dB
Distortion Ratio (Note 1)
Total Harmonic Distortion THD — -106.5 -103 dBc Includes the first 35 harmonics
(Note 1)
Signal-to-Noise Ratio SNR 92 95 — dB
(Note 1)
Spurious-Free Dynamic SFDR — 111 — dBFS
Range (Note 1)
Crosstalk (50, 60 Hz) CTALK — -122 — dB
AC Power Supply Rejection AC PSRR — -73 — dB AVDD = DVDD = 3.3V + 0.6VPP,
50/60 Hz, 100/120 Hz
DC Power DC PSRR — -73 — dB AVDD = DVDD = 2.7V to 3.6V
Supply Rejection
DC Common-Mode DC CMRR — -105 — dB VCM from -1V to +1V
Rejection

MCP3911
Internal Voltage Reference
Tolerance VREF 1.176 1.2 1.224 V VREFEXT = 0, TA = +25°C only
Temperature Coefficient TCVREF — 7 — ppm/°C TA = -40°C to +125°C,
VREFEXT = 0
Output Impedance ZOUTVREF — 2 — k VREFEXT = 0
Internal Voltage Reference AIDDVREF — 25 — µA VREFEXT = 0,
Operating Current SHUTDOWN[1:0] = 11
Voltage Reference Input
Input Capacitance — — 10 pF
Differential Input Voltage VREF 1.1 — 1.3 V VREFEXT = 1
Range (VREF+ – VREF-)
Absolute Voltage on VREF+ VREF- + 1.1 — VREF- + 1.3 V VREFEXT = 1
REFIN+ Pin
Absolute Voltage on VREF- -0.1 — +0.1 V REFIN- should be connected to
REFIN- Pin AGND when VREFEXT = 0
Master Clock Input
Master Clock Input fMCLK — — 20 MHz CLKEXT = 1 (Note 6)
Frequency Range
Crystal Oscillator fXTAL 1 — 20 MHz CLKEXT = 0 (Note 6)
Operating Frequency
Range
Analog Master Clock AMCLK — — 16 MHz Note 6
Power Supply
Operating Voltage, Analog AVDD 2.7 — 3.6 V
Operating Voltage, Digital DVDD 2.7 — 3.6 V
Operating Current, IDD,A — 1.5 2.3 mA BOOST[1:0] = 00
Analog (Note 2) — 1.8 2.8 mA BOOST[1:0] = 01
— 2.5 3.5 mA BOOST[1:0] = 10
— 4.4 6.25 mA BOOST[1:0] = 11

MCP3911
Operating Current, Digital IDD,D — 0.2 0.3 mA MCLK = 4 MHz,
proportional to MCLK
— 0.7 — mA MCLK = 16 MHz,
proportional to MCLK
Shutdown Current, Analog IDDS,A — — 1 µA AVDD pin only (Note 3)
Shutdown Current, Digital IDDS,D — — 1 µA DVDD pin only (Note 3)
1.2 Serial Interface Characteristics
TABLE 1-2: SERIAL DC CHARACTERISTICS

Electrical Specifications: Unless otherwise indicated, all parameters apply at DVDD = 2.7 to 3.6V;
TA = -40°C to +125°C; CLOAD = 30 pF; applies to all digital I/Os.
Characteristics Sym Min Typ Max Units Test Conditions
High-Level Input Voltage VIH 0.7 DVDD — — V Schmitt Triggered
Low-Level Input Voltage VIL — — 0.3 DVDD V Schmitt Triggered
Input Leakage Current ILI — — ±1 µA CS = DVDD,
VIN = DGND to DVDD
Output leakage Current ILO — — ±1 µA CS = DVDD,
VOUT = DGND or DVDD
Hysteresis of Schmitt VHYS — 200 — mV DVDD = 3.3V only (Note 2)
Trigger Inputs
Low-Level Output Voltage VOL — — 0.4 V IOL = +2.1 mA, DVDD = 3.3V
High-Level Output Voltage VOH DVDD – 0.5 — — V IOH = -2.1 mA, DVDD = 3.3V
Internal Capacitance CINT — — 7 pF TA = +25°C, SCK = 1.0 MHz,
(all inputs and outputs) DVDD = 3.3V (Note 1)
Note 1: This parameter is periodically sampled and not 100% tested.
2: This parameter is established by characterization and not production tested.

MCP3911
TABLE 1-3: SERIAL AC CHARACTERISTICS
Electrical Specifications: Unless otherwise indicated, all parameters apply at DVDD = 2.7 to 3.6V,
TA = -40°C to +125°C, GAIN = 1, CLOAD = 30 pF.
Characteristics Sym Min Typ Max Units Test Conditions
Serial Clock Frequency fSCK — — 20 MHz
CS Setup Time tCSS 25 — — ns
CS Hold Time tCSH 50 — — ns
CS Disable Time tCSD 50 — — ns
Data Setup Time tSU 5 — — ns
Data Hold Time tHD 10 — — ns
Serial Clock High Time tHI 20 — — ns
Serial Clock Low Time tLO 20 — — ns
Serial Clock Delay Time tCLD 50 — — ns
Serial Clock Enable Time tCLE 50 — — ns
Output Valid from SCK Low tDO — — 25 ns
Modulator Output tDOMDAT — — 1/(2 x AMCLK) s
Valid from AMCLK High
Output Hold Time tHO 0 — — ns Note 1
Output Disable Time tDIS — — 25 ns Note 1
Reset Pulse Width (RESET) tMCLR 100 — — ns
Data Transfer Time to DR tDODR — — 25 ns Note 2
(Data Ready)
Modulator Mode Entry to tMODSU — — 100 ns
Modulator Data Present
Data Ready Pulse Low Time tDRP — 1/DMCLK — µs
Note 1: This parameter is periodically sampled and not 100% tested.
2: This parameter is established by characterization and not production tested.
TABLE 1-4: TEMPERATURE SPECIFICATIONS

Electrical Specifications: Unless otherwise indicated, all parameters apply at AVDD = 2.7 to 3.6V;
DVDD = 2.7 to 3.6V.
Parameters Sym Min Typ Max Units Conditions
Temperature Ranges
Operating Temperature Range TA -40 — +125 °C Note 1
Storage Temperature Range TA -65 — +150 °C
Thermal Package Resistances
Thermal Resistance, 20-Lead QFN JA — 43 — °C/W
Thermal Resistance, 20-Lead SSOP JA — 87.3 — °C/W
Note 1: The internal junction temperature (TJ) must not exceed the absolute maximum specification of +150°C.

MCP3911
CS
fSCK
tHI tLO tCSH
Mode 1,1
SCK Mode 0,0
tDO tDIS
tHO
SDO MSB Out LSB Out
Don’t Care
SDI
FIGURE 1-1: Serial Output Timing Diagram.
tCSD
CS tCLE
tCSS fSCK tCLD
tHI tLO tCSH
Mode 1,1
SCK Mode 0,0
tSU tHD
SDI MSB In LSB In
High-Z
SDO
FIGURE 1-2: Serial Input Timing Diagram.
1/fD tDRP
DR
tDODR
SCK
SDO
FIGURE 1-3: Data Ready Pulse/Sampling Timing Diagram.

MCP3911
H
Timing Waveform for tDO Waveform for tDIS
SCK VIH
CS
tDO
90%
SDO tDIS
SDO High-Z
10%
Timing Waveform for MDAT0/1

Modulator Output Function
OSC1/CLKI
tDOMDAT
MDAT
FIGURE 1-4: Timing Diagrams (Continued).

MCP3911
NOTES:

MCP3911
2.0 TYPICAL PERFORMANCE CURVES
Note: The graphs and tables provided following this note are a statistical summary based on a limited number of
samples and are provided for informational purposes only. The performance characteristics listed herein
are not tested or guaranteed. In some graphs or tables, the data presented may be outside the specified
operating range (e.g., outside specified power supply range) and therefore outside the warranted range.
Note: Unless otherwise indicated, AVDD = 3.3V; DVDD = 3.3V; TA = +25°C; MCLK = 4 MHz; PRESCALE = 1;
OSR = 256; GAIN = 1; Dithering = Maximum; VIN = -0.5 dBFS at 60 Hz; VREFEXT = 0; CLKEXT = 1; AZ_FREQ = 0;
BOOST = 1x.
0 0
fIN = -0.5 dBFS @ 60 Hz fIN = -0.5 dBFS @ 60 Hz
-20 fD = 3.9 ksps -20
fD = 3.9 ksps
-40 16384 pt FFT -40 16384 pt FFT
OSR = 256
Amplitude (dB)
OSR = 256
Amplitude (dB)
-60 Dithering = None -60 Dithering = Maximum
-80 -80
-100 -100
-120 -120
-140 -140
-160 -160
-180 -180
-200 -200
0 200 400 600 800 1000 1200 1400 1600 1800 2000 0 200 400 600 800 1000 1200 1400 1600 1800 2000
Frequency (Hz) Frequency (Hz)
FIGURE 2-1: Spectral Response. FIGURE 2-4: Spectral Response.
0 0
fIN = -60 dBFS@ 60 Hz fIN = -60 dBFS @ 60 Hz
-20 fD = 3.9 ksps -20 fD = 3.9 ksps
-40 16384 pt FFT -40 16384 pt FFT
OSR = 256 OSR = 256
Amplitude (dB)
Amplitude (dB
-60 Dithering = None -60 Dithering = Maximum

-80 -80
-100 -100
-120 -120
-140 -140
-160 -160
-180 -180
-200 -200
0 200 400 600 800 1000 1200 1400 1600 1800 2000 0 200 400 600 800 1000 1200 1400 1600 1800 2000
Frequency (Hz) Frequency (Hz)
FIGURE 2-2: Spectral Response. FIGURE 2-5: Spectral Response.

Frequency of Occurrence
-107.3 -107.1 -107.0 -106.8 -106.7 -106.5 -106.4 -106.2 -106.1 -105.9 -105.8 94.2 94.3 94.5 94.6 94.8 94.9 95.1 95.2 95.4 95.5
Total Harmonic Distortion (-dBc) Signal-to-Noise and Distortion Ratio (dB)
FIGURE 2-3: THD Histogram. FIGURE 2-6: SINAD Histogram.

MCP3911
BOOST = 1x.
104.5 106 107.5 109 110.5 112 113.5 115 15.3 15.4 15.4 15.4 15.5 15.5 15.5 15.5 15.6 15.6
Spurious Free Dynamic Range (dBFS) Effective Number of Bits (SINAD)
FIGURE 2-7: Spurious-Free Dynamic FIGURE 2-10: ENOB SINAD Histogram.

Range Histogram.
94.5 94.6 94.8 94.9 95.1 95.2 95.4 95.5 95.6 95.8 95.9 15.4 15.4 15.5 15.5 15.5 15.5 15.6 15.6 15.6 15.6
Signal-to-Noise Ratio (dB) Effective Number of Bits (SNR)
FIGURE 2-8: SNR Histogram. FIGURE 2-11: ENOB SNR Histogram.
5000
Total Harmonic Distortion (dBc)
0
Channel 1 Dithering = Maximum
Frequency Of Occurrence
4500 VIN = 0V -10

Dithering = Medium
4000 TA = +25°C -20 Dithering = Minimum
16384 Consecutive
3500 Readings -30 Dithering = None
-40
3000
-50
2500
-60
2000 -70
1500 -80
1000 -90
500 -100
0 -110
-120
32 64 128 256 512 1024 2048 4096
Output Code (LSB) Oversampling Ratio (OSR)
FIGURE 2-9: Noise Histogram. FIGURE 2-12: THD vs. OSR.

MCP3911
BOOST = 1x.
120 0

Signal-to-Noise and Distortion
110 -10
100 -20 Boost = 0.5x
90 -30
Boost = 0.66x
80 -40
Ratio (dB)
70 -50
60 -60
50 -70 Boost = 1x
40 -80
Dithering = Maximum
30 -90
Dithering = Medium
20 Dithering = Minimum -100 Boost = 2x
10 Dithering = None -110
0 -120
32 64 128 256 512 1024 2048 4096 0 5 10 15 20 25 30
Oversampling Ratio (OSR) MCLK Frequency (MHz)
FIGURE 2-13: SINAD vs. OSR. FIGURE 2-16: THD vs. MCLK.
L
120 120

Signal-to-Noise Ratio (dB)
110 110
100 100
90 90 Boost = 2x
80 80
Ratio (dB)
70 70
60 60 Boost = 0.5x
Boost = 1x
50 50
40 Dithering = Maximum 40 Boost = 0.66x
30 Dithering = Medium 30
20 Dithering = Minimum 20
10 Dithering = NoQe 10
0 0
32 64 128 256 512 1024 2048 4096 0 5 10 15 20 25 30
FIGURE 2-14: SNR vs.OSR. FIGURE 2-17: SINAD vs. MCLK.
140 120
Spurious Free Dynamic Range
130 110
120 100
110 Boost = 2x
90
100
90 80
(dBFS)
80 70 Boost = 1x
70 60
Boost = 0.5x
60 50
50 Boost = 0.66x
40
40 Dithering = Maximum
30
30 Dithering = Medium
20
20 Dithering = Minimum
10 Dithering = None
10
0 0
32 64 128 256 512 1024 2048 4096 0 5 10 15 20 25 30
FIGURE 2-15: SFDR vs. OSR. FIGURE 2-18: SNR vs. MCLK.

MCP3911
BOOST = 1x.
120 100

110
Boost = 2x
100 95
90 Auto Zero Speed = Fast
80 90
Ratio (dB)
70 Boost = 1x
(dBFS)
60 85
Boost = 0.66x
50 Auto Zero Speed = Slow
40 Boost = 0.5x 80
30
20 75
10
0 70
0 5 10 15 20 25 30 1 2 4 8 16 32
Frequency (MHz) Gain (V/V)
FIGURE 2-19: SFDR vs. MCLK. FIGURE 2-22: SINAD vs. GAIN vs. AZ
Speed Chart.
120 0

-10
110
100 -20
90 -30
-40
80
Ratio (dB)
-50
70
-60
60
OSR = 32 -70
50 OSR = 64
-80 Channel 1
40 OSR = 128
OSR = 256 -90 Channel 0
30 OSR = 512 -100
20 OSR = 1024
OSR = 2048 -110
10
OSR = 4096 -120
0
-6 -5 -4 -3 -2 -1 0 1 2 3
1 2 4 8 16 32
Gain (V/V) Input Signal Amplitude (dBFS)
FIGURE 2-20: SINAD vs. GAIN. FIGURE 2-23: THD vs. Input Signal
Amplitude.
120 120
Signal to Noise and Distortion
110 110
100 100
90 90
80 80 Channel 1
Ratio (dB)
Ratio (dB)
70 70 Channel 0
60 OSR = 32 60
50 OSR = 64 50
OSR = 128 40
40 OSR = 256
30
30 OSR = 512
OSR = 1024 20
20
OSR = 2048 10
10 OSR = 4096 0
0
-6 -5 -4 -3 -2 -1 0 1 2 3
1 2 4 8 16 32
Gain (V/V) Input Signal Amplitude (dBFS)
FIGURE 2-21: SINAD vs. GAIN (Dithering FIGURE 2-24: SINAD vs. Input Signal
Off). Amplitude.

MCP3911
BOOST = 1x.
120 100

110
90
100 80
90
70
80 Channel 1
Ratio (dB)
70 Channel 0 60
60 50
50 40 G=1
40 G=2
30 G=4
30
20 G=8
20 G = 16
10 10 G = 32
0 0
-6 -5 -4 -3 -2 -1 0 1 2 3 -50 -25 0 25 50 75 100 125 150
Input Signal Amplitude (dBFS) Temperature (°C)
FIGURE 2-25: SNR vs. Input Signal FIGURE 2-28: SINAD vs. Temperature.
Amplitude.
120 100
Spurious Free Dyanmic Range
110 90

100 Channel 1
80
90 Channel 0
70
80
70 60
(dBFS)
60 50
50 40 G=1
40 G=2
30 G=4
30 G=8
20
20 G = 16
10 10 G = 32
0 0
-6 -5 -4 -3 -2 -1 0 1 2 3 -50 -25 0 25 50 75 100 125 150
Input Signal Amplitude (dBFS) Temperature (°C)
FIGURE 2-26: SFDR vs. Input Signal FIGURE 2-29: SNR vs. Temperature.
Amplitude.
0 120
Total Harominc Distortion (dBc)
G=1
-10 110
G=2
-20 G=4 100
-30 G=8 90
-40 G = 16
G = 32
80
(dBFS)
-50 70
-60 60
-70 50
G=1
-80 40 G=2
-90 30 G=4
-100 20 G=8
G = 16
-110 10 G = 32
-120 0
-50 -25 0 25 50 75 100 125 150 -50 -25 0 25 50 75 100 125 150
Temperature (°C) Temperature (°C)
FIGURE 2-27: THD vs. Temperature. FIGURE 2-30: SFDR vs. Temperature.

MCP3911
BOOST = 1x.
400 5
350 4
Channel 1 Offset (mV)
300 3 G=1
Gain Error (%)

250 2 G=2
G=1
200 G=2
1
G=4
150 G=4 0
G=8
100 G = 16 -1
G = 32 G=8
50 -2
G = 32 G = 16
0 -3
-50 -4
-100 -5
-50 -25 0 25 50 75 100 125 150 -50 -25 0 25 50 75 100 125 150
FIGURE 2-31: Channel 0 Offset vs. FIGURE 2-34: Gain Error vs. Temperature.
Temperature.
400 1.2008
Internal Voltage Reference (V)

350 1.2007
Channel 0 Offset (mV)
300 1.2006
250
1.2005
200 G=1
G=2 1.2004
150 G=4
G=8 1.2003
100
G = 16
50 G = 32
1.2002
0 1.2001
-50 1.2000
-100 1.1999
-50 -25 0 25 50 75 100 125 150 -50 0 50 100 150
FIGURE 2-32: Channel 1 Offset vs. FIGURE 2-35: Internal Voltage Reference
Temperature. vs. Temperature.
0 1.2003
Internal Voltage Reference (V)
-20 1.2002
Offset Error (mV)
-40 Channel 1 1.2001
-60 1.2000
-80 1.1999
Channel 0
-100 1.1998
-120 1.1997
-50 -25 0 25 50 75 100 125 150 2.5 2.6 2.7 2.8 2.9 3 3.1 3.2 3.3 3.4 3.5 3.6
Temperature (°C) VDD (V)
FIGURE 2-33: Channel-to-Channel Offset FIGURE 2-36: Internal Voltage Reference

Match vs. Temperature. vs. Supply Voltage.

MCP3911
BOOST = 1x.
4.5
14
4
AIDD, Boost = 2x
12
3.5
10 3
IDD (mA)
AIDD, Boost = 1x
8 2.5
2 AIDD, Boost = 0.6x
6
1.5
1
2 0.5 DIDD, All Boost Settings

0
0 0 2.5 5 7.5 10 12.5 15 17.5 20 22.5 25 27.5 30
0 3 6 9 12 15 18 21 24 MCLK Frequency (MHz)
Internal Voltage Reference Drift (ppm/C)
FIGURE 2-37: VREF Drift Data Histogram FIGURE 2-40: Operating Current vs.
Chart. MCLK, VDD = 3.3V.
25 4
Integral Non-Linearity Error
AIDD, Boost = 2x
20
Channel 1 3.5
15
3
10
IDD (mA)
(ppm)
5 2.5
AIDD, Boost = 1x
0 2
AIDD, Boost = 0.6x
-5 1.5
-10 Channel 0
-15
-20 0.5 DIDD, All Boost Settings
-25 0
-0.6 -0.3 0 0.3 0.6 0 2.5 5 7.5 10 12.5 15 17.5 20 22.5 25 27.5 30
Input Voltage (V) MCLK Frequency (MHz)
FIGURE 2-38: Integral Nonlinearity FIGURE 2-41: Operating Current vs.

(Dithering Maximum). MCLK, VDD = 2.7V.
25
Integral Non-Linearity Error
20
15
10 Channel 0
(ppm)
5
0
-5
Channel 1
-10
-15
-20
-25
-0.6 -0.3 0 0.3 0.6
Input Voltage (V)
FIGURE 2-39: Integral Nonlinearity

(Dithering Off).

MCP3911
NOTES:

MCP3911
3.0 PIN DESCRIPTION
The descriptions of the pins are listed in Table 3-1.
TABLE 3-1: PIN FUNCTION TABLE

Pin No. Pin No.
Symbol Function
SSOP QFN
1 18 RESET Master Reset Logic Input Pin

2 19 DVDD Digital Power Supply Pin
3 20 AVDD Analog Power Supply Pin
4 1 CH0+ Noninverting Analog Input Pin for Channel 0
5 2 CH0- Inverting Analog Input Pin for Channel 0
6 3 CH1- Inverting Analog Input Pin for Channel 1
7 4 CH1+ Noninverting Analog Input Pin for Channel 1
8 5 AGND Analog Ground Pin, Return Path for Internal Analog Circuitry
9 6 REFIN+/OUT Noninverting Voltage Reference Input and Internal Reference Output Pin
10 7 REFIN- Inverting Voltage Reference Input Pin
11 8 DGND Digital Ground Pin, Return Path for Internal Digital Circuitry
12 9 MDAT1 Modulator Data Output Pin for Channel 1
13 10 MDAT0 Modulator Data Output Pin for Channel 0
14 11 DR Data Ready Signal Output Pin
15 12 OSC1/CLKI Oscillator Crystal Connection Pin or External Clock Input Pin
16 13 OSC2 Oscillator Crystal Connection Pin
17 14 CS Serial Interface Chip Select Pin
18 15 SCK Serial Interface Clock Input Pin
19 16 SDO Serial Interface Data Input Pin
20 17 SDI Serial Interface Data Input Pin
— 21 EP Exposed Thermal Pad. Must be connected to AGND or left floating.
3.1 Master Reset (RESET) 3.2 Digital VDD (DVDD)

This pin is active-low and places the entire chip in a DVDD is the power supply pin for the digital circuitry
Reset state when active. within the MCP3911. For specified operation, this pin
When RESET = DGND, all registers are reset to their requires appropriate bypass capacitors and should be
default value and no communication can take place. maintained between 2.7V and 3.6V.
No clock is distributed inside the part, except in the
input structure, if MCLK is applied (if Idle, no clock is 3.3 Analog VDD (AVDD)
distributed). This state is equivalent to a POR state.
AVDD is the power supply pin for the analog circuitry
Since the default state of the ADCs is on, the analog within the MCP3911. For specified operation, this pin
power consumption when RESET = DGND is equivalent requires appropriate bypass capacitors and should be
to RESET = VDD. Only the digital power consumption is maintained between 2.7V and 3.6V.
largely reduced because this current consumption is
essentially dynamic and is reduced drastically when
there is no running clock.
All the analog biases are enabled during a Reset so
that the part is fully operational just after a RESET
rising edge, if the MCLK is applied during the rising
edge. If not applied, there is a small time after RESET
when the conversion may not be accurate, corresponding
to the start-up of the charge pump of the input structure.
This input is Schmitt triggered.

MCP3911
3.4 ADC Differential Analog inputs 3.7 Inverting Reference Input (REFIN-)
(CHn+/CHn-) This pin is the inverting side of the differential voltage
The two fully differential analog voltage inputs for the reference input for both ADCs. When using an external
Delta-Sigma ADCs are: differential voltage reference, it should be connected to
its VREF- pin. When using an external single-ended
• CH0- and CH0+
voltage reference, or when VREFEXT = 0 (default) and
• CH1- and CH1+ using the internal voltage reference, this pin should be
The linear and specified region of the channels is directly connected to AGND.
dependent on the PGA gain. This region corresponds
to a differential voltage range of ±600 mV/GAIN with 3.8 Digital Ground Connection (DGND)
VREF = 1.2V.
DGND is the ground connection to the internal digital
The maximum differential voltage is proportional to the circuitry (see Functional Block Diagram). To ensure
VREF voltage. The maximum absolute voltage, with optimal accuracy and noise cancellation, DGND must
respect to AGND, for each CHn+/- input pin is ±1V with be connected to the same ground as AGND, preferably
no distortion, and ±2V with no breaking after con- with a star connection. If a digital ground plane is
tinuous voltage. This maximum absolute voltage is not available, it is recommended that this pin is tied to this
proportional to the VREF voltage. PCB plane. This plane should also reference all other
digital circuitry in the system.
3.5 Analog Ground (AGND)
AGND is the ground connection to the internal analog 3.9 Modulator Data Output Pin for
circuitry (see the Functional Block Diagram). To Channel 1 and Channel 0
ensure accuracy and noise cancellation, this pin must (MDAT1/MDAT0)
be connected to the same ground as DGND, preferably
with a star connection. If an analog ground plane is MDAT0 and MDAT1 are the output pins for the modulator
available, it is recommended that this pin is tied to this serial bit streams of ADC Channels 0 and 1, respectively.
Printed Circuit Board (PCB) plane. This plane should These pins are high-impedance when their correspond-
also reference all other analog circuitry in the system. ing MODOUT bit is logic low. When the MODOUT[1:0]
bits are enabled, the modulator bit stream of the corre-
sponding channel is present on the pin and updated at
3.6 Noninverting Reference Input,
the AMCLK frequency (see Section 5.4 “Modulator
Internal Reference Output Output Block” for a complete description of the modula-
(REFIN+/OUT) tor outputs). These pins can be directly connected to an
MCU or a DSP when a specific digital filtering is needed.
This pin is the noninverting side of the differential
voltage reference input for both ADCs or the internal
voltage reference output. 3.10 Data Ready Output (DR)
When VREFEXT = 1, an external voltage reference The Data Ready pin indicates that a new conversion
source can be used and the internal voltage reference result is ready to be read. The default state of this pin
is disabled. When using an external differential voltage is high when DR_HIZ = 1 and is high-impedance when
reference, it should be connected to its VREF+ pin. DR_HIZ = 0 (default). After each conversion is finished,
When using an external single-ended reference, it a logic low pulse takes place on the Data Ready pin to
should be connected to this pin. indicate that the conversion result is ready as an inter-
When VREFEXT = 0, the internal voltage reference is rupt. This pulse is synchronous with the master clock
enabled and connected to this pin through a switch. If and has a defined and constant width.
used as a voltage source, this voltage reference has a The Data Ready pin is independent of the SPI interface
minimal drive capability, and thus needs proper and acts like an interrupt output. The Data Ready pin
buffering and bypass capacitances. A 0.1 µF ceramic state is not latched and the pulse width (and period) are
capacitor is sufficient in most cases. both determined by the MCLK frequency oversampling
If the voltage reference is only used as an internal rate and internal clock prescale settings. The DR pulse
VREF, adding bypass capacitance on REFIN+/OUT is width is equal to one DMCLK period and the frequency
not necessary for keeping ADC accuracy. If left floating, of the pulses is equal to DRCLK (see Figure 1-3).
a minimal 0.1 µF ceramic capacitance can be con- Note: This pin should not be left floating when the
nected to avoid EMI/EMC susceptibility issues due to DR_HIZ bit is low; a 100 k pull-up resistor
the antenna created by the REFIN+/OUT pin. connected to DVDD is recommended.

MCP3911
3.11 Oscillator and Master Clock Input 3.14 Serial Data Output (SDO)
Pins (OSC1/CLKI, OSC2) This is the SPI data output pin. Data are clocked out of
OSC1/CLKI and OSC2 provide the Master Clock the device on the FALLING edge of SCK.
(MCLK) for the device. When CLKEXT = 0, a resonant This pin stays high-impedance during the first
crystal or clock source with a similar sinusoidal wave- command byte. It also stays high-impedance during the
form must be placed across these pins to ensure whole communication for write commands and when
proper operation. The typical clock frequency specified the CS pin is high or when the RESET pin is low. This
is 4 MHz. For proper operation and optimizing ADC pin is active only when a read command is processed.
accuracy, AMCLK should be limited to the maximum Each read is processed by packet of eight bits.
frequency defined in Table 5-3 as a function of the
BOOST and PGA settings chosen. MCLK can take 3.15 Serial Data Input (SDI)
larger values as long as the prescaler settings
(PRE[1:0]) limit AMCLK = MCLK/PRESCALE in the This is the SPI data input pin. Data are clocked into the
defined range in Table 5-3. For proper operation, device on the RISING edge of SCK.
appropriate load capacitance should be connected to When CS is low, this pin is used to communicate with a
these pins. series of 8-bit commands.
The interface is half-duplex (inputs and outputs do not
3.12 Chip Select (CS)
happen at the same time).
This pin is the SPI chip select that enables the serial Each communication starts with a chip select falling
communication. When this pin is high, no communica- edge, followed by an 8-bit command word entered
tion can take place. A chip select falling edge initiates through the SDI pin. Each command is either a read or
the serial communication and a chip select rising edge write command. Toggling SDI during a read command
terminates the communication. No communication can has no effect.
take place when CS is low or when RESET is low.
3.13 Serial Data Clock (SCK)

This is the serial clock pin for SPI communication.
Data are clocked into the device on the RISING edge
and out of the device on the FALLING edge of SCK.
The MCP3911 interface is compatible with both SPI 0,0
and 1,1 modes. SPI modes can be changed during a
CS high time.
The maximum clock speed specified is 20 MHz.

MCP3911
NOTES:

MCP3911
4.0 TERMINOLOGIES AND 4.1 MCLK – Master Clock
FORMULAS This is the fastest clock present in the device. This is
This section defines the terms and formulas used the frequency of the crystal placed at the OSC1/OSC2
throughout this data sheet. The following terms are inputs when CLKEXT = 0 or the frequency of the clock
defined: input at the OSC1/CLKI when CLKEXT = 1. See
Figure 4-1.
• MCLK – Master Clock
• AMCLK – Analog Master Clock 4.2 AMCLK – Analog Master Clock
• DMCLK – Digital Master Clock
This is the clock frequency that is present on the analog
• DRCLK – Data Rate Clock
portion of the device after prescaling has occurred via
• OSR – Oversampling Ratio the CONFIG PRE[1:0] register bits. The analog portion
• Offset Error includes the PGAs and the two Delta-Sigma
• Gain Error modulators.
• Integral Nonlinearity Error
• Signal-to-Noise Ratio (SNR) MCLK
AMCLK = -------------------------------
• Signal-to-Noise Ratio and Distortion (SINAD) PRESCALE
• Total Harmonic Distortion (THD)
• Spurious-Free Dynamic Range (SFDR) TABLE 4-1: MCP3911 OVERSAMPLING
• MCP3911 Delta-Sigma Architecture RATIO SETTINGS
• Idle Tones Config Analog Master Clock
• Dithering Prescale
PRE[1:0]
• Crosstalk
• PSRR 0 0 AMCLK = MCLK/1 (default)
• CMRR 0 1 AMCLK = MCLK/2
• ADC Reset Mode 1 0 AMCLK = MCLK/4
• Hard Reset Mode (RESET = DGND) 1 1 AMCLK = MCLK/8
• ADC Shutdown Mode
• Full Shutdown Mode
FIGURE 4-1: Clock Sub-Circuitry.

MCP3911
4.3 DMCLK – Digital Master Clock 4.4 DRCLK – Data Rate Clock
This is the clock frequency that is present on the digital This is the output data rate (i.e., the rate at which the
portion of the device after prescaling and division by ADCs output new data). New data are signaled by a
four. This is also the sampling frequency, which is the data ready pulse on the DR pin.
rate at which the modulator outputs are refreshed. This data rate is dependent on the OSR and the
Each period of this clock corresponds to one sample prescaler with the following formula:
and one modulator output. See Figure 4-1.
EQUATION 4-2:
EQUATION 4-1:
DMCLK AMCLK MCLK
AMCLK MCLK DRCLK = ---------------------- = --------------------- = -----------------------------------------------------------
DMCLK = --------------------- = ---------------------------------------- OSR 4  OSR 4  OSR  PRESCALE
4 4  PRESCALE
Since this is the output data rate and the decimation
filter is a SINC (or notch) filter, there is a notch in the
filter transfer function at each integer multiple of this
rate.
The following table describes the various combinations
of OSR and PRESCALE and their associated AMCLK,
DMCLK and DRCLK rates.

MCP3911
TABLE 4-2: DEVICE DATA RATES IN FUNCTION OF MCLK, OSR AND PRESCALE, MCLK = 4 MHz
ENOB from
DRCLK SINAD
PRE[1:0] OSR[2:0] OSR AMCLK DMCLK DRCLK SINAD
(ksps) (dB)(1)
(bits)(1)
1 1 1 1 1 4096 MCLK/8 MCLK/32 MCLK/131072 0.035 98 16
1 1 1 1 1 2048 MCLK/8 MCLK/32 MCLK/65536 0.061 98 16
1 1 1 1 1 1024 MCLK/8 MCLK/32 MCLK/32768 0.122 97 15.8
1 1 1 1 1 512 MCLK/8 MCLK/32 MCLK/16384 0.244 96 15.6
1 1 0 1 1 256 MCLK/8 MCLK/32 MCLK/8192 0.488 95 15.5
1 1 0 1 0 128 MCLK/8 MCLK/32 MCLK/4096 0.976 90 14.7
1 1 0 0 1 64 MCLK/8 MCLK/32 MCLK/2048 1.95 83 13.5
1 1 0 0 0 32 MCLK/8 MCLK/32 MCLK/1024 3.9 70 11.3
1 0 1 1 1 4096 MCLK/4 MCLK/16 MCLK/65536 0.061 98 16
1 0 1 1 1 2048 MCLK/4 MCLK/16 MCLK/32768 0.122 98 16
1 0 1 1 1 1024 MCLK/4 MCLK/16 MCLK/16384 0.244 97 15.8
1 0 1 1 1 512 MCLK/4 MCLK/16 MCLK/8192 0.488 96 15.6
1 0 0 1 1 256 MCLK/4 MCLK/16 MCLK/4096 0.976 95 15.5
1 0 0 1 0 128 MCLK/4 MCLK/16 MCLK/2048 1.95 90 14.7
1 0 0 0 1 64 MCLK/4 MCLK/16 MCLK/1024 3.9 83 13.5
1 0 0 0 0 32 MCLK/4 MCLK/16 MCLK/512 7.8125 70 11.3
0 1 1 1 1 4096 MCLK/2 MCLK/8 MCLK/32768 0.122 98 16
0 1 1 1 1 2048 MCLK/2 MCLK/8 MCLK/16384 0.244 98 16
0 1 1 1 1 1024 MCLK/2 MCLK/8 MCLK/8192 0.488 97 15.8
0 1 1 1 1 512 MCLK/2 MCLK/8 MCLK/4096 0.976 96 15.6
0 1 0 1 1 256 MCLK/2 MCLK/8 MCLK/2048 1.95 95 15.5
0 1 0 1 0 128 MCLK/2 MCLK/8 MCLK/1024 3.9 90 14.7
0 1 0 0 1 64 MCLK/2 MCLK/8 MCLK/512 7.8125 83 13.5
0 1 0 0 0 32 MCLK/2 MCLK/8 MCLK/256 15.625 70 11.3
0 0 1 1 1 4096 MCLK MCLK/4 MCLK/16384 0.244 98 16
0 0 1 1 0 2048 MCLK MCLK/4 MCLK/8192 0.488 98 16
0 0 1 0 1 1024 MCLK MCLK/4 MCLK/4096 0.976 97 15.8
0 0 1 0 0 512 MCLK MCLK/4 MCLK/2048 1.95 96 15.6
0 0 0 1 1 256 MCLK MCLK/4 MCLK/1024 3.9 95 15.5
0 0 0 1 0 128 MCLK MCLK/4 MCLK/512 7.8125 90 14.7
0 0 0 0 1 64 MCLK MCLK/4 MCLK/256 15.625 83 13.5
0 0 0 0 0 32 MCLK MCLK/4 MCLK/128 31.25 70 11.3
Note 1: For OSR = 32 and 64, DITHER = None. For OSR = 128 and higher, DITHER = Maximum. The SINAD
values are given from GAIN = 1.

MCP3911
4.5 OSR – Oversampling Ratio 4.8 Integral Nonlinearity Error
This is the ratio of the sampling frequency to the output Integral nonlinearity error is the maximum deviation of
data rate. OSR = DMCLK/DRCLK. The default OSR is an ADC transition point from the corresponding point of
256 or with MCLK = 4 MHz, PRESCALE = 1, AMCLK = 4 an ideal transfer function, with the offset and gain
MHz, fS = 1 MHz, fD = 3.90625 ksps. The following bits in errors removed or with the end points equal to zero.
the CONFIG register are used to change the It is the maximum remaining error after the calibration
Oversampling Ratio (OSR). of offset and gain errors for a DC input signal.
TABLE 4-3: MCP3911 OVERSAMPLING 4.9 Signal-to-Noise Ratio (SNR)

RATIO SETTINGS For the MCP3911 ADCs, the Signal-to-Noise Ratio is a
CONFIG ratio of the output fundamental signal power to the
Oversampling Ratio noise power (not including the harmonics of the signal),
OSR[2:0] (OSR) when the input is a sine wave at a predetermined
frequency. It is measured in dB. Usually, only the
0 0 0 32
maximum Signal-to-Noise Ratio is specified. The SNR
0 0 1 64 figure depends mainly on the OSR and DITHER
0 1 0 128 settings of the device.
0 1 1 256 (default)
EQUATION 4-3: SIGNAL-TO-NOISE RATIO
1 0 0 512
SNR  dB  = 10 log  ----------------------------------
1 0 1 1024 SignalPower
NoisePower
1 1 0 2048
1 1 1 4096
4.10 Signal-to-Noise Ratio and
4.6 Offset Error Distortion (SINAD)
This is the error induced by the ADC when the inputs The most important figure of merit for the analog
are shorted together (VIN = 0V). The specification performance of the ADCs present on the MCP3911 is
incorporates both PGA and ADC offset contributions. the Signal-to-Noise Ratio and Distortion (SINAD)
This error varies with PGA and OSR settings. The specification.
offset is different on each channel and varies from chip-
to-chip. The offset is specified in µV. The offset error Signal-to-Noise and Distortion Ratio is similar to
can be digitally compensated independently on each Signal-to-Noise Ratio, with the exception that you must
channel through the OFFCAL registers with a 24-bit include the harmonics power in the noise power calcu-
Calibration Word. lation. The SINAD specification depends mainly on the
OSR and DITHER settings.
The offset on the MCP3911 has a low temperature
coefficient (see Section 2.0, Typical Performance EQUATION 4-4: SINAD EQUATION
Curves for more information, see Figure 2-33).
SINAD  dB  = 10 log  ---------------------------------------------------------------------
SignalPower
4.7 Gain Error  Noise + HarmonicsPower
This is the error induced by the ADC on the slope of the

transfer function. It is the deviation expressed in percent- The calculated combination of SNR and THD per the
age (%) compared to the ideal transfer function defined following formula also yields SINAD:
by Equation 5-3. The specification incorporates both
EQUATION 4-5: SINAD, THD AND SNR
PGA and ADC gain error contributions, but not the VREF
contribution (it is measured with an external VREF). RELATIONSHIP
This error varies with PGA and OSR settings. The gain  SNR - – THD
 ----------  ---------------
-
10  10 
error can be digitally compensated independently on SINAD  dB  = 10 log 10 + 10
each channel through the GAINCAL registers with a
24-bit Calibration Word.
The gain error on the MCP3911 has a low temperature
coefficient. For more information, see Figure 2-34.

MCP3911
4.11 Total Harmonic Distortion (THD) Multibit quantizers help lower the quantization error
(the error fed back in the loop can be very large with
The Total Harmonic Distortion is the ratio of the output 1-bit quantizers) without changing the order of the
harmonics power to the fundamental signal power for a modulator or the OSR, which leads to better SNR
sine wave input and is defined by Equation 4-6. figures. However, typically, the linearity of such
architectures is more difficult to achieve since the DAC
EQUATION 4-6:
is complicated and its linearity limits the THD of such
ADCs.
THD  dB  = 10 log  -----------------------------------------------------
HarmonicsPower
 FundamentalPower The MCP3911’s five-level quantizer is a Flash ADC
composed of four comparators, arranged with equally
spaced thresholds and a thermometer coding. The
The THD calculation includes the first 35 harmonics for MCP3911 also includes proprietary five-level DAC
the MCP3911 specifications. The THD is usually only architecture that is inherently linear for improved THD
measured with respect to the first ten harmonics. figures.
THD is sometimes expressed in percentage (%).
Equation 4-7 converts the THD in percentage (%):
4.14 Idle Tones
EQUATION 4-7: A Delta-Sigma converter is an integrating converter. It
THD  dB  also has a finite quantization step Least Significant
------------------------
THD  %  = 100  10 20 Byte (LSB) which can be detected by its quantizer. A
DC input voltage that is below the quantization step
should only provide an all zeros result, since the input
This specification depends mainly on the DITHER
is not large enough to be detected. As an integrating
setting.
device, any Delta-Sigma shows Idle tones in this case.
This means that the output will have spurs in the
4.12 Spurious-Free Dynamic Range frequency content that are depending on the ratio
(SFDR) between quantization step voltage and the input
voltage. These spurs are the result of the integrated
The ratio between the output power of the fundamental
sub-quantization step inputs that eventually cross the
and the highest spur in the frequency spectrum. The
quantization steps after a long enough integration. This
spur frequency is not necessarily a harmonic of the
induces an AC frequency at the output of the ADC and
fundamental, even though that is usually the case. This
can be shown in the ADC output spectrum.
figure represents the dynamic range of the ADC when
a full-scale signal is used at the input. This specification These Idle tones are residues that are inherent to the
depends mainly on the DITHER setting. quantization process and the fact that the converter is
integrating at all times without being reset. They are
EQUATION 4-8: residues of the finite resolution of the conversion
process. They are very difficult to attenuate and they
SFDR  dB  = 10 log  -----------------------------------------------------
FundamentalPower are heavily signal-dependent. They can degrade both
 HighestSpurPower  SFDR and THD of the converter, even for DC inputs.
They can be localized in the baseband of the converter
and thus difficult to filter from the actual input signal.
4.13 MCP3911 Delta-Sigma
For power metering applications, Idle tones can be very
Architecture disturbing because energy can be detected even at the
The MCP3911 incorporates two Delta-Sigma ADCs 50 or 60 Hz frequency, depending on the DC offset of
with a multibit architecture. A Delta-Sigma ADC is an the ADCs, while no power is really present at the
oversampling converter that incorporates a built-in inputs. The only practical way to suppress or attenuate
modulator, which is digitizing the quantity of charge Idle tones phenomenon is to apply dithering to the
integrated by the modulator loop (see Figure 5-1). The ADC. The Idle tone amplitudes are a function of the
quantizer is the block that is performing the order of the modulator, the OSR and the number of
Analog-to-Digital conversion. The quantizer is typically levels in the quantizer of the modulator. A higher order,
one bit or a simple comparator which helps to maintain a higher OSR or a higher number of levels for the
the linearity performance of the ADC (the DAC quantizer attenuate the Idle tones amplitude.
structure in this case is inherently linear).

MCP3911
4.15 Dithering The crosstalk is then calculated with the following
formula:
To suppress or attenuate the Idle tones present in any
Delta-Sigma ADCs, dithering can be applied to the EQUATION 4-9:
ADC. Dithering is the process of adding an error to the
 CH0Power
ADC feedback loop to “decorrelate” the outputs and CTalk  dB  = 10 log  ---------------------------------
  CH1Power
“break” the Idle tone behavior. Usually, a random or
pseudorandom generator adds an analog or digital
error to the feedback loop of the Delta-Sigma ADC to 4.17 PSRR
ensure that no tonal behavior can happen at its outputs.
This error is filtered by the feedback loop and typically This is the ratio between a change in the power supply
has a zero average value, so that the converter static voltage and the ADC output codes. It measures the
transfer function is not disturbed by the dithering influence of the power supply voltage on the ADC
process. However, the dithering process slightly outputs.
increases the noise floor (it adds noise to the part) while The PSRR specification can be DC (the power supply
reducing its tonal behavior, and thus improving SFDR is taking multiple DC values) or AC (the power supply
and THD (see Figure 2-14 and Figure 2-18). The is a sine wave at a certain frequency with a certain
dithering process scrambles the Idle tones into Common-mode). In AC, the amplitude of the sine wave
baseband white noise and ensures that dynamic specs is representing the change in the power supply. It is
(SNR, SINAD, THD, SFDR) are less signal-dependent. defined in Equation 4-10:
The MCP3911 incorporates a proprietary dithering
algorithm on both ADCs to remove Idle tones and EQUATION 4-10:
improve THD, which is crucial for power metering  VOUT
applications. PSRR  dB  = 20 log  -------------------
  AV DD
4.16 Crosstalk Where VOUT is the equivalent input voltage that the
The crosstalk is defined as the perturbation caused by output code translates to the ADC transfer function. In
one ADC channel on the other ADC channel. It is a the MCP3911 specification, AVDD varies from 2.7V to
measurement of the isolation between the two ADCs 3.6V. For AC PSRR, a 50/60 Hz sine wave is chosen,
present in the chip. centered around 3.3V with a maximum 300 mV
amplitude. The PSRR specification is measured with
This measurement is a two-step procedure:
AVDD = DVDD.
1. Measure one ADC input with no perturbation on
the other ADC (ADC inputs shorted). 4.18 CMRR
2. Measure the same ADC input with a perturba-
tion sine wave signal on the other ADC at a This is the ratio between a change in the
certain predefined frequency. Common-mode input voltage and the ADC output
codes. It measures the influence of the Common-mode
The crosstalk is then the ratio between the output power input voltage on the ADC outputs.
of the ADC when the perturbation is present and when it
is not divided by the power of the perturbation signal. The CMRR specification can be DC (the
Common-mode input voltage is taking multiple DC
A lower crosstalk value implies more independence values) or AC (the Common-mode input voltage is a
and isolation between the two channels. sine wave at a certain frequency with a certain
The measurement of this signal is performed under the Common-mode). In AC, the amplitude of the sine wave
default conditions at MCLK = 4 MHz: is representing the change in the power supply. It is
• GAIN = 1 defined in Equation 4-11:
• PRESCALE = 1 EQUATION 4-11:
• OSR = 256
 V OUT
CMRR  dB  = 20 log  -----------------
• MCLK = 4 MHz
  V CM 
Step 1
• CH0+ = CH0- = AGND
Where VCM = (CHn+ + CHn-)/2 is the Common-mode
• CH1+ = CH1- = AGND
input voltage and VOUT is the equivalent input voltage
Step 2 that the output code translates to using the ADC
• CH0+ = CH0- = AGND transfer function. In the MCP3911 specification, VCM
• CH1+ – CH1- = 1.2 VP-P at 50/60 Hz varies from -1V to +1V.
(full-scale sine wave)

MCP3911
4.19 ADC Reset Mode 4.20 Hard Reset Mode (RESET = DGND)
ADC Reset mode (also called Soft Reset mode) can This mode is only available during a POR or when the
only be entered through setting the RESET[1:0] bits in RESET pin is pulled low. The RESET pin low state
the Configuration register high. This mode is defined as places the device in a Hard Reset mode.
the condition where the converters are active, but their In this mode, all internal registers are reset to their
output is forced to ‘0’. default state.
The registers are not affected in this Reset mode and The DC biases for the analog blocks are still active (i.e.,
retain their state, except the data registers of the the MCP3911 is ready to convert). However, this pin
corresponding channel, which are reset to ‘0’. clears all conversion data in the ADCs. In this mode,
The ADCs can immediately output meaningful codes the MDAT outputs are in high-impedance. The
after leaving the Reset mode (and after the SINC filter comparator’s outputs of both ADCs are forced to their
settling time). This mode is both entered and exited Reset state (‘0011’). The SINC filters are all reset as
through the setting of bits in the Configuration register. well as their double-output buffers. See serial timing for
Each converter can be placed in Soft Reset mode minimum pulse low time in Section 1.0 “Electrical
independently. The Configuration registers are not Characteristics”.
modified by the Soft Reset mode. During a Hard Reset, no communication with the part is
A data ready pulse is not generated by any ADC while possible. The digital interface is maintained in a Reset
in Reset mode. state.
Reset mode also affects the modulator output block In this state, to properly bias the input structures of both
(i.e., the MDAT pin corresponding to the channel in channels, the MCLK can be applied to the part. If not
Reset). If enabled, it provides a bit stream correspond- applied, large analog input leakage currents can be
ing to a zero output (a series of ‘0011’ bits continuously observed for highly negative input signals, and after
repeated). removing the Reset state, a certain start-up time is nec-
essary to bias the input structure properly. During this
When an ADC exits the ADC Reset mode, any phase delay, the ADC conversions can be inaccurate.
delay present before Reset was entered is still present.
If one ADC is not in Reset mode, the ADC leaving the
4.21 ADC Shutdown Mode
Reset mode automatically resynchronizes the phase
delay relative to the other ADC channel, per the Phase ADC Shutdown mode is defined as a state where the
Delay register block, and gives data ready pulses converters and their biases are off, consuming only
accordingly. leakage current. When the Shutdown bit is reset to ‘0’,
If an ADC is placed in Reset mode while the other is the analog biases are enabled, as well as the clock and
converting, it is not shutting down the internal clock. the digital circuitry. The ADC gives a data ready pulse
When going back out of Reset, it is automatically after the SINC filter settling time has occurred.
resynchronized with the clock that did not stop during However, since the analog biases are not completely
Reset. settled at the beginning of the conversion, the sampling
may not be accurate during about 1 ms (corresponding
If both ADCs are in Soft Reset, the clock is no longer to the settling time of the biasing in worst-case
distributed to the digital core for low-power operation. conditions). To ensure the accuracy, the data ready
Once any of the ADCs is back to normal operation, the pulse coming within the delay of 1 ms + settling time of
clock is automatically distributed again. the SINC filter should be discarded.
However, when the two channels are in Soft Reset, the Each converter can be placed in Shutdown mode
input structure is still clocking if MCLK is applied to independently. The CONFIG registers are not modified
properly bias the inputs so that no leakage current is by the Shutdown mode. This mode is only available
observed. If MCLK is not applied, large analog input through the programming of the SHUTDOWN[1:0] bits
leakage currents can be observed for highly negative in the CONFIG register.
input voltages (typically below -0.6V, referred to AGND).
The output data are flushed to all zeros while in ADC
Shutdown mode. No data ready pulses are generated
by any ADC while in ADC Shutdown mode.
ADC Shutdown mode also affects the modulator output
block (i.e., if MDAT of the channel in Shutdown mode is
enabled, this pin provides a bit stream corresponding to
a zero output; series of ‘0011’ bits continuously
repeated).

MCP3911
When an ADC exits ADC Shutdown mode, any phase The clock is not distributed to the input structure any
delay present before shutdown was entered is still longer. This can cause potential high analog input
present. If one ADC was not in Shutdown mode, the leakage currents at the analog inputs if the input
ADC exiting Shutdown mode automatically resynchro- voltage is highly negative (typically below -0.6V,
nizes the phase delay relative to the other ADC channel, referred to AGND).
per the Phase Delay register block, and gives data ready The only circuit that remains active is the SPI interface,
pulses accordingly. but this circuit does not induce any static power
If an ADC is placed in Shutdown mode while the other consumption. If SCK is Idle, the only current
is converting, the internal clock is not shut down. When consumption comes from the leakage currents induced
exiting Shutdown mode, the ADC is automatically by the transistors and is less than 1 µA on each power
resynchronized with the clock that did not stop during supply.
Reset. This mode can be used to power down the chip
If both ADCs are in Shutdown mode, the clock is no completely and avoid power consumption when there
longer distributed to the input structure or to the digital are no data to convert at the analog inputs. Any SCK or
core for low-power operation. If the input voltage is MCLK edge coming while in this mode induces
highly negative (typically below -0.6V, referred to AGND), dynamic power consumption.
this can cause potential high analog input leakage Once any of the SHUTDOWN, CLKEXT and VREFEXT
currents at the analog inputs. Once any of the ADCs is bits return to ‘0’, the two POR monitoring blocks are
back to normal operation, the clock is automatically back to operation, and AVDD and DVDD monitoring can
distributed again. take place.
When exiting Full Shutdown mode, the device resets to
4.22 Full Shutdown Mode
its default configuration state. The Configuration bits all
The lowest power consumption can be achieved when reset to their default value, and the ADCs reset to their
SHUTDOWN[1:0] = 11, VREFEXT = CLKEXT = 1. This initial state, requiring three DRCLK periods for an initial
mode is called Full Shutdown mode and no analog data ready pulse. Exiting Full Shutdown mode is
circuitry is enabled. In this mode, both AVDD and DVDD effectively identical to an internal Reset or returning
POR monitoring are also disabled. No clock is propa- from a POR condition.
gated throughout the chip. Both ADCs are in shutdown,
and the internal voltage reference is disabled.

MCP3911
5.0 DEVICE OVERVIEW TABLE 5-1: PGA CONFIGURATION
SETTING
5.1 Analog Inputs (CHn+/-)
GAIN Gain Gain VIN Range
The MCP3911 analog inputs can be connected directly PGA_CHn[2:0] (V/V) (dB) (V)
to current and voltage transducers (such as shunts,
0 0 0 1 0 ±0.6
current transformers or Rogowski coils). Each input pin
is protected by specialized ESD structures that are 0 0 1 2 6 ±0.3
certified to pass 4.0 kV HBM and 300V MM contact 0 1 0 4 12 ±0.15
charge. These structures allow bipolar ±2V continuous 0 1 1 8 18 ±0.075
voltage, with respect to AGND, to be present at their
1 0 0 16 24 ±0.0375
inputs without the risk of permanent damage.
1 0 1 32 30 ±0.01875
Both channels have fully differential voltage inputs for
better noise performance. The absolute voltage at each Note: This table is defined with VREF = 1.2V. The
pin, relative to AGND, should be maintained in the ±1V two undefined settings, ‘110’ and ‘111’ are
range during operation to ensure the specified ADC G = 1.
accuracy. The Common-mode signals should be
adapted to respect both the previous conditions and 5.3 Delta-Sigma Modulator
the differential input voltage range. For best
performance, the Common-mode signals should be 5.3.1 ARCHITECTURE
maintained to AGND. Both ADCs are identical in the MCP3911 and they
include a proprietary second-order modulator with a
Note: If the analog inputs are held to a potential
multibit five-level DAC architecture (see Figure 5-1). The
of -0.6 to -1V for extended periods of time,
quantizer is a Flash ADC composed of four comparators
MCLK must be present inside the device
with equally spaced thresholds and a thermometer out-
to avoid large leakage currents at the
put coding. The proprietary five-level architecture
analog inputs. This is true even during the
ensures minimum quantization noise at the outputs of
Hard or Soft Reset mode of both ADCs.
the modulators without disturbing linearity or inducing
However, during the Shutdown mode of
additional distortion. The sampling frequency is DMCLK
the two ADCs or POR state, the clock is
(typically 1 MHz with MCLK = 4 MHz), so the modulator
not distributed inside the circuit. During
outputs are refreshed at a DMCLK rate. The modulator
these states, it is recommended to keep
outputs are available in the MOD register or serially
the analog input voltages above -0.6V,
transferred on each MDAT pin.
referred to AGND, to avoid high analog
inputs leakage currents. Figure 5-1 represents a simplified block diagram of the
Delta-Sigma ADC present on MCP3911.
5.2 Programmable Gain Amplifiers

(PGA)
Quantizer
The two Programmable Gain Amplifiers (PGAs) reside Differential Loop Filter Output
at the front end of each Delta-Sigma ADC. They have Voltage Input Bit Stream
Second-
two functions: translate the Common-mode of the input Order
from AGND to an internal level between AGND and Integrator Five-Level
AVDD, and amplify the input differential signal. The Flash ADC
translation of the Common-mode does not change the
differential signal, but recenters the Common-mode so
that the input signal can be properly amplified.
DAC
The PGA block can be used to amplify very low signals,
but the differential input range of the Delta-Sigma MCP3911 Delta-Sigma Modulator
modulator must not be exceeded. The PGA is con-
trolled by the PGA_CHn[2:0] bits in the GAIN register. FIGURE 5-1: Simplified Delta-Sigma ADC
Table 5-1 represents the gain settings for the PGA. Block Diagram.

MCP3911
5.3.2 MODULATOR INPUT RANGE AND 5.3.3 BOOST SETTINGS
SATURATION POINT The Delta-Sigma modulators include a programmable
For a specified voltage reference value of 1.2V, the biasing circuit to further adjust the power consumption
modulator’s specified differential input range is to the sampling speed applied through the MCLK. This
±600 mV. The input range is proportional to VREF and can be programmed through the BOOST[1:0] bits,
scales according to the VREF voltage. This range is which are applied to both channels simultaneously.
ensuring the stability of the modulator over amplitude The maximum achievable Analog Master Clock
and frequency. Outside of this range, the modulator is (AMCLK) speed and the maximum sampling frequency
still functional. However, its stability is no longer (DMCLK), and therefore, the maximum achievable
ensured and therefore, it is not recommended to data rate (DRCLK), highly depend on BOOST[1:0] and
exceed this limit. See Figure 2-24 for extended PGA_CHn[2:0] settings. Table 5-2 specifies the
dynamic range performance limitations. The saturation maximum AMCLK possible to keep optimal accuracy in
point for the modulator is VREF/1.5, since the transfer function of the BOOST[1:0] and PGA_CHn[2:0]
function of the ADC includes a gain of 1.5 by default settings.
(independent from the PGA setting). See Section 5.6
“ADC Output Coding”.
TABLE 5-2: MAXIMUM AMCLK LIMITS AS A FUNCTION OF BOOST AND PGA GAIN
Conditions VDD = 3.0V to 3.6V, TA from -40°C to +125°C VDD = 2.7V to 3.6V, TA from -40°C to +125°C
Maximum AMCLK (MHz) Maximum AMCLK (MHz) Maximum AMCLK (MHz) Maximum AMCLK (MHz)
Boost Gain (SINAD within -3 dB (SINAD within -5 dB from (SINAD within -3 dB (SINAD within -5 dB
from its maximum) its maximum) from its maximum) from its maximum)
0.5x 1 3 3 3 3
0.66x 1 4 4 4 4
1x 1 10 10 10 10
2x 1 16 16 16 16
0.5x 2 2.5 3 3 3
0.66x 2 4 4 4 4
1x 2 10 10 10 10
2x 2 14.5 16 13.3 14.5
0.5x 4 2.5 2.5 2.5 2.5
0.66x 4 4 4 4 4
1x 4 10 10 8 10
2x 4 13.3 16 10.7 11.4
0.5x 8 2.5 2.5 2.5 2.5
0.66x 8 4 4 4 4
1x 8 10 11.4 6.7 8
2x 8 10 14.5 8 8
0.5x 16 2 2 2 2
0.66x 16 4 4 4 4
1x 16 10.6 10.6 8 10
2x 16 12.3 16 8 10.7
0.5x 32 2 2 2 2
0.66x 32 4 4 4 4
1x 32 10 11.4 8 10
2x 32 13.3 16 8 10

MCP3911
5.3.4 AUTO-ZEROING FREQUENCY 5.4 Modulator Output Block
SETTING (AZ_FREQ)
If the user wishes to use the modulator output of the
The MCP3911 modulators include an auto-zeroing device, the appropriate bits to enable the modulator
algorithm to improve the offset error performance and output must be set in the Configuration register.
greatly diminish 1/f noise in the ADC. This algorithm
When the MODOUT[1:0] bits are enabled, the modulator
allows the device to reach very high SNR and flattens
output of the corresponding channel is present at the
the noise spectrum at the output of the ADC (see
corresponding MDAT output pin as soon as the
performance graphs in Figure 2-1, Figure 2-2,
command is placed. Additionally, the corresponding
Figure 2-3 and Figure 2-4). This auto-zeroing algorithm
SINC filter is disabled to consume less current. The
is performed synchronously with the MCLK coming to
corresponding DR pulse is also not present at the DR
the device. Its rate can be adjusted throughout by the
output pin. When MODOUT[1:0] bits are cleared, the cor-
AZ_FREQ bit in the CONFIG register.
responding SINC filters are back to normal operation and
When AZ_FREQ = 0 (default), the auto-zeroing occurs the corresponding MDAT outputs are in high-impedance.
at the slowest rate, which diminishes the 1/f noise while
Since the Delta-Sigma modulators have a five-level
not impacting the THD performance. This mode is
output given by the state of four comparators with ther-
recommended for low values of the PGA gain
mometer coding, their outputs can be represented on
(GAIN = 1x or 2x).
four bits, each bit giving the state of the corresponding
When AZ_FREQ = 1, the auto-zeroing occurs at the comparator (see Table 5-3). These bits are present on
fastest rate, which further diminishes the 1/f noise and the MOD register and are updated at the DMCLK rate.
further improves the SNR, especially at higher gain
To output the comparator’s result on a separate pin
settings. The THD may be slightly impacted in this
(MDAT0 and MDAT1), these comparator output bits
mode (see Figure 2-22). This mode is recommended
have been arranged to be serially output at the AMCLK
for higher PGA gain settings to improve SNR (gain
rate (see Figure 5-2).
superior or equal to 4x).
This 1-bit serial bit stream is identical to the one
5.3.5 DITHER SETTINGS produced by a 1-bit DAC modulator with a sampling
Both modulators also include a dithering algorithm that frequency of AMCLK. The modulator can either
can be enabled through the DITHER[1:0] bits in the operate as a five-level output at DMCLK rate or a 1-bit
Configuration register. This dithering process improves output at AMCLK rate. These two representations are
THD and SFDR (for high OSR settings), while interchangeable. The MDAT outputs can therefore be
increasing slightly the noise floor of the ADCs. For used in any application that requires 1-bit modulator
power metering applications and applications that are outputs. These applications often integrate and filter
distortion-sensitive, it is recommended to keep the 1-bit output with SINC or more complex decimation
DITHER at maximum settings for the best THD and filters computed by an MCU or DSP.
SFDR performance. In the case of power metering
TABLE 5-3: DELTA-SIGMA MODULATOR
applications, THD and SFDR are critical specifications.
CODING
Optimizing SNR (noise floor) is not really problematic
due to the large averaging factor at the output of the COMP[3:0] Modulator MDAT Serial
ADCs. Therefore, even for low OSR settings, the Code Output Code Stream
dithering algorithm shows a positive impact on the
1111 +2 1111
performance of the application.
0111 +1 0111
0011 0 0011
0001 -1 0001
0000 -2 0000

MCP3911
Since the Reset and shutdown SPI commands are
COMP COMP COMP COMP asynchronous, the MDAT pins are resynchronized with
[3] [2] [1] [0] DMCLK after each time the part goes out of Reset and
shutdown.
AMCLK This means that the first output of MDAT, after a Soft
Reset or a shutdown, is always ‘0011’ after the first
DMCLK DMCLK rising edge.
The two MDAT output pins are in high-impedance if the
RESET pin is low.
MDAT+2
5.5 SINC3 + SINC1 Filter
The decimation filter present in both channels of
MDAT+1 the MCP3911 is a cascade of two SINC filters
(SINC3 + SINC1): a third-order SINC filter with a
MDAT+0 decimation ratio of OSR3, followed by a first-order
SINC filter with a decimation ratio of OSR1 (moving
average of OSR1 values). Figure 5-3 represents the
MDAT-1 decimation filter architecture.
MDAT-2
FIGURE 5-2: MDAT Serial Outputs in

Function of the Modulator Output Code.
OSR1 = 1
Modulator SINC3 SINC1 Decimation

Output Filter Output
4
16 (WIDTH = 0)
24 (WIDTH = 1)
OSR3 OSR1
Decimation Filter
FIGURE 5-3: MCP3911 Decimation Filter Block Diagram.
Equation 5-1 contains the formula for calculating the EQUATION 5-2: SETTING TIME OF THE
transfer function of the digital decimation filter and ADC AS A FUNCTION OF
settling time of the ADC: DMCLK PERIODS
EQUATION 5-1: SINC FILTER TRANSFER SettlingTime  DMCLKPeriods  = 3  OSR +  OSR – 1   OSR
FUNCTION 3 1 3
- OSR 3 3 - OSR 1  OSR 3

1 – z  1 – z 
   
H  z  = ----------------------------------------------  ---------------------------------------------------------
 OSR  1 – z   – 1 3 - OSR 3
3 OSR   1 – z 
1  
Where z = EXP  2   j  f in  DMCLK 

MCP3911
The SINC1 filter following the SINC3 filter is only Any unsettled data are automatically discarded to avoid
enabled for the high OSR settings. This SINC1 filter data corruption. Each data ready pulse corresponds to
provides additional rejection at a low cost with little fully settled data at the output of the decimation filter.
modification to the -3 dB bandwidth. For 24-Bit Output The first data available at the output of the decimation
mode (WIDTH = 1), the output of the SINC filter is pad- filter are present after the complete settling time of the
ded on the right with least significant zeros, up to filter (see Table 5-4). After the first data have been
24 bits, for any resolution less than 24 bits. For 16-Bit processed, the delay between two data ready pulses is
Output modes, the output of the SINC filter is rounded 1/DRCLK. The data stream, from input to output, is
to the closest 16-bit number to conserve only 16-bit delayed by an amount equal to the settling time of the
words and to minimize truncation error. filter (which is the group delay of the filter).
The gain of the transfer function of this filter is one at The achievable resolution, the -3 dB bandwidth and the
each multiple of DMCLK (typically 1 MHz), so a proper settling time at the output of the decimation filter (the
anti-aliasing filter must be placed at the inputs. This output of the ADC), is dependent on the OSR of each
attenuates the frequency content around DMCLK and SINC filter and is summarized in Table 5-4:
keeps the desired accuracy over the baseband of the
converter. This anti-aliasing filter can be a simple, first-
order RC network with a sufficiently low time constant
to generate high rejection at DMCLK frequency.
TABLE 5-4: OVERSAMPLING RATIO AND SINC FILTER SETTLING TIME

Resolution In Bits
OSR[2:0] OSR3 OSR1 Total OSR Settling Time -3 dB Bandwidth
(No Missing Codes)
0 0 0 32 1 32 17 96/DMCLK 0.26 * DRCLK
0 0 1 64 1 64 20 192/DMCLK 0.26 * DRCLK
0 1 0 128 1 128 23 384/DMCLK 0.26 * DRCLK
0 1 1 256 1 256 24 768/DMCLK 0.26 * DRCLK
1 0 0 512 1 512 24 1536/DMCLK 0.26 * DRCLK
1 0 1 512 2 1024 24 2048/DMCLK 0.37 * DRCLK
1 1 0 512 4 2048 24 3072/DMCLK 0.42 * DRCLK
1 1 1 512 8 4096 24 5120/DMCLK 0.43 * DRCLK
0 0
-20
-20
-40
Magnitude (dB)
Magnitude (dB)
-40
-60
-60 -80
-80 -100
-120
-100
-140
-120 -160
1 10 100 1000 10000 100000 1 100 10000 1000000
Input Frequency (Hz) Input Frequency (Hz)
FIGURE 5-4: SINC Filter Frequency FIGURE 5-5: SINC Filter Frequency
Response, OSR = 256, MCLK = 4 MHz, Response, OSR = 4096 (pink), OSR = 512
PRE[1:0] = 00. (blue), MCLK = 4 MHz, PRE[1:0] = 00.

MCP3911
5.6 ADC Output Coding EQUATION 5-3:
The second-order modulator, SINC3 + SINC1 filter,
DATA_CHn = (CHn+ – CHn-)  8,388,608  G 1.5
PGA, VREF and analog input structure, all work  VREF+ – VREF- 
together to produce the device transfer function for the
Analog-to-Digital conversion (see Equation 5-3). For 24-Bit Mode or WIDTH = 1
The channel data are either a 16-bit or 24-bit word,
presented in 23-bit or 15-bit plus sign, two’s DATA_CHn = (CHn+ – CHn-)  32,768 G 1.5
complement format and are Most Significant Byte  VREF+ – VREF- 
(MSB) (left) justified.
For 16-Bit Mode or WIDTH = 0
The ADC data are two or three bytes wide depending
on the WIDTH[1:0] bits. The 16-bit mode includes a
The ADC resolution is a function of the OSR
round to the closest 16-bit word (instead of truncation)
(Section 5.5 “SINC3 + SINC1 Filter”). The resolution
to improve the accuracy of the ADC data.
is the same for both channels. No matter what the res-
In case of positive saturation (CHn+ – CHn- > VREF/1.5), olution is, the ADC output data are always presented in
the output is locked to 7FFFFF for 24-bit mode (7FFF 24-bit words, with added zeros at the end, if the OSR is
for 16-bit mode). In case of negative saturation not large enough to produce 24-bit resolution (left
(CHn+ – CHn- < -VREF/1.5), the output code is locked justification).
to 800000 for 24-bit mode (8000 for 16-bit mode).
Equation 5-3 is only true for DC inputs. For AC inputs,
this transfer function needs to be multiplied by the
transfer function of the SINC3 + SINC1 filter (see
Equation 5-1 and Equation 5-3).
TABLE 5-5: OSR = 256 (AND HIGHER) OUTPUT CODE EXAMPLES

Decimal
ADC Output Code (MSB First) Hexadecimal
24-Bit Resolution
0 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 0x7FFFFF + 8,388,607
0 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 0 0x7FFFFE + 8,388,606
0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0x000000 0
1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 0xFFFFFF –1
1 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 1 0x800001 – 8,388,607
1 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0x800000 – 8,388,608
TABLE 5-6: OSR = 128 OUTPUT CODE EXAMPLES

Decimal
23-Bit Resolution
0 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 0 0x7FFFFE + 4,194,303
0 1 1 1 1 1 1 1 1 1 1 1 1 1 1 0 1 1 1 1 1 1 0 0 0x7FFFFC + 4,194,302
0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0x000000 0
1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 0 0xFFFFFE –1
1 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 1 0 0x800002 – 4,194,303
1 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0x800000 – 4,194,304

Decimal
20-Bit Resolution
0 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 0 0 0 0 0x7FFFF0 + 524, 287
0 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 0 0 0 0 0 0x7FFFE0 + 524, 286
0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0x000000 0
1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 0 0 0 0 0xFFFFF0 –1
1 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 1 0 0 0 0 0x800010 – 524, 287
1 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0x800000 – 524, 288

MCP3911
Decimal
17-Bit Resolution
0 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 0 0 0 0 0 0 0 0x7FFF80 + 65, 535
0 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 0 0 0 0 0 0 0 0 0x7FFF00 + 65, 534
0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0x000000 0
1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 0 0 0 0 0 0 0 0xFFFF80 –1
1 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 1 0 0 0 0 0 0 0 0x800080 – 65, 535
1 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0x800000 – 65, 536
5.7 Voltage Reference 5.7.2 DIFFERENTIAL EXTERNAL

VOLTAGE INPUTS
5.7.1 INTERNAL VOLTAGE REFERENCE
When the VREFEXT bit is high, the two reference pins
The MCP3911 contains an internal voltage reference (REFIN+/OUT, REFIN-) become a differential voltage
source specially designed to minimize drift over- reference input. The internal voltage reference circuit is
temperature. To enable the internal voltage reference, placed into Shutdown mode and the switch connecting
the VREFEXT bit in the Configuration register must be this circuit to the reference voltage input of the ADC is
set to ‘0’ (Default mode). This internal VREF supplies opened. The internal voltage reference circuit is placed
reference voltage to both channels. The typical value of into Shutdown mode and the switch connecting this cir-
this voltage reference is 1.2V ±2%. The internal refer- cuit to the reference voltage input of the ADC is opened.
ence has a very low typical temperature coefficient of The voltage at the REFIN+/OUT is noted VREF+ and the
±7 ppm/°C, allowing the output to have minimal voltage at the REFIN- pin is noted VREF-. The differential
variation with respect to temperature, since it is voltage input value is given by the following equation:
proportional to (1/VREF).
The noise of the internal voltage reference is low EQUATION 5-4:
enough not to significantly degrade the SNR of the
VREF = VREF+ – VREF-
ADC if compared to a precision external low noise
voltage reference. The output pin for the internal
voltage reference is REFIN+/OUT. The specified VREF range is from 1.1V to 1.3V. The
REFIN- pin voltage (VREF-) should be limited to ±0.1V,
If the voltage reference is only used as an internal with respect to AGND. Typically, for single-ended refer-
VREF, adding bypass capacitance on REFIN+/OUT is ence applications, the REFIN- pin should be directly
not necessary for keeping ADC accuracy. A minimal connected to AGND, with its own separate track, to
0.1 µF ceramic capacitance can be connected to avoid avoid any spike due to switching noise.
EMI/EMC susceptibility issues due to the antenna
created by the REFIN+/OUT pin if left floating.
The bypass capacitors also help applications where the
voltage reference output is connected to other circuits.
In this case, additional buffering may be needed as the
output drive capability of this output is low.
Adding too much capacitance on the REFIN+/OUT pin
may slightly degrade the THD performance of the
ADCs.

MCP3911
5.7.3 TEMPERATURE COMPENSATION 5.8 Power-on Reset
(VREFCAL REGISTER)
The MCP3911 contains an internal POR circuit that
The internal voltage reference comprises a proprietary monitors both analog and digital supply voltages during
circuit and algorithm to compensate first-order and operation. The typical threshold for a power-up event
second-order temperature coefficients. The compensa- detection is 2.1V ±5% and a typical start-up time (tPOR)
tion allows very low temperature coefficients (typically of 50 µs. The POR circuit has a built-in hysteresis for
7 ppm/°C) on the entire range of temperatures, from improved transient spike immunity that has a typical
-40°C to +125°C. This temperature coefficient varies value of 200 mV. Proper decoupling capacitors (0.1 µF
from part to part. ceramic and 10 µF in parallel are sufficient in most
This temperature coefficient can be adjusted on each cases) should be mounted as close as possible to the
part through the VREFCAL register (address 0x1A). AVDD and DVDD pins, providing additional transient
This register is only for advanced users. This register immunity.
should not be written unless the user wants to calibrate Figure 5-7 illustrates the different conditions at
the temperature coefficient of the whole system or power-up and a power-down event in typical condi-
application. The default value of this register is set to tions. All internal DC biases are not settled until at least
0x42. The typical variation of the temperature coeffi- 1 ms, in worst-case conditions, after a system POR.
cient of the internal voltage reference, with respect to Any data ready pulse that occurs within 1 ms, plus the
VREFCAL register code, is shown in Figure 5-6. SINC filter settling time after system Reset, should be
Modifying the value stored in the VREFCAL register ignored to ensure proper accuracy. After POR, data
may also vary the output voltage in addition to the ready pulses are present at the pin with all the default
temperature coefficient. conditions in the Configuration registers.
Both AVDD and DVDD are monitored so either power
60
supply can sequence first.
50
VREF Drift (ppm)
40
30
20
10
0
0 64 128 192 256
VREFCAL Register Trim Code (decimal)
FIGURE 5-6: VREF Tempco vs. VREFCAL

Trim Code Chart.
Voltage Any data read pulse

(AVDD, DVDD) occuring during this time
can yield inaccurate output
data. It is recommended to
discard them.
POR Threshold
Up (2.1V typical)
(1.9V typical)
tPOR Analog Biases SINC Filter
Settling Time Settling
Time
Time
POR Power-up Normal POR
State Operation State
Biases are Biases are settled.
unsettled. Conversions started
Conversions here are accurate.
started here may
not be accurate.
FIGURE 5-7: Power-on Reset Operation.

MCP3911
5.9 RESET Effect On Delta-Sigma The data ready signals are affected by the phase delay
Modulator/SINC Filter settings. Typically, the time difference between the data
ready pulses of Channel 0 and Channel 1 are equal to
When the RESET pin is logic low, both ADCs are in the phase delay setting.
Reset mode and output code 0x0000h. The RESET pin
performs a Hard Reset (DC biases still on, part ready Note: A detailed explanation of the Data Ready
to convert) and clears all charges contained in the pin (DR) with phase delay is shown in
Delta-Sigma modulators. The comparator’s output is Figure 6-9.
‘0011’ for each ADC.
5.10.1 PHASE DELAY LIMITS
The SINC filters are all reset, as well as their double-
output buffers. This pin is independent of the serial The phase delay can only go from -OSR/2 to +OSR/2 – 1.
interface. It brings all the registers to the default state. This sets the fine phase resolution. The PHASE
When RESET is logic low, any write with the SPI register is coded with two’s complement.
interface is disabled and has no effect. All output pins If larger delays between the two channels are needed,
(SDO, DR, MDAT0/1) are high-impedance. they can be implemented externally to the chip with an
If MCLK is applied, the input structure is enabled and is MCU. A First-In, First-Out algorithm (FIFO) in the MCU
properly biasing the substrate of the input transistors. If can save incoming data from the leading channel for a
the analog inputs are between -1V and +1V, the number N of DRCLK. In this case, DRCLK represents
leakage current on the analog inputs is low. the coarse timing resolution and DMCLK represents
the fine timing resolution. The total delay is shown in
If MCLK is not applied when in Reset mode, the leak- Equation 5-6.
age can be high if the analog inputs are below -0.6V,
referred to AGND. EQUATION 5-6:
5.10 Phase Delay Block Delay = N/DRCLK + PHASE/DMCLK
The MCP3911 incorporates a phase delay generator, The PHASE register can be programmed once with the
which ensures that the two ADCs are converting the OSR = 4096 setting, and adjusts to the OSR automati-
inputs with a fixed delay between them. The two ADCs cally afterwards, without the need to change the value
are synchronously sampling, but the averaging of of the PHASE register.
modulator outputs is delayed, so that the SINC filter
outputs (thus, the ADC outputs) show a fixed phase Note: Rewriting the PHASE registers with the
delay as determined by the PHASE register’s setting. same value resets and automatically
restarts both ADCs.
The phase value (PHASE[11:0]) is an 11 bit + sign,
MSB first, two’s complement code that indicates how • OSR = 4096: The delay can go from -2048 to
much phase delay there is to be between Channel 0 +2047. PHASE[11] is the sign bit. Phase[10] is the
and Channel 1. The four MSBs of the first PHASE reg- MSB and PHASE[0] the LSB.
ister (address 0x07) are undefined and set to ‘0’. The • OSR = 2048: The delay can go from -1024 to
reference channel for the delay is Channel 1 (typically, +1023. PHASE[10] is the sign bit. Phase[9] is the
the voltage channel for power metering applications). MSB and PHASE[0] the LSB.
When the PHASE[11:0] bits are positive, Channel 0 is
• OSR = 1024: The delay can go from -512 to +511.
lagging versus Channel 1. When PHASE[11:0] are
PHASE[9] is the sign bit. Phase[8] is the MSB and
negative, Channel 0 is leading versus Channel 1. The
PHASE[0] the LSB.
amount of delay between two ADC conversions is
shown in Equation 5-5. • OSR = 512: The delay can go from -256 to +255.
EQUATION 5-5: PHASE[0] the LSB.
Phase Register Code • OSR = 256: The delay can go from -128 to +127.
Delay = -------------------------------------------------- PHASE[7] is the sign bit. Phase[6] is the MSB and
DMCLK
PHASE[0] the LSB.
The timing resolution of the phase delay is 1/DMCLK or • OSR = 128: The delay can go from -64 to +63.
1 µs in the default configuration with MCLK = 4 MHz. PHASE[6] is the sign bit. Phase[5] is the MSB and
PHASE[0] the LSB.
PHASE[0] the LSB.
PHASE[0] the LSB.

MCP3911
When CLKEXT = 1, the crystal oscillator is bypassed
TABLE 5-9: PHASE VALUES WITH
by a digital buffer to allow a direct clock input for an
MCLK = 4 MHz, OSR = 4096
external clock (see Figure 4-1).
Delay When CLKEXT = 1, it is recommended to connect the
Phase Register Value Hex (CH0 relative OSC2 pin to DGND directly at all times. The external
to CH1) clock should not be higher than 20 MHz before the
0 1 1 1 1 1 1 1 1 1 1 1 0x7FF + 2047 µs prescaler (MCLK < 20 MHz) for proper operation.
0 1 1 1 1 1 1 1 1 1 1 0 0x7FE + 2046 µs
Note: In addition to the conditions defining the
0 0 0 0 0 0 0 0 0 0 0 1 0x001 + 1 µs maximum MCLK input frequency range,
0 0 0 0 0 0 0 0 0 0 0 0 0x000 0 µs the AMCLK frequency should be main-
1 1 1 1 1 1 1 1 1 1 1 1 0xFFF – 1 µs tained inferior to the maximum limits
defined in Table 5-2 to ensure the accu-
1 0 0 0 0 0 0 0 0 0 0 1 0x801 – 2047 µs
racy of the ADCs. If these limits are
1 0 0 0 0 0 0 0 0 0 0 0 0x800 – 2048 µs exceeded, it is recommended to either
choose a larger OSR or a large prescaler
5.11 Crystal Oscillator value, so that AMCLK can respect these
limits.
The MCP3911 includes a Pierce-type crystal oscillator
with very high stability, and ensures very low tempco
and jitter for the clock generation. This oscillator can 5.12 Digital System Offset and Gain
handle up to 20 MHz crystal frequencies provided that Errors
proper load capacitances and quartz quality factor are
used. The MCP3911 incorporates two sets of additional
registers per channel to perform system digital offset
For a proper start-up, the load capacitors of the crystal and gain error calibration. If the calibration is enabled,
should be connected between OSC1 and DGND, and each channel has its own set of associated registers
between OSC2 and DGND. They should also respect that will modify the output result of the channel. The
the following equation: gain and offset calibrations can be enabled or disabled
through two Configuration bits (EN_OFFCAL and
EQUATION 5-7: EN_GAINCAL). These two bits enable or disable
2 system calibration on both channels at the same time.
R M < 1.6  10   ------------------------
6 1
When both calibrations are enabled, the output of the
 f  CLOAD
ADC is modified as in Equation 5-8.
Where:
f = Crystal frequency in MHz
CLOAD = Load capacitance in pF including
parasitics from the PCB
RM = Motional resistance in ohms of the
quartz
EQUATION 5-8: DIGITAL OFFSET AND GAIN ERROR CALIBRATION REGISTERS

CALCULATIONS
DATA_CHn  post – cal  =  DATA_CHn  pre – cal  + OFFCAL_CHn    1 + GAINCAL_CHn 

MCP3911
5.12.1 DIGITAL OFFSET ERROR Enabling EN_GAINCAL creates a pipeline delay of
CALIBRATION 24 DMCLK periods on both channels. All data ready
pulses are delayed by 24 DMCLK periods, starting from
The OFFCAL_CHn registers are 23-bit plus sign two’s
the data ready, following the command enabling the
complement register, whose LSB value is the same as
EN_GAINCAL bit. The gain calibration is effective on
the channel ADC data. These two registers are then
the next data ready, following the command enabling
added bit-by-bit to the ADC output codes if the
the EN_GAINCAL bit.
EN_OFFCAL bit is enabled. Enabling the EN_OFFCAL
bit does not create any pipeline delay; the offset addi- The digital gain calibration does not function when the
tion is instantaneous. For low OSR values, only the sig- corresponding channel is in Reset or Shutdown mode.
nificant digits are added to the output (up to the The gain multiplier value for an LSB in these 24-bit
resolution of the ADC). For example, at OSR = 32, only registers is shown in Equation 5-10.
the 17 first bits are added).
EQUATION 5-10:
The offset is not added when the corresponding
channel is in Reset or Shutdown mode. The GAIN (1LSB) = 1/8388608
corresponding input voltage offset value added by each
LSB in these 24-bit registers is shown in Equation 5-9. This register is a “Don’t Care” if EN_GAINCAL = 0
(offset calibration disabled), but its value is not cleared
EQUATION 5-9: by the EN_GAINCAL bit.
OFFSET(1LSB) = VREF /(PGA_CHn x 1.5 x 8388608) If the output result is out of bounds after all calibrations
are performed, the output data on the channel are kept
This register is a “Don’t Care” if EN_OFFCAL = 0 to either 7FFF or 8000 in 16-bit mode, or 7FFFFF or
(offset calibration disabled), but its value is not cleared 8000 in 24-bit mode.
by the EN_OFFCAL bit.
5.12.2 DIGITAL GAIN ERROR

CALIBRATION
This register is 24-bit signed MSB first coding with a
range of -1x to +0.9999999x (from 0x80000 to
0x7FFFFF). The gain calibration adds 1x to this regis-
ter and multiplies it to the output code of the channel,
bit-by-bit, after offset calibration. The range of the gain
calibration is thus from 0x to 1.9999999x (from
0x80000 to 0x7FFFFF). The LSB corresponds to a 2-23
increment in the multiplier.

MCP3911
NOTES:

MCP3911
6.0 SERIAL INTERFACE
DESCRIPTION
A6 A5 A4 A3 A2 A1 A0 R/W
6.1 Overview
Read/
The MCP3911 device is compatible with SPI Modes 0,0 Device Register Write Bit
and 1,1. Data are clocked out of the MCP3911 on the Address Address Bits
falling edge of SCK and data are clocked into the Bits
MCP3911 on the rising edge of SCK. In these modes,
FIGURE 6-1: Control Byte.
SCK can Idle either high or low.
Each SPI communication starts with a CS falling edge The default device address bits are ‘00’. Contact the
and stops with the CS rising edge. Each SPI Microchip factory for additional device address bits. For
communication is independent. When CS is high, SDO more information, please see the Product Identification
is in high-impedance, and transitions on SCK and SDI System section.
have no effect. Additional control pins, RESET, DR and A read on undefined addresses gives an all zeros
MDAT0/1, are also provided on separate pins for output on the first and all subsequent transmitted bytes.
advanced communication. A write on an undefined address has no effect and does
The MCP3911 interface has a simple command not increment the address counter.
structure. The first byte transmitted is always the The register map is defined in Table 7-1.
control byte and is followed by data bytes that are eight
bits wide. Both ADCs are continuously converting data
6.3 Reading from the Device
by default and can be reset or shut down through a
CONFIG register setting. The first data byte read is the one defined by the
Since each ADC data are either 16 or 24 bits (depending address given in the control byte. If the CS pin is
on the WIDTH bits), the internal registers can be maintained low after this first byte is transmitted, the
grouped together with various configurations (through communication continues and the address of the next
the READ bits) to allow easy data retrieval within only transmitted byte is determined by the status of the
one communication. For device reads, the internal READ[1:0] bits in the STATUSCOM register. Multiple
address counter can be automatically incremented to looping configurations can be defined through the
loop through groups of data within the register map. The READ[1:0] bits for the address increment (see
SDO then outputs the data located at the ADDRESS Section 6.7 “Continuous Communication, Looping
(A[4:0]) defined in the control byte and then on Address Sets”).
ADDRESS + 1, depending on the READ[1:0] bits, which
select the groups of registers. These groups are defined
6.4 Writing to the Device
in Section 7.1 “CHANNEL Registers – ADC Channel The first data byte written is the one defined by the
Data Output Registers” (Register Map). address given in the control byte. Two Write mode con-
figurations for the address increment can be defined
The Data Ready pin (DR) can be used as an interrupt
through the WRITE bit in the STATUSCOM register.
for an MCU and outputs pulses when new ADC chan-
When WRITE = 1, the write communication automati-
nel data are available. The RESET pin acts like a Hard
cally increments the address for subsequent bytes. The
Reset and can reset the part to its default power-up
address of the next transmitted byte within the same
configuration. The MDAT0/1 pins give the modulator
communication (CS stays logic low) is the next address
outputs (see Section 5.4 “Modulator Output Block”).
defined on the register map. At the end of the register
map, the address loops to the beginning of the writable
6.2 Control Byte part of the register map (address 0x06). Writing a non-
The control byte of the MCP3911 contains two device writable register has no effect. When WRITE = 0, the
Address bits (A[6:5]), five register Address bits (A[4:0]) address is not incremented on the subsequent writes.
and a Read/Write bit (R/W). The first byte transmitted The SDO pin stays in high-impedance during a write
to the MCP3911 is always the control byte. communication.
The MCP3911 interface is device-addressable (through
A[6:5]), so that multiple MCP3911 chips can be present
on the same SPI bus with no data bus contention. This
functionality enables three-phase power metering sys-
tems, containing three MCP3911 chips, controlled by a
single SPI bus (single CS, SCK, SDI and SDO pins).

MCP3911
6.5 SPI MODE 1,1 – Clock Idle High,
Read/Write Examples
In this SPI mode, SCK Idles high. For the MCP3911,
this means that there is a falling edge on SCK before
there is a rising edge.
Note: Changing from an SPI Mode 1,1 to an SPI

Mode 0,0 is possible and can be done
while the CS pin is logic high.
CS
Data Transitions on
the Falling Edge,
MCU and MCP3911 Latch
Bits on the Rising Edge
SCK
SDI A6 A5 A4 A3 A2 A1 A0 R/W
High-Z High-Z High-Z

SDO D7 D6 D5 D4 D3 D2 D1 D0 D7 D6 D5 D4 D3 D2 D1 D0
(ADDRESS) DATA (ADDRESS + 1) DATA
FIGURE 6-2: Device Read (SPI Mode 1,1 – SCK Idles High).
CS
Data Transition on
the Falling Edge,
SCK
R/W
SDI A6 A5 A4 A3 A2 A1 A0 D7 D6 D5 D4 D3 D2 D1 D0 D7 D6 D5 D4 D3 D2 D1 D0
High-Z (ADDRESS) DATA (ADDRESS + 1) DATA High-Z

SDO High-Z
FIGURE 6-3: Device Write (SPI Mode 1,1 – SCK Idles High).

MCP3911
6.6 SPI MODE 0,0 – Clock Idle Low,
Read/Write Examples
In this SPI mode, SCK Idles low. For the MCP3911, this
means that there is a rising edge on SCK before there
is a falling edge.
CS
Data Transition on
the Falling Edge,
SCK
SDI A6 A5 A4 A3 A2 A1 A0 R/W
High-Z High-Z High-Z

SDO D7 D6 D5 D4 D3 D2 D1 D0 D7 D6 D5 D4 D3 D2 D1 D0 D7 OF (ADDRESS + 2) DATA
(ADDRESS) DATA (ADDRESS + 1) DATA
FIGURE 6-4: Device Read (SPI Mode 0,0 – SCK Idles Low).
CS
Data Transition on
the Falling Edge,
SCK
SDI A6 A5 A4 A3 A2 A1 A0 R/W D7 D6 D5 D4 D3 D2 D1 D0 D7 D6 D5 D4 D3 D2 D1 D0 D7 OF (ADDRESS + 2) DATA
High-Z (ADDRESS) DATA (ADDRESS + 1) DATA High-Z

SDO
High-Z
FIGURE 6-5: Device Write (SPI Mode 0,0 – SCK Idles Low).

MCP3911
6.7 Continuous Communication, In the case of WIDTH = 0 (16-bit), the lower byte of the
Looping on Address Sets ADC data is not accessed and the part jumps
automatically to the following address (the user does
If the user wishes to read back one or both ADC not have to clock out the lower byte since it becomes
channels continuously, the internal address counter of undefined for WIDTH = 0).
the MCP3911 can be set to loop on specific register Figure 6-6 and Figure 6-7 represent a typical, continuous
sets. In this case, there is only one control byte on SDI read communication with the default settings
to start the communication. The part stays within the (DRMODE[1:0] = 00, READ[1:0] = 10) for both WIDTH
same loop until the CS pin returns logic high. settings in the case of the SPI Mode 0,0 (see
This internal address counter allows the following Figure 6-6) and SPI Mode 1,1 (see Figure 6-7). This
functionality: configuration is typically used for power metering
• Read one ADC channel data continuously applications.
• Read both ADC channels data continuously (both
ADC data can be independent or linked with Note: For continuous reading of ADC data in
DRMODE settings) SPI Mode 0,0 (see Figure 6-6), once the
data have been completely read after a
• Continuously read/write the entire register map
data ready, the SDO pin takes the MSB
• Continuously read/write each separate register value of the previous data at the end of the
• Continuously read all Configuration registers reading (falling edge of the last SCK
• Write all Configuration registers in one clock). If SCK stays Idle at logic low (by
communication (see Figure 6-8) definition of Mode 0,0), the SDO pin is
updated at the falling edge of the next
6.7.1 CONTINUOUS READ data ready pulse (synchronously with the
The STATUSCOM register contains the loop settings DR pin falling edge with an output timing
for the internal address counter (READ[1:0] bits and of tDODR) with the new MSB of the data
WRITE bit). The internal address counter can either corresponding to the data ready pulse.
stay constant (READ[1:0] = 00) and continuously read This mechanism allows the MCP3911 to
the same byte or it can auto-increment and loop continuously use Read mode seamlessly
through the register groups defined below in SPI Mode 0,0. In SPI Mode 1,1, the
(READ[1:0] = 01), register types (READ[1:0] = 10) or SDO stays in the last state (LSB of previ-
the entire register map (READ[1:0] = 11). ous data) after a complete reading, which
also allows seamless continuous Read
The WIDTH[1:0] bits determine three possible
mode (see Figure 6-7).
configurations for the channel output format:
• WIDTH[1:0] = 11 – Both channels have 24-bit format
• WIDTH[1:0] = 01 or 10 – CH1 has 16-bit format
(typically voltage channel), CH0 has 24-bit format
(typically current channel)
• WIDTH[0:0] = 00 – Both channels have 16-bit format
CS
SCK
CH0 ADC
SDI ADDR/R
HiZ CH0 ADC CH0 ADC CH0 ADC CH1 ADC CH1 ADC CH1 ADC CH0 ADC MSB CH0 ADC Upper byte CH0 ADC CH0 ADC CH1 ADC CH1 ADC CH1 ADC CH0 ADC Upper byte
SDO Upper byte Middle byte Lower byte Upper byte Middle byte Lower byte Old ADC data New ADC data Middle byte Lower byte Upper byte Middle byte Lower byte Old ADC data
DR
CH0 ADC Old MSB data – Previous MSB data present on SDO until the data ready pulse updates the
These bytes are not present when WIDTH=0 (16-bit mode)
SDO with the new incoming MSB dta
FIGURE 6-6: Typical Continuous Read Communication (SPI Mode 0,0).

MCP3911
CS
SCK
CH0 ADC
SDI ADDR/R
HiZ CH0 ADC CH0 ADC CH0 ADC CH1 ADC CH1 ADC CH0 ADC CH0 ADC CH0 ADC CH1 ADC CH1 ADC
SDO CH1 ADC Lower byte CH1 ADC Lower byte
Upper byte Middle byte Lower byte Upper byte Middle byte Upper byte Middle byte Lower byte Upper byte Middle byte
DR
These bytes are not present when WIDTH=0 (16-bit mode)
FIGURE 6-7: Typical Continuous Read Communication (SPI Mode 1,1).
6.7.2 CONTINUOUS WRITE The following register sets are defined as types:
Both ADCs are powered up with their default TABLE 6-2: REGISTER TYPES
configurations and begin to output data ready pulses
immediately (RESET[1:0] and SHUTDOWN[1:0] bits Type Addresses
are off by default). ADC DATA (both channels) 0x00-0x05
The default output codes for both ADCs are all zeros. CONFIGURATION 0x06-0x1A
The default modulator output for both ADCs is ‘0011’
(corresponding to a theoretical zero voltage at the
inputs). The default phase is zero between the two 6.8 Situations that Reset ADC Data
channels. Immediately after the following actions, the ADCs are
It is recommended to enter into ADC Reset mode for reset and automatically restarted to provide proper
both ADCs, just after power-up; this is because the operation:
desired MCP3911 register configuration may not be the 1. Change in PHASE register.
default one. In this case, the ADC outputs undesired
2. Change in the OSR setting.
data. Within the ADC Reset mode (RESET[1:0] = 11),
the user can configure the whole part with a single 3. Change in the PRESCALE setting.
communication. The write commands automatically 4. Overwrite of the same PHASE register value.
increment the address so that the user can start writing 5. Change in the CLKEXT setting.
the PHASE register and finish with the CONFIG 6. Change in the VREFEXT setting.
register in only one communication (see Figure 6-8).
7. Change in the MODOUT setting.
The RESET[1:0] bits are in the last byte of the CONFIG
register to allow exiting the Soft Reset mode, and have After these temporary Resets, the ADCs go back to
the whole part configured and ready to run in only one normal operation without the need for an additional
command. command. If the same value is written in the PHASE
register, it can be used to serially Soft Reset the ADCs,
6.7.3 REGISTER GROUPS AND TYPES without using the RESET bits in the Configuration
register.
The following register sets are defined as groups:
TABLE 6-1: REGISTER GROUPS

Group Addresses
ADC DATA CH0 0x00-0x02
ADC DATA CH1 0x03-0x05
MOD, PHASE, GAIN 0x06-0x09
CONFIG, STATUSCOM 0x0A-0x0D
OFFCAL_CH0, GAINCAL_CH0 0x0E-0x13
OFFCAL_CH1, GAINCAL_CH1 0x14-0x19
VREFCAL 0x1A

MCP3911
AVDD, DVDD
CS
SCK
00011010 11XXXXXX 00001110 xxxxxxxx xxxxxxxx xxxxxxxx xxxxxxxx xxxxxxxx xxxxxxxx xxxxxxxx
SDI
CONFIG2 CONFIG2 PHASE ADDR/W PHASE GAIN STATUSCOM CONFIG
ADDR/W
Optional RESET of both ADCs One command for writing complete configuration (without calibration)
FIGURE 6-8: Recommended Configuration Sequence at Power-up.
6.9 Data Ready Pin (DR) 6.10 ADC Data Latches and Data Ready
To signify when channel data are ready for transmis-
Modes (DRMODE[1:0])
sion, the data ready signal is available on the Data To ensure that both channels’ ADC data are present at
Ready pin (DR) through an active-low pulse at the end the same time for SPI read, regardless of phase delay
of a channel conversion. settings for either or both channels, there are two sets
The Data Ready pin outputs an active-low pulse with a of ADC data latches in series with both the data ready
period that is equal to the DRCLK period and a width and the ‘read start’ triggers.
equal to one DMCLK period. The first set of latches holds each output when the data
When not active-low, this pin can either be in high- are ready and latches both outputs together when
impedance (when DR_HIZ = 0) or in a defined logic DRMODE[1:0] = 00. When this mode is on, both ADCs
high state (when DR_HIZ = 1). This is controlled work together and produce one set of available data
through the STATUSCOM register. This allows multiple after each data ready pulse (that corresponds to the
devices to share the same Data Ready pin (with a lagging ADC data ready). The second set of latches
pull-up resistor connected between DR and DVDD) in ensures that when reading starts on an ADC output, the
3-phase energy meter designs to reduce pin count. A corresponding data are latched so that no data
single device on the bus does not require a pull-up corruption can occur.
resistor and therefore, it is recommended to use If an ADC read has started, to read the following ADC
DR_HIZ = 1 configuration for such applications. output, the current reading needs to be completed (all
After a data ready pulse has occurred, the ADC output bits must be read from the ADC Output Data registers).
data can be read through SPI communication. Two sets
of latches at the output of the ADC prevent the
communication from outputting corrupted data (see
Section 6.10 “ADC Data Latches and Data Ready
Modes (DRMODE[1:0])”).
The CS pin has no effect on the DR pin, which means
even if CS is logic high, data ready pulses will be
provided (except when the configuration prevents them
from outputting data ready pulses). The DR pin can be
used as an interrupt when connected to an MCU or a
DSP. While the RESET pin is logic low, the DR pin is
not active.

MCP3911
6.10.1 DATA READY PIN (DR) CONTROL Since the double-output buffer structure is triggered
USING DRMODE BITS with two events that depend on two asynchronous
clocks (data ready with MCLK and read start with SCK),
There are four modes that control the data ready
it is recommended to synchronize the reading of the
pulses and these modes are set with the DRMODE[1:0]
channels with the MCU or processor using one of the
bits in the STATUSCOM register. For power metering
following methods:
applications, DRMODE[1:0] = 00 is recommended
(Default mode). 1. Use the Data Ready pin pulses as an
interrupt – Once a falling edge occurs on the
The position of the data ready pulses vary, with respect
DR pin, the data are available for reading on the
to this mode, to the OSR and to the PHASE settings:
ADC Output registers after the tDODR timing. If
• DRMODE[1:0] = 11: Both data ready pulses from this timing is not respected, data corruption can
ADC Channel 0 and ADC Channel 1 are output occur.
on the DR pin. 2. Use a timer clocked with MCLK as a synchro-
• DRMODE[1:0] = 10: Data ready pulses from ADC nization event – Since the data ready is
Channel 1 are output on the DR pin. The data synchronous with MCLK, the user can calculate
ready pulse from ADC Channel 0 is not present the position of the data ready depending on the
on the pin. PHASE[11:0], OSR[2:0] and PRE[1:0] bits set-
• DRMODE[1:0] = 01: Data ready pulses from ADC tings for each channel. Here, the tDODR timing
Channel 0 are output on the DR pin. The data needs to be added to this calculation to avoid
ready pulse from ADC Channel 1 is not present data corruption.
on the pin. 3. Poll the DRSTATUS[1:0] bits in the
• DRMODE[1:0] = 00 (Recommended and STATUSCOM register – This method consists
Default mode): Data ready pulses from the of continuously reading the STATUSCOM regis-
lagging ADC between the two are output on the ter and waits for the DRSTATUS bits to be equal
DR pin. The lagging ADC depends on the PHASE to ‘0’. When this event happens, the user can
register and on the OSR. In this mode, the two start a new communication to read the desired
ADCs are linked so their data are latched together ADC data. In this case, no additional timing is
when the lagging ADC output is ready. required.
The first method is the preferred method as it can be
6.10.2 ADC CHANNELS LATCHING AND used without adding additional MCU code space, but it
SYNCHRONIZATION requires connecting the DR pin to an I/O pin of the micro-
The ADC Channel Data Output registers (addresses controller. The other two methods require more MCU
0x00 to 0x05) have a double-buffer output structure. code space and execution time, but they allow synchro-
The two sets of latches in series are triggered by the nizing the reading of the channels without connecting
data ready signal and an internal signal indicating the the DR pin, which saves one I/O pin on the MCU.
beginning of a read communication sequence (read
start). 6.10.3 DATA READY PULSES WITH
SHUTDOWN OR RESET
The first set of latches holds each ADC Channel Data
Output register when the data are ready and latches CONDITIONS
both outputs together when DRMODE[1:0] = 00. This There are no data ready pulses if DRMODE[1:0] = 00
behavior is synchronous with the MCLK. when either one or both of the ADCs are in Reset or
The second set of latches ensures that when reading Shutdown mode. In Mode 0,0, a data ready pulse only
starts on an ADC output, the corresponding data are happens when both ADCs are ready. Any data ready
latched so that no data corruption can occur within a pulse corresponds to one data on both ADCs. The two
read. This behavior is synchronous with the SCK clock. ADCs are linked together and act as if there was only
If an ADC read has started, to read the following ADC one channel with the combined data of both ADCs.
output, the current reading needs to be fully completed This mode is very practical when both ADC channels’
(all bits must be read on the SDO pin from the ADC data retrieval and processing need to be synchronized,
Output Data registers). as in power metering applications.
Note: If DRMODE[1:0] = 11, the user is still able
to retrieve the data ready pulse for the
ADC not in Shutdown or Reset mode (i.e.,
only 1 ADC channel needs to be awake).
Figure 6-9 represents the behavior of the Data Ready

pin with the different DRMODE configurations while
shutdown or Reset is applied.

DS20002286D-page 50
MCP3911
3 * DRCLK Period 3 * DRCLK Period
Internal Reset Synchronization
DRCLK Period 1 DMCLK Period DRCLK Period (1 DMCLK Period) DRCLK Period
RESET
RESET[0] or
SHUTDOWN[0]
RESET[1] or
SHUTDOWN[1]
DRMODE = 00; DR
D0 D1 D2 D3 D4 D5 D6 D7 D8 D9 D10 D11 D12 D13 D14

PHASE > 0
DRMODE = 01; DR
D0 D1 D2 D3 D4 D5 D6 D7 D8 D9 D10 D11 D12 D13 D14 D15 D16
DRMODE = 10; DR
D0 D1 D2 D3 D4 D5 D6 D7 D8 D9 D10 D11 D12 D13 D14 D15 D16 D17
DRMODE = 11; DR
D0 D1 D2 D3 D4 D5 D6 D7 D8 D9 D10 D11 D12 D13 D14 D15 D16 D17 D18 D19 D20 D21 D22 D23 D24 D25 D26 D27 D28 D29 D30 D31 D32 D33 D34
DRMODE = 00; DR
D0 D1 D2 D3 D4 D5 D6 D7 D8 D9 D10 D11 D12 D13

PHASE = 0
DRMODE = 01; DR
DRMODE = 10; DR
DRMODE = 11; DR
D0 D1 D2 D3 D4 D5 D6 D7 D8 D9 D10 D11 D12 D13 D14 D15 D16 D17 D18 D19
DRMODE = 00; DR
D0 D1 D2 D3 D4 D5 D6 D7 D8 D9 D10 D11 D12 D13 D14

 2012-2020 Microchip Technology Inc.
PHASE < 0
DRMODE = 01; DR
D0 D1 D2 D3 D4 D5 D6 D7 D8 D9 D10 D11 D12 D13 D14 D15 D16 D17
DRMODE = 10; DR
DRMODE = 11; DR
D0 D1 D2 D3 D4 D5 D6 D7 D8 D9 D10 D11 D12 D13 D14 D15 D16 D17 D18 D19 D20 D21 D22 D23 D24 D25 D26 D27 D28 D29 D30 D31 D32 D33 D34
DRMODE = 00: Select the Lagging Data Ready

DRMODE = 01: Select the Data Ready on Channel 0 Internal Data Ready Pulse (filtered because it corresponds to unsettled data)
DRMODE = 10: Select the Data Ready on Channel 1
DRMODE = 11: Select Both Data ready
FIGURE 6-9: Data Ready Behavior.

MCP3911
7.0 INTERNAL REGISTERS registers which can be addressed and read separately.
Read and Write modes define the groups and types of
The addresses associated with the internal registers registers for continuous read/write communication or
are listed below, followed by a detailed description of looping on address sets, as shown in Table 7-2.
the registers. All registers are split into 8-bit long
TABLE 7-1: REGISTER MAP

Address Name Bits R/W Description
0x00 CHANNEL0 24 R Channel 0 ADC 24-Bit Data [23:0], MSB First
0x03 CHANNEL1 24 R Channel 1 ADC 24-Bit Data [23:0], MSB First
0x06 MOD 8 R/W Modulator Output Register for Both ADC Channels
0x07 PHASE 16 R/W Phase Delay Configuration Register
0x09 GAIN 8 R/W Gain and Boost Configuration Register
0x0A STATUSCOM 16 R/W Status and Communication Register
0x0C CONFIG 16 R/W Configuration Register
0x0E OFFCAL_CH0 24 R/W Offset Correction Register – Channel 0
0x11 GAINCAL_CH0 24 R/W Gain Correction Register – Channel 0
0x14 OFFCAL_CH1 24 R/W Offset Correction Register – Channel 1
0x17 GAINCAL_CH1 24 R/W Gain Correction Register – Channel 1
0x1A VREFCAL 8 R/W Internal Voltage Reference Temperature Coefficient Adjustment
Register

MCP3911
.
TABLE 7-2: REGISTER MAP GROUPING FOR ALL CONTINUOUS READ/WRITE MODES
READ[1:0] WRITE
Function Address
= 11 = 10 = 01 = 00 =1 =0
0x00 Static
GROUP
CHANNEL 0 0x01 Static
TYPE
0x02 Static NOT
0x03 Static WRITABLE
GROUP
CHANNEL 1 0x04 Static
0x05 Static
MOD 0x06 Static Static
GROUP
0x07 Static Static
PHASE
0x08 Static Static
GAIN 0x09 Static Static
LOOP ENTIRE REGISTER MAP
0x0A Static Static

STATUSCOM
GROUP
0x0B Static Static
0x0C Static Static
CONFIG
0x0D Static Static
0x0E Static Static
OFFCAL_CH0 0x0F Static Static
GROUP
0x10 Static Static

TYPE
0x11 Static TYPE Static

GAINCAL_CH0 0x12 Static Static
0x13 Static Static
0x14 Static Static
OFFCAL_CH1 0x15 Static Static
GROUP
0x16 Static Static

0x17 Static Static
GAINCAL_CH1 0x18 Static Static
0x19 Static Static
GROUP
VREFCAL 0x1A
Static Static

MCP3911
7.1 CHANNEL Registers – event occurs during a read communication, the most
ADC Channel Data Output current ADC data are also latched to avoid data
corruption issues. The three bytes of each channel are
Registers
updated synchronously at a DRCLK rate. The three
The ADC Channel Data Output registers always bytes can be accessed separately if needed, but are
contain the most recent A/D conversion data for each refreshed synchronously.
channel. These registers are read-only and can be Name Bits Address R/W
accessed independently or linked together (with the
CHANNEL0 24 0x00 R
READ[1:0] bits). These registers are latched when an
ADC read communication occurs. When a data ready CHANNEL1 24 0x03 R
REGISTER 7-1: CHANNEL: ADC CHANNEL DATA OUTPUT REGISTER

R-0 (MSB) R-0 R-0 R-0 R-0 R-0 R-0 R-0
DATA_CHn[23:16]
bit 23 bit 16
R-0 R-0 R-0 R-0 R-0 R-0 R-0 R-0

DATA_CHn[15:8]
bit 15 bit 8
R-0 R-0 R-0 R-0 R-0 R-0 R-0 R-0

DATA_CHn[7:0]
bit 7 bit 0
Legend:
R = Readable bit W = Writable bit U = Unimplemented bit, read as ‘0’
-n = Value at POR ‘1’ = Bit is set ‘0’ = Bit is cleared x = Bit is unknown
bit 23-0 DATA_CHn[23:0]: Output Code from ADC Channel n

These data are post-calibration if the EN_OFFCAL or EN_GAINCAL bits are enabled.

MCP3911
7.2 MOD Register –
Modulators Output Register
The MOD register contains the most recent modulator
data output. The default value corresponds to an
equivalent input of 0V on both ADCs. Each bit in this
register corresponds to one comparator output on one
of the channels.
Name Bits Address Cof
MOD 8 0x06 R/W
Note: This register should not be written to

maintain ADC accuracy.
REGISTER 7-2: MOD: MODULATORS OUTPUT REGISTER

R/W-0 R/W-0 R/W-1 R/W-1 R/W-0 R/W-0 R/W-1 R/W-1
Comparator3 Comparator2 Comparator1 Comparator0 Comparator3 Comparator2 Comparator1 Comparator0
Channel 1 Channel 1 Channel 1 Channel 1 Channel 0 Channel 0 Channel 0 Channel 0
COMP3_CH1 COMP2_CH1 COMP1_CH1 COMP0_CH1 COMP3_CH0 COMP2_CH0 COMP1_CH0 COMP0_CH0
bit 7 bit 0
Legend:
bit 7-4 COMPn_CH1: Comparator Outputs from ADC Channel 1

bit 3-0 COMPn_CH0: Comparator Outputs from ADC Channel 0

MCP3911
7.3 PHASE Register –
Phase Configuration Register
Any write to one of these two addresses (0x07 and
0x08) creates an internal reset and restart sequence.
PHASE 16 0x07 R/W
REGISTER 7-3: PHASE: PHASE CONFIGURATION REGISTER

U-0 U-0 U-0 U-0 R/W-0 R/W-0 R/W-0 R/W-0
— — — — PHASE[11] PHASE[10] PHASE[9] PHASE[8]
bit 15 bit 8

PHASE[7] PHASE[6] PHASE[5] PHASE[4] PHASE[3] PHASE[2] PHASE[1] PHASE[0]
bit 7 bit 0
Legend:
bit 15-12 Unimplemented: Read as ‘0’

bit 11-0 PHASE[11:0]: CH0 Relative to CH1 Phase Delay
Delay = PHASE register’s two’s complement code/DMCLK (Default PHASE = 0).

MCP3911
7.4 GAIN – Gain and Boost
Configuration Register
GAIN 8 0x09 R/W
REGISTER 7-4: GAIN: GAIN AND BOOST CONFIGURATION REGISTER

BOOST[1] BOOST[0] PGA_CH1[2] PGA_CH1[1] PGA_CH1[0] PGA_CH0[2] PGA_CH0[1] PGA_CH0[0]
bit 15 bit 8
Legend:
bit 7-6 BOOST[1:0]: Bias Current Selection

11 = Both channels have current x 2
10 = Both channels have current x 1 (default)
01 = Both channels have current x 0.66
00 = Both channels have current x 0.5
bit 5-3 PGA_CH1[2:0]: PGA Setting for Channel 1
111 = Reserved (Gain = 1)
101 = Gain is 32
100 = Gain is 16
011 = Gain is 8
010 = Gain is 4
001 = Gain is 2
000 = Gain is 1 (default)
bit 2-0 PGA_CH0[2:0]: PGA Setting for Channel 0
101 = Gain is 32
100 = Gain is 16
011 = Gain is 8
010 = Gain is 4
001 = Gain is 2
000 = Gain is 1 (default)

MCP3911
7.5 STATUSCOM Register – Status
and Communication Register
STATUSCOM 16 0x0A R/W
REGISTER 7-5: STATUSCOM: STATUS AND COMMUNICATION REGISTER

R/W-0 R/W-0 U-0 R/W-0 R/W-0 R/W-0 R/W-1 R/W-1
MODOUT[1] MODOUT[0] — DR_HIZ DRMODE[1] DRMODE[0] DRSTATUS[1] DRSTATUS[0]
bit 15 bit 8
R/W-1 R/W-0 R/W-1 R/W-1 R/W-1 R/W-0 R/W-0 U-0

READ[1] READ[0] WRITE WIDTH[1] WIDTH[0] EN_OFFCAL EN_GAINCAL —
bit 7 bit 0
Legend:
bit 15-14 MODOUT[1:0]: Modulator Output Setting for MDAT Pins

11 = Both CH0 and CH1 modulator outputs are present on the MDAT1 and MDAT0 pins; both SINC
filters are off and no data ready pulse is present
10 = CH1 ADC modulator output present on the MDAT1 pin; SINC filter on Channel 1 is off and data
ready pulse from Channel 1 is not present on the DR pin
01 = CH0 ADC modulator output present on the MDAT0 pin; SINC filter on Channel 0 is off and data
ready pulse from Channel 0 is not present on DR pin
00 = No modulator output is enabled; SINC filters are on and data ready pulses are present on the DR
pin for both channels (default)
bit 13 Unimplemented: Read as ‘0’.
bit 12 DR_HIZ: Data Ready Pin Inactive State Control
1 = The DR pin state is a logic high when data are NOT ready
0 = The DR pin state is high-impedance when data are NOT ready (default)
bit 11-10 DRMODE[1:0]: Data Ready Pin (DR) Mode Configuration
11 = Both data ready pulses from CH0 and CH1 are output on the DR pin
10 = Data ready pulses from CH1 ADC are output on the DR pin; data ready pulses from CH0 are not
present on the DR pin
01 = Data ready pulses from CH0 ADC are output on the DR pin; data ready pulses from CH1 are not
present on the DR pin
00 = Data ready pulses from the lagging ADC between the two are output on the DR pin. The lagging
ADC depends on the PHASE register and on the OSR (default).
bit 9-8 DRSTATUS[1:0]: Data Ready Status
11 = ADC Channel 1 and Channel 0 data are not ready (default)
10 = ADC Channel 1 data are not ready, ADC Channel 0 data are ready
01 = ADC Channel 0 data are not ready, ADC Channel 1 data are ready
00 = ADC Channel 1 and Channel 0 data are ready
bit 7-6 READ[1:0]: Address Loop Setting
11 = Address counter incremented, cycle through entire register set
10 = Address counter loops on register types (default)
01 = Address counter loops on register groups
00 = Address not incremented, continually reads single register

MCP3911
REGISTER 7-5: STATUSCOM: STATUS AND COMMUNICATION REGISTER (CONTINUED)
bit 5 WRITE: Address Loop Setting for Write Mode
1 = Address counter loops on entire register map (default)
0 = Address not incremented, continually writes same single register
bit 4-3 WIDTH[1:0] ADC Channel Output Data Word Width
11 = Both channels are in 24-bit mode(default)
10 = Channel 1 in 16-bit mode, Channel 0 in 24-bit mode
01 = Channel 1 in 16-bit mode, Channel 0 in 24-bit mode
00 = Both channels are in 16-bit mode
bit 2 EN_OFFCAL Enables or Disables 24-Bit Digital Offset Calibration on Both Channels
1 = Enabled; this mode does not add any group delay
0 = Disabled (default)
bit 1 EN_GAINCAL Enables or Disables 24-Bit Digital Offset Calibration on Both Channels
1 = Enabled; this mode adds a group delay on both channels of 24 DMCLK periods, all data ready
pulses are delayed by 24 clock periods compared to the mode with EN_GAINCAL = 0
0 = Disabled (default)
bit 0 Unimplemented: Read as ‘0’

MCP3911
7.6 CONFIG Register –
Configuration Register
CONFIG 16 0x0C R/W
REGISTER 7-6: CONFIG: CONFIGURATION REGISTER

PRE[1] PRE[0] OSR[2] OSR[1] OSR[0] DITHER[1] DITHER[0] AZ_FREQ
bit 15 bit 8
R/W-0 R/W-0 R/W-0 R/W-0 U-0 R/W-0 R/W-1 U-0

RESET[1] RESET[0] SHUTDOWN[1] SHUTDOWN[0] — VREFEXT CLKEXT —
bit 7 bit 0
Legend:
bit 15-14 PRE[1:0]: Analog Master Clock (AMCLK) Prescaler Value

11 = AMCLK = MCLK/8
10 = AMCLK = MCLK/4
01 = AMCLK = MCLK/2
00 = AMCLK = MCLK (default)
bit 13-11 OSR[2:0]: Oversampling Ratio for Delta-Sigma A/D Conversion (All Channels, fd/fS)
111 = 4096 (fd = 244 sps for MCLK = 4 MHz, fs = AMCLK = 1 MHz)
100 = 512 (fd = 1.953 ksps for MCLK = 4 MHz, fs = AMCLK = 1 MHz)
011 = 256 (fd = 3.90625 ksps for MCLK = 4 MHz, fs = AMCLK = 1 MHz) (default)
bit 10-9 DITHER[1:0]: Control for dithering circuit for idle tones cancellation and improved THD
11 = Dithering on, both channels, Strength = Maximum(MCP3901 equivalent) – (default)
10 = Dithering on, both channels, Strength = Medium
01 = Dithering on, both channels, Strength = Minimum
00 = Dithering turned off
bit 8 AZ_FREQ: Auto-Zero Frequency Setting
1 = Auto-zeroing algorithm running at higher speed
0 = Auto-zeroing algorithm running at lower speed (default)
bit 7-6 RESET[1:0]: Reset Mode Setting for ADCs
11 = Both CH0 and CH1 ADC are in Reset mode
10 = CH1 ADC is in Reset mode
01 = CH0 ADC is in Reset mode
00 = Neither ADC is in Reset mode (default)
bit 5-4 SHUTDOWN[1:0]: Shutdown mode setting for ADCs
11 = Both CH0 and CH1 ADC are in shutdown
10 = CH1 ADC is in shutdown
01 = CH0 ADC is in shutdown
00 = Neither channel is in shutdown (default)
bit 3 Unimplemented: Read as ‘0’

MCP3911
REGISTER 7-6: CONFIG: CONFIGURATION REGISTER (CONTINUED)
bit 2 VREFEXT Internal Voltage Reference Shutdown Control
1 = Internal voltage reference disabled
0 = Internal voltage reference enabled (default)
bit 1 CLKEXT Internal Clock Selection
1 = External clock drive by MCU on OSC1 pin (crystal oscillator disabled, no internal power consumption)
(default)
0 = Crystal oscillator is enabled; a crystal must be placed between the OSC1 and OSC2 pins
bit 0 Not implemented: Read as ‘0’
7.7 OFFCAL_CHn Registers – Digital

Offset Error Calibration Registers
OFFCAL_CH0 24 0x0E R/W
OFFCAL_CH1 24 0x14 R/W
REGISTER 7-7: OFFCAL_CHn: DIGITAL OFFSET ERROR CALIBRATION REGISTER

R/W-0 R/W-0 R/W-0 ... R/W-0 R/W-0 R/W-0 R/W-0
OFFCAL_CHn[23:21] ... OFFCAL_CHn[3:0]
bit 23 bit 0
Legend:
bit 23-0 OFFCAL_CHn[23:0]: Corresponding Channel CHn Digital Offset Calibration Value
This register is simply added to the output code of the channel, bit-by-bit. This register is 24-bit two’s
complement MSB first coding.
CHn Output Code = OFFCAL_CHn + ADC CHn Output Code. This register is a “Don’t Care” if
EN_OFFCAL = 0 (offset calibration disabled), but its value is not cleared by the EN_OFFCAL bit.

MCP3911
7.8 GAINCAL_CHn Registers – Digital
Gain Error Calibration Registers
GAINCAL_CH0 24 0x11 R/W
GAINCAL_CH1 24 0x17 R/W
REGISTER 7-8: GAINCAL_CHn: DIGITAL GAIN ERROR CALIBRATION REGISTER

R/W-0 R/W-0 R/W-0 ... R/W-0 R/W-0 R/W-0 R/W-0
GAINCAL_CHn[23:21] ... GAINCAL_CHn[3:0]
bit 23 bit 0
Legend:
bit 23-0 GAINCAL_CHn: Corresponding Channel CHn Digital Gain Error Calibration Value
This register is 24-bit signed MSB first coding with a range of -1x to +0.9999999x (from 0x80000 to
0x7FFFFF). The gain calibration adds 1x to this register and multiplies it to the output code of the chan-
nel, bit-by-bit, after the offset calibration. Thus, the range of the gain calibration is from 0x to
1.9999999x (from 0x80000 to 0x7FFFFF). The LSB corresponds to a 2-23 increment in the multiplier.
CHn Output Code = (GAINCAL_CHn+1) x ADC CHn Output Code. This register is a “Don’t Care” if
EN_GAINCAL = 0 (offset calibration disabled), but its value is not cleared by the EN_GAINCAL bit.
7.9 VREFCAL Register – Internal

Voltage Reference Temperature
Coefficient Adjustment Register
This register is only for advanced users. This register
should not be written unless the user wants to calibrate
the temperature coefficient of the whole system or
application. The default value of this register is set to
0x42.
VREFCAL 8 0x1A R/W
REGISTER 7-9: VREFCAL REGISTER

VREFCAL[7:0]
bit 7 bit 0
Legend:
bit 7-0 VREFCAL[7:0]: Internal Voltage Temperature Coefficient Value

See Section 5.7.3 “Temperature Compensation (VREFCAL Register)” for complete description.

MCP3911
NOTES:

MCP3911
8.0 PACKAGING INFORMATION
8.1 Package Marking Information
20-Lead QFN (4x4x0.9 mm) Example
PIN 1
XXXXX PIN 1
3911A0
XXXXXX E/ML e 3
XXXXXX 916256
YWWNNN
20-Lead SSOP Example
XXXXXXXXXXX MCP3911A0
XXXXXXXXXXX E/SS e3
YYWWNNN 2016256
Legend: XX...X Customer-specific information

Y Year code (last digit of calendar year)
YY Year code (last 2 digits of calendar year)
WW Week code (week of January 1 is week ‘01’)
NNN Alphanumeric traceability code
e3 Pb-free Compliant JEDEC designator for Matte Tin (Sn)
* This package is Pb-free Compliant. The Pb-free Compliant JEDEC designator (e3 )
can be found on the outer packaging for this package.
Note: In the event the full Microchip part number cannot be marked on one line, it will be carried over
to the next line, thus limiting the number of available characters for customer-specific
information.

MCP3911
/HDG3ODVWLF4XDG)ODW1R/HDG3DFNDJH0/[PP%RG\>4)1@
$OVRFDOOHG94)1
1RWH )RUWKHPRVWFXUUHQWSDFNDJHGUDZLQJVSOHDVHVHHWKH0LFURFKLS3DFNDJLQJ6SHFLILFDWLRQORFDWHGDW
KWWSZZZPLFURFKLSFRPSDFNDJLQJ
' $ %
127( 1

(
'$780%
'$780$
;
&
;
& 7239,(:
& $
&
$
6($7,1*
3/$1( ;
$ &
6,'(9,(:
& $ %
'
& $ %
(

127(
1 .
/ ;E
& $ %
&
H
%277209,(:
0LFURFKLS7HFKQRORJ\'UDZLQJ&5HY&6KHHWRI

MCP3911
$OVRFDOOHG94)1
8QLWV 0,//,0(7(56
'LPHQVLRQ/LPLWV 0,1 120 0$;
1XPEHURI7HUPLQDOV 1
3LWFK H %6&
2YHUDOO+HLJKW $
6WDQGRII $
7HUPLQDO7KLFNQHVV $ 5()
2YHUDOO/HQJWK ' %6&
([SRVHG3DG/HQJWK '
2YHUDOO:LGWK ( %6&
([SRVHG3DG:LGWK (
7HUPLQDO:LGWK E
7HUPLQDO/HQJWK /
7HUPLQDOWR([SRVHG3DG .
Notes:
3LQYLVXDOLQGH[IHDWXUHPD\YDU\EXWPXVWEHORFDWHGZLWKLQWKHKDWFKHGDUHD
3DFNDJHLVVDZVLQJXODWHG
'LPHQVLRQLQJDQGWROHUDQFLQJSHU$60(<0
%6&%DVLF'LPHQVLRQ7KHRUHWLFDOO\H[DFWYDOXHVKRZQZLWKRXWWROHUDQFHV
5()5HIHUHQFH'LPHQVLRQXVXDOO\ZLWKRXWWROHUDQFHIRULQIRUPDWLRQSXUSRVHVRQO\
0LFURFKLS7HFKQRORJ\'UDZLQJ&5HY&6KHHWRI

MCP3911
$OVRFDOOHG94)1
&
;
(9

9

& <
(9
*
<
;
6,/.6&5((1
(
5(&200(1'('/$1'3$77(51
8QLWV 0,//,0(7(56
&RQWDFW3LWFK ( %6&
2SWLRQDO&HQWHU3DG:LGWK ;
2SWLRQDO&HQWHU3DG/HQJWK <
&RQWDFW3DG6SDFLQJ &
&RQWDFW3DG6SDFLQJ &
&RQWDFW3DG:LGWK; ;
&RQWDFW3DG/HQJWK; <
&RQWDFW3DGWR&HQWHU3DG; *
7KHUPDO9LD'LDPHWHU 9
7KHUPDO9LD3LWFK (9
1RWHV
%6&%DVLF'LPHQVLRQ7KHRUHWLFDOO\H[DFWYDOXHVKRZQZLWKRXWWROHUDQFHV
)RUEHVWVROGHULQJUHVXOWVWKHUPDOYLDVLIXVHGVKRXOGEHILOOHGRUWHQWHGWRDYRLGVROGHUORVVGXULQJ
UHIORZSURFHVV
0LFURFKLS7HFKQRORJ\'UDZLQJ&5HY%

MCP3911
/HDG3ODVWLF6KULQN6PDOO2XWOLQH66±PP%RG\>6623@
D
N
E1
NOTE 1
1 2
e
b
c
A A2
φ
A1
L1 L
8QLWV 0,//,0(7(56
1XPEHURI3LQV 1
3LWFK H %6&
2YHUDOO+HLJKW $ ± ±
0ROGHG3DFNDJH7KLFNQHVV $
6WDQGRII $ ± ±
2YHUDOO:LGWK (
0ROGHG3DFNDJH:LGWK (
2YHUDOO/HQJWK '
)RRW/HQJWK /
)RRWSULQW / 5()
/HDG7KLFNQHVV F ±
)RRW$QJOH
/HDG:LGWK E ±
1RWHV
3LQYLVXDOLQGH[IHDWXUHPD\YDU\EXWPXVWEHORFDWHGZLWKLQWKHKDWFKHGDUHD
'LPHQVLRQV'DQG(GRQRWLQFOXGHPROGIODVKRUSURWUXVLRQV0ROGIODVKRUSURWUXVLRQVVKDOOQRWH[FHHGPPSHUVLGH
%6& %DVLF'LPHQVLRQ7KHRUHWLFDOO\H[DFWYDOXHVKRZQZLWKRXWWROHUDQFHV
5() 5HIHUHQFH'LPHQVLRQXVXDOO\ZLWKRXWWROHUDQFHIRULQIRUPDWLRQSXUSRVHVRQO\
0LFURFKLS 7HFKQRORJ\ 'UDZLQJ &%

MCP3911
20-Lead Plastic Shrink Small Outline (SS) - 5.30 mm Body [SSOP]
Note: For the most current package drawings, please see the Microchip Packaging Specification located at
http://www.microchip.com/packaging
0.65 0.45
SILK SCREEN
c
Y1
G
X1
E
RECOMMENDED LAND PATTERN
Units MILLIMETERS
Dimension Limits MIN NOM MAX
Contact Pitch E 0.65 BSC
Contact Pad Spacing C 7.20
Contact Pad Width (X20) X1 0.45
Contact Pad Length (X20) Y1 1.75
Distance Between Pads G 0.20
Notes:
1. Dimensioning and tolerancing per ASME Y14.5M
BSC: Basic Dimension. Theoretically exact value shown without tolerances.
Microchip Technology Drawing No. C04-2072B

MCP3911
APPENDIX A: REVISION HISTORY
Revision D (January 2020)

The following is the list of modifications:
1. Updated Offset Error and Gain Error in
Table 1-1.
Revision C (October 2013)

1. Changed units from kW to kin Table 1-1.
Revision B (October 2013)

1. Corrected ESD values in Absolute Maximum
Ratings† section and throughout the document.
2. Updated Section 3.0, Pin Description.
3. Added new Section 6.10.2, ADC Channels
Latching and Synchronization.
4. Updated Table 7-2.
5. Added note to Section 7.2, MOD Register –
Modulators Output Register.
6. Minor grammatical and spelling corrections.
Revision A (March 2012)

• Original release of this document.

MCP3911
NOTES:

MCP3911
PRODUCT IDENTIFICATION SYSTEM
To order or obtain information, e.g., on pricing or delivery, refer to the factory or the listed sales office.
PART NO. XX X X /XX Examples:

a) MCP3911A0-E/ML: Extended Temperature,
Device Address Tape and Temperature Package
Two-Channel Analog
Options Reel Range Front-End Converter,
20-Lead QFN Package.
b) MCP3911A0T-E/ML: Tape and Reel,
Device: MCP3911A0: Two-Channel Analog Font-End Converter Extended Temperature,
Two-Channel Analog
Front-End Converter,
Address Options: XX A6 A5 20-Lead QFN Package.
A0* = 0 0
c) MCP3911A0-E/SS: Extended Temperature,
A1 = 0 1 Two-Channel Analog
A2 = 1 0
20-Lead SSOP Package.
A3 = 1 1
d) MCP3911A0T-E/SS: Tape and Reel,
* Default option. Contact Microchip factory for other Extended Temperature,
address options. Two-Channel Analog
20-Lead SSOP Package.
Tape and Reel: T = Tape and Reel
Temperature Range: E = -40°C to +125°C
Package: ML = Plastic Quad Flat No Lead Package (QFN)

SS = Small Shrink Output Package (20-Lead SSOP)

MCP3911
NOTES:

Note the following details of the code protection feature on Microchip devices:
• Microchip products meet the specification contained in their particular Microchip Data Sheet.
• Microchip believes that its family of products is one of the most secure families of its kind on the market today, when used in the
intended manner and under normal conditions.
• There are dishonest and possibly illegal methods used to breach the code protection feature. All of these methods, to our
knowledge, require using the Microchip products in a manner outside the operating specifications contained in Microchip’s Data
Sheets. Most likely, the person doing so is engaged in theft of intellectual property.
• Microchip is willing to work with the customer who is concerned about the integrity of their code.
• Neither Microchip nor any other semiconductor manufacturer can guarantee the security of their code. Code protection does not
mean that we are guaranteeing the product as “unbreakable.”
Code protection is constantly evolving. We at Microchip are committed to continuously improving the code protection features of our
products. Attempts to break Microchip’s code protection feature may be a violation of the Digital Millennium Copyright Act. If such acts
allow unauthorized access to your software or other copyrighted work, you may have a right to sue for relief under that Act.
Information contained in this publication regarding device Trademarks

applications and the like is provided only for your convenience The Microchip name and logo, the Microchip logo, Adaptec,
and may be superseded by updates. It is your responsibility to AnyRate, AVR, AVR logo, AVR Freaks, BesTime, BitCloud, chipKIT,
ensure that your application meets with your specifications. chipKIT logo, CryptoMemory, CryptoRF, dsPIC, FlashFlex,
flexPWR, HELDO, IGLOO, JukeBlox, KeeLoq, Kleer, LANCheck,
MICROCHIP MAKES NO REPRESENTATIONS OR LinkMD, maXStylus, maXTouch, MediaLB, megaAVR, Microsemi,
WARRANTIES OF ANY KIND WHETHER EXPRESS OR Microsemi logo, MOST, MOST logo, MPLAB, OptoLyzer,
IMPLIED, WRITTEN OR ORAL, STATUTORY OR PackeTime, PIC, picoPower, PICSTART, PIC32 logo, PolarFire,
OTHERWISE, RELATED TO THE INFORMATION, Prochip Designer, QTouch, SAM-BA, SenGenuity, SpyNIC, SST,
INCLUDING BUT NOT LIMITED TO ITS CONDITION, SST Logo, SuperFlash, Symmetricom, SyncServer, Tachyon,
TempTrackr, TimeSource, tinyAVR, UNI/O, Vectron, and XMEGA
QUALITY, PERFORMANCE, MERCHANTABILITY OR are registered trademarks of Microchip Technology Incorporated in
FITNESS FOR PURPOSE. Microchip disclaims all liability the U.S.A. and other countries.
arising from this information and its use. Use of Microchip
devices in life support and/or safety applications is entirely at APT, ClockWorks, The Embedded Control Solutions Company,
the buyer’s risk, and the buyer agrees to defend, indemnify and EtherSynch, FlashTec, Hyper Speed Control, HyperLight Load,
IntelliMOS, Libero, motorBench, mTouch, Powermite 3, Precision
hold harmless Microchip from any and all damages, claims, Edge, ProASIC, ProASIC Plus, ProASIC Plus logo, Quiet-Wire,
suits, or expenses resulting from such use. No licenses are SmartFusion, SyncWorld, Temux, TimeCesium, TimeHub,
conveyed, implicitly or otherwise, under any Microchip TimePictra, TimeProvider, Vite, WinPath, and ZL are registered
intellectual property rights unless otherwise stated. trademarks of Microchip Technology Incorporated in the U.S.A.
Adjacent Key Suppression, AKS, Analog-for-the-Digital Age, Any

Capacitor, AnyIn, AnyOut, BlueSky, BodyCom, CodeGuard,
CryptoAuthentication, CryptoAutomotive, CryptoCompanion,
CryptoController, dsPICDEM, dsPICDEM.net, Dynamic Average
Matching, DAM, ECAN, EtherGREEN, In-Circuit Serial
Programming, ICSP, INICnet, Inter-Chip Connectivity, JitterBlocker,
KleerNet, KleerNet logo, memBrain, Mindi, MiWi, MPASM, MPF,
MPLAB Certified logo, MPLIB, MPLINK, MultiTRAK, NetDetach,
Omniscient Code Generation, PICDEM, PICDEM.net, PICkit,
PICtail, PowerSmart, PureSilicon, QMatrix, REAL ICE, Ripple
Blocker, SAM-ICE, Serial Quad I/O, SMART-I.S., SQI,
SuperSwitcher, SuperSwitcher II, Total Endurance, TSHARC,
USBCheck, VariSense, ViewSpan, WiperLock, Wireless DNA, and
ZENA are trademarks of Microchip Technology Incorporated in the
U.S.A. and other countries.
SQTP is a service mark of Microchip Technology Incorporated in

the U.S.A.
The Adaptec logo, Frequency on Demand, Silicon Storage
Technology, and Symmcom are registered trademarks of Microchip
Technology Inc. in other countries.
GestIC is a registered trademark of Microchip Technology Germany
II GmbH & Co. KG, a subsidiary of Microchip Technology Inc., in
other countries.
All other trademarks mentioned herein are property of their
respective companies.
© 2012-2020, Microchip Technology Incorporated, All Rights

Reserved.
For information regarding Microchip’s Quality Management Systems,
please visit www.microchip.com/quality. ISBN: 978-1-5224-5543-1

Worldwide Sales and Service
AMERICAS ASIA/PACIFIC ASIA/PACIFIC EUROPE
Corporate Office Australia - Sydney India - Bangalore Austria - Wels
2355 West Chandler Blvd. Tel: 61-2-9868-6733 Tel: 91-80-3090-4444 Tel: 43-7242-2244-39
Chandler, AZ 85224-6199 China - Beijing India - New Delhi Fax: 43-7242-2244-393
Tel: 480-792-7200 Tel: 86-10-8569-7000 Tel: 91-11-4160-8631 Denmark - Copenhagen
Fax: 480-792-7277 Tel: 45-4450-2828
China - Chengdu India - Pune
Technical Support: Fax: 45-4485-2829
Tel: 86-28-8665-5511 Tel: 91-20-4121-0141
http://www.microchip.com/
China - Chongqing Japan - Osaka Finland - Espoo
support
Tel: 86-23-8980-9588 Tel: 81-6-6152-7160 Tel: 358-9-4520-820
Web Address:
www.microchip.com China - Dongguan Japan - Tokyo France - Paris
Tel: 86-769-8702-9880 Tel: 81-3-6880- 3770 Tel: 33-1-69-53-63-20
Atlanta Fax: 33-1-69-30-90-79
Duluth, GA China - Guangzhou Korea - Daegu
Tel: 678-957-9614 Tel: 86-20-8755-8029 Tel: 82-53-744-4301 Germany - Garching
Tel: 49-8931-9700
Fax: 678-957-1455 China - Hangzhou Korea - Seoul
Austin, TX Tel: 86-571-8792-8115 Tel: 82-2-554-7200 Germany - Haan
Tel: 512-257-3370 Tel: 49-2129-3766400
China - Hong Kong SAR Malaysia - Kuala Lumpur
Tel: 852-2943-5100 Tel: 60-3-7651-7906 Germany - Heilbronn
Boston
Tel: 49-7131-72400
Westborough, MA China - Nanjing Malaysia - Penang
Tel: 774-760-0087 Tel: 86-25-8473-2460 Tel: 60-4-227-8870 Germany - Karlsruhe
Fax: 774-760-0088 Tel: 49-721-625370
China - Qingdao Philippines - Manila
Chicago Tel: 86-532-8502-7355 Tel: 63-2-634-9065 Germany - Munich
Itasca, IL Tel: 49-89-627-144-0
China - Shanghai Singapore
Tel: 630-285-0071 Fax: 49-89-627-144-44
Tel: 86-21-3326-8000 Tel: 65-6334-8870
Fax: 630-285-0075 Germany - Rosenheim
China - Shenyang Taiwan - Hsin Chu
Dallas Tel: 49-8031-354-560
Tel: 86-24-2334-2829 Tel: 886-3-577-8366
Addison, TX Israel - Ra’anana
China - Shenzhen Taiwan - Kaohsiung
Tel: 972-818-7423 Tel: 972-9-744-7705
Tel: 86-755-8864-2200 Tel: 886-7-213-7830
Fax: 972-818-2924 Italy - Milan
China - Suzhou Taiwan - Taipei
Detroit Tel: 39-0331-742611
Tel: 86-186-6233-1526 Tel: 886-2-2508-8600
Novi, MI Fax: 39-0331-466781
Tel: 248-848-4000 China - Wuhan Thailand - Bangkok
Tel: 86-27-5980-5300 Tel: 66-2-694-1351 Italy - Padova
Houston, TX Tel: 39-049-7625286
Tel: 281-894-5983 China - Xian Vietnam - Ho Chi Minh
Tel: 86-29-8833-7252 Tel: 84-28-5448-2100 Netherlands - Drunen
Indianapolis Tel: 31-416-690399
Noblesville, IN China - Xiamen Fax: 31-416-690340
Tel: 317-773-8323 Tel: 86-592-2388138
Norway - Trondheim
Fax: 317-773-5453 China - Zhuhai Tel: 47-7288-4388
Tel: 317-536-2380 Tel: 86-756-3210040
Poland - Warsaw
Los Angeles Tel: 48-22-3325737
Mission Viejo, CA
Romania - Bucharest
Tel: 949-462-9523
Tel: 40-21-407-87-50
Fax: 949-462-9608
Tel: 951-273-7800 Spain - Madrid
Tel: 34-91-708-08-90
Raleigh, NC Fax: 34-91-708-08-91
Tel: 919-844-7510
Sweden - Gothenberg
New York, NY Tel: 46-31-704-60-40
Tel: 631-435-6000
Sweden - Stockholm
San Jose, CA Tel: 46-8-5090-4654
Tel: 408-735-9110
Tel: 408-436-4270 UK - Wokingham
Tel: 44-118-921-5800
Canada - Toronto Fax: 44-118-921-5820
Tel: 905-695-1980
Fax: 905-695-2078

05/14/19

mcp3911 3.3v Two Channel Analog Front End ds20002286d

Uploaded by

Copyright:

Available Formats

mcp3911 3.3v Two Channel Analog Front End ds20002286d

Uploaded by

Document Information

Original Title

Copyright

Available Formats

Share this document

Share or Embed Document

Sharing Options

Did you find this document useful?

Is this content inappropriate?

Copyright:

Available Formats

mcp3911 3.3v Two Channel Analog Front End ds20002286d

Uploaded by

Copyright:

Available Formats

MCP3911

3.3V Two-Channel Analog Front End

• Available in Small 20-Lead QFN and SSOP

Packages, Pin-to-Pin Compatible with MCP3901

• Extended Temperature Range: -40°C to +125°C 4x4 QFN*

Applications CH0+ 1 15 SCK

*Includes Exposed Thermal Pad (EP); see Table 3-1.

 2012-2020 Microchip Technology Inc. DS20002286D-page 1

VREF- VREF+ ANALOG DIGITAL

DS20002286D-page 2  2012-2020 Microchip Technology Inc.

1.1 Electrical Specifications

 2012-2020 Microchip Technology Inc. DS20002286D-page 3

DS20002286D-page 4  2012-2020 Microchip Technology Inc.

 2012-2020 Microchip Technology Inc. DS20002286D-page 5

1.2 Serial Interface Characteristics

TABLE 1-2: SERIAL DC CHARACTERISTICS

DS20002286D-page 6  2012-2020 Microchip Technology Inc.

TABLE 1-4: TEMPERATURE SPECIFICATIONS

 2012-2020 Microchip Technology Inc. DS20002286D-page 7

SDO MSB Out LSB Out

FIGURE 1-1: Serial Output Timing Diagram.

SDI MSB In LSB In

FIGURE 1-2: Serial Input Timing Diagram.

FIGURE 1-3: Data Ready Pulse/Sampling Timing Diagram.

DS20002286D-page 8  2012-2020 Microchip Technology Inc.

Timing Waveform for tDO Waveform for tDIS

Timing Waveform for MDAT0/1

FIGURE 1-4: Timing Diagrams (Continued).

 2012-2020 Microchip Technology Inc. DS20002286D-page 9

DS20002286D-page 10  2012-2020 Microchip Technology Inc.

FIGURE 2-1: Spectral Response. FIGURE 2-4: Spectral Response.

-60 Dithering = None -60 Dithering = Maximum

FIGURE 2-2: Spectral Response. FIGURE 2-5: Spectral Response.

FIGURE 2-3: THD Histogram. FIGURE 2-6: SINAD Histogram.

 2012-2020 Microchip Technology Inc. DS20002286D-page 11

FIGURE 2-7: Spurious-Free Dynamic FIGURE 2-10: ENOB SINAD Histogram.

FIGURE 2-8: SNR Histogram. FIGURE 2-11: ENOB SNR Histogram.

4500 VIN = 0V -10

FIGURE 2-9: Noise Histogram. FIGURE 2-12: THD vs. OSR.

DS20002286D-page 12  2012-2020 Microchip Technology Inc.

Total Harmonic Distortion (dBc)

Signal-to-Noise and Distortion

FIGURE 2-14: SNR vs.OSR. FIGURE 2-17: SINAD vs. MCLK.

 2012-2020 Microchip Technology Inc. DS20002286D-page 13

Signal-to-Noise and Distortion

Total Harmonic Distortion (dBc)

DS20002286D-page 14  2012-2020 Microchip Technology Inc.

Signal-to-Noise and Distortion

Signal-to-Noise Ratio (dB)

Spurious Free Dynamic Range

 2012-2020 Microchip Technology Inc. DS20002286D-page 15

Gain Error (%)

Internal Voltage Reference (V)

-40 Channel 1 1.2001

FIGURE 2-33: Channel-to-Channel Offset FIGURE 2-36: Internal Voltage Reference

DS20002286D-page 16  2012-2020 Microchip Technology Inc.

2 0.5 DIDD, All Boost Settings

FIGURE 2-38: Integral Nonlinearity FIGURE 2-41: Operating Current vs.

FIGURE 2-39: Integral Nonlinearity