I.

DIGITAL LOGIC BOARD

1. Power-up the Digital Logic Board

Connect the 6V adapter to the Digital Logic Board. At this point, a
red indicator will turn-on.

2. Using the Breadboard

The breadboard has many holes into which circuit components like
ICs and connectors are inserted. Always use the side lines for power
supply connections. Power the ICs from the side lines and not directly
from the power supply. Use black wires for ground connections („0‟), and
red for other connections.

3. Using the LED

There are 8 red LEDs on the Digital Logic Board. The 8 LEDs are
labeled as LED0, LED1, LED2, LED3, LED4, LED5, LED6 and LED7.
Driving its associated pin to a high logic level turns the LED on and driving
the pin low turns it off.

4. Using the Switches

There are 8 toggle switches (sliders) and pushbutton switches on
the Digital Logic Board. These switches are not debounced and are
intended for use as data inputs to a circuit. When a switch is in the DOWN
position (closest to the edge of the board) it provides a low logic level („0‟)
and when the switch is in the UP position it provides a high logic level („1‟).
Both of the switches are labeled as SW0, SW1, SW2, SW3, SW4, SW5,
SW6 and SW7 on the Digital Logic Board.

5. Using the 7-segment display

The Digital Logic Board has two 7-segment displays. These
displays are arranged with the intent of displaying numbers. Applying a
low logic level to the four input of the decoder causes it to light up, and
applying a high logic level turns it off. The dot in the middle is connected
and can be used.

6. Using the Clock

The clock input is useful in experiments regarding counters and for
future project presentations. It is labeled as Clk in the Digital Logic Board.

1
II. DE2 BOARD

1. LAYOUT AND COMPONENTS

A photograph of the DE2 board is shown in Figure 1. It depicts the

layout of the board and indicates the location of the connectors and key
components.

Figure 1: The DE2 Board

The DE2 board has many features. The following hardware is

provided on the DE2 board:
 Altera Cyclone® II 2C35 FPGA device
 Altera Serial Configuration device - EPCS16
 USB Blaster (on board) for programming and user API control; both
JTAG and Active Serial (AS) programming modes are supported
 512-Kbyte SRAM
 8-Mbyte SDRAM
 4-Mbyte Flash memory (1 Mbyte on some boards
 SD Card socket
 4 pushbutton switches
 18 toggle switches
 18 red user LEDs
 9 green user LEDs
 50-MHz oscillator and 27-MHz oscillator for clock sources

2
  24-bit CD-quality audio CODEC with line-in, line-out, and
microphone-in jacks
 VGA DAC (10-bit high-speed triple DACs) with VGA-out connector
 TV Decoder (NTSC/PAL) and TV-in connector
 10/100 Ethernet Controller with a connector
 USB Host/Slave Controller with USB type A and type B connectors
 RS-232 transceiver and 9-pin connector
 PS/2 mouse/keyboard connector
 IrDA transceiver
 Two 40-pin Expansion Headers with diode protection

In order to use the DE2 board, the user has to be familiar with the
Quartus II software.

2. POWER-UP THE DE2 BOARD

To power-up the board perform the following steps:

2.a Connect the provided USB cable from the host computer to the
USB Blaster connector on the DE2 board. For communication
between the host and the DE2 board, it is necessary to install the
Altera USB Blaster driver software.

2.b Connect the 9V adapter to the DE2 board.

2.c Turn the RUN/PROG switch on the left edge of the DE2 board to
RUN position; the PROG position is used only for the AS Mode
programming.

2.d Turn the power on by pressing the ON/OFF switch on the DE2
board.

At this point you should observe the following:

 All user LEDs are flashing
 All 7-segment displays are cycling through the numbers 0 to F

3. USING THE LEDs AND SWITCHES

3.a SWITCHES

The DE2 board provides four pushbutton switches. Each of these

switches is debounced using a Schmitt Trigger circuit. The four outputs
called KEY0,…, KEY3 of the Schmitt Trigger device are connected directly
to the Cyclone II FPGA. Each switch provides a high logic level (3.3 volts)
when it is not pressed, and provides a low logic level (0 volts) when

3
depressed. Since the pushbutton switches are debounced, they are
appropriate for use as clock or reset inputs in a circuit.

There are also 18 toggle switches (sliders) on the DE2 board.

These switches are not debounced, and are intended for use as level-
sensitive data inputs to a circuit. Each switch is connected directly to a pin
on the Cyclone II FPGA. When a switch is in the DOWN position (closest
to the edge of the board) it provides a low logic level (0 volts) to the FPGA,
and when the switch is in the UP position it provides a high logic level (3.3
volts).

3.b LEDs

There are 27 user-controllable LEDs on the DE2 board. Eighteen

red LEDs are situated above the 18 toggle switches, and eight green
LEDs are found above the pushbutton switches (the 9th green LED is in
the middle of the 7-segment displays). Each LED is driven directly by a pin
on the Cyclone II FPGA; driving its associated pin to a high logic level
turns the LED on, and driving the pin low turns it off.

A list of the pin names on the Cyclone II FPGA that are connected
to the toggle switches is given in Table 1. Similarly, the pins used to
connect to the pushbutton switches and LEDs are displayed in Tables 2
and 3, respectively.

Signal Name FPGA Pin No. Description

SW[0] PIN_N25 Toggle Switch[0]
SW[1] PIN_N26 Toggle Switch[1]
SW[2] PIN_P25 Toggle Switch[2]
SW[3] PIN_AE14 Toggle Switch[3]
SW[4] PIN_AF14 Toggle Switch[4]
SW[5] PIN_AD13 Toggle Switch[5]
SW[6] PIN_AC13 Toggle Switch[6]
SW[7] PIN_C13 Toggle Switch[7]
SW[8] PIN_B13 Toggle Switch[8]
SW[9] PIN_A13 Toggle Switch[9]
SW[10] PIN_N1 Toggle Switch[10]
SW[11] PIN_P1 Toggle Switch[11]
SW[12] PIN_P2 Toggle Switch[12]
SW[13] PIN_T7 Toggle Switch[13]
SW[14] PIN_U3 Toggle Switch[14]
SW[15] PIN_U4 Toggle Switch[15]
SW[16] PIN_V1 Toggle Switch[16]
SW[17] PIN_V2 Toggle Switch[17]
Table 1: Pin Assignments for the toggle switches

4
 Signal Name FPGA Pin No. Description
KEY[0] PIN_G26 Pushbutton[0]
KEY[1] PIN_N23 Pushbutton[1]
KEY[2] PIN_P23 Pushbutton[2]
KEY[3] PIN_W26 Pushbutton [3]
Table 2: Pin Assignments for the pushbutton switches

Signal Name FPGA Pin No. Description

LEDR[0] PIN_AE23 LED Red[0]
LEDR[1] PIN_AF23 LED Red[1]
LEDR[2] PIN_AB21 LED Red[2]
LEDR[3] PIN_AC22 LED Red[3]
LEDR[4] PIN_AD22 LED Red[4]
LEDR[5] PIN_AD23 LED Red[5]
LEDR[6] PIN_AD21 LED Red[6]
LEDR[7] PIN_AC21 LED Red[7]
LEDR[8] PIN_AA14 LED Red[8]
LEDR[9] PIN_Y13 LED Red[9]
LEDR[10] PIN_AA13 LED Red[10]
LEDR[11] PIN_AC14 LED Red[11]
LEDR[12] PIN_AD15 LED Red[12]
LEDR[13] PIN_AE15 LED Red[13]
LEDR[14] PIN_AF13 LED Red[14]
LEDR[15] PIN_AE13 LED Red[15]
LEDR[16] PIN_AE12 LED Red[16]
LEDR[17] PIN_AD12 LED Red[17]
LEDG[0] PIN_AE22 LED Green[0]
LEDG[1] PIN_AF22 LED Green[1]
LEDG[2] PIN_W19 LED Green[2]
LEDG[3] PIN_V18 LED Green[3]
LEDG[4] PIN_U18 LED Green[4]
LEDG[5] PIN_U17 LED Green[5]
LEDG[6] PIN_AA20 LED Green[6]
LEDG[7] PIN_Y18 LED Green[7]
LEDG[8] PIN_Y12 LED Green[8]
Table 3: Pin Assignments for the LEDs

4. USING THE 7-SEGMENT DISPLAYS

The DE2 Board has eight 7-segment displays. These displays are
arranged into two pairs and a group of four, with the intent of displaying
numbers of various sizes. The seven segments are connected to pins on the

5
Cyclone II FPGA. Applying a low logic level to a segment causes it to light up,
and applying a high logic level turns it off.

Each segment in a display is identified by an index from 0 to 6, with the

positions given in Figure 3. Note that the dot in each display is unconnected
and cannot be used. Table 4 shows the assignments of FPGA pins to the
7segment displays.

Figure 3: Position and index of each segment

in a 7-segment display

Signal FPGA Pin Description

Name No.
HEX0[0] PIN_AF10 Seven Segment Digit 0[0]
HEX0[1] PIN_AB12 Seven Segment Digit 0[1]
HEX0[2] PIN_AC12 Seven Segment Digit 0[2]
HEX0[3] PIN_AD11 Seven Segment Digit 0[3]
HEX0[4] PIN_AE11 Seven Segment Digit 0[4]
HEX0[5] PIN_V14 Seven Segment Digit 0[5]
HEX0[6] PIN_V13 Seven Segment Digit 0[6]
HEX1[0] PIN_V20 Seven Segment Digit 1[0]
HEX1[1] PIN_V21 Seven Segment Digit 1[1]
HEX1[2] PIN_W21 Seven Segment Digit 1[2]
HEX1[3] PIN_Y22 Seven Segment Digit 1[3]
HEX1[4] PIN_AA24 Seven Segment Digit 1[4]
HEX1[5] PIN_AA23 Seven Segment Digit 1[5]
HEX1[6] PIN_AB24 Seven Segment Digit 1[6]
HEX2[0] PIN_AB23 Seven Segment Digit 2[0]
HEX2[1] PIN_V22 Seven Segment Digit 2[1]
HEX2[2] PIN_AC25 Seven Segment Digit 2[2]
HEX2[3] PIN_AC26 Seven Segment Digit 2[3]
HEX2[4] PIN_AB26 Seven Segment Digit 2[4]
HEX2[5] PIN_AB25 Seven Segment Digit 2[5]
HEX2[6] PIN_Y24 Seven Segment Digit 2[6]
HEX3[0] PIN_Y23 Seven Segment Digit 3[0]
HEX3[1] PIN_AA25 Seven Segment Digit 3[1]
HEX3[2] PIN_AA26 Seven Segment Digit 3[2]
6
 HEX3[3] PIN_Y26 Seven Segment Digit 3[3]
HEX3[4] PIN_Y25 Seven Segment Digit 3[4]
HEX3[5] PIN_U22 Seven Segment Digit 3[5]
HEX3[6] PIN_W24 Seven Segment Digit 3[6]
HEX4[0] PIN_U9 Seven Segment Digit 4[0]
HEX4[1] PIN_U1 Seven Segment Digit 4[1]
HEX4[2] PIN_U2 Seven Segment Digit 4[2]
HEX4[3] PIN_T4 Seven Segment Digit 4[3]
HEX4[4] PIN_R7 Seven Segment Digit 4[4]
HEX4[5] PIN_R6 Seven Segment Digit 4[5]
HEX4[6] PIN_T3 Seven Segment Digit 4[6]
HEX5[0] PIN_T2 Seven Segment Digit 5[0]
HEX5[1] PIN_P6 Seven Segment Digit 5[1]
HEX5[2] PIN_P7 Seven Segment Digit 5[2]
HEX5[3] PIN_T9 Seven Segment Digit 5[3]
HEX5[4] PIN_R5 Seven Segment Digit 5[4]
HEX5[5] PIN_R4 Seven Segment Digit 5[5]
HEX5[6] PIN_R3 Seven Segment Digit 5[6]
HEX6[0] PIN_R2 Seven Segment Digit 6[0]
HEX6[1] PIN_P4 Seven Segment Digit 6[1]
HEX6[2] PIN_P3 Seven Segment Digit 6[2]
HEX6[3] PIN_M2 Seven Segment Digit 6[3]
HEX6[4] PIN_M3 Seven Segment Digit 6[4]
HEX6[5] PIN_M5 Seven Segment Digit 6[5]
HEX6[6] PIN_M4 Seven Segment Digit 6[6]
HEX7[0] PIN_L3 Seven Segment Digit 7[0]
HEX7[1] PIN_L2 Seven Segment Digit 7[1]
HEX7[2] PIN_L9 Seven Segment Digit 7[2]
HEX7[3] PIN_L6 Seven Segment Digit 7[3]
HEX7[4] PIN_L7 Seven Segment Digit 7[4]
HEX7[5] PIN_P9 Seven Segment Digit 7[5]
HEX7[6] PIN_N9 Seven Segment Digit 7[6]
Table 4: Pin assignments for the 7-segment displays

5. CLOCK INPUTS

The DE2 board includes two oscillators that produce 27 MHz and 50 MHz
clock signals. The board also includes an SMA connector which can be used to
connect an external clock source to the board. The pin assignments appear in
Table 5.
Signal Name FPGA Pin No. Description
CLOCK_27 PIN_D13 27 MHz clock input
CLOCK_50 PIN_N2 50 MHz clock input
EXT_CLOCK PIN_P26 External (SMA) clock input
Table 5: Pin assignments for the clock

7
8
 LABORATORY EXPERIMENT 1
DIGITAL LOGIC GATES
VCC
5V

1A VCC
1B 4A
1Y 4B
2A 4Y
2B 3A
2Y 3B
GND 3Y

74LS00N
1Y VCC
1A 4Y
1B 4B
2Y 4A
2A 3Y
2B 3B
GND 3A

74LS02N
1A VCC
1Y 6A
2A 6Y
2Y 5A
3A 5Y
3Y 4A
GND 4Y

74LS04N
1A VCC
1B 4B
1Y 4A
2A 4Y
2B 3B
2Y 3A
GND 3Y

74LS08N
1A VCC
1B 4B
1Y 4A
2A 4Y
2B 3B
2Y 3A
GND 3Y

74LS32N
1A VCC
1B 4B
1Y 4A
2A 4Y
2B 3B
2Y 3A
GND 3Y

74LS86N

LEARNING OBJECTIVES:
 Identify various ICs, connection diagrams, and their specifications.
 To study and verify the truth table of logic gates.
 To demonstrate NAND gates as a universal gate.
 To implement a Boolean function using NAND gates.

9
BASIC CONCEPTS:
The basic logic gates are the building blocks of more complex logic circuits.
These logic gates perform the basic Boolean functions, such as AND, OR, NAND, NOR,
Inversion, Exclusive-OR, Exclusive-NOR. Figure 1 shows the pin assignment to the
various logic gates. It is seen from the Figure 1 that each gate has one or two binary
inputs. The small circle on the output of the circuit symbols designates the logic
complement. The AND, OR, NAND, and NOR gates can be extended to have more
than two inputs.
Digital circuits are frequently constructed with NAND or NOR gates rather than
with AND and OR gates. NAND and NOR gates are easier to fabricate with electronic
components and are the basic gates used in all IC digital logic families. Because of the
prominence of NAND and NOR gates in the design of digital circuits, rules and
procedures have been developed for the conversion from Boolean functions given in
terms of AND, OR, and NOT into equivalent NAND and NOR logic diagrams.

EQUIPMENT AND MATERIALS:

 Digital Logic Board
 2 IC 7400, IC 7402, IC 7404, IC 7408, IC 7432, IC 7486

PROCEDURES:
1. Check the ICs for their working by inserting the IC into the breadboard.
2. The pin assignments to the various gates are shown in Figure 1.

2-input OR gate 2-input AND gate

7432 7408

Inverters 2-input NAND gate

7404 7400

10
 2-input XOR gate 2-input NOR gate
7486 7402

Figure 1: Digital gates in IC packages with identification numbers

and pin assignments

3. Provide the input data in the input switches, SW0 and SW7, and observe the
output on the LED0. Complete the table below.
No. IC Number SYMBOL INPUTS OUTPUT
3.1 SW0 SW7 LED0
AND IC SW0
0 0
7408 LED0 0 1
SW7
1 0
1 1
3.2 SW0
0 0
OR IC 0 1
LED0
7432 SW7
1 0
1 1
3.3
NOT/INVERTER SW0 0 -
LED0
7404
1 -
3.4 SW0
0 0
NAND IC 0 1
LED0
7400 SW7
1 0
1 1
3.5 SW0
0 0
NOR IC 0 1
LED0
7402 1 0
SW7
1 1
3.6 SW0
0 0
EX-OR IC 0 1
7486 LED0
SW7
1 0
1 1
Table 1

11
4. Universal NAND Gate
Using 7400 IC, connect a circuit that produces
a. an inverter.
b. a two-input AND.
c. a two-input OR.
d. a two-input NOR.
e. a two-input XOR.
In each case, verify your circuit by checking its truth table in Procedure 3.
5. Construct a circuit using 7400 IC that implements the Boolean function:

a. Draw the circuit diagram.

b. Obtain the truth table for F as a function of the four inputs.
c. Connect the circuit and verify the truth table.

12
 LABORATORY EXPERIMENT 2
SIMPLIFICATION OF BOOLEAN FUNCTIONS

VCC
5V
LED0

1A VCC 1A VCC
1B 4A 1B 1C
1Y 4B 2A 1Y
2A 4Y 2B 3C
2B 3A 2C 3B
2Y 3B 2Y 3A
GND 3Y GND 3Y

74LS00N 74LS10N

VCC
5V LED0

1A VCC
1B 4A
1Y 4B
2A 4Y
2B 3A
2Y 3B
GND 3Y

74LS00N

LEARNING OBJECTIVES:
 To simplify the Boolean expression and to implement the logic circuit.
 Given a truth table to derive the Boolean expressions and build the logic circuit.

BASIC CONCEPTS:
Gate-level minimization refers to the design task of finding an optimal gate-level
implementation of the Boolean functions describing a digital circuit. The complexity of
the digital logic gates that implement a Boolean function is directly related to the
complexity of the algebraic expression from which the function is implemented.
Although the truth table representation of a function is unique, when it is expressed
algebraically it can appear in many different, but equivalent, forms. Boolean expressions
may be simplified by algebraic means. However, this procedure of minimization is
awkward because it lacks specific rules to predict each succeeding step in the
manipulative process.
A Karnaugh map (K-map) is a straightforward procedure for minimizing Boolean
functions. A K-map is a diagram made up of squares, with each square representing
one minterm of the function that is to be minimized. The simplified expressions

13
produced by the map are always in one of the two standard forms: sum of products or
product of sums.

EQUIPMENT AND MATERIALS:

 Digital Logic Board
 2 IC 7400, IC 7404, IC 7410

PROCEDURES:

LOGIC DIAGRAM
1. This part of the experiment starts with a given logic diagram from which we
proceed to apply simplification procedures to reduce the number of gates and,
possibly, the number of ICs. The logic diagram shown below requires two ICs – a
7400 and 7410. Note that the inverters for inputs x, y, and z are obtained from
the remaining three gates in the 7400 IC. If the inverters were taken from 7404
IC, the circuit would have required three ICs.

Figure 1

2. Connect the circuit in Figure 1 with the x, y, and z inputs going to three switches
(SW0, SW1 and SW2) and the output F to a LED0 indicator. Test the circuit and
complete the truth table below.

x y z F
0 0 0
0 0 1
0 1 0
0 1 1
1 0 0
1 0 1
1 1 0
1 1 1
Table 1

14
 3. Obtain the Boolean function of the circuit and simplify it, using map method.
Construct the simplified circuit using NAND gates. Test the circuit by connecting
the inputs to the switches and output to LED0. Show that the eight possible input
combinations of the circuits have identical outputs. This will prove that the
simplified circuit behaves exactly like the original circuit.

BOOLEAN FUNCTIONS
4. Consider two Boolean functions in sum-of-minterms form:
( ) ( )
( ) ( )
Simplify these functions by means of maps. Obtain a composite logic diagram
with four inputs, A, B, C and D connected to SW0, SW1, SW2 and SW3
respectively, and two outputs, F1 and F2 connected to LED0 and LED1.
Implement the two functions together, using a minimum number of NAND ICs.
Do not duplicate the same gate if the corresponding term is needed for both
functions. Use any extra gates in existing ICs for inverters if possible. Connect
the circuit and check its operation. The truth table for F 1 and F2 obtained from the
circuit should conform to the minterms listed.

COMPLEMENT
5. Plot the following Boolean function in a map:

Combine the 1‟s in the map to obtain the simplified function for F in sum-of-
products form then combine the 0‟s in the map to obtain the simplified function F‟,
also in sum-of-products form. Implement both F and F‟ with NAND gates and
connect the two circuits to the same input switches, but to separate output LED
displays. Obtain the truth table of each circuit and show that they are
complements of each other.

15
 LABORATORY EXPERIMENT 3
ADDERS AND SUBTRACTORS

VCC
5V SUM

1A VCC
1B 4B
1Y 4A
2A 4Y
2B 3B
2Y 3A
GND 3Y

74LS86N

CARRY
1A VCC
1B 4B
1Y 4A
2A 4Y
2B 3B
2Y 3A
GND 3Y

74LS08N

VCC
5V DIFFERENCE

1A VCC
1B 4B
1Y 4A
2A 4Y
2B 3B
2Y 3A
GND 3Y

74LS86N

BORROW
1A VCC
1Y 6A
2A 6Y 1A VCC
2Y 5A 1B 4B
3A 5Y 1Y 4A
3Y 4A 2A 4Y
GND 4Y 2B 3B
2Y 3A
74LS04N GND 3Y

74LS08N

LEARNING OBJECTIVES:
 To realize the adders and subtractors circuits using basic gates.
 To learn about IC 7483 and its internal structure.

BASIC CONCEPTS:

Half Adder: A combinational logic circuit that performs the addition of two data
bits, A and B, is called a half-adder. Addition will result in two output bits; one of
which is the sum bit, S, and the other is the carry bit, C.

16
 Half Subtractor: Subtracting a single-bit binary value B from another A (i.e. A -
B) produces a difference bit D and a borrow bit Bo. This operation is called half
subtraction and the circuit to realize it is called a half-subtractor.

Full Adder: The half-adder does not take the carry bit from its previous stage
into account. This carry bit from its previous stage is called carry-in bit. A
combinational logic circuit that adds two data bits, A and B, and a carry-in bit,
Cin, is called a full-adder.

Full Subtractor: Subtraction of three bits, A (minuend) and B (subtrahend) and

C (Subtrahend), produces two outputs D (difference) and Bo (borrow).

Four-bit Parallel Adder: The Full adder can add single-digit binary numbers and
carries. The largest sum that can be obtained using a full adder is 11 2. Parallel
adders can add multiple-digit numbers. If full adders are placed in parallel, we
can add two- or four-digit numbers or any other size desired. Figure below uses
STANDARD SYMBOLS to show a parallel adder capable of adding two four-digit
binary numbers. The addend would be on A inputs, and the augend on the B
inputs. For this explanation we will assume there is no input to C in (carry from a
previous circuit)

EQUIPMENT AND MATERIALS:

 Digital Logic Board
 IC 7400, IC 7404, IC 7410, IC 7432, IC 7483

PROCEDURES:

HALF ADDER

1. Construct and test a half-adder circuit shown in Figure 1 using one XOR gate AND
gate. Connect the inputs A and B to SW1 and SW0 respectively, the sum and carry
to LED0 and LED1 respectively. Complete the table 1 to determine the status of

17
 the LED0 and LED1, with the possible combinations of the switches, if they are ON
or OFF.
INPUTS OUTPUTS
SW0 SW1 Sum Carry
(LED0) (LED1)
0 0
0 1
1 0
1 1

Table 1

A
Sum
B
7486N
Carry

7408N
Figure 1

Write the output Boolean equation for the Sum and Carry. _________
_________

FULL ADDER
2. Construct and test a full-adder circuit shown in Figure 2. Connect the inputs A, B,
CIN to SW0, SW1 and SW2 respectively, the sum and carry to LED0 and LED1
respectively. Complete the table 2 to determine the status of the LED0 and
LED1, with the possible combinations of the switches, if they are ON or OFF.

INPUTS OUTPUTS
SW0 SW1 SW2 Sum Carry
(A) (B) (Cin) (LED0) (LED1)
0 0 0
0 0 1
0 1 0
0 1 1
1 0 0
1 0 1
1 1 0
1 1 1
Table 2

18
 A

B Sum

74LS86N
74LS86N
Cin

74LS08N
74LS32N Carry
74LS08N
74LS32N

74LS08N
Figure 2

Write the output Boolean equation for the Sum and Carry. _________
_________

HALF SUBTRACTOR
3. Construct and test a half-subtractor circuit shown in Figure 3. Connect the inputs
A and B to SW0 and SW1 respectively, the Difference(D) and Borrow(Bo) to
LED0 and LED1 respectively. Complete the table 3 to determine the status of the
LED0 and LED1, with the possible combinations of the switches, if they are ON
or OFF.

INPUTS OUTPUTS
SW0 SW1 D Bo
(A) (B) (LED0) (LED1)
0 0
0 1
1 0
1 1

Table 3
A
Difference
B
74LS86N

Borrow

74LS04N 74LS08N

Figure 3

Write the output Boolean equation for the Difference and Borrow. _________
_________

19
FULL SUBTRACTOR
4. Construct and test a full-subtractor circuit shown in figure 4. Connect the inputs
A, B, C to SW0, SW1 and SW2 respectively, the difference and borrow to LED0
and LED1 respectively. Complete the table 4 to determine the status of the LED0
and LED1, with the possible combinations of the switches, if they are ON or OFF.

INPUTS OUTPUTS
SW1 SW2 SW3 D Bo
(A) (B) (C) (LED0) (LED1)
0 0 0
0 0 1
0 1 0
0 1 1
1 0 0
1 0 1
1 1 0
1 1 1

Table 4

A
74LS86N
B Difference

C
74LS86N

74LS04N 74LS08N

74LS32N

74LS08N
Borrow

74LS32N
74LS08N
Figure 4

Write the output Boolean equation for the Difference and Borrow. _________
_________

PARALLEL ADDER
5. IC type 7483 is a four-bit binary parallel adder. The pin assignment is shown in
figure 5. The 2 four bit input binary numbers are A1 through A4 and B1 through
B4. The four bit sum is obtained from S1 through S4. C0 is the input carry and
C4 the output carry.

20
Test the four-bit binary adder 7483 by connecting the power supply and
ground terminals. Then connect the four inputs A to (SW0, SW1, SW2 and SW3)
and B inputs (SW4, SW5, SW6, SW7). The five outputs are applied to LEDs.
Perform the addition of a few binary numbers and check that the output sum
and output carry give the proper values. Show that when the input carry is equal
to 1, it adds 1 to the output sum.

Figure 5

21
 LABORATORY EXPERIMENT 4
DECODERS and ENCODERS

VCC
5V

CA
J1 16
VCC
7 A OA 13
1 B OB 12
2 C OC 11
6 D OD 10
OE 9
3 ~LT OF 15
5 14 ABCDEFGHABCDEFGH
~RBI OG
4 ~BI/RBO
8 GND

74LS47N

VCC 16
7 A OA 13
1 B OB 12
2 C OC 11
6 D OD 10
OE 9
3 ~LT OF 15
5 ~RBI OG 14
4 ~BI/RBO
8 GND

74LS47N

VCC
5V
LED2 LED1 LED0

10 D0 VCC 16
11 D1 A0 9
12 D2 A1 7
13 D3 A2 6
1 D4
2 D5 GS 14
3 D6 EO 15
4 D7
5 EI
8 GND

74LS148N

LEARNING OBJECTIVES:
 To realize a decoder circuit using basic gates
 To design a 2x4 decoder using basic gates.
 To verify IC 74LS138 and IC 74LS139.
 To use 7447 IC for BCD to decimal conversion

22
  To learn and understand the working IC 74147, IC 74148 and IC 74157.
 To learn to do code conversion using encoders

BASIC CONCEPTS
A decoder is a combinational circuit that connects the binary information
from „n‟ input lines to a maximum of 2 n unique output lines. Decoder is also called
a minterm generator or maxterm generator. A minterm generator is constructed
using AND and INVERTER gates. The output is indicated by logic 1. A maxterm
generator is constructed using NAND gates. The output is indicated by a logic 0.
The name decoder is also used in conjunction with other code converters, such
as BCD-to-seven-segment decoder.

The light emitting diode (LED) finds its place in many applications in these
modern electronics fields. One of them is the Seven Segment Display. Seven
segment displays contains the arrangement of the LEDs in eight passion and a
dot(.) with a common electrode (Anode or Cathode). The purpose of arranging it
in the passion is that we can make any number out of that by switching ON and
OFF the particular LEDs. Figure 1 is the block diagram of the Seven Segment
LED arrangement.

Figure 1

An encoder is a digital circuit that performs the inverse operation of a

decoder. An encoder has 2n (or fewer) input lines and n output lines. The output
lines, as an aggregate, generate the binary code corresponding to the input
value. An example of an encoder is the octal-to-binary encoder. It has eight
inputs (one for each of the octal digits) and three outputs that generate the
corresponding binary number. It is assumed that only one input has a value of 1
at any given time.

EQUIPMENT AND MATERIALS:

 Digital Logic Board
 IC 7404, IC 7408, IC 74139, IC 74138, IC 74147, IC 74148 and IC 74157

23
PROCEDURES:

I. DECODERS

1. 2x4 DECODER using logic gates

a. Set-up the circuit as shown in Figure 1. In this circuit A and B are

connected to SW0 and SW1 respectively. I0, I1, I2, I3 are the decoded
outputs. Connect the outputs to LED0, LED1, LED2 and LED3
respectively. For this circuit vary the inputs (all possible combinations of
inputs) and note the corresponding outputs. Complete the table 1 below.
A B
Inputs Outputs
A B I0 I1 I2 I3
0 0
74LS04N 74LS04N
0 1
1 0 I0
1 1
74LS08N
I1
Table 1
74LS08N
I2

74LS08N
I3

74LS08N

Figure 1

b. Replace the IC 7408 to IC 7400 in Procedure 1.a. For this circuit vary the
inputs (all possible combinations of inputs) and note the corresponding
outputs. Complete the table 2 below.
A B
Inputs Outputs
A B I0 I1 I2 I3
0 0 7404N 7404N
0 1
1 0
I0
1 1
7400N
I1
Table 2
7400N
I2

7400N
I3

7400N
Figure 2

24
 Compare the truth table in procedure 1.a and procedure 1.b.
________________________________________________________________
________________________________________________________________
________________________________________________________________

2. 2x4 decoder using 74LS139

The IC 74139 accepts two binary inputs and when enable provides 4
individual active low outputs. The device has 2 enable inputs (two active low).
Study the IC type 74LS139 shown in figure 2. Test the 2x4 decoder by
connecting the power supply and ground terminals. Then connect the two inputs
1A and 1B to (SW0, SW1 respectively) and 1Y0, 1Y1, 1Y2, 1Y3 outputs to LED0,
LED1, LED2, and LED3 indicators respectively. Make sure that ~1G is connected
to ground Complete the table 3.

~1G VCC
Inputs Outputs 1A ~2G
1A 1B IY0 IY1 IY2 IY3 1B 2A
0 0 1Y0 2B
0 1 1Y1 2Y0
1 0 1Y2 2Y1
1Y3 2Y2
1 1
GND 2Y3
Table 3
74LS139N
Figure 3

3. 3x8 Decoder
Study the IC type 74LS138 shown in figure 4. Test the 3x8 decoder by
connecting the power supply, ground terminals and implementing a full adder.
Inputs A, B and C are connected to SW0, SW1 and SW2 respectively. Connect
G1 to SW3 and set to „1‟. ~G2A and ~G2B serve as an enable and they are
connected to ground.

1 A VCC 16
2 B Y0 15
3 C Y1 14
Y2 13
6 G1 Y3 12
4 ~G2A Y4 11
5 ~G2B Y5 10
Y6 9
8 GND Y7 7

74LS138N
Figure 4

25
4. BCD to Seven Segment Decoder

Use the dual seven segment display in the training module to complete
the column in Decimal Number Display. The IC 7447 in Figure 6 takes the Binary
Coded Decimal (BCD) as the input and outputs the relevant 7 segment code.
Test the dual 7-segment in the board by connecting the power supply and ground
terminals. Connect the D, C, B, A to switches SW0, SW1, SW2 and SW3.
Complete the table 4 below and observe the outputs. Make sure that the Gnd
and Vcc is connected.

VCC 16
7 A OA 13
1 B OB 12
2 C OC 11
6 D OD 10
OE 9
3 ~LT OF 15
5 ~RBI OG 14
4 ~BI/RBO
8 GND

74LS47N
Figure 5

BCD Inputs Output Logic Levels from IC Decimal

7447 to 7-segments Number
Display
D C B A a b c d e f g
0 0 0 0 0 0 0 0 0 0 1
0 0 0 1 1 0 0 1 1 1 1
0 0 1 0 0 0 1 0 0 1 0
0 0 1 1 0 0 0 0 1 1 0
0 1 0 0 1 0 0 1 1 0 0
0 1 0 1 0 1 0 0 1 0 0
0 1 1 0 1 1 0 0 0 0 0
0 1 1 1 0 0 0 1 1 1 1
1 0 0 0 0 0 0 0 0 0 0
1 0 0 1 0 0 0 1 1 0 0

Table 4

26
 II. ENCODERS

1. DECIMAL-TO BCD ENCODER USING IC 74147

Construct and test a decimal-to BCD encoder using IC 74147 shown in Figure 7.
Connect the output lines D, C, B, A to LED0, LED1, LED2 and LED3 respectively. I1, I2,
I3, I4, I5, I6, I7 and I8 are connected to the input switches SW0, SW1, SW2, SW3,
SW4, SW5,SW6 AND SW7 respectively. Complete the truth table shown in Table 5.

INPUTS OUTPUTS
I1 I2 I3 I4 I5 I6 I7 I8 I9 D C B A
1 1 1 1 1 1 1 1 0
X X X X X X X 0 1
X X X X X X 0 1 1
X X X X X 0 1 1 1
X X X X 0 1 1 1 1
X X X 0 1 1 1 1 1
X X 0 1 1 1 1 1 1
X 0 1 1 1 1 1 1 1
0 1 1 1 1 1 1 1 1
1 1 1 1 1 1 1 1 1
Table 5

11 1 A 9
12 2 B 7
13 3 C 6
1 4 D 14
2 5
3 6
4 7
5 8
10 9

74LS147N
Figure 6

27
 LABORATORY EXPERIMENT 5
MULTIPLEXERS AND DEMULTIPLEXERS

VCC
5V Sum Carry

VCC 16
6 1C0 1Y 7
5 1C1
4 1C2
3 1C3
10 2C0 2Y 9
11 2C1
12 2C2
13 2C3
14 A
2 B VCC
1A VCC
1Y 6A 1 ~1G
2A 6Y 15 ~2G 5V
2Y 5A 8 GND
3A 5Y
3Y 4A 74LS153N
GND 4Y

74LS04N
~1G VCC
1A ~2G
1B 2A
1Y0 2B
1Y1 2Y0
1Y2 2Y1
1Y3 2Y2
GND 2Y3

74LS139N

LEARNING OBJECTIVES:
 To design and set up a 4-1 Multiplexer (MUX) using only NAND gates.
 To design and set up a 1-4 Demultiplexer(DE-MUX) using only NAND gates.
 To verify the various functions of IC 74153(MUX) and IC 74139(DEMUX).
 To set up a Half Adder and Half Subtractor using IC 74153.

BASIC CONCEPTS
Multiplexers are very useful components in digital systems. They transfer
a large number of information units over a smaller number of channels, (usually
one channel) under the control of selection signals. Multiplexer means many to
one. A multiplexer is a circuit with many inputs but only one output. By using
control signals (select lines) we can select any input to the output. Multiplexer is
also called as data selector because the output bit depends on the input data bit
that is selected. The general multiplexer circuit has 2 n input signals, n
control/select signals and 1 output signal.

28
 INPUTS 4-1
4:1 MUX Y = E’S1’S0’I0 + E’S1’S0I1 + E’S1S0’I2 +
MUX E’S1S0I3
ENABLE
(E’)

SELECT
INPUTS

Figure 1: Block Diagram of a 4 to 1 Multiplexer

De-multiplexers perform the opposite function of multiplexers. They transfer a

small number of information units (usually one unit) over a larger number of channels
under the control of selection signals. The general de-multiplexer circuit has 1 input
signal, n control/select signals and 2n output signals. De-multiplexer circuit can also be
realized using a decoder
circuit with enable.

EQUIPMENT AND MATERIALS:

 Digital Logic Board
 IC 7400, IC 7404, IC 7410, 3 IC 7420, IC 74139, IC 74153

PROCEDURES:

I. MULTILPLEXER

1. 4 to 1 MULTIPLEXER

a. Construct and test a 4-to-1 Multiplexer circuit shown in Figure 2 using

NAND gates. Connect the select lines S1, S0 to SW2, SW1 respectively.
Connect the Enable input (En) to SW0. I0, I1, I2, and I3 are connected to
SW3, SW4, SW5, and SW6 and output Y is connected to LED0. Complete
truth table in Table 1.

29
 S1 S0 En

74LS00N 74LS00N 74LS00N

I0
74LS20N

I1
Y
74LS20N

74LS20N
I2
74LS20N

I3
74LS20N

Figure 2: 4-to-1 Multiplexer using NAND gates

Select Enable Inputs Output

Inputs Input
S1 S0 E I0 I1 I2 I3 Y
x x 1 X x x x
0 0 0 0 x x x
0 0 0 1 x x x
0 1 0 X 0 x x
0 1 0 X 1 x x
1 0 0 X x 0 x
1 0 0 X x 1 x
1 1 0 X x x 0
1 1 0 X x x 1
Table 1

b. IC type 74153 is a Dual 4-Input Multiplexer with common select inputs and
individual enable inputs for each section. It can select two bits of data from
four sources. The pin assignment is shown in Figure 3.

Test the Dual 4-Input Multiplexer by connecting the power supply and
ground terminals. Then connect the four inputs 1C0, 1C1, 1C2 and IC3 to
SW0, SW1, SW2 and SW3 respectively. A and B are the select lines
connected to SW6 and SW7 respectively, and ~1G as the enable input
connected to the input switch SW5. The output 1Y is applied to LED.
Verify your answers in Table 1.

30
 VCC 16
6 1C0 1Y 7
5 1C1
4 1C2
3 1C3
10 2C0 2Y 9
11 2C1
12 2C2
13 2C3
14 A
2 B
1 ~1G
15 ~2G
8 GND

74LS153N
Figure 3: IC 74153

c. HALF ADDER USING MUX

Connect the half-adder circuit using Multiplexer and test it for
proper operation. Show that figure 4 is a half adder using a multiplexer.
Connect the A and B to SW0 and SW1. The sum and carry are also
connected to the output LEDs, LED0 and LED1.

5V
VCC 16
A 6 1C0 1Y 7 Sum
5 1C1
4 1C2
3 1C3
10 2C0 2Y 9 Carry
11 2C1
12 2C2
13 2C3
B
14 A
2 B
1 ~1G
15 ~2G
8 GND

74LS153N

Figure 4: Half Adder using MUX

d. HALF-SUBTRACTOR USING MUX

Connect the half-subtractor circuit using Multiplexer and test it for
proper operation. Show that figure 5 is a half subtractor using a
multiplexer. Connect the A and B to SW0 and SW1. The output difference
and borrow are also connected to the output LEDs, LED0 and LED1

5V
A VCC 16
6 1C0 1Y 7 Difference
5 1C1
4 1C2
3 1C3
10 2C0 2Y 9 Borrow
11 2C1
12 2C2
13 2C3
B
14 A
2 B
1 ~1G
15 ~2G
8 GND

74LS153N

Figure 5: Half Subtractor using MUX

31
II. DEMULTIPLEXER

1. 1-to-4 DEMULTIPLEXER

a. Construct and test a 1-to-4 demultiplexer circuit shown in Figure 6 using

NAND gates. Connect the select lines S1, S2 to SW1, SW2 respectively.
Connect the Enable input to SW0 and data input to SW7. Y0, Y1, Y2, and
Y3 outputs are connected to LED0, LED1, LED2 and LED3 respectively.
Complete the truth table in table 2.
S1 S0 Enable_Input Data_Input

74LS00N 74LS00N 74LS00N

Y0

74LS00N
74LS20N
Y1

74LS00N
74LS20N

Y2

74LS00N
74LS20N

Y3

74LS00N
74LS20N

Figure 6: 1-to-4 Demultiplexer using NAND gates

Enable Data Select Inputs Outputs

Inputs Input
E D S1 S0 Y3 Y2 Y1 Y0
1 0 X X
0 1 0 0
0 1 0 1
0 1 1 0
0 1 1 1
Table 2

b. IC type 74139 is a Dual 4-Input Multiplexer with common select inputs and
individual enable inputs for each section. It can select two bits of data from
four sources. The pin assignment is shown in Figure 7. Make sure that
Vcc and Gnd of the IC is connected. 1Y0, 1Y1, 1Y2, 1Y3 are connected to
LED0, LED1, LED2 and LED3 respectively. Attach the enable input, ~1G,
to SW0. Verify your answer in Table 2.

32
 ~1G VCC
1A ~2G
1B 2A
1Y0 2B
1Y1 2Y0
1Y2 2Y1
1Y3 2Y2
GND 2Y3

74LS139N
Figure7: 74139

33
 LABORATORY EXPERIMENT 6
FLIP-FLOPS AND COUNTERS

VCC
A

555_timer U1 U2
1 1CLK 1K 16 1 1CLK 1K 16
2 ~1PR 1Q 15 2 ~1PR 1Q 15
3 ~1CLR ~1Q 14 3 ~1CLR ~1Q 14
4 1J GND 13 4 1J GND 13
5 VCC 2K 12 5 VCC 2K 12
6 2CLK 2Q 11 6 2CLK 2Q 11
7 ~2PR ~2Q 10 7 ~2PR ~2Q 10
8 ~2CLR 2J 9 8 ~2CLR 2J 9

74LS76N 74LS76N

LEARNING OBJECTIVES:
 Characteristic table verification of
- RS flip-flop
- T flip-flop
- D flip-flop
- JK flip-flop
 To learn about various flip-flops
 Conversion of one type of flip-flop to another
 To test a 4-bit binary synchronous counter using flip-flop IC 7476.

BASIC CONCEPTS:
Logic circuits that incorporate memory cells are called sequential logic circuits;
their output depends not only upon the present value of the input but also upon the
previous values. Sequential logic circuits often require a timing generator (a clock) for
their operation. The latch (flip-flop) is a basic bi-stable memory element widely used in
sequential logic circuits. Usually there are two outputs, Q and its complementary value,
~Q.

34
 An S-R latch consists of two cross-coupled NOR gates. An S-R flip-flop can also
be design using cross-coupled NAND gates.
A clocked S-R flip-flop has an additional clock input so that the S and R inputs
are active only when the clock is high. When the clock goes low, the state of flip-flop is
latched and cannot change until the clock goes high again. Therefore, the clocked S-R
flip-flop is also called “enabled” S-R flip-flop.
A D latch combines the S and R inputs of an S-R latch into one input by adding
an inverter. When the clock is high, the output follows the D input, and when the clock
goes low, the state is latched.
A S-R flip-flop can be converted to T-flip flop by connecting S input to Q‟ and R to
Q.
The J-K flip-flop can be compared to the bistable flip-flop and the triggered
bistable flip-flop combined. Refer to the logic diagram symbol of the JK flip-flop shown in
Figure 1. The clear and preset inputs correspond to the reset and set inputs of the
bistable flip-flop. The J, K and clock inputs correspond to the set, reset and trigger
inputs of a triggered bistable flip-flop. The Q and Q‟are inverse outputs that correspond
to set and reset. Thus, the JK flip-flop the clear and preset inputs are normally used to
reset it or preset it to an initial condition before or after a particular operation. The J, K
and clock inputs then are used during the operation to trigger the flip-flop as required.
The small circles on the clear, clock and preset inputs mean that these input signals
must go to a low level (logic 1 to logic 0 for positive logic) to cause the flip-flop to set or
reset. The absence of the small circles on the J and K inputs means that these input
signals must be at high level (logic 1) before the flip-flop can be triggered to either state
by the clock pulse. A low level signal applied to either of these inputs prevents triggering
to that state. It should be pointed out that when any input is disconnected or unused, the
flip-flop assumes a high level input and operates accordingly. The J-K flip-flop is one of
the most commonly used flip-flops in digital electronics. Because of its basic operation
and versatility it can be used in digital counters, registers, encoders, decoders, or simply
as a slip-flop.
~1PR

1J 1Q

1CLK
1K ~1Q

~1CLR

Figure 1: J-K flip-flop

EQUIPMENT AND MATERIALS:

 Digital Logic Board
 IC 7400, IC 7402, and 2 IC 7476

35
PROCEDURES:

I. SR flip-flop
a. Examine the circuits shown in Figure 1, Figure 2 and Figure 3. Switches SW0
and SW1 are used to apply logic levels to S and R flip-flop input. Connect the
circuit and complete the characteristic tables of the circuits shown below. The
output Q and ~Q are connected to LED0 and LED1 respectively. Use the out of
the 555 timer to serve as the Clk in Figure 3.

Figure 1: Cross-coupled
NOR gates
R
Q S R Q Q’ Remarks
1 0
7402N
0 0 After S=1, R=0
~Q 0 1
S
0 0 After S=0, R=1
7402N 1 1 forbidden

Figure 2: Cross-coupled
NAND gates
S S R Q Q’ Remarks
Q
1 0
7400N 1 1 After S=1, R=0
0 1
~Q
R 1 1 After S=0, R=1
7400N 0 0 forbidden

Figure 3: Cross-coupled NAND gates

with Clock
S
Q Clk S R Next state of Q
7400N
0 X X
Clk
7400N 1 0 0
~Q
1 0 1
R 1 1 0
7400N 1 1 1
7400N

36
II. CONVERSION OF JK-FLIP FLOP TO T-FLIP FLOP
The T (toggle) flip-flop is a complementing flip-flop and can be obtained
from a JK flip-flop when J and K are tied together. This is shown in Figure 4.
When T = 0 (J=K=0), a clock edge does not change the output. When T=1
(J=K=1), a clock edge complements the outputs. Connect the circuit shown in
Figure 4. Connect the Clk to SW0 and vary the input from 1 to 0 repeatedly and
observe the output (1Q and ~1Q) to LED0 and LED1. Show that if functions as a
Toggle flip-flop.

Figure 4: T FLIP FLOP USING IC 7476

VCC

2
~1PR
4 1J 1Q 15
Clk
1 1CLK
16 1K ~1Q 14

~1CLR
3 74LS76N

III. CONVERSION OF JK FLIP FLOP TO D-FLIP FLOP

This latch has only two inputs: D (data) and Clk (clock). Connect the figure
5 and complete the characteristic table of a D flip-flop. Connect the input D to
SW0 and Clk to SW1. Complete the table.

Figure 5: D FLIP FLOP USING IC 7476

VCC

2
~1PR Clk D Qt+1
D
4 1J 1Q 15 1 X
Clk 1 1CLK 0 0
16 14
1K ~1Q 0 1
7404N ~1CLR
3 74LS76N

IV. JK-FLIP FLOP USING IC 7476

The five inputs to a JK flip-flop are clear, preset, J, K and clock. Clear and
preset inputs are used to insure a defined flip-flop condition prior to a J, K or
clock signal to control the output. If J = K = 0 the clock produces no change in
output; if J = K =1 the output changes with each clock pulse. Connect the circuit
in Figure 6 and demonstrate the operation of a JK flip-flop and complete the
table.
37
 Figure 6: JK FLIP FLOP USING IC 7476
VCC

2
J J K Q Remarks
~1PR
4 1J 1Q 15 0 0
Clk 1 1CLK 0 1
16 1K ~1Q 14 1 0
K
~1CLR 1 1
3 74LS76N

V. FOUR BIT BINARY COUNTER

The four bit binary counter is one of the many circuits used to process and
control digital data. This circuit consists of four triggered flip-flops connected so as to
trigger each other in succession. By applying clock pulses to the first flip-flop and using
the set output of each trigger the next flip-flop, the set-reset states of the four flip-flops
will represent a binary count of 0 through 15. Connect the circuit shown in Figure 7 and
verify the functionality. The LEDs are used to read out the four bits of the binary count.
Use the 555 timer output to produce continuous clock pulses.

VCC
LED3 LED2 LED1 LED0
5V

~1PR ~1PR ~1PR ~1PR

555 1J 1Q 1J 1Q 1J 1Q 1J 1Q
1CLK 1CLK 1CLK 1CLK
1K ~1Q 1K ~1Q 1K ~1Q 1K ~1Q

~1CLR ~1CLR ~1CLR ~1CLR

Figure 7

VI. DECADE COUNTER

The decade counter is another of the many circuits used to process and
control digital data. This circuit is similar to the four bit binary counter except that
two of the flip-flops are gated to reset all flip-flops on the tenth count. Refer to
Figure 8. The decade counter operates as a straight binary counter for clock
pulses 1 through 9.

38
 Connect the circuit shown in Figure 8. The four flip-flops form the decade
counter. Output D, C, B and A are connected to the seven segment display to
read out in numerical value. Use the Clk(555) output to produce continuous clock
pulses.
D C B A
VCC
5V

~1PR ~1PR ~1PR ~1PR

555 1J 1Q 1J 1Q 1J 1Q 1J 1Q

1CLK 1CLK 1CLK 1CLK

1K ~1Q 1K ~1Q 1K ~1Q 1K ~1Q

~1CLR ~1CLR ~1CLR ~1CLR

Figure 8

39
40
 LABORATORY EXERCISE 1
TOOL FAMILIARIZATION
LEARNING OBJECTIVES
 To familiarize yourselves with Quartus II Web Editon 10.1
 To implement and test a combinational logic circuit in VHDL

EQUIPMENT AND MATERIALS

 Quartus II Web Edition 10.1
 ALTERA DE2 board

PROCEDURE:

I. Setting up a New Project

1. Start the Quartus II software. You should see a display similar to the one
in Figure 1. This display consists of several windows that provide access to all
features of Quartus II.

Figure 1: The main Quartus II display

Create a new project. To start working on a new design we

first have to define a new design project. Select File > New Project
Wizard and press Next to get the window shown in Figure 2. Set
the working directory to be tutorial1\designstyle1. The project must
have a name which may optionally be the same as the name of the
directory. We have chosen the name example_vhdl. Observe that
Quartus II automatically suggests that the name example_vhdl be

41
also the name of the top-level design entity in the project. Press
Next. Since we have not yet created the directory
tutorial1\designstyle1, Quartus II displays the pop-up box in Figure
3 asking if it should create the desired directory. Click Yes, which
leads to the window in Figure 4. In this window the designer can
specify which existing files (if any) should be included in the project.
We have no existing files, so click Next.

Figure 2: Specifying the project directory and name

Figure 3: Quartus II can create the desired directory

42
Figure 4: A window for inclusion of design files

In the window shown in Figure 5 we can specify the type of

device in which the designed circuit will be implemented. Choose
the device family called Cyclone II, which is a type of FPGA that is
to be used. Choose a specific device within the Cyclone II family,
so click on the Specific Device selected in „Available devices‟ list.
Choose the EP2C35F672C6 device and click finish

Figure 5: Selecting a Cyclone II device

43
II. Using the Text Editor
2. Quartus II provides a text editor that can be used for typing VHDL code.
Select File > New to get the window in Figure 6, choose VHDL File, and click
OK. This opens the Text Editor window. The first step is to specify a name for
the file that will be created. Select File > Save As to open pop-up box shown
in Figure 7. In the box labeled Save as type choose VHDL file. In the box
labeled File Name type example_vhdl. (Quartus II will add the filename
extension vhd, which must be used for all files that contain VHDL code.)
Leave the box checked at the bottom of the figure, which specifies Add file to
current project.

Figure 6: Choosing a type of design file

Figure 7: Opening a new VHDL file

44
 The VHDL code for this example is shown in Figure 8. Enter
this code into the Text Editor window. When creating a new project,
we chose the name example_vhdl for the top-level design entity.
Hence, the VHDL entity must match this name. Save the file, by
using File > Save or the shortcut Ctrl-s.

Figure 8: The VHDL code entered in the Text Editor

3. Synthesizing a circuit from a VHDL Code.

Select Processing | Start | Start Analysis and Synthesis (shortcut Ctrl-

k) so that the compiler will synthesize a circuit that implements the given
VHDL code. If the VHDL code has been typed correctly, the Compiler will
display a message that says that no errors were generated. A summary of the
compilation report will appear. See Figure 9.

Figure 9: The compilation summary

45
III. Simulating the Designed Circuit

4. Creating Waveforms for Simulation

Select Start > All Programs > Altera > University Program >
Simulation Tools > Altera U.P. Simulator. In the displayed
window select File > Open Project, which leads to the pop-up
window in Figure 10. Here, choose the Quartus II project that you
created. This is done by selecting the file example_vhdl.qpf as
shown in the figure. Note that the suffix .qpf stands for “quartus
project file".

Figure 10: The Qsim Window

Figure 11: Choosing the existing Quartus II project

46
 To create test vectors for your design, select the Qsim
command File > New Simulation Input File. This command opens
the Waveform Editor tool, shown in Figure 12, which allows you to
specify the desired input waveforms.

Figure 12: The Waveform Editor window

For our simple circuit, we can do a complete simulation by

applying all eight possible valuations of the input signals x1, x2 and
x3. The output f should then display the logic values defined by the
truth table for the majority function. We will run the simulation for
800 ns; so, select Edit > Set End Time in the Waveform Editor and
in the pop-up window that will appear specify the time of 800 ns,
and click OK. This will adjust the time scale in the window of Figure
10.

In the Waveform Editor window, select Edit > Insert > Insert
Node or Bus. In the pop-up window that appears, which is shown
in Figure 13, click on Node Finder.

The Node Finder window is presented in Figure 14. A filter is

used to identify the nodes of interest. In our circuit, we are only
interested in the nodes that appear on the pins (i.e. external
connections) of the FPGA chip. Hence, the filter setting should be
Pins: all. Click on List, which will display the nodes as indicated in
the figure. In a large circuit there could be many nodes displayed.
We need to select the nodes that we wish to observe in the
simulation. This is done by highlighting the desired nodes and
clicking on the > button. Select the nodes labeled x1, x2, x3, and f,
which will lead to the image in Figure 14. Click OK in this window

47
and also upon return to the window in Figure 13.This returns to the
Waveform Editor window, with the selected signals included as
presented in Figure 16.

Figure 13: The Insert Node or Bus Dialog

Figure 14: The node finder dialog

48
 Figure 15: The Selected signals

Figure 16: Signals in the Waveform Editor window

Observe that in Figure 16 all input signals are at logic level

0. The output, f is shown as undefined. Next, we have to draw the
input waveforms. Then, we will simulate the circuit, which will
produce the output waveform. To make it easier to draw the input
waveforms, the Waveform Editor displays dashed grid lines. The
spacing of the grid lines can be adjusted by selecting Edit > Grid
Size, and in the pop-up box in Figure 17 specifying the desired
size. The spacing of grid lines in Figure 16 is 10 ns. Another
convenience in drawing is to have transitions of a waveform snap

49
on grid lines. This feature is activated by clicking on the Snap to
Grid icon.

Figure 17: Specifying the grid spacing

Input waveforms can be drawn in different ways. The most

straightforward way is to indicate a specific time range and specify
the value of a signal. To illustrate this approach, click the mouse on
the x1 waveform near the 400-ns point and then drag the mouse to
the 800-ns point. The selected time interval will be highlighted in
blue, as depicted in Figure 18. Change the value of the waveform
to 1 by clicking on the Forcing High (1) icon , as illustrated in
Figure 19.

Figure 18: Selection of time interval

50
 Figure 19: Drawing waveform for x1

In creating the waveform for x1, we used the icon to

implement the logic value 1. Another possibility is to invert the value
of the signal in a selected time interval by using the Invert icon.
We will use this approach to create the waveform for x2, which
should change from 0 to 1 at 200 ns, then back to 0 at 400 ns, and
again to 1 at 600 ns. Select the interval from 200 to 400 ns and
click on the icon, as illustrated in Figure 20. Then do the same for
the interval from 600 to 800 ns.

Figure 20: Drawing the waveform for x2

We will use a third approach to draw the waveform for x3.

This signal should alternate between logic values 0 and 1 at each
100-ns interval. Such a regular pattern is indicative of a clock signal
that is used in many logic circuits. Even though there is no clock
signal in our example circuit, it is convenient to specify x3 in this

51
manner. Click on the x3 input, which selects the entire 800-ns
interval. Then, click on the Overwrite Clock icon , as indicated in
Figure 21. This leads to the pop-up window in Figure 22. Specify the
clock period of 200 ns and the duty cycle of 50%, and click OK. The result
is depicted in Figure 23.

Figure 21: Drawing the waveform for x3

Figure 22: Defining the clock characteristics

52
 Figure 23: The completed input waveforms

Save the waveform file using a suitable name; we chose the name
example_vhdl.vwf. Note that the suffix vwf stands for vector waveform
file.

5. Simulation
Return to the Qsim window (in Figure 10). Select Assign >
Simulation Settings. A pop-up window shown in Figure 24 will appear
and browse for the file example_vhdl.vwf. Choose Functional.

To enable the functional simulation to be performed, it is necessary

to generate a functional netlist of the circuit. This netlist specifies the logic
elements and the connections needed to implement the circuit. Select
Processing > Generate Functional Simulation Netlist, or click on the
icon .

Now, we can simulate the circuit. Select Processing > Start

Simulation, or click on the icon . A pop-up window will indicate

that “simulator was successful". Click OK. Another pop-up window will
state that “the file is read-only and cannot be edited". This states that the
output of the simulation is a file that you cannot alter. Any changes in

53
 simulation have to be done by modifying the example_vhdl.vwf file and
resimulating the circuit. Click OK. Qsim will now display the waveforms
produced in the simulation process, which are depicted in Figure 25.

Figure 25: The completed input waveforms

IV. Making Pin Assignments

To assign pins manually, it is first necessary to specify the chip to use.
This was already done when we selected the EP2C35F672C6 FPGA as
shown in Figure 5. Select Pin Assignments > Pin Planner to open the
display shown in Figure 9. To make the window look like the one in the figure
it may be necessary to enable or disable some of the settings under the View
menu. The settings are View > Show > Package Top, View > Show > Show
Fitter Placements, and View > All Pins List.

This tutorial will be implemented on the DE2 Development and Education

Board, which is an FPGA-based board available from Altera. The inputs to the
circuit x1, x2, and x3 will be assigned to slider switches SW0, SW1, and SW2.
These switches are connected to the FPGA pins N25, N26, and P25,
respectively. The output f, of our circuit will be connected to the green light
called LEDG0, which is connected to pin AE22.

The table in the bottom of Figure 26 lists the input and output ports of our
design project, and allows these ports to be assigned to specific pins. To
make the desired connection for input x1, double-click on its Location
column, as indicated in Figure 27, and choose pin N25 from the displayed list.
Repeat this procedure to complete all of the pin assignments, which leads to
the display in Figure 28.

54
 Recompile the project with pin assignments to cause pin assignments to
be applied. .

Figure 26: The Pin Planner display

Figure 27: Making a pin assignment

Figure 28: The completed pin assignment

55
V. Programming and Configuring the FPGA Device

Once the circuit has been compiled, it can be downloaded into the FPGA
chip on the DE2 board. The board supports a programming mode known as
JTAG programming. The configuration data is transferred from the host
computer (which runs the Quartus II software) to the board by means of a
cable that connects a USB port on the host computer to the corresponding
USB connector on the DE2 board. To use this connection, it is necessary to
have Altera‟s USB-Blaster software driver installed.
In the JTAG mode, the configuration data is loaded directly into the FPGA
device. The acronym JTAG stands for Joint Test Action Group.

6. JTAG Programming

Make sure that the RUN/PROG switch on the DE2 board is set to
the RUN position. Select Tools > Programmer to reach the window in Figure
29. If not already chosen in default, select JTAG in the Mode box. Also, if the
USB-Blaster is not chosen by default, press Hardware Setup button and
select the USB-Blaster in the window that pops-up as shown in Figure 30.
In the window in Figure 29 make sure that Program/Configure is
checked and then press Start. A blue LED on the board will light up when the
configuration data has been downloaded successfully.
Having downloaded the configuration data into the FPGA device,
you can now test the implemented circuit. Try all eight combinations of the
input variables x1, x2 and x3 by setting the corresponding states of the
switches SW0, SW1, and SW2.

Figure 29

56
Figure 30

57
 LABORATORY EXPERIMENT 2
ADDERS AND SUBTRACTORS

LEARNING OBJECTIVES:
 The purpose of this exercise is to learn to create connect simple input and output
devices to an FPGA chip and implement a circuit that performs binary addition
and subtraction that uses these devices.

EQUIPMENT AND MATERIALS:

 DE2 Board

PROCEDURES:

Part I

Figure 1a shows a circuit for a full adder, which has the inputs x, y, and cin, and
produces the output Sum and cout. Parts b and c of the figure show a circuit symbol and
truth table for the full adder. Write VHDL code that implements this circuit, as described
below.
Cin
Sum

Cout

(a) Circuit (b) Block Diagram

Cin X Y S Cout
0 0 0 0 0
0 0 1 1 0
0 1 0 1 0
0 1 1 0 1
1 0 0 1 0
1 0 1 0 1
1 1 0 0 1
1 1 1 1 1

(c) Truth Table

Figure 1: Full Adder

You are to write a VHDL code for a full-adder circuit.

1. Create a new Quartus II project for your circuit.
2. Create a VHDL code for the Figure 1 and include it in your project.

58
 3. Use switch SW0-2 on the DE2 board as the Cin, x, and y inputs. Connect the
output Sum to the green light LEDG7 and Cout to LEDR0.
4. Compile the project.
5. Download the compiled circuit into the FPGA chip. Test the functionality of the
full-adder by toggling the switches and observing the LEDs.

Part II

Figure 2a shows a circuit for a full subtractor, which has the inputs x, y, and z,
and produces the outputs Borrow(Bo) and Difference (D). Parts b and c of the figure
show a circuit symbol and truth table for the full subtractor. Write VHDL code that
implements this circuit, as described below.

X Y Z

Bo

(a) Circuit X Y Z D Bo
(b) Block Diagram 0 0 0 0 0
0 0 1 1 1
0 1 0 1 1
0 1 1 0 1
1 0 0 1 0
1 0 1 0 0
1 1 0 0 0
1 1 1 1 1

(c) Truth Table

Figure 2: Full Subtractor

You are to write a VHDL code for a full-adder circuit.

1. Create a new Quartus II project for your circuit.
2. Create a VHDL code for the Figure 2 and include it in your project.
3. Use switch SW0-2 on the DE2 board as the x, y, and z inputs. Connect the output
Difference (D) to the green light LEDG7 and Bo to LEDR0.

59
 4. Compile the project.
5. Download the compiled circuit into the FPGA chip. Test the functionality of the
full-adder by toggling the switches and observing the LEDs.
Part III

Figure 3 shows how four instances of full adder entity can be used to design a
circuit that adds two four-bit numbers. This type of circuit is usually called a ripple-carry
adder, because of the way that the carry signals are passed from one full adder to the
next. Write VHDL code that implements this circuit, as described below.

Figure 3: Four bit ripple carry adder

1. Create a new Quartus II project for your circuit.

2. Create a VHDL code for the Figure 3 and include it in your project.
3. Use switch SW7-0 on the DE2 board as the a3-0 and b3-0 inputs. Connect the
output s3-0 to the red light LEDR3-0 and cout to LEDR4.
4. Compile the project.
5. Download the compiled circuit into the FPGA chip. Test the functionality of the
full-adder by toggling the switches and observing the LEDs.

60
 LABORATORY EXPERIMENT 3
DECODERS and ENCODERS

LEARNING OBJECTIVES:
 The purpose of this exercise is to learn and verify the operation of decoders and
encoders. We would write the VHDL code for the circuits and download to the
FPGA chip and test for the functionality by toggling the switches at the DE2
board.

EQUIPMENT AND MATERIALS

 DE2 board

PROCEDURES:

Part I

A 2-to-4 decoder is given in Figure 1. The two data inputs are w1 and w0. They
represent a two-bit number that causes the decoder to assert one of the outputs y0,…y3.
A decoder can be designed to have either active high or active low outputs. Setting the
inputs w1w0 to 00, 01, 10, or 11 causes the y0, y1, y2, or y3 to be set to 1, respectively. A
graphical symbol for the decoder is given in part (b) of the figure, and a logic circuit is
shown in part (c).

En w1 w0 y0 y1 y2 y3
1 0 0 1 0 0 0
1 0 1 0 1 0 0
1 1 0 0 0 1 0
1 1 1 0 0 0 1
x X X 0 0 0 0
(a) Truth Table w0 (b) Symbol
w1

y0

y1

y2

y3

En

(c) Logic Circuit

Figure 1: A 2-to-4 Decoder

61
Create a new Quartus II project for your circuit.
1. Create a VHDL code for the Figure 1 and include it in your project.
2. Use switch SW16-17 on the DE2 board as the s1,s0 input respectively, and
switches SW3−0 for w1-0 respectively. Connect the output f to the green light
LEDG0.
3. Compile the project.
4. Download the compiled circuit into the FPGA chip. Test the functionality of the 4-
to-1 multiplexer by toggling the switches and observing the LEDs.

Part II

The DE2 Board has eight 7-segment displays. These displays are arranged into
two pairs and a group of four, with the intent of displaying numbers of various sizes.
Figure 2 shows a 7-segment decoder module that has the four-bit input c3c2c1c0.
This decoder produces seven outputs that are used to display a numeric on a 7-
segment display. The seven segments in the display are identified by the indices 0 to 6
shown in the figure. Each segment is illuminated by driving it to the logic value 0. You
are to write a VHDL code that represents BCD-to-7-segment decoder.

1. Create a new Quartus II project for your circuit.

2. Create a VHDL entity for the BCD to 7-segment decoder. Connect the c3c2c1c0
inputs to switches SW 17−14, and connect the outputs of the decoder to the HEX0
display on the DE2 board. The segments in this display are called HEX00,
HEX01. . . HEX06, corresponding to Figure 4.
3. After making the required DE2 board pin assignments, compile the project.
4. Download the compiled circuit into the FPGA chip. Test the functionality of the
circuit by toggling the SW 17-14 switches and observing the 7-segment display.

Figure 2: A BCD to 7-segment decoder

PART III

An encoder performs the opposite function of a decoder. A binary encoder

encodes information from 2n inputs into an n-bit code, as indicated in Figure 4. Exactly

62
one of the input signals should have a value of 1, and the outputs present the binary
number that identifies which input is equal to 1. The truth table for a 4-to2 encoder is
provided figure 4.a. Observe that the output y0 is 1 when either input w1 or w3 is 1, and
output y1 is 1 when input w2 or w3 is 1.

w3 w2 w1 w0 y1 y0
0 0 0 1 0 0
0 0 1 0 0 1
0 1 0 0 1 0
1 0 0 0 1 1
(a) Truth Table (b) Symbol

w0

w1 y0

w2
y1
w3

(c) Circuit

Figure 4: A 4-to2 binary encoder

63
 LABORATORY EXPERIMENT 4
MULTIPLEXERS AND DEMULTIPLEXERS

LEARNING OBJECTIVES:
 To learn and verify the operation of multiplexers and demultiplexers. We would
write the VHDL code for the circuits and download to the FPGA chip and test for
the functionality by toggling the switches at the DE2 board.

EQUIPMENT AND MATERIALS

 DE2 board

PROCEDURES:

Part I

Figure 1.a. depicts a multiplexer with four data inputs, w0, w1, w2, and w3 and two
select inputs, s1 and s0. As shown in the truth table in part (b) of the figure, the two-bit
number represented by s1s0 selects one of the data inputs as the output of the
multiplexer. You are to write a VHDL code for a 4-to-1 demultiplexer.

s1 s0 f
0 0 w0
0 1 w1
1 0 w2
1 1 w3
a. Symbol b. Truth Table

Figure 1: A 4-to-1 multiplexer

1. Create a new Quartus II project for your circuit.

2. Create a VHDL code for the 4-to-1 demultiplexer and include it in your project.
3. Use switch SW16-17 on the DE2 board as the s1 s0 input, and switches SW3−0 for
w3, w2, w1, wo respectively. Connect the output f to the green light LEDG7.
4. Compile the project.
5. Download the compiled circuit into the FPGA chip. Test the functionality of the 4-
to-1 multiplexer by toggling the switches and observing the LEDs.

64
Part II

A circuit that performs the opposite function of multiplexer is called demultiplexer.

The demultiplexer can be implemented using a decoder circuit with enable. In this case
the En input serves as the data input for the demultiplexer, and y0 to y3 outputs are the
data outputs. The valuation of w1w0 determines which outputs are set to the value of En.
You are to write a VHDL code for a 1-to-4 demultiplexer.

w1 w0 En y0 y1 y2 y3
0 0 X En 0 0 0
0 1 X 0 En 0 0
1 0 X 0 0 En 0
1 1 X 0 0 0 En
a. Symbol b. Truth Table

Figure 2: A 1-to-4 demultiplexer

1. Create a new Quartus II project for your circuit.

2. Create a VHDL code for the 1-to-4 demultiplexer and include it in your project.
3. Use switch SW17 on the DE2 board as the s input, and switches SW1−0 for w1, w0
respectively. Connect the output y0, y1, y2 and y3 to the green light LEDG0-3.
4. Compile the project.
5. Download the compiled circuit into the FPGA chip. Test the functionality of the 1-
to-4 multiplexer by toggling the switches and observing the LEDs.

65
 LABORATORY EXERCISE 5
FLIP-FLOPS

LEARNING OBJECTIVES:
 The purpose of this exercise is to learn and verify the operations of a flip-flop.

EQUIPMENT AND MATERIALS:

 DE2 Board

PART I
A D flip-flop has a single input, called D, and it stores the value of this input,
under the control of a clock signal. Figure 1.b shows the circuit for a gated D flip-flop. In
the gated D flip-flop, the output merely tracks the value of the input D while Clk = 1. As
soon as Clk goes to 0, the state of the latch is frozen until the next time the clock signal
goes to 1. Write a VHDL file that defines the D flip-flop circuit. Implement your circuit on
the DE2 board and test its functionality by operating the implemented switches.
D
Q

Clk D Q(t+1) Clk

0 x Q(t)
1 0 0 -Q
1 1 1
(a) Characteristic Table (b) Circuit

(c) Symbol

Figure 1: A D flip-flop

PART II

The JK flip-flop is the most versatile of the basic flip-flops. It has the input-
following character of the clocked D flip-flop but has two inputs, traditionally labeled J
and K. If J and K are different then the output Q takes the value of J at the next clock
edge. A JK flip-flop has two inputs J and K. If J and K are both low then no change
occurs. If J and K are both high at the clock edge then the output will toggle from one
state to the other. Write a VHDL file that defines the JK flip-flop circuit. Implement your

66
circuit on the DE2 board and test its functionality by operating the implemented
switches.

J K Q(t+1)
0 0 Q(t)
0 1 0
1 0 1
1 1 Q(t)

(a) Characteristic Table (b) Circuit

(c) Symbol

Figure 2: A JK flip-flop

PART III

The SR flip-flop is a circuit with two cross coupled NOR gates or two cross-
coupled NAND gates, and two inputs labeled S for set and R for reset. The SR latch
constructed with two cross-coupled NAND gate with clock input is shown in Figure 3.
The clock input (Clk) acts as an enable signal for other two inputs. The outputs of the
NAND gates stay at logic-1 level as long as the clock input remains at 0. When the
clock input goes to 1, information from the S or R input is allowed to affect the latch. The
set state is reached with S = 1, R = 0, and Clk = 1. To change this reset state, the inputs
must be S = 0, R = 1, and Clk = 1. Write a VHDL file that defines the SR flip-flop circuit.
Implement your circuit on the DE2 board and test its functionality by operating the
implemented switches.
Clk S R Next state of Q
0 x x No Change
1 0 0 No Change
1 0 1 Q = 0; reset state
1 1 0 Q = 1; set state
1 1 1 Indeterminate
(a) Characteristic Table

67
 S
Q

Clk

~Q
R

(b) Circuit (c) Symbol

Figure 3: A SR flip-flop

Part IV
The T (toggle) flip-flop is a single input flip-flop. It has two outputs which are Q
and Q‟. Write a VHDL file that defines the T flip-flop circuit. Implement your circuit on the
DE2 board and test its functionality by operating the implemented switches.

T Q(t+1)
0 Q(t) No Change
1 Q'(t) Complement

(a) Characteristic Table

(b) Symbol

68
 References

A. Books

Stephen Brown and Zvonko Vranesic, “Fundamental of Digital Logic with VHDL
Design”, 2nd edition, 2005

M. Morris Mano and Michael D Ciletti, “Digital Design”, 4th edition.

B. Internet Materials

Retrieved August 10, 2013 from http://elearning.vtu.ac.in/15/E -Notes/Logic

deslab/LD%20Manual.pdf

Retrieved August 20, 013 from http://www.altera.com/education/univ/materials

/digital_logic/labs/unv-labs.html

Retrieved November 10, 2013 http://jjackson.eng.ua.edu/courses/ece 480/assignments

/ECE480%20VHDL% 20Code%20Evaluation%20Rubric.pdf

69