Usman Institute of Technology UIT

Course Code: EE 401

Course Title: VLSI DESIGN
Scheme: Undergraduate
Credit Rating: 2 + 1 credits
Delivery method: Lectures: 32 hrs
Practical: 16

Department involved: Electronics Engineering (EE)

Course Tutors:

Engr. Atif Fareed (AF) Asst. Professor

Prerequisites: EE 204 DIGITAL ELECTRONICS /

EE 311 INTEGRATED ELECTRONICS

Recommended prior learning: Revision of the Logic Families and Fundamental Architecture
of the analogue circuits.

Co-requisites: Ability to programming in any advanced level, for example C

would be an added advantage.

Professional body requirements: N/A

Course aims: As a first course in VLSI, to give the students the feel and
understanding of the subject and to make them realize the
technicalities involved in the design and fabrication of this
enchanting world of miniaturization.

Course synopsis: This course will offer the students a sound base to the VLSI
design processing. Substantial coverage will be given to the
fabrication methodologies also but the prime focus will be on
the design aspect. The practical aspect will revolve around
simulation and modelling in the VERILOG language, a
preferred tool globally for design testing and simulation.

Learning Outcomes:

1. Knowledge Outcomes
Upon completion of this course, the learner will be able to:
a. Understand the norms of the micro-fabrication processing

b. Recognize the design and fabrication techniques.

c. Perform Simulation, modelling and timing analysis of the designed circuits.

2. Ability Outcomes
Upon completion of this module, the learner will be able to:
a) Design, model and simulate various building blocks of the VLSI systems.
b) Understand the processing methodologies
c) Differentiate Fabrication Techniques and their selection according to a specific requirement.

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Outline syllabus of topics to be covered:

LECTURE
NO. TOPICS TO BE COVERED
1 Introduction to the Subject: Overview of Silicon Processing
2 Material Growth and Deposition: Silicon Dioxide, Silicon Nitride
3 Poly crystal Silicon, Metals,
4 Doped Silicon Layers
5 Chemical & Mechanical Polishing, Lithography
6 Clean Rooms, The CMOS Process Flow (cont..)
7 The CMOS Process Flow
8 Variations: Sidewall Spacers, Damascene Process,,,,
9 Design Rules
10 Physical Limitations
11 Practical Considerations
12 Layout of Basic Structures: n wells, Active Areas, Doped Silicon Regions
13 Layout Basic Structures: MOSFETS, Drawn & Effective Values in MOSFETS, Active Contacts
14 Layout of Basic Structures: Metals
15 Layout of Basic Structures: Vias and Higher Level Metals
16 Introduction to Cell Concepts
17 FET Sizing & Unit Transistor
18 Physical Design of the Logic Gates
19 Physical Design of the Logic Gates (Contd.)
20 Physical Design of the Logic Gates (Contd.)
21 Designing High Speed CMOS Logic Networks: Gate Delays
22 Delay Minimization
23 Advanced Techniques in CMOS Logic Circuits :Mirror Circuits
24 Pseudo NMOS , Tristate Circuits
25 Clocked CMOS
26 Dynamic CMOS Circuits
27 Domino Logic, Power Dissipation of Dynamic Logic Circuits
28 Complementary Pass Transistor Logic
29 CMOS IMPLEMENTATION: The Static Ram
30 CMOS IMPLEMENTATION: DRAMs
31 System Level Physical Design: Interconnect Delay Modeling, Signal Delay versus Line Length
32 Cross Talk and Interconnect Scaling, Floor Planning and Routing

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Indicative learning strategy:

Lectures will provide an introduction to the syllabus topics as well as discussing the theoretical aspects
of the course. A series of labs will explore a range of issues relevant to the field of subject. Students are
required to take an active role in the preparation and delivery of certain lab materials.

Indicative references/learning materials:

TEXT BOOKS
Reference Books for Consultation:
1 Introduction to VLSI Circuits & Systems by John P. Uyemura 2003
2 Principles of CMOS VLSI Design by Neil H. E. Weste & Kamran Eshraghian 2ND Edition 1993
3 VLSI Design Techniques for Analog & Digital Circuits by Randall L. Geiger, Phillip E. Allen
and Noel R. Strader 1990
4 Basic VLSI Design by Douglas A. Pucknell & Kamran Eshraghian 3RD Edition 1995
5 CMOS Digital Integrated Circuits Analysis & Design by Sung-Mo Kang & Yusuf Leblebici
Third Edition (11th Reprint 2006)

Resources required:
Multimedia presentations will be given in theoretical lectures.

Assessment Strategy:

Students must demonstrate basic competency in all the outcomes, listed above, in order to receive a passing grade
for the course. Basic competency will be assessed based on a specific set of exam questions, for which a passing
threshold of a minimum of 40% will be required. Two opportunities will be provided for students to demonstrate
these outcomes: (1) the primary assessment exams; and (2) the final assessment exam. A score equal to or
greater than the passing threshold on either of these evaluation instruments will be sufficient to establish basic
competency but students must have successfully demonstrated at least one of the three outcomes on the primary
assessment exams and have a passing grade (based on the results of the homework, labs, and primary
assessment exams) in order to qualify for the final.

INSTRUCTION TO THE STUDENTS:

- CELLULAR PHONES SHALL REMAIN MUTE/UNDER VIBRATION MODE IN
THE CLASS.
- ASSIGNMENT DUE DATE AND TIME SHALL BE STRICTLY FOLLOWED.
- PROPER CONSULTATION FOR INDIVIDUAL PROBLEMS CAN BE
OBTAINED BY SIMPLY WALKING INTO MY OFFICE AND DISCUSSING.
FEEL FREE TO TALK WHENEVER YOU LIKE AND I AM FREE!
- ATTENDANCE SHALL BE STRICTLY MONITORED AND WILL BE
SUBMITTED TO THE ACADEMIC ADMINISTRATION DEPARTMENT ON
WEEKLY BASIS. NO COMPENSATION WHATSOEVER IN THIS REGARD
SHALL BE CONSIDERED.
- ENTRY TO CLASS/LABS WILL NOT BE POSSIBLE AFTER 10 MIN. OF THE
STARTING TIME.
- REGULAR REVISION OF THE CLASS ROOM TEACHING IS HIGHLY
RECOMMENDED IN THIS COURSE.

ALL THE BEST!

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