Data Sheet No.

PD60230 revD
IR1150(S)(PbF)
IR1150I(S)(PbF)

µPFC ONE CYCLE CONTROL PFC IC

Features
• PFC with IR proprietary “One Cycle Control” • Open loop protection
• Continuous conduction mode (CCM) boost type PFC • Maximum duty cycle limit of 98%
• No line voltage sense required • User programmable fixed frequency operation
• Programmable switching frequency (50kHz-200kHz) • Min. off time of 150-350ns over freq range
• Programmable output overvoltage protection • VCC under voltage lockout
• Brownout and output undervoltage protection • Internally clamped 13V gate drive
• Cycle-by-cycle peak current limit • Fast 1.5A peak gate drive
• Soft start • Micropower startup (<200 µA)
• User initiated micropower “Sleep Mode” • Latch immunity and ESD protection
• Parts also available Lead-Free

Description
The µPFC IR1150 is a power factor correction (PFC) control IC designed to
operate in continuous conduction mode (CCM) over a wide range input line Packages
voltages. The IR1150 is based on IR's proprietary "One Cycle Control" (OCC)
technique providing a cost effective solution for PFC.
The proprietary control method allows major reductions in component count,
PCB area and design time while delivering the same high system performance
as traditional solutions.
The IC is fully protected and eliminates the often noise sensitive line voltage 8-Lead SOIC
sensing requirements of existing solutions.
The IR1150 features include programmable switching frequency,
programmable dedicated over voltage protection, soft start, cycle- by-cycle
peak current limit, brownout, open loop, UVLO and micropower startup current.
In addition, for low standby power requirements (Energy Star, 1W 8-Lead PDIP
Standby, Blue Angel, etc.), the IC can be driven into sleep mode with total
current consumption below 200µA, by pulling the OVP pin below 0.62V.

www.irf.com 1
 IR1150(S)/IR1150I(S)(PbF)

Absolute Maximum Ratings

Absolute maximum ratings indicate sustained limits beyond which damage to the device may occur. All voltages are
absolute voltages referenced to COM. Thermal resistance and power dissipation are measured under board mounted and
still air conditions.
Parameters Symbols Min. Max. Units Remarks
VCC voltage VCC -0.3 22 V Not internally clamped
Freq. voltage VFREQ. -0.3 10.5 V
ISNS voltage VISNS -10 3 V
OVP/EN voltage VOVP/EN -0.3 9 V
VFB voltage VFB -0.3 10.5 V
COMP voltage VCOMP -0.3 10 V
Gate voltage VGATE -0.3 18 V
Continuous gate current IGATE -5 5 mA
Max peak gate current IGATEPK -1.5 1.5 A
Junction temperature TJ -40 150 ˚C
Storage temperature TS -55 150 ˚C
— 128 ˚C/W SOIC-8
Thermal resistance Rθ JA
— 84 ˚C/W PDIP-8
— 675 mW SOIC-8 TAMB = 25 ˚C
Package power dissipation PD
— 1000 mW PDIP-8 TAMB = 25 ˚C
ESD protection VESD — 2 kV Human body model*

Recommended Operating Conditions

Recommended operating conditions for reliable operation with margin
Parameters Symbols Min. Typ. Max. Units Remarks
Supply voltage VCC 15 18 20 V
Junction temperature TJ -25 — 125 °C
Ambient temperature TA 0 — 70 °C IR1150(S)
Ambient temperature TA -25 — 85 °C IR1150I(S)
Switching frequency FSW 50 — 200 kHz

Electrical Characteristics
The electrical characteristics involve the spread of values guaranteed within the specified supply voltage and junction
temperature range TJ from – 25°C to 125°C. Typical values represent the median values, which are related to 25°C. If
not otherwise stated, a supply voltage of VCC =15V is assumed for test condition

Supply Section
Parameters Symbols Min. Typ. Max. Units Remarks
VCC turn-on threshold VCC ON 12.2 12.7 13.2 V
VCC turn-off threshold
VCC UVLO 10.2 10.7 11.2 V
(under voltage lock out)
*Per EIA/JESD22-A114-B (discharging a 100pF capacitor through a 1.5KΩ series resistor)

www.irf.com 2
 IR1150(S)/IR1150I(S)(PbF)

Electrical Characteristics cont.

The electrical characteristics involve the spread of values guaranteed within the specified supply voltage and junction
temperature range TJ from – 25°C to 125°C. Typical values represent the median values, which are related to 25°C. If not
otherwise stated, a supply voltage of VCC =15V is assumed for test condition.
Parameters Symbols Min. Typ. Max. Units Remarks
VCC turn-off hysteresis VCC HYST 1.8 — 2.2 V
— 18 22 mA CLOAD=1nF fSW=200kHZ
— 36 40 mA CLOAD=10nF fSW=200kHZ
Operating current ICC
Standby mode - inactive gate
— 8 10 mA
Internal oscillator running
Startup current ICCSTART — — 175 uA VCC=VCC ON - 0.1V
Sleep current ISLEEP — 125 200 uA VOVP<0.5V, VCC =15V
Sleep threshold VSLEEP 0.56 0.62 0.68 V

Oscillator Section
Parameters Symbols Min. Typ. Max. Units Remarks
Switching frequency fSW 50 — 200 kHz RSET = 165kΩ-37kΩ approx.
Initial accuracy fSW ACC — — 5 % TA = 25˚C
Voltage stability VSTAB — 0.2 3 % 13V <VCC <20V
Temperature stability TSTAB — 2 — % -25˚C ≤ TJ≤ 125˚C
Total variation fVT — 10 — % Line & temperature
Long term stability FSTABLT — 0.1 0.5 % TAMB = 125˚C, 1000Hrs
Maximum duty cycle DMAX 93 — 98 % fSW=200kHz
Minimum duty cycle DMIN — — 0 %
Minimum off time Toffmin 200 300 400 Ns fSW= 50kHz to 200kHz

Protection Section
Parameters Symbols Min. Typ. Max. Units Remarks
Open loop protection(OLP)
VOLP 17 19 21 %VREF
Vfb threshold
Output under voltage
VOUV 49 51 53 %VREF Brown out protection
protection (OUV)
Output over voltage
VOVP 104 105.5 107 %VREF
protection (OVP)
OVP hysteresis — 350 450 550 mV
Peak current limit protection
(IPKLMT) ISNS voltage VISNS -1.11 -1.04 -0.96 V
threshold

www.irf.com 3
 IR1150(S)/IR1150I(S)(PbF)

Internal Voltage Reference Section

Parameters Symbols Min. Typ. Max. Units Remarks
Reference voltage VREF 6.9 7.0 7.1 V TA = 25˚C
Line regulation RREG — 12 25 mV 13.5V <VCC < 20V
Temp stability TSTAB — 0.4 — % -25˚C ≤TAMB≤ 125˚C
Total variation ∆VTOT 6.8 — 7.1 V Over VCC and Tj ranges

Voltage Error Amplifier Section

Parameters Symbols Min. Typ. Max. Units Remarks
Transconductance gm 30 40 55 µS -25˚C ≤TAMB≤ 125˚C
Source/sink current 30 40 65 TAMB = 25˚C
IOVEA µA
20 45 90 -25˚C ≤TAMB≤ 125˚C
Soft start delay time RGAIN=1kΩ , CZERO=0.33µF
tss — 40 — ms
(calculated) CPOLE=0.01µF, fXO=28Hz
— 1.2 1.5 @ 1mA (max) initial
VCOMP voltage (fault) VCOMP FLT
0.2 V @ 25µA steady state
Effective VCOMP voltage VCOMP EFF 6.05 V
VFB=0V
Input bias current IIB — -0.2 -0.5 µA
-25˚C ≤ TAMB≤ 125˚C
Open loop bandwidth BW — 1 — MHz
Input offset voltage temp
TCIOV — — 10 µV/˚C Note 1
coefficient
Common mode rejection ratio CMRR — 100 — dB
Output low voltage VOL — — 0.5 V
Output high voltage VOH 5.71 6.15 6.8 V
VCOMP start voltage VCOMP START 300 500 700 mV

Current Amplifier Section

Parameters Symbols Min. Typ. Max. Units Remarks
DC gain gDC — 2.5 — V/V
Corner frequency fC 200 — 280 kHz Note 1
Input offset voltage VIO — 1 4 mV Note 1
ISNS bias current ΙIB — 200 300 µA VFB=0V,-25˚C ≤ TAMB≤ 125˚C
Input offset voltage temp
TCIOV — — 10 µV/˚C Note 1
coefficient
Common mode rejection ratio CMRR — 100 — dB
230 350 450 ns TAMB = 25˚C
Blanking time TBLANK
150 600 ns -25˚C ≤TAMB≤ 125˚C

www.irf.com 4
 IR1150(S)/IR1150I(S)(PbF)
Gate Driver Section
Parameters Symbols Min. Typ. Max. Units Remarks
Gate low voltage VGLO — 1.2 1.5 V IGATE=200mA
Gate high voltage VGTH — 13 18 V VCC=20V
Gate high voltage VGTH 9.5 — — V VCC =11.5V
— 20 — ns CLOAD = 1nF, VCC=16V
Rise time tr
— 70 — ns CLOAD = 10nF, VCC=16V
— 20 — ns CLOAD = 1nF, VCC=16V
Fall time tf
— 70 — ns CLOAD = 10nF, VCC=16V
Out peak current IOPK 1.5 — — A CLOAD = 10nF, VCC=16V
Gate voltage @ fault VG fault — — 1.8 V IGATE=20mA
Note 1: Guaranteed by design, but not tested in production.

www.irf.com 5
 IR1150(S)/IR1150I(S)(PbF)
Block Diagram

0.62V

Lead Assignments & Definitions

Lead Assignment Pin# Symbol Description

1 COM Ground

2 FREQ Frequency Set

3 ISNS Current Sense

4 OVP/EN Overvoltage Fault Detect / Enable

5 COMP Voltage Loop Compensation

6 VFB Output Voltage Sense

7 VCC IC Supply Voltage

8 GATE Gate Drive Output

www.irf.com 6
 IR1150(S)/IR1150I(S)(PbF)
General Description

The µPFC IR1150 is intended for boost converters for IC Supply

power factor correction operating at a fixed frequency in
The UVLO circuit monitors the VCC pin and maintains the
continuous conduction mode. The IC operates with two
gate drive signal inactive until the VCC pin voltage
loops; an inner current loop and an outer voltage loop.
reaches the UVLO turn on threshold, (VCC ON). As soon as
The inner current loop is fast, reliable and does not
the VCC voltage exceeds this threshold, provided that the
require sensing of the input voltage in order to create a
VFB pin voltage is greater than 20%VREF, the gate drive
current reference.
will begin switching (under Soft Start) and increase the
pulse width to its maximum value as demanded by the
This inner current loop sustains the sinusoidal profile of
output voltage error amplifier. If the voltage on the VCC
the average input current based on the dependency of
pin falls below the UVLO turn off threshold, (VCC UVLO), the
the pulse width modulator duty cycle on the input line
IC turns off, gate drive is terminated, and the turn on
voltage in order to determine the analogous input line
threshold must again be exceeded in order to re-start the
current. Thus, the current loop uses the embedded
process and move into Soft Start mode.
input voltage signal to control the average input current
to follow the input voltage.
Soft Start
The IR1150 enables excellent THD performance. In Soft Start controls the rate of rise of the output voltage
light load conditions, a small distortion occurs at zero- error amplifier in order to obtain a linear control of the
crossing due to the finite boost inductance but this is increasing duty cycle as a function of time. The Soft Start
negligible and well within EN61000-3-2 Class D time is controlled by voltage error amplifier compensation
specifications. components selected, and is user programmable based
on desired loop crossover frequency.
The outer voltage loop controls the DC bus voltage.
This voltage is fed into the voltage error amplifier to Frequency Select
control the slope of the integrator ramp and sets the The switching frequency of the IC is programmable by an
amplitude of the average input current. external resistor at the FREQ pin. The design
incorporates min/max restrictions such that the minimum
The two loops combine to control the amplitude, phase and maximum operating frequency fall within the range of
and shape of the input current, with respect to the input 50-200kHz.
voltage, giving near-unity power factor.
Gate Drive
The IC is designed for robust operation and provides The gate drive is a totem pole driver with 1.5A capability.
protection from system level over current, over voltage, If higher currents are required, additional external drivers
under voltage, and brownout conditions. can be used.

www.irf.com 7
 IR1150(S)/IR1150I(S)(PbF)
Detailed Pin Description

COM: Ground ISNS: Current Sense input

This is the ground potential pin of the integrated control This pin is the inverting Current Sense Input & Peak
circuit. All internal devices are referenced to this point. Current Limit. The voltage at this pin is the negative
voltage drop, sensed across the system current sense
VFB: Output Voltage Feedback resistor, representing the inductor current.
The output voltage of the boost converter is sensed via a This voltage is fed into the Peak Current Limit protection
resistive divider and fed into this pin, which is the inverting comparator with threshold around -1V. This protection
input of the output voltage error amplifier. The impedance circuit incorporates a leading edge blanking circuit
of the divider string must be low enough so as to not following the comparator to improve noise immunity of the
introduce substantial error due to the input bias currents of protection process.
the amplifier, yet high enough so as to minimize power The current sense signal is also fed into the current sense
dissipation. A typical value of external divider impedance amplifier. The signal is amplified, filtered of high frequency
is 1MΩ. noise and then injected into a summing node where it is
The error amplifier is a transconductance type which yields subtracted from the compensation voltage VCOMP.
high output impedance, thus increasing the noise immunity The signal on this pin must be previously filtered with an
of the error amplifier output. This also eliminates input RC cell to provide additional noise immunity. The input
divider string interaction with compensation feedback impedance of this pin is 5kΩ .
capacitors and reducing the loading of divider string due to
a low impedance output of the amplifier. VCC: Supply Voltage
This is the supply voltage pin of the IC and it is monitored
COMP: Voltage Loop Compensation by the under voltage lockout circuit. It is possible to turn
External circuitry from this pin to ground compensates the off the IC by pulling this pin below the minimum turn off
system voltage loop and soft start time. This is the output threshold voltage, without damage to the IC.
of the voltage error amplifier. This pin will be discharged To prevent noise problems, a bypass ceramic capacitor
via internal resistance when a fault mode occurs. connected to VCC and COM should be placed as close as
possible to the IR1150.
GATE: Gate Drive Output This pin is not internally clamped, therefore damage will
This is the gate drive output of the IC. Drive voltage is occur if the maximum voltage is exceeded.
internally limited and provides ±1.5A peak with matched
OVP/EN: Over Voltage Protection / Enable
rise and fall times.
This pin is the input to the over voltage protection
FREQ: Frequency Set comparator the threshold of which is internally
programmed to 105.5% of VREF.
This is the user programmable frequency pin. An A resistive divider feeds this pin from the output volt-age
external resistor from this pin to the COM pin pro- to COM and inhibits the gate drive whenever the threshold
grams the frequency. The operational switching is exceeded. Normal operation resumes when the voltage
frequency range for the device is 50kHz – 200kHz. level on this pin decreases to below the pin threshold.
This pin is also used to activate “sleep” mode by pulling
the voltage level below 0.62V (typ).

www.irf.com 8
 IR1150(S)/IR1150I(S)(PbF)
Operating States

UVLO Mode Normal Mode

The IC remains in the UVLO condition until the voltage on The IC enters normal operating mode once the soft start
the VCC pin exceeds the VCC turn on threshold voltage, transition has been completed. At this point the gate drive
VCC ON. is switching and the IC draws a maximum of ICC from the
During the time the IC remains in the UVLO state, the gate supply voltage source. The device will initiate another soft
drive circuit is inactive and the IC draws a start sequence in the event of a shutdown due to a fault,
quiescent current of ICC START. The UVLO mode is which activates the protection circuitry, or if the supply
accessible from any other state of operation whenever the voltage drops below the UVLO turn off threshold of VCC
IC supply voltage condition of VCC < VCC UVLO occurs. UVLO.

Standby Mode Fault Protection Mode

The IC is in this state if the supply voltage has exceeded
The fault mode will be activated when any of the protection
VCC ON and the VFB pin voltage is less than 20% of VREF .
circuits are activated. The IC protection circuits include
The oscillator is running and all internal circuitry is biased
Supply Voltage Under Voltage Lockout (UVLO), Output
in this state but the gate is inactive. This state is
Over Voltage Protection (OVP), Open Loop Protection
accessible from any other state of operation except OVP.
(OLP), Output Undervoltage Protection (OUV), and Peak
The IC enters this state whenever the VFB pin voltage has
Current Limit Protection (IPK LIMIT).
decreased to 50% of VREF when operating in normal
mode or during a peak current limit fault condition, or 20% Sleep Mode
VREF when operating in soft start mode.
The sleep mode is initiated by pulling the OVP pin below
Soft Start Mode 0.62V (typ). In this mode the IC draws a very low
This state is activated once the VCC voltage has quiescent supply current.
exceeded VCCON and the VFB pin voltage has exceeded
20% of VREF.
The soft start time, which is defined as the time required
for the duty cycle to linearly increase from zero to
maximum, is dependent upon the values selected for
compensation of the voltage loop pin COMP to pin COM.
Throughout the soft start cycle, the output of the voltage
error amplifier (pin COMP) charges through the
compensation network. This forces a linear rise of the
voltage at this node which in turn forces a linear increase
in the gate drive duty cycle from 0. This controlled duty
cycle reduces system component stress during start up
conditions as the input current amplitude is increasing
linearly.

www.irf.com 9
 IR1150(S)/IR1150I(S)(PbF)

VOVP <0.62V

VOVP >0.62V

VOVP <0.62V

VOVP <0.62V

VOVP <0.62V

VOVP <0.62V
VOVP <99%VREF

VOVP <0.62V

www.irf.com 10
 IR1150(S)/IR1150I(S)(PbF)

www.irf.com 11
 IR1150(S)/IR1150I(S)(PbF)

www.irf.com 12
 IR1150(S)/IR1150I(S)(PbF)

www.irf.com 13
 IR1150(S)/IR1150I(S)(PbF)

www.irf.com 14
 IR1150(S)/IR1150I(S)(PbF)

Tape & Reel Information (SOIC 8-Lead only)

Dimensions are shown in millimeters (inches)

TERMINAL NUMBER 1

12.3 ( .484 )
11.7 ( .461 )

8.1 ( .318 )
7.9 ( .312 ) FEED DIRECTION

NOTES:
1. OUTLINE CONFORMS TO EIA-481 & EIA-541.
2. CONTROLLING DIMENSION : MILLIMETER.

330.00
(12.992) MAX.

14.40 ( .566 )
NOTES : 12.40 ( .488 )

1. CONTROLLING DIMENSION : MILLIMETER.

2. OUTLINE CONFORMS TO EIA-481 & EIA-541.

www.irf.com 15
 IR1150(S)/IR1150I(S)(PbF)

PART MARKING INFORMATION

ORDER INFORMATION
Basic Part Lead-free Part
8-Lead SOIC IR1150STR order IR1150STR 8-Lead SOIC IR1150S order IR1150STRPbF
8-Lead SOIC IR1150ISTR order IR1150ISTR 8-Lead SOIC IR1150ISTR order IR1150ISTRPbF
8-Lead PDIP IR1150 order IR1150PbF
8-Lead PDIP IR1150I order IR1150IPbF

The IR1150(S)(PbF) has been designed and qualified for the Consumer Market
The IR1150I(S)(PbF) has been designed and qualified for the Industrial Market
Qualification Standards can be found on IR’s Web site.

WORLD HEADQUARTERS: 233 Kansas Street, El Segundo, California 90245 Tel: (310) 252-7105
http://www.irf.com/ Data and specifications subject to change without notice. 2/5/2007

www.irf.com 16