0

R Virtex™-E 1.8 V
Field Programmable Gate Arrays
DS022-1 (v2.3) July 17, 2002 0 0 Production Product Specification

Features
• Fast, High-Density 1.8 V FPGA Family • High-Performance Built-In Clock Management Circuitry
- Densities from 58 k to 4 M system gates - Eight fully digital Delay-Locked Loops (DLLs)
- 130 MHz internal performance (four LUT levels) - Digitally-Synthesized 50% duty cycle for Double
- Designed for low-power operation Data Rate (DDR) Applications
- PCI compliant 3.3 V, 32/64-bit, 33/ 66-MHz - Clock Multiply and Divide
• Highly Flexible SelectI/O+™ Technology - Zero-delay conversion of high-speed LVPECL/LVDS
- Supports 20 high-performance interface standards clocks to any I/O standard
- Up to 804 singled-ended I/Os or 344 differential I/O • Flexible Architecture Balances Speed and Density
pairs for an aggregate bandwidth of > 100 Gb/s - Dedicated carry logic for high-speed arithmetic
• Differential Signalling Support - Dedicated multiplier support
- LVDS (622 Mb/s), BLVDS (Bus LVDS), LVPECL - Cascade chain for wide-input function
- Differential I/O signals can be input, output, or I/O - Abundant registers/latches with clock enable, and
- Compatible with standard differential devices dual synchronous/asynchronous set and reset
- LVPECL and LVDS clock inputs for 300+ MHz - Internal 3-state bussing
clocks - IEEE 1149.1 boundary-scan logic
• Proprietary High-Performance SelectLink™ - Die-temperature sensor diode
Technology • Supported by Xilinx Foundation™ and Alliance Series™
- Double Data Rate (DDR) to Virtex-E link Development Systems
- Web-based HDL generation methodology - Further compile time reduction of 50%
• Sophisticated SelectRAM+™ Memory Hierarchy - Internet Team Design (ITD) tool ideal for
- 1 Mb of internal configurable distributed RAM million-plus gate density designs
- Up to 832 Kb of synchronous internal block RAM - Wide selection of PC and workstation platforms
- True Dual-Port BlockRAM capability • SRAM-Based In-System Configuration
- Memory bandwidth up to 1.66 Tb/s (equivalent - Unlimited re-programmability
bandwidth of over 100 RAMBUS channels) • Advanced Packaging Options
- Designed for high-performance Interfaces to - 0.8 mm Chip-scale
External Memories - 1.0 mm BGA
- 200 MHz ZBT* SRAMs - 1.27 mm BGA
- 200 Mb/s DDR SDRAMs - HQ/PQ
- Supported by free Synthesizable reference design • 0.18 µm 6-Layer Metal Process
• 100% Factory Tested
* ZBT is a trademark of Integrated Device Technology, Inc.

© 2000-2002 Xilinx, Inc. All rights reserved. All Xilinx trademarks, registered trademarks, patents, and disclaimers are as listed at http://www.xilinx.com/legal.htm.
All other trademarks and registered trademarks are the property of their respective owners. All specifications are subject to change without notice.

DS022-1 (v2.3) July 17, 2002 www.xilinx.com Module 1 of 4

Production Product Specification 1-800-255-7778 1
 R

Virtex™-E 1.8 V Field Programmable Gate Arrays

Table 1: Virtex-E Field-Programmable Gate Array Family Members

System Logic CLB Logic Differential User BlockRAM Distributed
Device Gates Gates Array Cells I/O Pairs I/O Bits RAM Bits
XCV50E 71,693 20,736 16 x 24 1,728 83 176 65,536 24,576
XCV100E 128,236 32,400 20 x 30 2,700 83 196 81,920 38,400
XCV200E 306,393 63,504 28 x 42 5,292 119 284 114,688 75,264
XCV300E 411,955 82,944 32 x 48 6,912 137 316 131,072 98,304
XCV400E 569,952 129,600 40 x 60 10,800 183 404 163,840 153,600
XCV600E 985,882 186,624 48 x 72 15,552 247 512 294,912 221,184
XCV1000E 1,569,178 331,776 64 x 96 27,648 281 660 393,216 393,216
XCV1600E 2,188,742 419,904 72 x 108 34,992 344 724 589,824 497,664
XCV2000E 2,541,952 518,400 80 x 120 43,200 344 804 655,360 614,400
XCV2600E 3,263,755 685,584 92 x 138 57,132 344 804 753,664 812,544
XCV3200E 4,074,387 876,096 104 x 156 73,008 344 804 851,968 1,038,336

Virtex-E Compared to Virtex Devices The Virtex-E family is not bitstream-compatible with the Vir-
tex family, but Virtex designs can be compiled into equiva-
The Virtex-E family offers up to 43,200 logic cells in devices
lent Virtex-E devices.
up to 30% faster than the Virtex family.
The same device in the same package for the Virtex-E and
I/O performance is increased to 622 Mb/s using Source
Virtex families are pin-compatible with some minor excep-
Synchronous data transmission architectures and synchro-
tions. See the data sheet pinout section for details.
nous system performance up to 240 MHz using sin-
gled-ended SelectI/O technology. Additional I/O standards
are supported, notably LVPECL, LVDS, and BLVDS, which
General Description
use two pins per signal. Almost all signal pins can be used The Virtex-E FPGA family delivers high-performance,
for these new standards. high-capacity programmable logic solutions. Dramatic
increases in silicon efficiency result from optimizing the new
Virtex-E devices have up to 640 Kb of faster (250 MHz)
architecture for place-and-route efficiency and exploiting an
block SelectRAM, but the individual RAMs are the same
aggressive 6-layer metal 0.18 µm CMOS process. These
size and structure as in the Virtex family. They also have
advances make Virtex-E FPGAs powerful and flexible alter-
eight DLLs instead of the four in Virtex devices. Each indi-
natives to mask-programmed gate arrays. The Virtex-E fam-
vidual DLL is slightly improved with easier clock mirroring
ily includes the nine members in Table 1.
and 4x frequency multiplication.
Building on experience gained from Virtex FPGAs, the
VCCINT, the supply voltage for the internal logic and mem-
Virtex-E family is an evolutionary step forward in program-
ory, is 1.8 V, instead of 2.5 V for Virtex devices. Advanced
mable logic design. Combining a wide variety of program-
processing and 0.18 µm design rules have resulted in
mable system features, a rich hierarchy of fast, flexible
smaller dice, faster speed, and lower power consumption.
interconnect resources, and advanced process technology,
I/O pins are 3 V tolerant, and can be 5 V tolerant with an the Virtex-E family delivers a high-speed and high-capacity
external 100 Ω resistor. PCI 5 V is not supported. With the programmable logic solution that enhances design flexibility
addition of appropriate external resistors, any pin can toler- while reducing time-to-market.
ate any voltage desired.
Banking rules are different. With Virtex devices, all input Virtex-E Architecture
buffers are powered by VCCINT. With Virtex-E devices, the
Virtex-E devices feature a flexible, regular architecture that
LVTTL, LVCMOS2, and PCI input buffers are powered by
comprises an array of configurable logic blocks (CLBs) sur-
the I/O supply voltage VCCO.
rounded by programmable input/output blocks (IOBs), all
interconnected by a rich hierarchy of fast, versatile routing

Module 1 of 4 www.xilinx.com DS022-1 (v2.3) July 17, 2002

2 1-800-255-7778 Production Product Specification
 R

Virtex™-E 1.8 V Field Programmable Gate Arrays

resources. The abundance of routing resources permits the

Table 2: Performance for Common Circuit Functions
Virtex-E family to accommodate even the largest and most
complex designs. Function Bits Virtex-E (-7)
Virtex-E FPGAs are SRAM-based, and are customized by Register-to-Register
loading configuration data into internal memory cells. Con-
figuration data can be read from an external SPROM (mas- Adder 16 4.3 ns
ter serial mode), or can be written into the FPGA 64 6.3 ns
(SelectMAP™, slave serial, and JTAG modes).
Pipelined Multiplier 8x8 4.4 ns
The standard Xilinx Foundation Series™ and Alliance 16 x 16 5.1 ns
Series™ Development systems deliver complete design
support for Virtex-E, covering every aspect from behavioral Address Decoder 16 3.8 ns
and schematic entry, through simulation, automatic design 64 5.5 ns
translation and implementation, to the creation and down-
loading of a configuration bit stream. 16:1 Multiplexer 4.6 ns
Parity Tree 9 3.5 ns
Higher Performance 18 4.3 ns
Virtex-E devices provide better performance than previous 36 5.9 ns
generations of FPGAs. Designs can achieve synchronous
system clock rates up to 240 MHz including I/O or 622 Mb/s Chip-to-Chip
using Source Synchronous data transmission architech- HSTL Class IV
tures. Virtex-E I/Os comply fully with 3.3 V PCI specifica-
tions, and interfaces can be implemented that operate at LVTTL,16mA, fast slew
33 MHz or 66 MHz.
LVDS
While performance is design-dependent, many designs
operate internally at speeds in excess of 133 MHz and can LVPECL
achieve over 311 MHz. Table 2 shows performance data for
representative circuits, using worst-case timing parameters.

Virtex-E Device/Package Combinations and Maximum I/O

Table 3: Virtex-E Family Maximum User I/O by Device/Package (Excluding Dedicated Clock Pins)
XCV XCV XCV XCV XCV XCV XCV XCV XCV XCV XCV
50E 100E 200E 300E 400E 600E 1000E 1600E 2000E 2600E 3200E
CS144 94 94 94
PQ240 158 158 158 158 158
HQ240 158 158
BG352 196 260 260
BG432 316 316 316
BG560 404 404 404 404 404
FG256 176 176 176 176
FG456 284 312
FG676 404 444
FG680 512 512 512 512
FG860 660 660 660
FG900 512 660 700
FG1156 660 724 804 804 804

DS022-1 (v2.3) July 17, 2002 www.xilinx.com Module 1 of 4

Production Product Specification 1-800-255-7778 3
 R

Virtex™-E 1.8 V Field Programmable Gate Arrays

Virtex-E Ordering Information

Example: XCV300E-6PQ240C

Device Type Temperature Range

C = Commercial (Tj = 0 C to +85 C)
I = Industrial (Tj = -40 C to +100 C)
Speed Grade Number of Pins
(-6, -7, -8)
Package Type
BG = Ball Grid Array
FG = Fine Pitch Ball Grid Array
HQ = High Heat Dissipation
DS022_043_072000

Figure 1: Ordering Information

Revision History
The following table shows the revision history for this document.

Date Version Revision

12/7/99 1.0 Initial Xilinx release.
1/10/00 1.1 Re-released with spd.txt v. 1.18, FG860/900/1156 package information, and additional DLL,
Select RAM and SelectI/O information.
1/28/00 1.2 Added Delay Measurement Methodology table, updated SelectI/O section, Figures 30, 54,
& 55, text explaining Table 5, TBYP values, buffered Hex Line info, p. 8, I/O Timing
Measurement notes, notes for Tables 15, 16, and corrected F1156 pinout table footnote
references.
2/29/00 1.3 Updated pinout tables, VCC page 20, and corrected Figure 20.
5/23/00 1.4 Correction to table on p. 22.
7/10/00 1.5 • Numerous minor edits.
• Data sheet upgraded to Preliminary.
• Preview -8 numbers added to Virtex-E Electrical Characteristics tables.
8/1/00 1.6 • Reformatted entire document to follow new style guidelines.
• Changed speed grade values in tables on pages 35-37.
9/20/00 1.7 • Min values added to Virtex-E Electrical Characteristics tables.
• XCV2600E and XCV3200E numbers added to Virtex-E Electrical Characteristics
tables (Module 3).
• Corrected user I/O count for XCV100E device in Table 1 (Module 1).
• Changed several pins to “No Connect in the XCV100E“ and removed duplicate VCCINT
pins in Table ~ (Module 4).
• Changed pin J10 to “No connect in XCV600E” in Table 74 (Module 4).
• Changed pin J30 to “VREF option only in the XCV600E” in Table 74 (Module 4).
• Corrected pair 18 in Table 75 (Module 4) to be “AO in the XCV1000E, XCV1600E“.

Module 1 of 4 www.xilinx.com DS022-1 (v2.3) July 17, 2002

4 1-800-255-7778 Production Product Specification
 R

Virtex™-E 1.8 V Field Programmable Gate Arrays

Date Version Revision

11/20/00 1.8 • Upgraded speed grade -8 numbers in Virtex-E Electrical Characteristics tables to
Preliminary.
• Updated minimums in Table 13 and added notes to Table 14.
• Added to note 2 to Absolute Maximum Ratings.
• Changed speed grade -8 numbers for TSHCKO32, TREG, TBCCS, and TICKOF.
• Changed all minimum hold times to –0.4 under Global Clock Setup and Hold for
LVTTL Standard, with DLL.
• Revised maximum TDLLPW in -6 speed grade for DLL Timing Parameters.
• Changed GCLK0 to BA22 for FG860 package in Table 46.
2/12/01 1.9 • Revised footnote for Table 14.
• Added numbers to Virtex-E Electrical Characteristics tables for XCV1000E and
XCV2000E devices.
• Updated Table 27 and Table 78 to include values for XCV400E and XCV600E devices.
• Revised Table 62 to include pinout information for the XCV400E and XCV600E devices
in the BG560 package.
• Updated footnotes 1 and 2 for Table 76 to include XCV2600E and XCV3200E devices.
4/2/01 2.0 • Updated numerous values in Virtex-E Switching Characteristics tables.
• Converted data sheet to modularized format. See the Virtex-E Data Sheet section.
10/25/01 2.1 • Updated the Virtex-E Device/Package Combinations and Maximum I/O table to
show XCV3200E in the FG1156 package.
11/09/01 2.2 • Minor edits.

07/17/02 2.3 • Data sheet designation upgraded from Preliminary to Production.

Virtex-E Data Sheet

The Virtex-E Data Sheet contains the following modules:
• DS022-1, Virtex-E 1.8V FPGAs: • DS022-3, Virtex-E 1.8V FPGAs:
Introduction and Ordering Information (Module 1) DC and Switching Characteristics (Module 3)
• DS022-2, Virtex-E 1.8V FPGAs: • DS022-4, Virtex-E 1.8V FPGAs:
Functional Description (Module 2) Pinout Tables (Module 4)

DS022-1 (v2.3) July 17, 2002 www.xilinx.com Module 1 of 4

Production Product Specification 1-800-255-7778 5
 R

Virtex™-E 1.8 V Field Programmable Gate Arrays

Module 1 of 4 www.xilinx.com DS022-1 (v2.3) July 17, 2002

6 1-800-255-7778 Production Product Specification