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Multiplication of Signed Numbers: CSE 430 - Assignment 3

This document provides steps for implementing the control logic for multiplication of signed numbers using a sequence register and decoder method with 5-bit sign-magnitude numbers. It outlines 7 steps: 1) Design an ALU sub-circuit, 2) Design an accumulator sub-circuit using a shift register, 3) Implement a multiplier register, 4) Implement a counter, 5) Implement state transition logic using JK flip-flops and a decoder, 6) Implement control signals, 7) Implement the A and E signals. The deadline for submission is April 16.

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92 views

Multiplication of Signed Numbers: CSE 430 - Assignment 3

This document provides steps for implementing the control logic for multiplication of signed numbers using a sequence register and decoder method with 5-bit sign-magnitude numbers. It outlines 7 steps: 1) Design an ALU sub-circuit, 2) Design an accumulator sub-circuit using a shift register, 3) Implement a multiplier register, 4) Implement a counter, 5) Implement state transition logic using JK flip-flops and a decoder, 6) Implement control signals, 7) Implement the A and E signals. The deadline for submission is April 16.

Uploaded by

alam sifat
Copyright
© © All Rights Reserved
We take content rights seriously. If you suspect this is your content, claim it here.
Available Formats
Download as PDF, TXT or read online on Scribd
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Multiplication of Signed

Numbers
CSE 430 – Assignment 3
Problem Statement
For this assignment you will need to implement the control logic for multiplication of
signed numbers using sequence register and decoder method. We will be using 5 bit
sign-magnitude form for this. Meaning 1 bit sign and 4 bit magnitude.

In this slide we will be going step by step of what we need to do to implement this
control logic
Step 1: ALU Sub-circuit
First we need design the sub-circuit of our
basic ALU. Use your previously designed
ALU here.
Step 2: Accumulator Sub-circuit
We don’t need our accumulator to implement many functions here. We just need it to load
the output from ALU or hold it’s current value. For this we will be using a universal shift
register (74194).
The shift register operates as follows-
S1S0 = 00  Hold value
S1S0 = 10  Shift right (MSB in SL)
S1S0 = 11  Parallel Load
MR = 0  Reset
Similar to the ALU we check if it can load and value as expected.
Once you have checked that, connect the ALU’s output to the accumulators input, and the
accumulators output to the A input of ALU. Now check the components together.
Step 3: Implement Multiplier register Q
It will be the same as the accumulator. Except we will need provision to load an initial
value
Step 4: Implement Counter
We will need to control the number of
iterations depending on the number of bits,
4 in this case. In this case we will not count
down from 4 to 0 like the algorithm
suggests. It will be easier for us to count up
from 0 to 4 and terminate after 4 count.

Use a 74193 to implement the counter


Step 5: Implement Transition logic
Implement the state transition logic using JK flip flops and a decoder.
Step 6: Implement the control signals
Implement the control signals as the functions
of the states.
Check the values with logicprobes when you are
done.
Control signals of A:
State S1 S0 RES
T1 0 0 0
Q1T2 1 1 1
T3 1 0 1
Functions:
S1 = Q1T2 + T3
S0 = Q1T2
RES = T1
Also, MSB = E
Control signals of Q:
State S1 S0
T1 1 1
T3 1 0

Functions:
S1 = T 1 + T 3
S0 = T 1
Also, RES = 1
and MSB = A1
Control signals of Counter:
Functions:
D3 – D0 = 0100 (4)
DN = T2.CLK
PL = T1
MR = 0

Output:
Pz = TCD’
Step 7: Implement As and E
Use E (like previous assignment)

Implement As = Bs xor Qs
Control signals of E:
State JE KE
T1 0 1
Q1T2 Cout Cout’
T3 0 1
Functions:
JE = Q1T2Cout
KE = T1 + T3 + Q1T2Cout’
Final Step:
You are good to go now, check the design for all possible scenarios in ±𝐵 × (±𝑄)
Deadline
Section B: 16/4

Submit your Proteus files in ELMS.

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