C28 X 1 Day Workshop

C2000™ Piccolo™ 1-Day Workshop
Workshop Guide and Lab Manual
F28xPodw
Revision 2.0
June 2010
Technical Training
Organization
Workshop Topics
Important Notice
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Copyright © 2009 – 2010 Texas Instruments Incorporated
Revision History
April 2009 – Revision 1.0
October 2009 – Revision 1.1
June 2010 – Revision 2.0
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2 C2000 Piccolo 1-Day Workshop

Workshop Topics
Workshop Topics
Workshop Topics.........................................................................................................................................3
Workshop Introduction ...............................................................................................................................4
Architecture Overview ................................................................................................................................8
Programming Development Environment.................................................................................................10
Code Composer Studio.........................................................................................................................10
Linking Sections in Memory ................................................................................................................12
Lab 1: Linker Command File....................................................................................................................15
Peripheral Register Header Files .............................................................................................................21
Reset, Interrupts and System Initialization ...............................................................................................28
Reset .....................................................................................................................................................28
Interrupts ..............................................................................................................................................30
Peripheral Interrupt Expansion (PIE) ...................................................................................................32
Oscillator / PLL Clock Module ............................................................................................................34
Watchdog Timer Module......................................................................................................................35
GPIO.....................................................................................................................................................36
Lab 2: System Initialization ......................................................................................................................38
Control Peripherals ..................................................................................................................................43
ADC Module ........................................................................................................................................43
Pulse Width Modulation.......................................................................................................................45
ePWM...................................................................................................................................................46
eCAP ....................................................................................................................................................59
eQEP.....................................................................................................................................................60
Lab 3: Control Peripherals.......................................................................................................................62
Flash Programming ..................................................................................................................................68
Flash Programming Basics ...................................................................................................................68
Programming Utilities and CCS Flash Programmer.............................................................................69
Code Security Module and Password ...................................................................................................70
Lab 4: Programming the Flash.................................................................................................................72
The Next Step….........................................................................................................................................79
Training ................................................................................................................................................79
Development Tools...............................................................................................................................80
Development Support ...........................................................................................................................82
NOTES:.....................................................................................................................................................84
C2000 Piccolo 1-Day Workshop 3

Workshop Introduction
C2000™ Piccolo™ 1-Day Workshop
Texas Instruments
Technical Training
T TO
Technical Training
Organization C2000 and Piccolo are trademarks of Texas Instruments. Copyright © 2010 Texas Instruments. All rights reserved.
C2000 Piccolo 1-Day Workshop Outline

Architecture Overview
Programming Development Environment
Lab: Linker command file
Peripheral Register Header Files
Reset, Interrupts and System Initialization
Lab: Watchdog and interrupts
Control Peripherals
Lab: Generate and graph a PWM waveform
Flash Programming
Lab: Run the code from flash memory
The Next Step…

Introductions
Name
Company
Project Responsibilities
DSP / Microcontroller Experience
TI Processor Experience
Hardware / Software - Assembly / C
Interests
TI Embedded Processing Portfolio

TI Embedded Processors
Microcontrollers (MCUs) ARM®-Based Processors Digital Signal Processors (DSPs)
16-bit ultra- 32-bit 32-bit ARM ARM Ultra

DSP Multi-core
low power real-time Cortex™-M3 Cortex-A8 Low power
DSP+ARM DSP
MCUs MCUs MCUs MPUs DSP
C2000™ Sitara ™ C6000 ™

Delfino ™ Stellaris ® DaVinci™ C6000™ C5000™
MSP430™ ®
ARM Cortex™-M3
ARM® Cortex™-A8
& ARM9 video pr ocesso rs
Piccolo™ OMAP™ 24.000
Up to 40MHz to Up to 300MHz to 300MHz to >1Ghz MMACS Up to 300 MHz
25 MHz 300 MHz 100 MHz >1GHz +Accelerator +Accelerator
Flash Flash, RAM Flash Cache, Cache Cache Up to 320KB RAM
1 KB to 256 KB 16 KB to 512 KB 8 KB to 256 KB RAM, ROM RAM, ROM RAM, ROM Up to 128KB ROM
Analog I/O, ADC PWM, ADC, USB, ENET USB, CAN, USB, ENET, SRIO, EMAC USB, ADC
LCD, USB, RF CAN, SPI, I2C MAC+PHY CAN, PCIe, EMAC PCIe, SATA, SPI DMA, PCIe McBSP, SPI, I2 C
ADC, PWM, SPI
Measurement, Motor Control, Connectivity, Security, Industrial computing, Flo ating/Fixed Point Telecom T&M, Audio, Voice
Sensing, General Digital Power, Motion Control, HMI, POS & portable Video, Audio, Voice, media gateways,
Purpose Lighting, Ren. Enrgy Industrial Automation data terminals Security, Confer. base stations Medical, Biometrics
$0.25 to $9.00 $1.50 to $20.00 $1.00 to $8.00 $5.00 to $20.00 $5.00 to $200.00 $40 to $200.00 $3.00 to $10.00
Software & Dev. Tools

C2000 Portfolio Expanding with

Price/Performance Optimized Derivatives
High-end
High-Precision Control Derivatives
C2834x
300 MIPS
Control Performance
F2833x/23x
150 MIPS
F281x
Multi-Function, 150 MIPS
Appliance & F280x/xx F2803x/2x
100 MIPS 60 MIPS
Consumer Control
F24xx
40 MIPS Cost
optimized
versions
Broad C2000 Application Base
Renewable Telecom AC Drives, Industrial

Energy Digital Power & Consumer Motor
Generation Control
Automotive
Radar, Electric
Power Steering Power Line
& Digital Power Communications
LED Lighting
Consumer,
Medical &
Non-traditional

C2000 Piccolo™ Microcontroller Family

F2802x / F2803x
Flash RAM Analog ADC* PWM C Q
MHz CLA A E Communication Ports
(x16) (x16) Comp* (ch) / (HR)* P P
F28020 40 16Kw 3Kw No 1/2 7 / 13 8 (0) 1 0 SPI, SCI, I2C
F28032 60 32Kw 10Kw No 3 14 / 16 12(6) / 14(7) 1 1 SPI,SCI,I2C,LIN,eCAN

F28033 60 32Kw 10Kw Yes 3 14 / 16 12(6) / 14(7) 1 1 SPI,SCI,I2C,LIN,eCAN
F28034 60 64Kw 10Kw No 3 14 / 16 12(6) / 14(7) 1 1 SPI,SCI,I2C,LIN,eCAN
F28035 60 64Kw 10Kw Yes 3 14 / 16 12(6) / 14(7) 1 1 SPI,SCI,I2C,LIN,eCAN
* number dependent on package type: F2802x – 38/48 pins, F2803x – 64/80 pins
• All devices have VREG, POR/BOR, Watchdog, OTP, CPU Timers
For details and information on other C2000 family members refer to the “Embedded Proc essing Guide” and specific “Data Manuals”
Piccolo™ ControlSTICK
LED LD1 LED LD2 TMS320F28027

(Power) (GPIO34) 48-Pin Package
USB JTAG On-board USB Peripheral

Interface & Power JTAG Emulation Header Pins

TMS320F2802x/3x Block Diagram
Program Bus
ePWM
Boot eCAP
Sectored RAM
ROM
Flash eQEP
CLA Bus
12-bit ADC
Watchdog
PIE
32-bit R-M-W Interrupt CAN 2.0B
32x32 bit Manager
Auxiliary Atomic CLA
Multiplier I2C
Registers ALU
3
Real-Time SCI
32-bit
JTAG Register Bus Timers SPI
Emulation CPU
LIN
Data Bus
GPIO
Available only on TMS320F2803x devices: CLA, QEP, CAN, LIN
TMS320F28027 Memory Map

Data Program
0x000000
M0 SARAM (1Kw)
0x000400 0x3D7C80
M1 SARAM (1Kw) ADC / OSC cal. data
0x000800 0x3D8000
reserved
0x000D00 PIE Vectors
0x3F0000
(256 w )
0x000E00 reserved FLASH (32Kw)
PF 0 (6Kw)
0x002000 0x3F7FF8
PASSWORDS (8w)
0x006000 0x3F8000
PF 1 (4Kw) L0 SARAM (4Kw)
0x007000 0x3F9000
PF 2 (4Kw) reserved
0x008000 0x3FE000
L0 SARAM (4Kw) Boot ROM (8Kw)
0x009000
reserved 0x3FFFC0
0x3D7800 0x3FFFFF BROM Vectors (64w)
User OTP (1Kw)
0x3D7C00 Data Program
reserved
0x3D7C80
Dual Mapped: L0
CSM Protected:
L0, OTP
FLASH, ADC CAL,
Flash Regs in PF0

F28x Fast Interrupt Response Manager

96 dedicated PIE
vectors
PIE module
No software decision
Peripheral Interrupts 12x8 = 96

For 96 28x CPU Interrupt logic
interrupts
making required
INT1 to
Direct access to RAM INT12
vectors 96 12 interrupts IFR IER
28x
PIE INTM CPU
Auto flags update Register
Concurrent auto Map
context save
Auto Context Save
T ST0
AH AL
PH PL
AR1 (L) AR0 (L)
DP ST1
DBSTAT IER
PC(msw) PC(lsw)


Code Composer Studio
Code Composer Studio: IDE
Integrates: edit, code generation,

and debug
Single-click access using buttons
Powerful graphing/profiling tools
Automated tasks using Scripts
Built-in access to BIOS functions
Based on the Eclipse open

source software framework
C/C++ and Debug Perspective (CCSv4)

Each Perspective provides a set of functionality
aimed at accomplishing a specific task
C/C++ Perspective Debug Perspective

Displays views used Displays views used for
during code development debugging
C/C++ project, editor, etc. Menus and toolbars
associated with debugging,
watch and memory
windows, graphs, etc.

CCSv4 Project
Project files contain:
List of files:
Source (C, assembly)
Libraries
DSP/BIOS configuration file
Linker command files
Project settings:
Build options (compiler,
Linker, assembler, and
DSP/BIOS)
Build configurations
Creating a New CCSv4 Project

3
File Æ New Æ CCS Project

CCSv4 Build Options – Compiler / Linker
Compiler Linker
16 categories for code 9 categories for linking
generation tools Specify various link
Controls many aspects of options
the build process, such as: ${PROJECT_ROOT}
Optimization level specifies the current
Target device
project directory
Compiler / assembly / link
options
Linking Sections in Memory

Sections
Global vars (.ebss) Init values (.cinit)
All code consists of

int x = 2; different parts called
int y = 7; sections
All default section
names begin with “.”
void main(void) The compiler has
{ default section
names for initialized
long z; and uninitialized
z = x + y; sections
Local vars (.stack) Code (.text)

Compiler Section Names

Initialized Sections
Name Description Link Location
.text code FLASH
.cinit initialization values for FLASH
global and static variables
.econst constants (e.g. const int k = 3;) FLASH
.switch tables for switch statements FLASH
.pinit tables for global constructors (C++) FLASH
Uninitialized Sections
Name Description Link Location
.ebss global and static variables RAM
.stack stack space low 64Kw RAM
.esysmem memory for far malloc functions RAM
Note: During development initialized sections could be linked to RAM since

the emulator can be used to load the RAM
Placing Sections in Memory
Memory
Sections
0x00 0000 M0SARAM
(0x400)
.ebss
0x00 0400 M1SARAM
(0x400)
.stack
0x3F 0000 FLASH .cinit

(0x8000)
.text

Linking
z Memory description
z How to place s/w into h/w
Link.cmd
.obj Linker .out
.map
Linker Command File

MEMORY
{
PAGE 0: /* Program Memory */
FLASH: origin = 0x3F0000, length = 0x8000
PAGE 1: /* Data Memory */

M0SARAM: origin = 0x000000, length = 0x400
M1SARAM: origin = 0x000400, length = 0x400
}
SECTIONS
{
.text:> FLASH PAGE = 0
.ebss:> M0SARAM PAGE = 1
.cinit:> FLASH PAGE = 0
.stack:> M1SARAM PAGE = 1
}

Lab 1: Linker Command File

¾ Objective
Use a linker command file to link the C program file (Lab1.c) into the system described below.

Memory 0x00 0000 M0SARAM
(0x400)
on-chip
0x00 0400 M1SARAM
memory
(0x400)
0x00 8000 L0SARAM
F28027 (0x1000)
System Description:
• TMS320F28027
• All internal RAM
blocks allocated
Placement of Sections:
• .text into RAM Block L0SARAM on PAGE 0 (program memory)
• .cinit into RAM Block L0SARAM on PAGE 0 (program memory)
• .ebss into RAM Block M0SARAM on PAGE 1 (data memory)
• .stack into RAM Block M1SARAM on PAGE 1 (data memory)
System Description
• TMS320F28027
• All internal RAM blocks allocated
Placement of Sections:
• .text into RAM Block L0SARAM on PAGE 0 (program memory)
• .cinit into RAM Block L0SARAM on PAGE 0 (program memory)
• .ebss into RAM Block M0SARAM on PAGE 1 (data memory)
• .stack into RAM Block M1SARAM on PAGE 1 (data memory)
¾ Procedure
Start Code Composer Studio and Open a Workspace

1. Start Code Composer Studio (CCS) by double clicking the icon on the desktop or
selecting it from the Windows Start menu. When CCS loads, a dialog box will prompt
you for the location of a workspace folder. Use the default location for the workspace
and click OK.

This folder contains all CCS custom settings, which includes project settings and views
when CCS is closed so that the same projects and settings will be available when CCS is
opened again. The workspace is saved automatically when CCS is closed.
2. The first time CCS opens a “Welcome to Code Composer Studio v4” page appears.
Close the page by clicking on the CCS icon in the upper right or by clicking the X on the
“Welcome” tab. You should now have an empty workbench. The term workbench refers
to the desktop development environment. Maximize CCS to fill your screen.
The workbench will open in the “C/C++ Perspective” view. Notice the C/C++ icon in
the upper right-hand corner. A perspective defines the initial layout views of the
workbench windows, toolbars, and menus which are appropriate for a specific type of
task (i.e. code development or debugging). This minimizes clutter to the user interface.
The “C/C++ Perspective” is used to create or build C/C++ projects. A “Debug
Perspective” view will automatically be enabled when the debug session is started. This
perspective is used for debugging C/C++ projects.
Setup Target Configuration

3. Open the emulator target configuration dialog box. On the menu bar click:
Target Æ New Target Configuration…
In the file name field type F28027_ctrlSTK.ccxml. This is just a descriptive name since
multiple target configuration files can be created. Leave the “use shared location” box
checked and select Finish.
4. In the next window that appears, select the emulator using the “Connection” pull-down
list and choose “Texas Instruments XDS100v1 USB Emulator”. In the box
below, check the box to select “controlSTICK – Piccolo F28027”. Click
Save to save the configuration, then close the “Cheat Sheets” and
“F28027_ctrlSTK.ccxml” file by clicking the X on the tabs.
5. To view the target configurations, click:
View Æ Target Configurations
and click the plus sign (+) to the left of User Defined. Notice that the
F28027_ctrlSTK.ccxml file is listed and set as the default. If it is not set as the default,
right-click on the .ccxml file and select “Set as Default”. Close the Target Configurations
window by clicking the X on the tab.
Create a New Project

6. A project contains all the files you will need to develop an executable output file (.out)
which can be run on the MCU hardware. To create a new project click:
File Æ New Æ CCS Project
In the Project name field type Lab1. Uncheck the “use default location” box. Click the
Browse… button and navigate to:

C:\C28x\Labs\Lab1\Project
Click OK and then click Next.
7. The next window that appears selects the platform and configurations. Select the
“Project Type” using the pull-down list and choose “C2000”. In the “Configurations”
box below, leave the “Debug” and “Release” boxes checked. This will create folders that
will hold the output files. Click Next.
8. In the next window, inter-project dependencies (if any) are defined. Select Next.
9. In the last window, the CCS project settings are selected. Change the “Runtime Support
Library” using the pull-down list to “rts2800_ml.lib”. This will select the large
memory model runtime support library. Click Finish.
10. A new project has now been created. Notice the C/C++ Projects window contains
Lab1. The project is set Active and the output files will be located in the Debug
folder. At this point, the project does not include any source files. The next step is to add
the source files to the project.
11. To add the source files to the project, right-click on Lab1 in the C/C++ Projects
window and select:
Add Files to Project…
or click: Project Æ Add Files to Active Project…
and make sure you’re looking in C:\C28x\Labs\Lab1\Files. With the “files of

type” set to view all files (*.*) select Lab1.c and Lab1.cmd then click OPEN. This
will add the files to the project.
12. In the C/C++ Projects window, click the plus sign (+) to the left of Lab1 and notice
that the files are listed.
Project Build Options

13. There are numerous build options in the project. Most default option settings are
sufficient for getting started. We will inspect a couple of the default options at this time.
Right-click on Lab1 in the C/C++ Projects window and select Properties or
click:
Project Æ Properties
14. A “Properties” window will open and in the section on the left be sure that “C/C++
Build” category is selected. In the “Configuration Settings” section make sure that the
Tool Settings tab is selected. Next, under “C2000 Linker” select the “Basic
Options”. Notice that .out and .map files are being specified. The .out file is the
executable code that will be loaded into the MCU. The .map file will contain a linker
report showing memory usage and section addresses in memory.
15. Next in the “Basic Options” set the Stack Size to 0x200.

16. Under “C2000 Compiler” select the “Runtime Model Options”. Check the “Use
large memory model” box. Select OK to save and close the Properties window.
Linker Command File – Lab1.cmd

17. Open and inspect Lab1.cmd by double clicking on the filename in the project window.
Notice that the Memory{} declaration describes the system memory shown on the
“Lab1: Linker Command File” slide in the objective section of this lab exercise.
Memory block L0SARAM has been placed in program memory on page 0, and the other
memory blocks have been placed in data memory on page 1.
18. In the Sections{} area notice that the sections defined on the slide have been “linked”
into the appropriate memories. Also, notice that a section called .reset has been allocated.
The .reset section is part of the rts2800_ml.lib, and is not needed. By putting the TYPE =
DSECT modifier after its allocation, the linker will ignore this section and not allocate it.
Close the inspected file.
Build and Load the Project

19. Three buttons on the horizontal toolbar control code generation. Hover your mouse over
each button as you read the following descriptions:
Button Name Description_____________________________________

1 Build Incremental build and link of only modified source files
2 Rebuild Full build and link of all source files
3 Debug Automatically build, link, load and launch debug-session
20. Click the “Build” button and watch the tools run in the Console window. Check for
errors in the Problems window (we have deliberately put an error in Lab1.c). When
you get an error, you will see the error message (in red) in the Problems window, and
simply double-click the error message. The editor will automatically open to the source
file containing the error, and position the mouse cursor at the correct code line.
21. Fix the error by adding a semicolon at the end of the “z = x + y” statement. For
future knowlege, realize that a single code error can sometimes generate multiple error
messages at build time. This was not the case here.
22. Build the project again. There should be no errors this time.
23. CCS can automatically save modified source files, build the program, open the debug
perspective view, connect and download it to the target, and then run the program to the
beginning of the main function.
Click on the “Debug” button (green bug) or click Target Æ Debug Active
Project.
Notice the Debug icon in the upper right-hand corner indicating that we are now in the
“Debug Perspective” view. The program ran through the C-environment initialization
routine in the rts2800_ml.lib and stopped at main() in Lab1.c.

Debug Enviroment Windows

It is standard debug practice to watch local and global variables while debugging code. There
are various methods for doing this in Code Composer Studio. We will examine two of them
here: memory windows, and watch windows.
24. Open a memory window to view the global variable “z”.
Click: View Æ Memory on the menu bar.
Type &z into the address field and select “Data” memory page. Note that you must use
the ampersand (meaning “address of”) when using a symbol in a memory window
address box. Also note that Code Composer Studio is case sensitive.
Set the properties format to “Hex 16 Bit – TI Style Hex” in the window. This will give
you more viewable data in the window. You can change the contents of any address in
the memory window by double-clicking on its value. This is useful during debug.
25. Notice the watch window automatically opened and the local variables x and y are
present. (The watch window can be manually opened by clicking: View Æ Watch
Window on the menu bar). The watch window will always contain the local variables
for the code function currently being executed.
(Note that local variables actually live on the stack. You can also view local variables in
a memory window by setting the address to “SP” after the code function has been
entered).
26. We can also add global variables to the watch window if desired. Let's add the global
variable “z”.
Click the “Watch (1)” tab at the top of the watch window. In the empty box in the
“Name” column, type z and then enter. An ampersand is not used here. The watch
window knows you are specifying a symbol.
Check that the watch window and memory window both report the same value for “z”.
Trying changing the value in one window, and notice that the value also changes in the
other window.
Single-stepping the Code

27. Click the “Local (1)” tab at the top of the watch window. Single-step through main()
by using the <F5> key (or you can use the Step Into button on the horizontal
toolbar). Check to see if the program is working as expected. What is the value for “z”
when you get to the end of the program?
Terminate Debug Session and Close Project

28. The Terminate All button will terminate the active debug session, close the
debugger and return CCS to the “C/C++ Perspective” view.

Click: Target Æ Terminate All or use the Terminate All icon:
Close the Terminate Debug Session “Cheat Sheet” by clicking on the X on the tab.
29. Next, close the project by right-clicking on Lab1 in the C/C++ Projects window
and select Close Project.
End of Exercise


Traditional Approach to C Coding
#define ADCCTL1 (volatile unsigned int *)0x00007100
...
void main(void)
{
*ADCCTL1 = 0x1234; //write entire register
*ADCCTL1 |= 0x4000; //enable ADC module
}
Advantages - Simple, fast and easy to type

- Variable names exactly match register names (easy
to remember)
Disadvantages - Requires individual masks to be generated to
manipulate individual bits
- Cannot easily display bit fields in debugger window
- Will generate less efficient code in many cases
Structure Approach to C Coding

void main(void)
{
AdcRegs.ADCCTL1.all = 0x1234; //write entire register
AdcRegs.ADCCTL1.bit.ADCENABLE = 1; //enable ADC module
}
Advantages - Easy to manipulate individual bits

- Watch window is amazing! (next slide)
- Generates most efficient code (on C28x)
Disadvantages - Can be difficult to remember the structure names

(Editor Auto Complete feature to the rescue!)
- More to type (again, Editor Auto Complete feature
to the rescue)

Built-in CCSv4 Register Window
CCSv4 Watch Window using Structures

Structure Naming Conventions

The DSP2802x header files define:
All of the peripheral structures
All of the register names
All of the bit field names
All of the register addresses
PeripheralName.RegisterName.all // Access full 16 or 32-bit register
PeripheralName.RegisterName.half.LSW // Access low 16-bits of 32-bit register
PeripheralName.RegisterName.half.MSW // Access high 16-bits of 32-bit register
PeripheralName.RegisterName.bit.FieldName // Access specified bit fields of register
Notes: [1] “PeripheralName” are assigned by TI and found in the DSP2802x header files.
They are a combination of capital and small letters (i.e. CpuTimer0Regs).
[2] “RegisterName” are the same names as used in the data sheet.
They are always in capital letters (i.e. TCR, TIM, TPR,..).
[3] “FieldName” are the same names as used in the data sheet.
They are always in capital letters (i.e. POL, TOG, TSS,..).
Editor Auto Complete to the Rescue!

DSP2802x Header File Package

(http://www.ti.com, literature # SPRC832)
Contains everything needed to use the

structure approach
Defines all peripheral register bits and
register addresses
Header file package includes:
\DSP2802x_headers\include Æ .h files
\DSP2802x_headers\cmd Æ linker .cmd files
\DSP2802x_headers\gel Æ .gel files for CCS
\DSP2802x_examples Æ CCS3 examples
\DSP2802x_examples_ccsv4 Æ CCS4 examples
\doc Æ documentation
Peripheral Structure .h files (1 of 2)

Contain bits field structure definitions for each peripheral register
DSP2802x_Adc.h
// ADC Individual Register Bit Definitions:
struct ADCCTL1_BITS { // bits description
Uint16 TEMPCONV:1; // 0 Temperature sensor connection
Uint16 VREFLOCONV:1; // 1 VSSA connection
Your C-source file (e.g., Adc.c) Uint16 INTPULSEPOS:1; // 2 INT pulse generation control
Uint16 ADCREFSEL:1; // 3 Internal/external reference select
#include "DSP2802x_Device.h"
Uint16 rsvd1:1; // 4 reserved
Uint16 ADCREFPWD:1; // 5 Reference buffers powerdown
Void InitAdc(void)
Uint16 ADCBGPWD:1; // 6 ADC bandgap powerdow n
{
Uint16 ADCPWDN:1; // 7 ADC powerdown
/* Reset the ADC m odule */
Uint16 ADCBSYCHN:5; // 12:8 ADC busy on a channel
AdcRegs.ADCCTL1.bit.RESET = 1;
Uint16 ADCBSY:1; // 13 ADC busy signal
Uint16 ADCENABLE:1; // 14 ADC enable
/* configure the ADC register */
Uint16 RESET:1; // 15 ADC master reset
AdcRegs.ADCCTL1.all = 0x00E4;
};
};
// Allow access to the bit fields or entire register:
union ADCCTL1_REG {
Uint16 all;
struct ADCCTL1_BITS bit;
};
// ADC External References & Function Declarations:
extern volatile struct ADC_REGS AdcRegs;

Peripheral Structure .h files (2 of 2)

The header file package contains a .h file
for each peripheral in the device
DSP2802x_Adc.h DSP2802x_BootVars.h DSP2802x_Comp.h
DSP2802x_CpuTimers.h DSP2802x_DevEmu.h DSP2802x_Device.h
DSP2802x_ECap.h DSP2802x_EPwm.h DSP2802x_Gpio.h
DSP2802x_I2c.h DSP2802x_NmiIntrupt.h DSP2802x_PieCtrl.h
DSP2802x_PieVect.h DSP2802x_Sci.h DSP2802x_Spi.h
DSP2802x_SysCtrl.h DSP2802x_XIntrupt.h
DSP2802x_Device.h
Main include file
Will include all other .h files
Include this file (directly or indirectly)
in each source file:
#include “DSP2802x_Device.h”
Global Variable Definitions File

DSP2802x_GlobalVariableDefs.c
Declares a global instantiation of the structure

for each peripheral
Each structure is placed in its own section
using a DATA_SECTION pragma to allow
linking to the correct memory (see next slide)
#include "DSP2802x_Device.h"
…
#pragma DATA_SECTION(AdcRegs,"AdcRegsFile");
volatile struct ADC_REGS AdcRegs;
…
Add this file to your CCS project:


Linker Command Files for the Structures

DSP2802x_nonBIOS.cmd
#include "DSP2802x_Device.h" Links each structure to
…
the address of the
peripheral using the
#pragma DATA_SECTION(AdcRegs,"AdcRegsFile");
structures named
volatile struct ADC_REGS AdcRegs; section
…
DSP2802x_Headers_nonBIOS.cmd
MEMORY Add this file to your
{ CCS project:
PAGE1:
... DSP2802x_nonBIOS.cmd
ADC: origin=0x007100, length=0x000080
...
}
SECTIONS
{
...
AdcRegsFile: > ADC PAGE = 1
...
}
Peripheral Specific Examples
Example projects for each peripheral

Helpful to get you started


Summary
Easier code development
Easy to use
Generates most efficient code
Increases effectiveness of CCS watch window
TI has already done all the work!
Use the correct header file package for your device:
F2802x # SPRC832
F2803x # SPRC892
F2833x and F2823x # SPRC530
F280x and F2801x # SPRC191
F2804x # SPRC324
F281x # SPRC097
Go to http://www.ti.com and enter the literature number in the keyword search box


Reset
Reset Sources
Missing Clock Detect F28x core

Watchdog Timer
Power-on Reset XRS
Brown-out Reset
XRS pin active
To XRS pin
Logic shown is functional representation, not actual implementation
POR – Power-on Reset generates a device reset during

power-up conditions
BOR – Brown-out Reset generates a device reset if the
power supply drops below specification for the device
Note: Devices support an on-chip voltage regulator (VREG) to
generate the core voltage
Reset – Bootloader
Reset Reset vector
OBJMODE = 0 fetched from Bootloader sets
AMODE = 0 boot ROM OBJMODE = 1
ENPIE = 0 AMODE = 0
0x3F FFC0
INTM = 1
YES Emulator NO
TRST = 1 Connected ? TRST = 0
Emulation Boot Stand-alone Boot

Boot determined by Boot determined by
2 RAM locations: 2 GPIO pins and
EMU_KEY and EMU_BMODE 2 OTP locations:
OTP_KEY and OTP_BMODE
TRST = JTAG Test Reset EMU_KEY & EMU_BMODE located in PIE at 0x0D00 & 0x0D01, respectively
OTP_KEY & OTP_BMODE located in OTP at 0x3D78FE & 0x3D78FF, respectively

Emulation Boot Mode (TRST = 1)

Emulator Connected
Emulation Boot If either EMU_KEY or EMU_BMODE
are invalid, the “wait” boot mode is
Boot determined by used. These values can then be
2 RAM locations: modified using the debugger and a
EMU_KEY and EMU_BMODE reset issued to restart the boot process
NO Boot Mode
EMU_KEY = 0x55AA ?
Wait
YES
EMU_BMODE = Boot Mode NO Boot Mode

0x0000 Parallel I/O OTP_KEY = 0x55AA ?
FLASH
0x0001 SCI
YES
0x0003 GetMode
0x0004 SPI OTP_BMODE = Boot Mode
0x0005 I2C 0x0001 SCI
0x0006 OTP 0x0004 SPI
0x000A M0 SARAM 0x0005 I2C
0x000B FLASH 0x0006 OTP
other Wait other FLASH
Stand-Alone Boot Mode (TRST = 0)
Emulator Not Connected

Note that the boot behavior for
Stand-alone Boot unprogrammed OTP is the
“FLASH” boot mode
Boot determined by
2 GPIO pins and
2 OTP locations:
OTP_KEY and OTP_BMODE
NO Boot Mode
OTP_KEY = 0x55AA ?
FLASH
GPIO GPIO YES
37 34 Boot Mode OTP_BMODE = Boot Mode
0 0 Parallel I/O 0x0001 SCI
0 1 SCI 0x0004 SPI
1 0 Wait 0x0005 I2C
1 1 GetMode 0x0006 OTP
other FLASH

Reset Code Flow - Summary

0x000000 0x000000
M0 SARAM (1Kw)
0x3D7800 0x3D7800
OTP (1Kw)
0x3F0000
FLASH (32Kw)
0x3F7FF6
0x3FE000 Boot ROM (8Kw) Execution Entry

determined by
Boot Code Emulation Boot Mode or
0x3FF7BB Stand-Alone Boot Mode
• •
• •
BROM vector (64w)

RESET 0x3FFFC0 0x3FF7BB Bootloading
Routines
(SCI, SPI, I2C,
Parallel I/O)
Interrupts
Interrupt Sources
Internal Sources
TINT2
TINT1 F28x CORE
TINT0 XRS
NMI
ePWM, eCAP, PIE INT1
ADC, SCI, SPI, (Peripheral
I2C, WD Interrupt INT2
Expansion) INT3
•
•
•
External Sources
INT12
INT13
XINT1 – XINT3
INT14
TZx
XRS

Maskable Interrupt Processing

Conceptual Core Overview
Core (IFR) (IER) (INTM)

Interrupt “Latch” “Switch” “Global Switch”
INT1 1
INT2 0 C28x
Core
INT14 1
A valid signal on a specific interrupt line causes the latch

to display a “1” in the appropriate bit
If the individual and global switches are turned “on” the

interrupt reaches the core
Core Interrupt Registers

Interrupt Flag Register (IFR) (pending = 1 / absent = 0)
15 14 13 12 11 10 9 8
RTOSINT DLOGINT INT14 INT13 INT12 INT11 INT10 INT9
INT8 INT7 INT6 INT5 INT4 INT3 INT2 INT1
7 6 5 4 3 2 1 0
Interrupt Enable Register (IER) (enable = 1 / disable = 0)
15 14 13 12 11 10 9 8
RTOSINT DLOGINT INT14 INT13 INT12 INT11 INT10 INT9
INT8 INT7 INT6 INT5 INT4 INT3 INT2 INT1
7 6 5 4 3 2 1 0
Interrupt Global Mask Bit (INTM) Bit 0
ST1 INTM (enable = 0 / disable = 1)
/*** Interrupt Enable Register ***/

extern cregister volatile unsigned int IER;
IER |= 0x0008; //enable INT4 in IER
IER &= 0xFFF7; //disable INT4 in IER
/*** Global Interrupts ***/
asm(“ CLRC INTM”); //enable global interrupts
asm(“ SETC INTM”); //disable global interrupts

Peripheral Interrupt Expansion (PIE)

Peripheral Interrupt Expansion - PIE
Interrupt Group 1
PIE module for 96 Interrupts
Peripheral Interrupts 12x8 = 96 PIEIFR1 PIEIER1
INT1.x interrupt group INT1.1 1
INT2.x interrupt group
INT1.2 0
INT3.x interrupt group INT1
• •
INT4.x interrupt group • •
• •
INT5.x interrupt group INT1.8 1
96
28x Core Interrupt logic
INT1 – INT12
INTM
INT10.x interrupt group 28x
IFR
IER
12 Interrupts
INT11.x interrupt group Core
INT13 (TINT1)
INT14 (TINT2)
NMI
F2802x PIE Interrupt Assignment Table

INTx.8 INTx.7 INTx.6 INTx.5 INTx.4 INTx.3 INTx.2 INTx.1
INT1 WAKEINT TINT0 ADCINT9 XINT2 XINT1 ADCINT2 ADCINT1

EPWM4 EPWM3 EPWM2 EPWM1
INT2 _TZINT _TZINT _TZINT _TZINT
EPWM4 EPWM3 EPWM2 EPWM1
INT3 _INT _INT _INT _INT
INT4 ECAP1
_INT
INT5
INT6 SPITX SPIRX

INTA INTA
INT7
INT8 I2CINT2A I2CINT1A

SCITX SCIRX
INT9 INTA INTA
INT10 ADCINT8 ADCINT7 ADCINT6 ADCINT5 ADCINT4 ADCINT3 ADCINT2 ADCINT1
INT11
INT12 XINT3

PIE Registers
PIEIFRx register (x = 1 to 12)
15 - 8 7 6 5 4 3 2 1 0
reserved INTx.8 INTx.7 INTx.6 INTx.5 INTx.4 INTx.3 INTx.2 INTx.1
PIEIERx register (x = 1 to 12)

15 - 8 7 6 5 4 3 2 1 0
reserved INTx.8 INTx.7 INTx.6 INTx.5 INTx.4 INTx.3 INTx.2 INTx.1
PIE Interrupt Acknowledge Register (PIEACK)

15 - 12 11 10 9 8 7 6 5 4 3 2 1 0
reserved PIEACKx
PIECTRL register 15 - 1 0
PIEVECT ENPIE
#include “DSP2802x_Device.h”
PieCtrlRegs.PIEIFR1.bit.INTx4 = 1; //manually set IFR for XINT1 in PIE group 1
PieCtrlRegs.PIEIER3.bit.INTx2 = 1; //enable EPWM2_INT in PIE group 3
PieCtrlRegs.PIEACK.all = 0x0004; //acknowledge the PIE group 3
PieCtrlRegs.PIECTRL.bit.ENPIE = 1; //enable the PIE
Default Interrupt Vector Table at Reset

Vector Offset
RESET 00 Default Vector Table
INT1 02 Re-mapped when
INT2 04 ENPIE = 1
INT3 06 Memory
INT4 08 0
INT5 0A
INT6 0C
INT7 0E
INT8 10
INT9 0x00 0D00
12
INT10 14
PIE Vectors
256w
INT11 16
INT12 18
INT13 1A
INT14 1C BROM Vectors 0x3F FFC0
DATALOG 1E 64w
20 ENPIE = 0
RTOSINT 0x3F FFFF
EMUINT 22
NMI 24
PieVectTableInit{ }
ILLEGAL 26
Used to initialize PIE vectors
USER 1-12 28-3E

Oscillator / PLL Clock Module

F2802x Oscillator / PLL Clock Module
(lab file: SysCtrl.c)
WDCLKSRCSEL
Internal OSC1CLK
OSC 1 0* WDCLK Watchdog
(10 MHz) 1 Module
OSCCLKSRCSEL
OSCCLKSRC2
Internal OSC2CLK 0* OSCCLK DIVSEL

OSC 2 1 (PLL bypass)
(10 MHz) 1
MUX
0* CLKIN
1/n C28x
VCOCLK Core
PLL
XCLKINOFF SYSCLKOUT
XCLKIN DIV
0*
EXTCLK LOSPCP
0 1 TMR2CLKSRCSEL
X1
XTAL OSC
10 LSPCLK
11 CPUTMR2CLK
XTAL
SCI, SPI
01 All other peripherals
SYSCLKOUT 00* CPU clocked by SYSCLKOUT
X2 Timer 2
* = default
F2802x PLL and LOSPCP

(lab file: SysCtrl.c)
SysCtrlRegs.PLLSTS.bit.DIVSEL
OSCCLK
(PLL bypass)
C28x
MUX
CLKIN SYSCLKOUT
1/n Core
LSPCLK
VCOCLK LOSPCP
PLL
SysCtrlRegs.LOSPCP.bit.LSPCLK
SysCtrlRegs.PLLCR.bit.DIV
LSPCLK Peripheral Clk Freq
DIV CLKIN DIVSEL n 000 SYSCLKOUT / 1
0 00 0 OSCCLK / n * (PLL bypass) 0x /4 * 001 SYSCLKOUT / 2
0 00 1 OSCCLK x 1 / n 010 SYSCLKOUT / 4 *
10 /2
011 SYSCLKOUT / 6
0 01 0 OSCCLK x 2 / n 11 /1
0 01 1 OSCCLK x 3 / n 100 SYSCLKOUT / 8
* default 101 SYSCLKOUT / 10
0 10 0 OSCCLK x 4 / n Note: /1 mode can
0 10 1 OSCCLK x 5 / n 110 SYSCLKOUT / 12
only be used when 111 SYSCLKOUT / 14
0 11 0 OSCCLK x 6 / n PLL is bypassed
0 11 1 OSCCLK x 7 / n
1 00 0 OSCCLK x 8 / n
Input Clock Fail Detect Circuitry
1 00 1 OSCCLK x 9 / n
1 01 0 OSCCLK x 10 / n PLL will issue a “limp mode” clock (1-4 MHz) if input
1 01 1 OSCCLK x 11 / n clock is removed after PLL has locked.
1 10 0 OSCCLK x 12 / n An internal device reset will also be issued (XRSn
pin not driven).

Watchdog Timer Module

Watchdog Timer
Resets the C28x if the CPU crashes

Watchdog counter runs independent of CPU
If counter overflows, a reset or interrupt is
triggered (user selectable)
CPU must write correct data key sequence to
reset the counter before overflow
Watchdog must be serviced or disabled
within 131,072 WDCLK cycles after reset
This translates to 13.11 ms with a 10 MHz
WDCLK
Watchdog Timer Module

(lab file: Watchdog.c)
WDOVERRIDE
WDPS
WDCLK
Watchdog
/512
Prescaler WDDIS
8-bit Watchdog
Counter
CLR
WDRST
System
Reset Output
Pulse
WDCHK WDINT
55 + AA
Detector Good Key 3
/
/ Bad WDCHK Key
3
Watchdog 1 0 1
Reset Key
Register

GPIO
F2802x GPIO Grouping Overview
(lab file: Gpio.c)
GPIO Port A Mux1

Input
GPIO Port A
Register (GPAMUX1)
[GPIO 0 to 15] GPIO Port A
Direction Register Qual
(GPADIR)
GPIO Port A Mux2 [GPIO 0 to 31]
Register (GPAMUX2)
[GPIO 16 to 31]
Input
Internal Bus
GPIO Port B
GPIO Port B
GPIO Port B Mux1 Direction Register Qual
Register (GPBMUX1) (GPBDIR)
[GPIO 32 to 38] [GPIO 32 to 38]
ANALOG Port
ANALOG I/O Mux1 ANALOG Port
Direction Register
Register (AIOMUX1) (AIODIR)
[AIO 0 to 15] [AIO 0 to 15]
F2802x GPIO Pin Block Diagram

(lab file: Gpio.c)
Peripheral Peripheral Peripheral

I/O DIR Bit 1 2 3
GPxSET 0 = Input
GPxCLEAR 1 = Output
GPxTOGGLE
GPxDIR
GPxDAT
Out
• • 10
01
GPxMUX1
00• •11 GPxMUX2
I/O DAT
Bit (R/W) In MUX Control Bits *
00 = GPIO
01 = Peripheral 1
10 = Peripheral 2
11 = Peripheral 3
Input
Qualification
GPxPUD
• (GPIO 0-38)
GPxQSEL1
GPxQSEL2
Internal Pull-Up GPxCTRL
0 = enable (default GPIO 12-38)
1 = disable (default GPIO 0-11)
Pin
* See device datasheet for pin function selection matrices

F2802x GPIO Input Qualification
Input to GPIO and

pin peripheral
Qualification modules
SYSCLKOUT
Qualification available on ports A & B (GPIO 0 - 38) only

Individually selectable per pin samples taken
no qualification (peripherals only)
sync to SYSCLKOUT only
qualify 3 samples
qualify 6 samples
AIO pins are fixed as T T T
‘sync to SYSCLKOUT’ T = qual period
Lab 2: System Initialization
LAB2 files have been provided

LAB2 consists of two parts:
Part 1
Test behavior of watchdog when disabled and enabled
Part 2
Initialize peripheral interrupt expansion (PIE) vectors
and use watchdog to generate an interrupt
Modify, build, and test code using Code
Composer Studio


¾ Objective
The objective of this lab is to perform the processor system initialization. Additionally, the
peripheral interrupt expansion (PIE) vectors will be initialized and tested. The system
initialization for this lab will consist of the following:
• Setup the clock module – PLL, LOSPCP = /4, low-power modes to default values, enable
all module clocks
• Disable the watchdog – clear WD flag, disable watchdog, WD prescale = 1
• Setup watchdog system control register – DO NOT clear WD OVERRIDE bit, WD
generate a CPU reset
• Setup shared I/O pins – set all GPIO pins to GPIO function (e.g. a "00" setting for GPIO
function, and a “01”, “10”, or “11” setting for peripheral function.)
The first part of the lab exercise will setup the system initialization and test the watchdog
operation by having the watchdog cause a reset. In the second part of the lab exercise the PIE
vectors will be tested by using the watchdog to generate an interrupt. This lab will make use of
the DSP2802x C-code header files to simplify the programming of the device, as well as take care
of the register definitions and addresses. Please review these files, and make use of them in the
future, as needed.
¾ Procedure
Open the Project

1. A project named Lab2 has been created for this lab. Open the project by clicking on
Project Æ Import Existing CCS/CCE Eclipse Project. The “Import”
window will open then click Browse… next to the “Select root directory” box. Navigate
to: C:\C28x\Labs\Lab2\Project and click OK. Then click Finish to import the
project.
2. In the C/C++ Projects window, click the plus sign (+) to the left of Lab2 to view
the project files. All Build Options have been configured for this lab. The files used in
this lab are:
CodeStartBranch.asm Lab_2_3.cmd
DefaultIsr_2.c Main_2.c
DelayUs.asm PieCtrl.c
DSP2802x_GlobalVariableDefs.c PieVect.c
DSP2802x_Headers_nonBIOS.cmd SysCtrl.c
Gpio.c Watchdog.c

Modified Memory Configuration

3. Open and inspect the linker command file Lab_2_3.cmd. Notice that the user defined
section “codestart” is being linked to a memory block named BEGIN_M0. The
codestart section contains code that branches to the code entry point of the project. The
bootloader must branch to the codestart section at the end of the boot process. Recall that
the emulation boot mode "M0 SARAM" branches to address 0x000000 upon bootloader
completion.
The linker command file (Lab_2_3.cmd) has a new memory block named BEGIN_M0:
origin = 0x000000, length = 0x0002, in program memory. Additionally, the existing
memory block M0SARAM in data memory has been modified to avoid overlaps with this
new memory block.
System Initialization
4. Open and inspect SysCtrl.c. Notice that the PLL and module clocks have been
enabled.
5. Open and inspect Watchdog.c. Notice that watchdog control register (WDCR) is
configured to disable the watchdog, and the system control and status register (SCSR) is
configured to generate a reset.
6. Open and inspect Gpio.c. Notice that the shared I/O pins have been set to the GPIO
function, except for GPIO0 which will be used in the next lab exercise. Close the
inspected files.
Build and Load

errors in the Problems window.
8. Click the “Debug” button (green bug). The “Debug Perspective” view should open, the
program load automatically, and you should now be at the start of Main().
9. By default, in Emulation Boot Mode CCS is configured to automatically load values into
EMU_KEY and EMU_BMODE so that the bootloader will jump to “M0 SARAM” at
0x000000. This mode is very useful when running RAM-only based code during debug.
(Note that the default execution entry point can be changed to any of the valid boot mode
options, if desired).
Run the Code – Watchdog Reset

10. Place the cursor in the “main loop” section (on the asm(“ NOP”); instruction line)
and right click the mouse key and select Run To Line. This is the same as setting a
breakpoint on the selected line, running to that breakpoint, and then removing the
breakpoint.
11. Place the cursor on the first line of code in main() and set a breakpoint by right clicking
the mouse key and select Toggle Breakpoint. Notice that line is highlighted with a

blue dot indicating that the breakpoint has been set. Alternately, you can double-click in
the line number field to the left of the code line to set the breakpoint. The breakpoint is
set to prove that the watchdog is disabled. If the watchdog causes a reset, code execution
will stop at this breakpoint.
12. Run your code for a few seconds by using the Run button on the toolbar, or using
Target Æ Run on the menu bar. After a few seconds halt your code by using the
Halt button on the toolbar, or by using Target Æ Halt. Where did your code stop?
Are the results as expected? If things went as expected, your code should be in the
“main loop”.
13. Switch to the “C/C++ Perspective” view by clicking the C/C++ icon in the upper right-
hand corner. Modify the InitWatchdog() function to enable the watchdog (WDCR).
In Watchdog.c change the WDCR register value to 0x00A8. This will enable the
watchdog to function and cause a reset. Save the file.
14. Click the “Build” button. Select Yes to “Reload the program automatically”. Switch
back to the “Debug Perspective” view by clicking the Debug icon in the upper right-
hand corner.
15. Like before, place the cursor in the “main loop” section (on the asm(“ NOP”);
instruction line) and right click the mouse key and select Run To Line.
16. Run your code. Where did your code stop? Are the results as expected? If things went
as expected, your code should have stopped at the breakpoint. What happened is as
follows. While the code was running, the watchdog timed out and reset the processor.
The reset vector was then fetched and the ROM bootloader began execution. Since the
device is in emulation boot mode (i.e. the emulator is connected) the bootloader read the
EMU_KEY and EMU_BMODE values from the PIE RAM. These values were
previously set for boot to M0 SARAM bootmode by CCS. Since these values did not
change and are not affected by reset, the bootloader transferred execution to the
beginning of our code at address 0x000000 in the M0SARAM, and execution continued
until the breakpoint was hit in main( ).
Setup PIE Vector for Watchdog Interrupt

The first part of this lab exercise used the watchdog to generate a CPU reset. This was tested
using a breakpoint set at the beginning of main(). Next, we are going to use the watchdog
to generate an interrupt. This part will demonstrate the interrupt concepts learned in this
module.
17. Switch to the “C/C++ Perspective” view by clicking the C/C++ icon in the upper right-
hand corner. Notice that the following files are included in the project:
DefaultIsr_2.c
PieCtrl.c
PieVect.c
18. In Main_2.c, uncomment the code used to call the InitPieCtrl() function. There
are no passed parameters or return values, so the call code is simply:

InitPieCtrl();
19. Using the “PIE Interrupt Assignment Table” shown in the slides find the location for the
watchdog interrupt, “WAKEINT”. This is used in the next step.
PIE group #: # within group:
20. In main() notice the code used to enable global interrupts (INTM bit), and in
InitWatchdog() the code used to enable the “WAKEINT” interrupt in the PIE
(using the PieCtrlRegs structure) and to enable core INT1 (IER register).
21. Modify the system control and status register (SCSR) to cause the watchdog to generate
a WAKEINT rather than a reset. In Watchdog.c change the SCSR register value to
0x0002. Save the modified files.
22. Open and inspect DefaultIsr_2.c. This file contains interrupt service routines. The
ISR for WAKEINT has been trapped by an emulation breakpoint contained in an inline
assembly statement using “ESTOP0”. This gives the same results as placing a breakpoint
in the ISR. We will run the lab exercise as before, except this time the watchdog will
generate an interrupt. If the registers have been configured properly, the code will be
trapped in the ISR.
23. Open and inspect PieCtrl.c. This file is used to initialize the PIE RAM and enable
the PIE. The interrupt vector table located in PieVect.c is copied to the PIE RAM to
setup the vectors for the interrupts. Close the modified and inspected files.
Build and Load

24. Click the “Build” button and select Yes to “Reload the program automatically”.
Switch to the “Debug Perspective” view by clicking the Debug icon in the upper right-
hand corner.
Run the Code – Watchdog Interrupt

25. Place the cursor in the “main loop” section, right click the mouse key and select Run
To Line.
26. Run your code. Where did your code stop? Are the results as expected? If things went
as expected, your code should stop at the “ESTOP0” instruction in the WAKEINT ISR.

27. Terminate the active debug session using the Terminate All button. This will close
the debugger and return CCS to the “C/C++ Perspective” view.

End of Exercise
Note: By default, the watchdog timer is enabled out of reset. Code in the file
CodeStartBranch.asm has been configured to disable the watchdog. This can be
important for large C code projects (ask your instructor if this has not already been
explained). During this lab exercise, the watchdog was actually re-enabled (or disabled
again) in the file Watchdog.c.

Control Peripherals
Control Peripherals
ADC Module
ADC Module Block Diagram
ADCINA0
ADCINA1 MUX S/H RESULT0
A A
RESULT1
ADCINA7 12-bit A/D Result
MUX
RESULT2
Converter MUX
ADCINB0
ADCINB1 MUX S/H SOC RESULT15
B B
ADCINB7
CHSEL ADC EOCx ADC ADCINT1-9
ADC full-scale Generation Interrupt
input range is Logic Logic
0 to 3.3V
SOCx Signal ADCINT1
ADCINT2
SOC0 TRIGSEL CHSEL ACQPS
SOCx Triggers
SOC1 TRIGSEL CHSEL ACQPS

SOC2 TRIGSEL CHSEL ACQPS Software
SOC3 TRIGSEL CHSEL ACQPS CPU Timer (0,1,2)
EPWMxSOCA (x = 1 to 7)
EPWMxSOCB (x = 1 to 7)
SOC15 TRIGSEL CHSEL ACQPS External Pin
SOCx Configuration Registers (GPIO/XINT2_ADCSOC)
Example – ADC Triggering (1 of 2)

Sample A2 Æ B3 Æ A7 when ePWM1 SOCB is generated and then generate ADCINT1n:
SOC0 Channel Sample

SOCB (ETPWM1)
A2 7 cycles Result0 no interrupt
SOC1 Channel Sample

B3 10 cycles Result1 no interrupt
SOC2 Channel Sample Result2 ADCINT1n

A7 8 cycles
As above, but also sample A0 Æ B0 Æ A5 continuously and generate ADCINT2n:

SOC0 Channel Sample no interrupt
SOCB (ETPWM1)
A2 7 cycles Result0
SOC1 Channel Sample
B3 10 cycles Result1 no interrupt
SOC2 Channel Sample Result2 ADCINT1n

Software Trigger A7 8 cycles
SOC3 Channel Sample no interrupt
A0 10 cycles Result3
SOC4 Channel Sample
ADCINT2n B0 15 cycles Result4 no interrupt
SOC5 Channel Sample

A5 12 cycles Result5 ADCINT2n

Control Peripherals
Example – ADC Triggering (2 of 2)

Sample all channels continuously and provide Ping-Pong interrupts to CPU/system:
Software Trigger SOC0 Channel Sample Result0

no interrupt
ADCINT2n A0:B0 7 cycles Result1
SOC2 Channel Sample Result2
no interrupt
A1:B1 7cycles Result3
no interrupt
A2:B2 7 cycles Result5
ADCINT1n
no interrupt
no interrupt
no interrupt
A7:B7 7 cycles ADCINT2n
Result15
Comparator
A0
B0
A1
B1
A2
AIO2 10-bit COMP1OUT
COMP1
AIO10 DAC
B2
A3
B3
A4 ADC
COMP2
AIO12 DAC
B4
A5
B5
A6
COMP3
AIO14 DAC
B6
A7
B7
Comparator 3 available only on TMS320F2803x devices

Control Peripherals
ADC Control Registers (file: Adc.c)

ADCTRL1 (ADC Control Register 1)
module reset, ADC enable
busy/busy channel
reference select
Interrupt generation control
ADCSOCxCTL (SOC0 to SOC15 Control Registers)
trigger source
channel
acquisition sampling window
ADCINTSOCSELx (Interrupt SOC Selection 1 and 2 Registers)
selects ADCINT1 / ADCINT2 trigger for SOCx
ADCSAMPLEMODE (Sampling Mode Register)
sequential sampling / simultaneous sampling
INTSELxNy (Interrupt x and y Selection Registers)
EOC0 – EOC15 source select for ADCINT1-9
ADCRESULTx (ADC Result 0 to 15 Registers)
Note: refer to the reference guide for a complete listing of registers
Pulse Width Modulation

What is Pulse Width Modulation?
PWM is a scheme to represent a

signal as a sequence of pulses
fixed carrier frequency
fixed pulse amplitude
pulse width proportional to
instantaneous signal amplitude
PWM energy ≈ original signal energy
t t
T
Original Signal PWM representation

Control Peripherals
Why use PWM with Power

Switching Devices?
Desired output currents or voltages are known
Power switching devices are transistors
Difficult to control in proportional region
Easy to control in saturated region
PWM is a digital signal ⇒ easy for DSP to output
DC Supply DC Supply
? PWM
Desired PWM approx.
signal to of desired
system signal
Unknown Gate Signal Gate Signal Known with PWM
ePWM
ePWM Module Signals and Connections
ePWMx -1
EPWMxSYNCI EPWMxTZINT
GPIO TZ1 – TZ3
EPWMxINT PIE
MUX
EQEP1ERR – TZ4 EPWMxA
eQEP1
GPIO
SYSCTRL
CLOCKFAIL – TZ5 ePWMx EPWMxB
MUX
EMUSTOP – TZ6
CPU
EPWMxSOCA
COMPxOUT EPWMxSOCB ADC
COMP
EPWMxSYNCO
ePWMx+1

Control Peripherals
ePWM Block Diagram
Shadowed Shadowed
Clock Compare Compare
Prescaler Register Register
16-Bit
Compare Action Dead
Time-Base
TBCLK Logic Qualifier Band
Counter
EPWMxSYNCI EPWMxSYNCO
Period
Register EPWMxA
PWM Trip
Shadowed
Chopper Zone
SYSCLKOUT EPWMxB
TZy
Digital TZ1-TZ3
Compare COMPxOUT
ePWM Time-Base Sub-Module
Shadowed Shadowed
16-Bit
Compare Action Dead
Time-Base
Counter
Period
Register EPWMxA
PWM Trip
Shadowed
Chopper Zone
SYSCLKOUT EPWMxB
TZy
Digital TZ1-TZ3
Compare COMPxOUT

Control Peripherals
ePWM Time-Base Count Modes

TBCTR
TBPRD
Asymmetrical
Waveform
Count Up Mode
TBCTR
TBPRD
Asymmetrical
Waveform
Count Down Mode

TBCTR
TBPRD
Symmetrical
Waveform
Count Up and Down Mode
ePWM Phase Synchronization

Ext. SyncIn
(optional)
Phase
φ=0°
En
o o .o
SyncIn
EPWM1A
CTR=zero o
CTR=CMPB o o EPWM1B
X o
SyncOut
To eCAP1
SyncIn
Phase
φ=120°
En
o o .o
SyncIn
EPWM2A φ=120°
CTR=zero o
CTR=CMPB o o EPWM2B
X o
SyncOut
Phase
φ=240°
En
o o .
SyncIn
EPWM3A
φ=120°
o
CTR=zero o
CTR=CMPB o o EPWM3B
X o
SyncOut φ=240°

Control Peripherals
ePWM Compare Sub-Module
Shadowed Shadowed
16-Bit
Compare Action Dead
Time-Base
Counter
Period
Register EPWMxA
PWM Trip
Shadowed
Chopper Zone
SYSCLKOUT EPWMxB
TZy
Digital TZ1-TZ3
Compare COMPxOUT
ePWM Compare Event Waveforms

TBCTR . = compare events are fed to the Action Qualifier Sub-Module
.. .. ..
TBPRD
CMPA Asymmetrical
CMPB Waveform
Count Up Mode
TBCTR
TBPRD
CMPA
CMPB
.. .. .. Asymmetrical
Waveform
Count Down Mode

TBCTR
.. .. .. ..
TBPRD
CMPA Symmetrical
CMPB Waveform
Count Up and Down Mode

Control Peripherals
ePWM Action Qualifier Sub-Module
Shadowed Shadowed
16-Bit
Compare Action Dead
Time-Base
Counter
Period
Register EPWMxA
PWM Trip
Shadowed
Chopper Zone
SYSCLKOUT EPWMxB
TZy
Digital TZ1-TZ3
Compare COMPxOUT
ePWM Action Qualifier Actions

for EPWMA and EPWMB
Time-Base Counter equals: EPWM

S/W Output
Force Actions
Zero CMPA CMPB TBPRD
SW Z CA CB P Do Nothing
X X X X X
SW Z CA CB P Clear Low
↓ ↓ ↓ ↓ ↓
SW Z CA CB P Set High
↑ ↑ ↑ ↑ ↑
SW Z CA CB P Toggle
T T T T T

Control Peripherals
ePWM Count Up Asymmetric Waveform

with Independent Modulation on EPWMA / B
TBCTR
TBPRD
. .
. .
Z P CB CA Z P CB CA Z P
↑ X X ↓ ↑ X X ↓ ↑ X
EPWMA
Z P CB CA Z P CB CA Z P
↑ X ↓ X ↑ X ↓ X ↑ X
EPWMB
ePWM Count Up Asymmetric Waveform

with Independent Modulation on EPWMA
TBCTR
TBPRD
. .
. .
CA CB CA CB
↑ ↓ ↑ ↓
EPWMA
Z Z Z
T T T
EPWMB

Control Peripherals
ePWM Count Up-Down Symmetric

Waveform
with Independent Modulation on EPWMA / B
TBCTR
. . . . . . . .
TBPRD
CA CA CA CA
↑ ↓ ↑ ↓
EPWMA
CB CB CB CB
↑ ↓ ↑ ↓
EPWMB
ePWM Count Up-Down Symmetric

Waveform
with Independent Modulation on EPWMA
TBCTR
TBPRD
. . . .
CA CB CA CB
↑ ↓ ↑ ↓
EPWMA
Z P Z P
↓ ↑ ↓ ↑
EPWMB

Control Peripherals
ePWM Dead-Band Sub-Module
Shadowed Shadowed
16-Bit
Compare Action Dead
Time-Base
Counter
Period
Register EPWMxA
PWM Trip
Shadowed
Chopper Zone
SYSCLKOUT EPWMxB
TZy
Digital TZ1-TZ3
Compare COMPxOUT
Motivation for Dead-Band
supply rail
gate signals are to power

complementary PWM switching
device
♦ Transistor gates turn on faster than they shut off

♦ Short circuit if both gates are on at same time!

Control Peripherals
ePWM PWM Chopper Sub-Module
Shadowed Shadowed
16-Bit
Compare Action Dead
Time-Base
Counter
Period
Register EPWMxA
PWM Trip
Shadowed
Chopper Zone
SYSCLKOUT EPWMxB
TZy
Digital TZ1-TZ3
Compare COMPxOUT
ePWM Chopper Waveform

Allows a high frequency carrier signal to
modulate the PWM waveform generated by the
Action Qualifier and Dead-Band modules
Used with pulse transformer-based gate drivers
to control power switching elements
EPWMxA
EPWMxB
CHPFREQ
EPWMxA
EPWMxB

Control Peripherals
ePWM Digital Compare Sub-Module
Shadowed Shadowed
16-Bit
Compare Action Dead
Time-Base
Counter
Period
Register EPWMxA
PWM Trip
Shadowed
Chopper Zone
SYSCLKOUT EPWMxB
TZy
Digital TZ1-TZ3
Compare COMPxOUT
Digital Compare Sub-Module Signals

Time-Base Sub-Module
DCAH Digital Trip Generate PWM Sync
TZ1 Event A1
Compare Event-Trigger Sub-Module
Generate SOCA
TZ2 Trip-Zone Sub-Module
Digital Trip
DCAL Event A2 Trip PWMA Output
Compare
TZ3 Generate Trip Interrupt
COMP1OUT Time-Base Sub-Module

DCBH Digital Trip Generate PWM Sync
COMP2OUT Event B1
Compare Event-Trigger Sub-Module
Generate SOCB
COMP3OUT Digital Trip Trip-Zone Sub-Module
DCBL
Event B2 Trip PWMB Output
Compare
Generate Trip Interrupt
DCTRIPSEL TZDCSEL DCACTL / DCBCTL
The Digital Compare sub-module compares signals external to the ePWM module to directly
generate events which are then feed to the Event-Trigger, Trip-Zone, and Time-Base sub-modules

Control Peripherals
ePWM Trip-Zone Sub-Module
Shadowed Shadowed
16-Bit
Compare Action Dead
Time-Base
Counter
Period
Register EPWMxA
PWM Trip
Shadowed
Chopper Zone
SYSCLKOUT EPWMxB
TZy
Digital TZ1-TZ3
Compare COMPxOUT
Trip-Zone Features
♦ Trip-Zone has a fast, clock independent logic path to high-impedance
the EPWMxA/B output pins
♦ Interrupt latency may not protect hardware when responding to over
current conditions or short-circuits through ISR software
♦ Supports: #1) one-shot trip for major short circuits or over
current conditions
#2) cycle-by-cycle trip for current limiting operation
Over
Current
Sensors EPWM1A
CPU
P
core EPWM1B W
COMPxOUT Digital
Compare M
EPWMxTZINT •
O
TZ1 Cycle-by-Cycle • U
TZ2
Mode • T
TZ3 P
eQEP1
TZ4 EQEP1ERR EPWMxA U
TZ5 CLOCKFAIL
One-Shot T
SYSCTRL EPWMxB S
TZ6 EMUSTOP Mode
CPU

Control Peripherals
ePWM Event-Trigger Sub-Module
Shadowed Shadowed
16-Bit
Compare Action Dead
Time-Base
Counter
Period
Register EPWMxA
PWM Trip
Shadowed
Chopper Zone
SYSCLKOUT EPWMxB
TZy
Digital TZ1-TZ3
Compare COMPxOUT
ePWM Event-Trigger Interrupts and SOC

TBCTR
. . . . . . . .
TBPRD
CMPB
CMPA
EPWMA
EPWMB
CTR = 0
CTR = PRD
CTR = 0 or PRD
CTRU = CMPA
CTRD = CMPA
CTRU = CMPB
CTRD = CMPB

Control Peripherals
Hi-Resolution PWM (HRPWM)

PWM Period
Regular
Device Clock PWM Step
(i.e. 60 MHz) (i.e. 16.67 ns)
HRPWM divides a clock Calibration Logic tracks the

cycle into smaller steps number of Micro Steps per
ms ms ms ms ms ms
called Micro Steps clock to account for
(Step Size ~= 150 ps) Calibration Logic variations caused by
Temp/Volt/Process
HRPWM
Micro Step (~150 ps)
Significantly increases the resolution of conventionally derived digital PWM

Uses 8-bit extensions to Compare registers (CMPxHR), Period register
(TBPRDHR) and Phase register (TBPHSHR) for edge positioning control
Typically used when PWM resolution falls below ~9-10 bits which occurs at
frequencies greater than ~120 kHz (with system clock of 60 MHz)
Not all ePWM outputs support HRPWM feature (see device datasheet)
ePWM Control Registers (file: EPwm.c)

TBCTL (Time-Base Control)
counter mode (up, down, up & down, stop); clock prescale; period
shadow load; phase enable/direction; sync select
CMPCTL (Compare Control)
compare load mode; operating mode (shadow / immediate)
AQCTLA/B (Action Qualifier Control Output A/B)
action on up/down CTR = CMPA/B, PRD, 0 (nothing/set/clear/toggle)
DBCTL (Dead-Band Control)
in/out-mode (disable / delay PWMxA/B); polarity select
PCCTL (PWM-Chopper Control)
enable / disable; chopper CLK freq. & duty cycle; 1-shot pulse width
DCTRIPSEL (Digital Compare Trip Select)
Digital compare A/B high/low input source select
TZCTL (Trip-Zone Control)
enable /disable; action (force high / low / high-Z /nothing)
ETSEL (Event-Trigger Selection)
interrupt & SOCA/B enable / disable; interrupt & SOCA/B select
Note: refer to the reference guide for a complete listing of registers

Control Peripherals
eCAP
Capture Module (eCAP)
Timer
Trigger
pin
Timestamp
Values
The eCAP module timestamps transitions

on a capture input pin
eCAP Module Block Diagram – Capture Mode

CAP1POL
Capture 1 Polarity
Register Select 1
CAP2POL
Capture 2 Polarity
Event Logic
Register Select 2 PRESCALE

32-Bit Event
Time-Stamp Prescale
Counter CAP3POL ECAPx
Capture 3 Polarity pin
Register Select 3
SYSCLKOUT
CAP4POL
Capture 4 Polarity
Register Select 4

Control Peripherals
eCAP Module Block Diagram – APWM Mode
Shadowed
Period
Period shadow
Register mode
immediate Register (CAP3)
mode
(CAP1)
32-Bit PWM
Time-Stamp Compare
Counter Logic ECAP
pin
SYSCLKOUT
Compare
immediate Register
mode Compare
shadow
(CAP2) Register mode
Shadowed (CAP4)
eQEP
What is an Incremental Quadrature

Encoder?
A digital (angular) position sensor
photo sensors spaced θ/4 deg. apart
slots spaced θ deg. apart θ/4

light source (LED)
θ
Ch. A
Ch. B
shaft rotation
Incremental Optical Encoder Quadrature Output from Photo Sensors
Note: eQEP available only on the TMS320F2803x devices

Control Peripherals
How is Position Determined from

Quadrature Signals?
Position resolution is θ/4 degrees
(00) (11)
increment decrement
(A,B) = counter 10 counter
(10) (01)
Illegal
Ch. A 00 Transitions;
generate 11
phase error
interrupt
Ch. B
01
Quadrature Decoder
State Machine
eQEP Module Connections
Ch. A
Quadrature Ch. B
Capture
EQEPxA/XCLK
32-Bit Unit EQEPxB/XDIR
Time-Base Quadrature
QEP Decoder EQEPxI Index
Watchdog
EQEPxS Strobe
from homing sensor
SYSCL KOUT
Position/Counter
Compare

Lab 3: Control Peripherals

¾ Objective
The objective of this lab is to demonstrate and become familiar with the operation of the on-chip
analog-to-digital converter and ePWM. ePWM1A will be setup to generate a 2 kHz, 25% duty
cycle symmetric PWM waveform. The waveform will then be sampled with the on-chip analog-
to-digital converter and displayed using the graphing feature of Code Composer Studio. The
ADC has been setup to sample a single input channel at a 50 kHz sampling rate and store the
conversion result in a buffer in the MCU memory. This buffer operates in a circular fashion, such
that new conversion data continuously overwrites older results in the buffer.
Two ePWM modules have been configured for this lab exercise:
ePWM1A – PWM Generation
• Used to generate a 2 kHz, 25% duty cycle symmetric PWM waveform
ePWM2 – ADC Conversion Trigger
• Used as a timebase for triggering ADC samples (period match trigger SOCA)
ePWM1
TB Counter CPU copies
data
Compare ADC result to
memory
connector
wire buffer during
Action Qualifier RESULT0
pointer rewind
ADC ISR
ADC-
INA0
...
View ADC
buffer PWM
ePWM2 triggering Samples
ADC on period match
using SOCA trigger every
20 µs (50 kHz) ePWM2 Code Composer
Studio
The software in this exercise configures the ePWM modules and the ADC. It is entirely interrupt
driven. The ADC end-of-conversion interrupt will be used to prompt the CPU to copy the results
of the ADC conversion into a results buffer in memory. This buffer pointer will be managed in a
circular fashion, such that new conversion results will continuously overwrite older conversion
results in the buffer. The ADC interrupt service routine (ISR) will also toggle LED LD2 on the
Piccolo™ ControlSTICK as a visual indication that the ISR is running.

Notes
• ePWM1A is used to generate a 2 kHz PWM waveform
• Program performs conversion on ADC channel A0 (ADCINA0 pin)
• ADC conversion is set at a 50 kHz sampling rate
• ePWM2 is triggering the ADC on period match using SOCA trigger
• Data is continuously stored in a circular buffer
• Data is displayed using the graphing feature of Code Composer Studio
• ADC ISR will also toggle the LED LD2 as a visual indication that it is running
¾ Procedure
Open the Project

project.
this lab are:
Adc.c Gpio.c
CodeStartBranch.asm Lab_2_3.cmd
DefaultIsr_3_4.c Main_3.c
DelayUs.asm PieCtrl.c
DSP2802x_GlobalVariableDefs.c PieVect.c
DSP2802x_Headers_nonBIOS.cmd SysCtrl.c
EPwm.c Watchdog.c
Setup of Shared I/O, General-Purpose Timer1 and Compare1
Note: DO NOT make any changes to Gpio.c and EPwm.c – ONLY INSPECT
3. Open and inspect Gpio.c by double clicking on the filename in the project window.
Notice that the shared I/O pin in GPIO0 has been set for the ePWM1A function. Next,
open and inspect EPwm.c and see that the ePWM1 has been setup to implement the
PWM waveform as described in the objective for this lab. Notice the values used in the
following registers: TBCTL (set clock prescales to divide-by-1, no software force, sync
and phase disabled), TBPRD, CMPA, CMPCTL (load on 0 or PRD), and AQCTLA (set
on up count and clear on down count for output A). Software force, deadband, PWM
chopper and trip action has been disabled. (Note that the last steps enable the timer count
mode and enable the clock to the ePWM module). See the global variable names and
values that have been set using #define in the beginning of the Lab.h file. Notice that
ePWM2 has been initialized earlier in the code for the ADC. Close the inspected files.

Build and Load

errors in the Problems window.
5. Click the “Debug” button (green bug). The “Debug Perspective” view should open, the
program load automatically, and you should now be at the start of Main().
Run the Code – PWM Waveform

6. Open a memory window to view some of the contents of the ADC results buffer. To
open a memory window click: View Æ Memory on the menu bar. The address label
for the ADC results buffer is AdcBuf in the “Data” memory page.
Note: Exercise care when connecting any wires, as the power to the ControlSTICK is on,
and we do not want to damage the ControlSTICK! Details of pin assignments can be
found on the last page of this lab exercise.
7. Using a connector wire provided, connect the PWM1A (pin # 17) to ADCINA0 (pin # 3)
on the ControlSTICK.
8. Run your code for a few seconds by using the Run button on the toolbar, or using
Target Æ Run on the menu bar. After a few seconds halt your code by using the
Halt button on the toolbar, or by using Target Æ Halt. Verify that the ADC result
buffer contains the updated values.
9. Open and setup a graph to plot a 50-point window of the ADC results buffer.
Click: Tools Æ Graph Æ Single Time and set the following values:
Acquisition Buffer Size 50
DSP Data Type 16-bit unsigned integer
Sampling Rate (Hz) 50000
Start Address AdcBuf
Display Data Size 50
Time Display Unit μs
Select OK to save the graph options.
10. The graphical display should show the generated 2 kHz, 25% duty cycle symmetric
PWM waveform. The period of a 2 kHz signal is 500 μs. You can confirm this by
measuring the period of the waveform using the “measurement marker mode” graph
feature. Right-click on the graph and select Measurement Marker Mode. Move
the mouse to the first measurement position and left-click. Again, right-click on the
graph and select Measurement Marker Mode. Move the mouse to the second

measurement position and left-click. The graph will automatically calculate the
difference between the two values taken over a complete waveform period. When done,
clear the measurement points by right-clicking on the graph and select Remove All
Measurement Marks.
Frequency Domain Graphing Feature of Code Composer Studio

11. Code Composer Studio also has the ability to make frequency domain plots. It does this
by using the PC to perform a Fast Fourier Transform (FFT) of the DSP data. Let's make
a frequency domain plot of the contents in the ADC results buffer (i.e. the PWM
waveform).
Click: Tools Æ Graph Æ FFT Magnitude and set the following values:
Acquisition Buffer Size 50
DSP Data Type 16-bit unsigned integer
Sampling Rate (Hz) 50000
Start Address AdcBuf
Data Plot Style Bar
FFT Order 10
Select OK to save the graph options.
12. On the plot window, hold the mouse left-click key and move the marker line to observe
the frequencies of the different magnitude peaks. Do the peaks occur at the expected
frequencies?
Using Real-time Emulation

Real-time emulation is a special emulation feature that allows the windows within Code
Composer Studio to be updated at up to a 1 Hz rate while the MCU is running. This not only
allows graphs and watch windows to update, but also allows the user to change values in
watch or memory windows, and have those changes affect the MCU behavior. This is very
useful when tuning control law parameters on-the-fly, for example.
13. The memory and single time graph windows displaying AdcBuf should still be open. The
connector wire between PWM1A (pin # 17) and ADCINA0 (pin # 3) should still be
connected. In real-time mode, we would like to have our window continuously refresh
faster than the default rate. Click:
Window Æ Preferences…
and in the section on the left select the “CCS” category. Click the plus sign (+) to the left
of “CCS” and select “Debug”. In the section on the right change the following:

• “Continuous refresh interval (seconds)” from 5 to 1
• “Continuous refresh interval – Graph views (milliseconds)” from 100 to 1000
Click OK.
Note: This change to the “Continuous refresh interval” causes all enabled continuous
refresh windows to refresh at a faster rate. This can be problematic when a large number
of windows are enabled, as bandwidth over the emulation link is limited. Updating too
many windows can cause the refresh frequency to bog down. In this case you can just
selectively enable continuous refresh for the individual windows of interest.
14. Next we need to enable the graph window for continuous refresh. In the upper right-hand
corner of the graph window, left-click on the yellow icon with the arrows rotating in a
circle over a pause sign. Note when you hover your mouse over the icon, it will show
“Enable Continuous Refresh”. This will allow the graph to continuously
refresh in real-time while the program is running.
15. Enable the memory window for continuous refresh using the same procedure as the
previous step.
16. Run the code and watch the windows update in real-time mode. Click:
Scripts Æ Realtime Emulation Control Æ Run_Realtime_with_Reset
17. Carefully remove and replace the connector wire from ADCINA0 (pin # 3). Are the
values updating as expected?
18. Fully halt the CPU in real-time mode. Click:

Scripts Æ Realtime Emulation Control Æ Full_Halt

Optional Exercise
You might want to experiment with this code by changing some of the values or just modify the
code. Try generating another waveform of a different frequency and duty cycle. Also, try to
generate complementary pair PWM outputs. Next, try to generate additional simultaneous
waveforms by using other ePWM modules. Hint: don’t forget to setup the proper shared I/O pins,
etc. (This optional exercise requires some further working knowledge of the ePWM.
Additionally, it may require more time than is allocated for this lab. Therefore, you may want to
try this after the class).
End of Exercise

Lab Reference: Piccolo™ ControlSTICK Header Pin Diagram
1 2 3 4
ADC-A7 ADC-A2 ADC-A0 3V3
COMP1 (+VE) Vref-HI
5 6 7 8
ADC-A4 ADC-B1 EPWM-4B TZ1
COMP2 (+VE) GPIO-07 GPIO-12
9 10 11 12
SCL ADC-B6 EPWM-4A ADC-A1
GPIO-33 GPIO-06
13 14 15 16
SDA ADC-B7 EPWM-3B 5V0
GPIO-32 GPIO-05
17 18 19 20
EPWM-1A ADC-B4 EPWM-3A SPISOMI
GPIO-00 COMP2 (-VE) GPIO-04 GPIO-17
21 22 23 24
EPWM-1B ADC-B3 EPWM-2B SPISIMO
GPIO-01 GPIO-03 GPIO-16
25 26 27 28
SPISTE ADC-B2 EPWM-2A GND
GPIO-19 COMP1 (-VE) GPIO-02
29 30 31 32
SPICLK GPIO-34 PWM1A-DAC GND
GPIO-18 (LED) (Filtered)

Flash Programming
Flash Programming
Flash Programming Basics
The DSP CPU itself performs the flash programming
The CPU executes Flash utility code from RAM that reads the
Flash data and writes it into the Flash
We need to get the Flash utility code and the Flash data into RAM
FLASH CPU
Flash Emulator JTAG

Utility
Code RAM
RS232 SCI
Bootloader
SPI
ROM
Flash
Data I2C
GPIO
TMS320F2802x

Sequence of steps for Flash programming:
Algorithm Function
1. Erase - Set all bits to zero, then to one
2. Program - Program selected bits with zero
3. Verify - Verify flash contents
Minimum Erase size is a sector (4Kw or 8Kw)

Minimum Program size is a bit!
Important not to lose power during erase step:
If CSM passwords happen to be all zeros, the
CSM will be permanently locked!
Chance of this happening is quite small! (Erase
step is performed sector by sector)

Flash Programming
Programming Utilities and CCS Flash Programmer

Flash Programming Utilities
JTAG Emulator Based
Code Composer Studio Plug-in
BlackHawk Flash utilities (requires Blackhawk emulator)
Elprotronic FlashPro2000
Spectrum Digital SDFlash JTAG (requires SD emulator)
Signum System Flash utilities (requires Signum emulator)
SCI Serial Port Bootloader Based
Code-Skin (http://www.code-skin.com)
Elprotronic FlashPro2000
Production Test/Programming Equipment Based
BP Micro programmer
Data I/O programmer
Build your own custom utility
Can use any of the ROM bootloader methods
Can embed flash programming into your application
Flash API algorithms provided by TI
* TI web has links to all utilities (http://www.ti.com/c2000)
CCS On-Chip Flash Programmer

On-Chip Flash programmer is integrated into the CCS debugger

Flash Programming
Code Security Module and Password

Code Security Module (CSM)
Access to the following on-chip memory is restricted:
0x000A80
Flash Registers
0x008000
L0 SARAM (4Kw)
0x009000
reserved
0x3D7800 Dual
User OTP (1Kw)
0x3D7C00 reserved
0x3D7C80 Mapped
ADC / OSC cal. data
0x3D8000 reserved
0x3F0000
FLASH (32Kw)
0x3F7FF8 PASSWORDS (8w )
0x3F8000
L0 SARAM (4Kw)
0x3F9000
Data reads and writes from restricted memory are only

allowed for code running from restricted memory
All other data read/write accesses are blocked:
JTAG emulator/debugger, ROM bootloader, code running in
external memory or unrestricted internal memory
CSM Password
0x3F0000
FLASH (32Kw) CSM Password

Locations (PWL)
0x3F7FF8 128-Bit Password
0x3F7FF8 - 0x3F7FFF
128-bit user defined password is stored in Flash
128-bit KEY registers are used to lock and unlock

the device
Mapped in memory space 0x00 0AE0 – 0x00 0AE7
Registers “EALLOW” protected

Flash Programming
CSM Password Match Flow
Start Is PWL = Yes

Device permanently locked
all 0s?
No
Flash device
secure after Yes
reset or runtime Is PWL =
all Fs?
No
Do dummy reads of PWL Write password to KEY registers
0x3F 7FF8 – 0x3F 7FFF 0x00 0AE0 – 0x00 0AE7
(EALLOW) protected
Device unlocked
Correct Yes
password? User can access on-
chip secure memory
No

Lab 4: Programming the Flash

¾ Objective
The objective of this lab is to program and execute code from the on-chip flash memory. The
TMS320F28027 device has been designed for standalone operation in an embedded system.
Using the on-chip flash eliminates the need for external non-volatile memory or a host processor
from which to bootload. In this lab, the steps required to properly configure the software for
execution from internal flash memory will be covered.

data
ePWM1 ADC memory
TB Counter ADCINA0 RESULT0
pointer rewind
Compare
Action Qualifier CPU copies
connector result to
wire buffer during
ADC ISR
...
ePWM2 triggering
ADC on period match
using SOCA trigger every
20 µs (50 kHz) ePWM2 View ADC
buffer PWM
Samples
Objective: Code Composer

Studio
Program system into Flash Memory
Learn use of CCS Flash Programmer
DO NOT PROGRAM PASSWORDS
¾ Procedure
Open the Project

project.
this lab are:

Adc.c Gpio.c
CodeStartBranch.asm Lab_4.cmd
DefaultIsr_3_4.c Main_4.c
DelayUs.asm Passwords.asm
DSP2802x_GlobalVariableDefs.c PieCtrl.c
DSP2802x_Headers_nonBIOS.cmd PieVect.c
EPwm.c SysCtrl.c
Flash.c Watchdog.c
Link Initialized Sections to Flash

Initialized sections, such as code and constants, must contain valid values at device power-up.
Stand-alone operation of an F28027 embedded system means that no emulator is available to
initialize the device RAM. Therefore, all initialized sections must be linked to the on-chip flash
memory.
Each initialized section actually has two addresses associated with it. First, it has a LOAD
address which is the address to which it gets loaded at load time (or at flash programming time).
Second, it has a RUN address which is the address from which the section is accessed at runtime.
The linker assigns both addresses to the section. Most initialized sections can have the same
LOAD and RUN address in the flash. However, some initialized sections need to be loaded to
flash, but then run from RAM. This is required, for example, if the contents of the section needs
to be modified at runtime by the code.
3. Open and inspect the linker command file Lab_4.cmd. Notice that a memory block
named FLASH_ABCD has been been created at origin = 0x3F0000, length = 0x007F80
on Page 0. This flash memory block length has been selected to avoid conflicts with
other required flash memory spaces. See the reference slide at the end of this lab exercise
for further details showing the address origins and lengths of the various memory blocks
used.
4. In Lab_4.cmd the following compiler sections have been linked to on-chip flash
memory block FLASH_ABCD:
Compiler Sections:
.text .cinit .const .econst .pinit .switch
Copying Interrupt Vectors from Flash to RAM

The interrupt vectors must be located in on-chip flash memory and at power-up needs to be
copied to the PIE RAM as part of the device initialization procedure. The code that performs this
copy is located in InitPieCtrl(). The C-compiler runtime support library contains a
memory copy function called memcpy() which will be used to perform the copy.
5. Open and inspect InitPieCtrl() in PieCtrl.c. Notice the memcpy() function used to
initialize (copy) the PIE vectors. At the end of the file a structure is used to enable the
PIE.

Initializing the Flash Control Registers

The initialization code for the flash control registers cannot execute from the flash memory (since
it is changing the flash configuration!). Therefore, the initialization function for the flash control
registers must be copied from flash (load address) to RAM (run address) at runtime. The memory
copy function memcpy() will again be used to perform the copy. The initialization code for the
flash control registers InitFlash() is located in the Flash.c file.
6. Open and inspect Flash.c. The C compiler CODE_SECTION pragma is used to place
the InitFlash() function into a linkable section named “secureRamFuncs”.
7. The “secureRamFuncs” section will be linked using the user linker command file
Lab_4.cmd. Open and inspect Lab_4.cmd. The “secureRamFuncs” will load to
flash (load address) but will run from L0SARAM (run address). Also notice that the
linker has been asked to generate symbols for the load start, load end, and run start
addresses.
While not a requirement from a MCU hardware or development tools perspective (since
the C28x MCU has a unified memory architecture), historical convention is to link code
to program memory space and data to data memory space. Therefore, notice that for the
L0SARAM memory we are linking “secureRamFuncs” to, we are specifiying “PAGE
= 0” (which is program memory).
8. Open and inspect Main_4.c. Notice that the memory copy function memcpy() is being
used to copy the section “secureRamFuncs”, which contains the initialization
function for the flash control registers.
9. The following line of code in main() is used call the InitFlash() function. Since
there are no passed parameters or return values the code is just:
InitFlash();
at the desired spot in main().
Code Security Module and Passwords

The CSM module provides protection against unwanted copying (i.e. pirating!) of your code from
flash, OTP memory, and the L0SARAM block. The CSM uses a 128-bit password made up of 8
individual 16-bit words. They are located in flash at addresses 0x3F7FF8 to 0x3F7FFF. During
this lab, dummy passwords of 0xFFFF will be used – therefore only dummy reads of the
password locations are needed to unsecure the CSM. DO NOT PROGRAM ANY REAL
PASSWORDS INTO THE DEVICE. After development, real passwords are typically placed in
the password locations to protect your code. We will not be using real passwords in the
workshop.
The CSM module also requires programming values of 0x0000 into flash addresses 0x3F7F80
through 0x3F7FF5 in order to properly secure the CSM. Both tasks will be accomplished using a
simple assembly language file Passwords.asm.

10. Open and inspect Passwords.asm. This file specifies the desired password values
(DO NOT CHANGE THE VALUES FROM 0xFFFF) and places them in an initialized
section named “passwords”. It also creates an initialized section named “csm_rsvd”
which contains all 0x0000 values for locations 0x3F7F80 to 0x3F7FF5 (length of 0x76).
11. Open Lab_4.cmd and notice that the initialized sections for “passwords” and
“csm_rsvd” are linked to memories named PASSWORDS and CSM_RSVD,
respectively.
Executing from Flash after Reset

The F28027 device contains a ROM bootloader that will transfer code execution to the flash after
reset. When the boot mode selection is set for “Jump to Flash” mode, the bootloader will branch
to the instruction located at address 0x3F7FF6 in the flash. An instruction that branches to the
beginning of your program needs to be placed at this address. Note that the CSM passwords
begin at address 0x3F7FF8. There are exactly two words available to hold this branch
instruction, and not coincidentally, a long branch instruction “LB” in assembly code occupies
exactly two words. Generally, the branch instruction will branch to the start of the C-
environment initialization routine located in the C-compiler runtime support library. The entry
symbol for this routine is _c_int00. Recall that C code cannot be executed until this setup routine
is run. Therefore, assembly code must be used for the branch. We are using the assembly code
file named CodeStartBranch.asm.
12. Open and inspect CodeStartBranch.asm. This file creates an initialized section
named “codestart” that contains a long branch to the C-environment setup routine.
This section has been linked to a block of memory named BEGIN_FLASH.
13. In the earlier lab exercises, the section “codestart” was directed to the memory
named BEGIN_M0. Open and inspect Lab_4.cmd and notice that the section
“codestart” will now be directed to BEGIN_FLASH. Close the inspected files.
On power up the reset vector will be fetched and the ROM bootloader will begin execution. If
the emulator is connected, the device will be in emulator boot mode and will use the EMU_KEY
and EMU_BMODE values in the PIE RAM to determine the bootmode. This mode was utilized
in an earlier lab. In this lab, we will be disconnecting the emulator and running in stand-alone
boot mode (but do not disconnect the emulator yet!). The bootloader will read the OTP_KEY
and OTP_BMODE values from their locations in the OTP. The behavior when these values have
not been programmed (i.e., both 0xFFFF) or have been set to invalid values is boot to flash
bootmode.
Build – Lab.out
14. Click the “Build” button to generate the Lab.out file to be used with the CCS Flash
Programmer. Check for errors in the Problems window.
CCS Flash Plug-in

In CCS (version 4.x) the on-chip flash programmer is integrated into the debugger. When the
program is loaded CCS will automatically determine which sections reside in flash memory based

on the linker command file. CCS will then program these sections into the on-chip flash memory.
Additionally, in order to effectively debug with CCS, the symbolic debug information (e.g.,
symbol and label addresses, source file links, etc.) will automatically load so that CCS knows
where everything is in your code.
Clicking the “Debug” button in the C/C++ Perspective will automatically launch the
debugger, connect to the target, and program the flash memory in a single step.
15. Program the flash memory by clicking the “Debug” button (green bug). As soon as the
“Progress Information” box opens, if needed select “Details” in order to watch the
programming operation and status. After successfully programming the flash memory
the “Progress Information” box will close.
16. Flash programming options are configured with the “On-Chip Flash” control panel.
Open the control panel by clicking:
Tools Æ On-Chip Flash
Scroll the control panel and notice the various options that can be selected. You will see
that specific actions such as “Erase Flash” can be performed.
The CCS on-chip flash programmer was automatically configured to use the Piccolo™
10 MHz internal oscillator as the device clock during programming. Notice the “Clock
Configuration” settings has the OSCCLK set to 10 MHz, the DIVSEL set to /2, and the
PLLCR value set to 12. Recall that the PLL is divided by two, which gives a
SYSCLKOUT of 60 MHz.
The flash programmer should be set for “Erase, Program, Verify” and all boxes in the
“Erase Sector Selection” should be checked. We want to erase all the flash sectors.
We will not be using the on-chip flash programmer to program the “Code Security
Password”. Do not modify the Code Security Password fields. They should remain as
all 0xFFFF.
17. Close the “On-Chip Flash” control panel by clicking the X on the tab.
Running the Code – Using CCS

18. Reset the CPU. The program counter should now be at 0x3FF7BB in the “Disassembly”
window, which is the start of the bootloader in the Boot ROM.
19. Under Scripts on the menu bar click:

EMU Boot Mode Select Æ EMU_BOOT_FLASH.
This has the debugger load values into EMU_KEY and EMU_BMODE so that the
bootloader will jump to "FLASH" at 0x3F7FF6.
20. Single-Step by using the <F5> key (or you can use the Step Into button on the
horizontal toolbar) through the bootloader code until you arrive at the beginning of the
codestart section in the CodeStartBranch.asm file. (Be patient, it will take about

125 single-steps). Notice that we have placed some code in CodeStartBranch.asm

to give an option to first disable the watchdog, if selected.
21. Step a few more times until you reach the start of the C-compiler initialization routine at
the symbol _c_int00.
22. Now do Target Æ Go Main. The code should stop at the beginning of your
main()routine. If you got to that point succesfully, it confirms that the flash has been
programmed properly, that the bootloader is properly configured for jump to flash mode,
and that the codestart section has been linked to the proper address.
23. You can now RUN the CPU, and you should observe the LED on the ControlCARD
blinking. Try resetting the CPU, select the EMU_BOOT_FLASH boot mode, and then
hitting RUN (without doing all the stepping and the Go Main procedure). The LED
should be blinking again.
24. HALT the CPU.

Running the Code – Stand-alone Operation (No Emulator)

27. Close Code Composer Studio.
28. Disconnect the ControlSTICK from the computer USB port.
29. Re-connect the ControlSTICK to the computer USB port.
30. The LED should be blinking, showing that the code is now running from flash memory.
End of Exercise

Lab 4 Reference: Programming the Flash
Flash Memory Section Blocks
origin =
0x3F 0000
FLASH
length = 0x7F80
page = 0 Lab_4.cmd
SECTIONS
{
0x3F 7F80 CSM_RSVD codestart :> BEGIN_FLASH, PAGE = 0
length = 0x76 passwords :> PASSWORDS, PAGE = 0
page = 0 csm_rsvd :> CSM_RSVD, PAGE = 0
0x3F 7FF6 BEGIN_FLASH }
length = 0x2
page = 0
0x3F 7FF8 PASSWORDS
length = 0x8
page = 0
Startup Sequence from Flash Memory
0x3F 0000 _c_int00 “rts2800_ml.lib”

FLASH (32Kw)
4
0x3F 7FF6 LB
_c_int00 5
“user” code sections
Passwords (8w) main ( )
{
……
3 ……
……
0x3F E000 Boot ROM (8Kw) }
Boot Code
0x3F F7BB
{SCAN GPIO}
2
BROM vector (32w)
0x3F FFC0 0x3F F7BB
1
RESET

The Next Step…
The Next Step…

Training
F28x Multi-day Training Course
TMS320F2803x Workshop Outline
- Architectural Overview
- Programming Development Environment
- Peripheral Register Header Files
- Reset and Interrupts
- System Initialization
- Analog-to-Digital Converter
- Control Peripherals
- Numerical Concepts and IQmath
In-depth hands-on - Control Law Accelerator (CLA)
TMS320F28035 Design - System Design
and Peripheral - Communications
Training - DSP/BIOS
- Support Resources

The Next Step…
Development Tools
C2000 Experimenter’s Kits
F28027, F28035, F2808, F28335
Experimenter Kits include

F28027, F28035, F2808 or F28335
ControlCARD
TMDXDOCK28027 USB docking station
C2000 Applications Software CD
with example code and full
hardware details
Code Composer Studio v3.3 with
code size limit of 32KB
TMDXDOCK28035
Docking station features
Access to ControlCARD signals
Breadboard areas
TMDSDOCK2808 Onboard USB JTAG Emulation
JTAG emulator not required
Available through TI authorized
distributors and the TI eStore
TMDSDOCK28335
C2834x Experimenter’s Kits

C28343, C28346
Experimenter Kits include

C2834x ControlCARD
Docking station
hardware details
TMDXDOCK28343
5V power supply
Docking station features
Access to ControlCARD signals
Breadboard areas
JTAG emulator required – sold
separately
TMDXDOCK28346-168 distributors and the TI eStore

The Next Step…
F28335 Peripheral Explorer Kit

Experimenter Kit includes
F28335 ControlCARD
Peripheral Explorer baseboard
hardware details
5V DC power supply
Peripheral Explorer features
ADC input variable resistors
GPIO hex encoder & push buttons
eCAP infrared sensor
GPIO LEDs, I2C & CAN connection
Analog I/O (AIC+McBSP)
JTAG emulator required – sold
separately
TMDSPREX28335 distributors and the TI eStore
C2000 ControlCARD Application Kits

Digital Power Kits includes
Experimenter’s
Kit ControlCARD and application
specific baseboard
Full version of Code Composer
Digital Power Studio v3.3 with 32KB code size
Developer’s limit
Kit
Software download includes
Resonant Complete schematics, BOM, gerber
DC/DC
Developer’s Kit files, and source code for board
and all software
Renewable Quickstart demonstration GUI for
Energy
Developer’s Kit quick and easy access to all board
features
AC/DC Fully documented software
Developer’s specific to each kit and application
Kit
See www.ti.com/c2000 for more
Dual Motor details
Control and
PFC Available through TI authorized
Developer’s
Kit distributors and the TI eStore

The Next Step…
Development Support
C2000 Signal Processing Libraries
Signal Processing Libraries & Applications Software Literature #
ACI3-1: Control with Constant V/Hz SPRC194
ACI3-3: Sensored Indirect Flux Vector Control SPRC207
ACI3-3: Sensored Indirect Flux Vector Control (simulation) SPRC208
ACI3-4: Sensorless Direct Flux Vector Control SPRC195
ACI3-4: Sensorless Direct Flux Vector Control (simulation) SPRC209
PMSM3-1: Sensored Field Oriented Control using QEP SPRC210
PMSM3-2: Sensorless Field Oriented Control SPRC197
PMSM3-3: Sensored Field Oriented Control using Resolver SPRC211
PMSM3-4: Sensored Position Control using QEP SPRC212
BLDC3-1: Sensored Trapezoidal Control using Hall Sensors SPRC213
BLDC3-2: Sensorless Trapezoidal Drive SPRC196
DCMOTOR: Speed & Position Control using QEP without Index SPRC214
Digital Motor Control Library (F/C280x) SPRC215
Communications Driver Library SPRC183
DSP Fast Fourier Transform (FFT) Library SPRC081
DSP Filter Library SPRC082
DSP Fixed-Point Math Library SPRC085
DSP IQ Math Library SPRC087
DSP Signal Generator Library SPRC083
DSP Software Test Bench (STB) Library SPRC084
C28x FPU Fast RTS Library SPRC664
DSP2802x C/C++ Header Files and Peripheral Examples SPRC832
Available from TI Website ⇒ http://www.ti.com/c2000
C2000 Workshop Download Wiki
http://processors.wiki.ti.com/index.php/Hands-On_Training_for_TI_Embedded_Processors

The Next Step…
For More Information . . .

Internet
Website: http://www.ti.com
FAQ: http://www-k.ext.ti.com/sc/technical_support/knowledgebase.htm
Device information my.ti.com
Application notes News and events
Technical documentation Training
Enroll in Technical Training: http://www.ti.com/sc/training
USA - Product Information Center (PIC)

Phone: 800-477-8924 or 972-644-5580
Email: support@ti.com
Information and support for all TI Semiconductor products/tools
Submit suggestions and errata for tools, silicon and documents
European Product Information Center (EPIC)

Web: http://www-k.ext.ti.com/sc/technical_support/pic/euro.htm
Phone: Language Number

Belgium (English) +32 (0) 27 45 55 32
France +33 (0) 1 30 70 11 64
Germany +49 (0) 8161 80 33 11
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United Kingdom +44 (0) 1604 66 33 99
Finland (English) +358(0) 9 25 17 39 48
Fax: All Languages +49 (0) 8161 80 2045
Email: epic@ti.com
Literature, Sample Requests and Analog EVM Ordering

Information, Technical and Design support for all Catalog TI
Semiconductor products/tools
Submit suggestions and errata for tools, silicon and documents

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C2000™ Piccolo™ 1-Day Workshop

Workshop Guide and Lab Manual

Customers are responsible for their applications using TI components.

Copyright © 2009 – 2010 Texas Instruments Incorporated

2 C2000 Piccolo 1-Day Workshop

C2000 Piccolo 1-Day Workshop 3

C2000 Piccolo 1-Day Workshop Outline

4 C2000 Piccolo 1-Day Workshop

TI Embedded Processing Portfolio

16-bit ultra- 32-bit 32-bit ARM ARM Ultra

C2000™ Sitara ™ C6000 ™

Software & Dev. Tools

C2000 Piccolo 1-Day Workshop 5

C2000 Portfolio Expanding with

Broad C2000 Application Base

Renewable Telecom AC Drives, Industrial

6 C2000 Piccolo 1-Day Workshop

C2000 Piccolo™ Microcontroller Family

F28032 60 32Kw 10Kw No 3 14 / 16 12(6) / 14(7) 1 1 SPI,SCI,I2C,LIN,eCAN

• All devices have VREG, POR/BOR, Watchdog, OTP, CPU Timers

LED LD1 LED LD2 TMS320F28027

USB JTAG On-board USB Peripheral

C2000 Piccolo 1-Day Workshop 7

TMS320F28027 Memory Map

8 C2000 Piccolo 1-Day Workshop

F28x Fast Interrupt Response Manager

Peripheral Interrupts 12x8 = 96

C2000 Piccolo 1-Day Workshop 9

Programming Development Environment

 Integrates: edit, code generation,

 Single-click access using buttons

 Powerful graphing/profiling tools

 Automated tasks using Scripts

 Built-in access to BIOS functions

 Based on the Eclipse open

C/C++ and Debug Perspective (CCSv4)

 C/C++ Perspective  Debug Perspective

10 C2000 Piccolo 1-Day Workshop

Project files contain:

Creating a New CCSv4 Project

C2000 Piccolo 1-Day Workshop 11

CCSv4 Build Options – Compiler / Linker

Linking Sections in Memory

 All code consists of

Local vars (.stack) Code (.text)

12 C2000 Piccolo 1-Day Workshop

Compiler Section Names

Note: During development initialized sections could be linked to RAM since

Placing Sections in Memory

0x3F 0000 FLASH .cinit

C2000 Piccolo 1-Day Workshop 13

.obj Linker .out

Linker Command File

PAGE 1: /* Data Memory */

14 C2000 Piccolo 1-Day Workshop

Lab 1: Linker Command File

Lab 1: Linker Command File

Start Code Composer Studio and Open a Workspace

C2000 Piccolo 1-Day Workshop 15

Integrates: edit, code generation,

Single-click access using buttons

Powerful graphing/profiling tools

Automated tasks using Scripts

Built-in access to BIOS functions

Based on the Eclipse open

C/C++ Perspective Debug Perspective

All code consists of

Contains everything needed to use the

Declares a global instantiation of the structure

Add this file to your CCS project:

Example projects for each peripheral

POR – Power-on Reset generates a device reset during

A valid signal on a specific interrupt line causes the latch

If the individual and global switches are turned “on” the

/* Interrupt Enable Register */