ELL 740

Compact Modeling of Semiconductor Devices

Dr. Abhisek Dixit

Department of Electrical Engineering,
Indian Institute of Technology (IIT) Delhi

ELL740/Dr. Abhisek Dixit slide#1

 FEOL Capacitors: MOS Technology

•  Why MOS Technology is needed

–  Boolean algebra (0,1)
–  Transistor as an ideal switch (0=Open, 1=Short)
–  Input isolated from output by reverse biased p-n junction
in BJT (high input impedance) while in MOSFET input is
isolated by gate insulator (very high input impedance)

ELL740/Dr. Abhisek Dixit slide#2

 MOS Technology

•  MOS interface is heart of a MOSFET

–  Quality of oxide determines gate tunneling (input
impedance)
–  Quality of oxide-silicon interface affects transport
through the channel (trans-conductance)

ELL740/Dr. Abhisek Dixit slide#3

 MOS

•  MOS stands for metal–oxide–semiconductor

•  A MOS capacitor is made of a semiconductor body or substrate,
an insulator film, such as SiO2, and a metal electrode called a
gate
•  The oxide film can be as thin as 1.5 nm. One nano-meter is
equal to 10 Å, or the size of a few oxide molecules.
•  Before 1970, the gate was typically made of metals such as Al
(hence the M in MOS). After 1970, heavily doped polycrystalline
silicon has been the standard gate material because of its ability
to withstand high temperature without reacting with SiO2.

ELL740/Dr. Abhisek Dixit slide#4

 MOS

•  After 2008, the trend is to reintroduce metal gate and replace

SiO2 with more advanced dielectrics for the most advanced
transistors.
•  The MOS capacitor is not a widely used device in itself.
However, it is part of the MOS transistor. The MOS transistor is
by far the most widely used semiconductor device.
•  An MOS transistor is an MOS capacitor with two PN junctions
flanking the capacitor. This transistor structure is often a better
structure for studying the MOS capacitor properties than the
MOS capacitor itself

ELL740/Dr. Abhisek Dixit slide#5

Band Diagram at Vgb=0

ELL740/Dr. Abhisek Dixit slide#6

 Band Diagram at Flat Band Condition
•  Flat band is the condition where the energy
band (Ec and Ev) of the substrate is flat at
the Si–SiO2 interface. This condition is
achieved by applying a negative voltage to
the gate. thus raising the band diagram on
the left-hand side.
•  When the band is flat in the body, the
surface electric field in the substrate is zero.
Therefore the electric field in the oxide is
also zero 1, i.e.,Ec and Ev of SiO2 are flat,
too.
•  Ec and Ev of SiO2 are separated by 9 eV,
the Eg of SiO2. E0, the vacuum level, is the
energy state of electrons outside the
material.

ELL740/Dr. Abhisek Dixit slide#7

 Band Diagram at Flat Band Condition
•  E0 of SiO2 is above Ec by 0.95 eV. The
difference between E0 and Ec is called the
electron affinity, another material parameter just
as Eg is a material parameter. Si has an
electron affinity equal to 4.05 eV.
•  E0 must be continuous at the Si–SiO2 interface
(otherwise the electric field would be infinite).
Therefore, Ec of SiO2 is 3.1 eV higher than Ec
of Si. This 3.1 eV is the Si–SiO2 electron
energy barrier. The hole energy barrier is 4.8
eV. Because of these large energy barriers,
electrons and holes normally cannot pass
through the SiO2 gate dielectric.
•  Ec in the poly-silicon gate is also lower than the
Ec of SiO2 by 3.1 eV (the Si–SiO2 energy
barrier).
•  EF of the N+ poly-Si may be assumed to
coincide with Ec for simplicity.

ELL740/Dr. Abhisek Dixit slide#8

 Band Diagram at Flat Band Condition
•  In SiO2, the exact position of EF has no
significance. If we place EF anywhere
around the middle of the SiO2 band gap,
n=Nc exp[(Ec– EF)/kT] would be a
meaninglessly small number such as 10e–
60cm–3. Therefore, the position of EF in
SiO2 is immaterial.
•  The applied voltage at the flat-band
condition, called Vfb, the flat-band voltage, is
the difference between the Fermi levels at
the two terminals. Vfb=ψg- ψs, ψg and ψs
are the gate work function and the
semiconductor work function.
•  The work function is the difference between
E0 and EF. For an N+ -poly-Si gate, ψg=
4.05 V, for the P-Si body, ψs= 4.05 V + (Ec–
EF)/q. In this case, a negative Vfb is
obtained, about –0.7 V.

ELL740/Dr. Abhisek Dixit slide#9

 Surface Accumulation in MOS Cap.

•  When Vg ≠ Vfb, φs (surface voltage) and

Vox (oxide voltage) will be non-zero in
general.
•  qφs is the band bending in the substrate.
Because the substrate is the voltage
reference, φs is negative if Ec bends
upward toward the surface as shown in
Fig. and positive if Ec bends downward.
•  Vox is the voltage across the oxide.
Again, Vox is negative if the SiO2 energy
band tilts up toward the gate as it does in
Fig. and positive if it tilts downward
toward the gate.

ELL740/Dr. Abhisek Dixit slide#10

 Surface Accumulation in MOS Cap.

•  Because Ev is closer to EF at the surface than in the bulk, the surface hole
concentration, ps, is larger than the bulk hole concentration, p0 = Na.
–  ps=Na exp[–qφs ⁄ kT]
–  Since φs may be –100 or –200 mV, ps >> Na. That is to say, there are a
large number of holes at or near the surface. They form an accumulation
layer and these holes are called the accumulation-layer holes, and their
charge the accumulation charge, Qacc. This condition is known as
surface accumulation. If the substrate was N type, the accumulation
layer would hold electrons.
•  A relationship that we will use again and again is Vg = Vfb+φs+Vox
–  At flat band, Vg = Vfb, φs = Vox = 0 and above Eq. is satisfied.
–  If Vg ≠ Vfb, the difference must be picked up by φs and Vox.
–  In the case of surface accumulation, φs may be ignored in a first-order model
since it is quite small and Vg Eq. becomes Vox = Vg – Vfb

ELL740/Dr. Abhisek Dixit slide#11

 Surface Accumulation in MOS Cap.

•  where Cox is the oxide capacitance per unit area (F/cm2) and Qacc is the
accumulation charge (C/cm2). Equation is the usual capacitor relationship, V = Q/C
(or Q = C*V) except for the negative sign. In V = Q/C, the capacitor voltage and
charge are both taken from the same electrode. In the MOS capacitor theory, the
voltage is the gate voltage, but the charge is the substrate charge because interesting
things happen in the substrate. This unusual choice leads to the negative sign in Eq.
•  Qacc = –Cox(Vg – Vfb)
•  Therefore, the MOS capacitor in accumulation behaves like a capacitor with Q= C*V
(or –C*V as explained earlier) but with a shift in V by Vfb. The shift is easily
understandable because Qacc = 0 when Vg =Vfb. In general, Eq. is
•  Vox = –Qsub ⁄ Cox, where Qsub is all the charge that may be present in the substrate,
including Qacc.

ELL740/Dr. Abhisek Dixit slide#12

 Surface Depletion in MOS Cap.
•  If a more positive Vg than Vfb is applied, the band diagram
on the gate side will be pulled downward as shown in Fig.,
there is now a depletion region at the surface because EF
is far from both Ec and Ev and electron and hole densities
are both small. This condition is called surface depletion.
The depletion region has a width, Wdep, given by

Qdep is negative because the acceptor ions (after accepting

the extra electrons) are negatively charged.

ELL740/Dr. Abhisek Dixit slide#13

 Threshold Condition and Voltage
•  Let’s make Vg in Fig. increasingly more
positive. This bends the energy band down
further. At some Vg, EF will be close enough
to Ec at the Si–SiO2 interface that the surface
is no longer in depletion but at the threshold
of inversion.
•  The term inversion means that the surface is
inverted from P type to N type, or electron
rich. Threshold is often defined as the
condition when the surface electron
concentration, ns, is equal to the bulk doping
concentration, Na. That means
•  (Ec – EF)surface = (EF – Ev)bulk, or A = B in
Fig. This, in turn, means C = D.
•  Ei is a curve drawn at midgap, which is half
way between Ec and Ev.

ELL740/Dr. Abhisek Dixit slide#14

 Threshold Condition and Voltage
•  Let the surface potential (band bending) at the
threshold condition be φst. It is equal to (C +
D)/q = 2C/q = 2φB. Assuming Nc=Nv

The Vg at the threshold condition is called the

threshold voltage, Vt.

ELL740/Dr. Abhisek Dixit slide#15

 Vt Plots

ELL740/Dr. Abhisek Dixit slide#16

 Strong Inversion Beyond Threshold

•  Qinv = –Cox(Vg – Vt), confirms that the MOS capacitor

in strong inversion behaves like a capacitor except for
a voltage offset of Vt.
•  At Vg = Vt, Qinv = 0
•  we have assumed that electrons will appear in the
inversion layer whenever the closeness between Ec
and EF suggests their presence. However, there are
few electrons in the P-type body, and it can take
minutes for thermal generation to generate the
necessary electrons to form the inversion layer. The
MOS transistor structure solves this problem as the
inversion electrons are supplied by the N+ junctions

ELL740/Dr. Abhisek Dixit slide#17

 Review of MOS Cap Concepts

•  The surface potential, φs, is zero at Vfb and approximately zero in the accumulation
region. As Vg increases from Vfb into the depletion regime, φs increases from zero
toward 2φB. When φs reaches 2φΒ, the surface electron concentration becomes so
large that the surface is considered inverted. The Vg at that point is called Vt, the
threshold voltage.

ELL740/Dr. Abhisek Dixit slide#18

 Review of MOS Cap Concepts

•  There is no depletion region when the MOS interface is in accumulation. Wdep in the MOS
capacitor is proportional to the square root of the band bending (φs). Wdep saturates at
Wdmax when Vg ≥ Vt, because φs saturates at 2φB.

ELL740/Dr. Abhisek Dixit slide#19

 Review of MOS Cap Concepts

•  The depletion charge Qdep is constant in the inversion region because Wdep is a constant
there. Qinv = –Cox(Vg – Vt) appears in the inversion region. Qacc shows up in the
accumulation region. In both (b) and (c), the slope is –Cox.

ELL740/Dr. Abhisek Dixit slide#20

 Review of MOS Cap Concepts

•  Total substrate charge Qsub in the accumulation region is made of accumulation charge.
Qsub is made of Qdep in the depletion region. In the inversion region, there are two
components, Qdep that is a constant and Qinv that is equal to –Cox(Vg – Vt).

ELL740/Dr. Abhisek Dixit slide#21

 MOS Cap C-V Characteristics
•  The capacitance–voltage (C–V) measurement is a
powerful and commonly used method of determining
the gate oxide thickness, substrate doping
concentration, threshold voltage, and flat-band
voltage.
•  The C–V curve is usually measured with a C–V
meter, which applies a DC bias voltage, Vg, and a
small sinusoidal signal (1 kHz–10 MHz) to the MOS
capacitor and measures the capacitive current with
an AC ammeter. The capacitance is calculated from
icap/vac = ωC.
•  The capacitance in the MOS theory is always the
small-signal capacitance

ELL740/Dr. Abhisek Dixit slide#22

 MOS C-V

•  -ve sign as Qsub taken on substrate

plate
•  Derivative of Qsub shown
•  In the accumulation region, the MOS
capacitor is just a simple capacitor with
capacitance Cox. In the depletion
region, the MOS capacitor consists of
two capacitors in series: the oxide
capacitor, Cox, and the depletion-layer
capacitor, Cdep. Under the AC small-
signal voltage, Wdep expands and
contracts slightly at the AC frequency.
Therefore, the AC charge appears at
the bottom of the depletion.

ELL740/Dr. Abhisek Dixit slide#23

 MOS C-V

•  As Vg>Vfb, Cdep reduces, C also

reducesan inversion layer exists at
the Si–SiO2 interface.
•  In response to the AC signal, Qinv
increases and decreases at the AC
frequency. The inversion layer
plays the role of the bottom
electrode of the capacitor.
Therefore, C reverts to Cox in the
inversion region.

ELL740/Dr. Abhisek Dixit slide#24

 MOS C-V
•  This C-V curve is the quasi-static C–V
because Qinv can respond to the AC signal
as if the frequency were infinitely low (static
case). That would require a ready source of
electrons, which can be provided by the N
region. PN junctions are always present in
an MOS transistor. Therefore, the MOS
transistor C–V characteristics at all
frequencies follow this curve.
•  What if, the PN junctions are not present?
The P-type substrate is an inefficient
supplier of electrons. It produces electrons
through thermal generation at a very slow
rate. Qinv cannot respond to the AC signal
and remains constant at its DC value.

ELL740/Dr. Abhisek Dixit slide#25

 MOS C-V
•  Instead, the AC signal causes φs to
oscillate around 2φB and causes Wdep to
expand and contract slightly around
Wdmax. This change of Wdep can
respond at very high frequencies because
it only involves the movement of the
abundant majority carriers. Consequently,
the AC charge exists at the bottom of the
depletion region. The result is a saturation
of C at Vt as illustrated by the lower curve,
known as the high-frequency MOS
capacitor C–V (HF C–V).
•  The name connotes that, in principle, at a
sufficiently low frequency, even the MOS
capacitor’s C–V would follow the upper
curve. Following that reasoning, the upper
curve is also known as the low-frequency
C–V (LF C–V).

ELL740/Dr. Abhisek Dixit slide#26

 MOS C-V
•  In reality, even at a low frequency such as 1 kHz, the C–V of modern high-quality
MOS capacitors does not follow the LF C–V curve. At yet lower frequencies, the C–V
meter is ineffective (the capacitive current is too low) for studying the MOS capacitor.
•  The term low-frequency C–V has a historical significance and is still used, but it no
longer has a practical significance.
•  Measuring the Quasi-Static C–V Using an MOS Capacitor
–  There is a practical way to obtain the “low frequency” or quasi-static C–V using a MOS
capacitor without the PN junction. It involves applying a very slow linear-ramp voltage
(<0.1V/s) to the gate and measuring Ig with a very sensitive DC ammeter during the ramp. C
is calculated from Ig = C·dVg/dt.
–  This technique provides sufficient time for Qinv to respond to the slowly changing Vg.
–  Plotting Ig/(dVg/dt) vs. Vg produces the QS C–V curve.
–  This technique becomes impracticable if the gate dielectric has too large a leakage current.

ELL740/Dr. Abhisek Dixit slide#27

 MOS C-V: Oxide Charge

•  The basic MOS theory ignores the possible presence of electric charge in the gate
dielectric. Assuming surface charge, Qox (C/cm2), exists at the SiO2–Si interface, the band
diagram at the flat-band condition could be modified
•  The flat-band voltage is ψg – ψs. The oxide charge (assumed to be located at the oxide–
substrate interface for simplicity) induces an electric field in the oxide and an oxide voltage,
− Qox/Cox. Clearly, Vfb now is different from the Vfb0

ELL740/Dr. Abhisek Dixit slide#28

 MOS C-V: Types of Oxide Charge

•  Because Qox changes Vfb, it also changes Vt.

•  There are several types of oxide charge.
•  Positive fixed oxide charge is attributed to silicon ions present at the Si–SiO2
interface.
•  Mobile oxide charge is believed to be mostly sodium ions. Mobile ions can be
detected by observing Vfb and Vt shift under a gate bias at an elevated
temperature (e.g., at 200 °C) due to the movement of the ions in the oxide.
Sodium contamination must be eliminated from the water, chemicals, and
containers used in an MOS fabrication line in order to prevent instabilities in Vfb
and Vt.
•  In addition, significant interface traps or interface states (dangling bonds)
may be present and they can trap and release electrons and generate noise and
degrade the sub-threshold current of MOSFET.

ELL740/Dr. Abhisek Dixit slide#29

 MOS C-V: Reliability
•  More interface states and fixed oxide charge appear after the oxide is subjected to
high electric field for some time due to the breaking or rearrangement of chemical
bonds.
•  This raises a reliability concern because the threshold voltage and transistor current
would change with usage and can potentially cause sensitive circuits to fail.
•  Engineers ensure device reliability by controlling the stress field and improving the
MOS interface quality and verifying or projecting the reliability with careful long-term
testing.
–  Suggested reading Bias Temperature Stress (BTI)
–  Such as Negative Bias Temperature Instability (NBTI) in PMOS (B penetration, Nitrided
oxides) and PBTI in NMOS
–  Time Dependent Dielectric Breakdown (TDDB)
–  In addition Hot Carrier Injection (HCI) is the other reliability concern
•  All this falls under device ageing, added to compact models using RELXPERT
platform

ELL740/Dr. Abhisek Dixit slide#30

 MOS C-V: Poly Depletion Effect
•  Consider an MOS capacitor with P+ poly-Si gate and N body. The capacitor
is biased into surface inversion. Continuity of electric flux across the
interface requires that the band bends in the gate. This indicates the
presence of a thin depletion layer in the gate. Depending on the gate doping
concentration and the oxide field, the poly-Si gate depletion layer
thickness, Wdpoly, may be 1–2 nm. According to Gauss’s Law

•  Because a depletion layer is present in the gate, one may say that a poly-
silicon-gate capacitor is added in series with the oxide capacitor. The MOS
capacitance in the inversion region becomes

•  This poly-depletion effect effectively increases Tox by Wdpolyεox/εs or

Wdpoly/3, and can have a significant impact on the C–V curve if Tox is thin.
The gate capacitance drops as the capacitor is biased deeper into the
inversion region due to increasing poly-depletion. The poly-depletion effect
is

ELL740/Dr. Abhisek Dixit slide#31

 MOS C-V: Poly Depletion Effect
•  This poly-depletion effect effectively increases Tox by Wdpolyεox/εs or Wdpoly/3, and can
have a significant impact on the C–V curve if Tox is thin. The gate capacitance drops as the
capacitor is biased deeper into the inversion region due to increasing poly-depletion. The
poly-depletion effect is undesirable because a reduced C means reduced Qinv, and reduced
transistor current.
•  The solution is to dope the poly-Si heavily. Unfortunately, very heavy doping may cause
dopant penetration from the gate through the oxide into the substrate. Poly-SiGe gate can
be doped to a higher concentration, thus improving gate depletion. Poly-gate depletion is
eliminated in advanced MOSFET technology by substitution of the poly-gate with a metal
gate. The effect of poly-gate depletion on Qinv may be modeled in another way:

•  Poly-gate depletion effectively reduces Vg by φpoly. Even 0.1 V φpoly would be highly
undesirable when the power-supply voltage (the maximum Vg) is only around 1 V.

ELL740/Dr. Abhisek Dixit slide#32

 MOS C-V: Inversion and Accumulation
Charge Layer Thickness, QM Effect

•  So far, we have implicitly assumed that the inversion charge is a sheet charge at the Si–
SiO2 interface (i.e., the inversion layer is infinitely thin). In reality, the inversion-charge
profile is determined by the solution of the Schrödinger equation and Poisson’s equation.
For this reason, the present topic is often referred to as the quantum mechanical effect in
an MOS device.
•  The average location or centroid of the inversion charge below the Si–SiO2 interface is
called the inversion-layer thickness, Tinv.

ELL740/Dr. Abhisek Dixit slide#33

 MOS C-V: Inversion and Accumulation
Charge Layer Thickness, QM Effect

•  Tinv is shown as a function of Vg. When Vg is large, Tinv is around 1.5 nm. When Vg is low,
Tinv can be 3 nm.

ELL740/Dr. Abhisek Dixit slide#34

 MOS C-V: Inversion and Accumulation
Charge Layer Thickness, QM Effect

•  It is reasonable that Tinv is a function of the average field, and therefore a function of (Vg +
Vt)/Tox. The electron inversion layer is thinner than the hole inversion layer because the
electron effective mass is smaller. It is valid to think that the bottom electrode of the MOS
capacitor is not exactly at the Si–SiO2 interface but rather effectively located below the
interface by Tinv. In other words, Tox is effectively increased by Tinv/3, where 3 is the ratio
of εs/εox. The accumulation layer has a similar thickness.
•  The effect on the C–V characteristics is to depress the C–V curve at the onset of inversion
and accumulation.

ELL740/Dr. Abhisek Dixit slide#35

 MOS C-V: Inversion and Accumulation
Charge Layer Thickness, QM Effect

•  In the depletion region, Cinv is negligible (there is no inversion charge) and Cpoly can be
neglected because Wdpoly << Wdep. Therefore, cap network reduces to the basic series
combination of Cox and Cdep.
•  As Vg increases toward Vt, Cinv increases as the inversion charge begins to appear, and
the total capacitance rises above the basic C–V. The capacitance rises smoothly toward
Cox because the inversion charge is not located exactly at the silicon–oxide interface, but at
some depth that varies with Vg. At larger Vg, Cpoly cannot be assumed to be infinity
(Wdpoly increases), and C drops.

ELL740/Dr. Abhisek Dixit slide#36

 MOS C-V: Inversion and Accumulation
Charge Layer Thickness, QM Effect

•  Tinv and Wdpoly used to be negligible when Tox was large (>10 nm). For thinner oxides,
they are not. Because it is difficult to separate Tox from Tinv and Wdpoly by measurement,
an electrical oxide thickness, Toxe, is often used to characterize the total effective oxide
thickness. Toxe is deduced from the inversion-region capacitance measured at Vg = Vdd.
•  One may think of Toxe as an effective oxide thickness, corresponding to an effective
gate capacitance, Coxe. Toxe is the sum of three thicknesses,

•  Typically, Toxe is larger than Tox by 6–10 Å.

ELL740/Dr. Abhisek Dixit slide#37

 MOS C-V: QME on Vt
•  In addition, there is another quantum effect that increases the threshold voltage. At
high substrate doping concentration, the high electric field in the substrate at the oxide
interface causes the energy levels to be quantized and effectively increases Eg and
decreases ni.
•  This requires the band to bend down more before reaching threshold, i.e., causes φst
to increase. The net effect is that the threshold voltage is increased by 100mV or so
depending on the doping concentration due to this quantum effect on threshold
voltage.

ELL740/Dr. Abhisek Dixit slide#38