Program : B.

E
Subject Name: VLSI Design
Subject Code: EC-8001
Semester: 8th
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Unit-2
Device Modeling:
Dc Models, Small Signal Models, MOS Models, MOSFET Models in High Frequency and small signal, Short
ha el devi es, Su th eshold Ope atio s, Modeli g Noise Sou es i MOSFET’s, Diode Models, Bipola
Models, Passive component Models

Introduction to device modeling :

Device models used for developing design equations, hand analysis and initial computer simulations. DC
model are useful for biasing and large signal analysis and AC models are useful for small signal steady state
analysis.
The dc model of a device is a mathematical or numerical relationship that relates the actual terminal voltage
and current of the device at dc and low frequency. The dc model should be valid over a large range of terminal
voltage and current. It is valid at frequency where the difference between the actual and dc solution is
deemed negligible for the problem under inversion.

DC Model

Simple dc Equivalent Simple small

model circuit signal model
(ac)

Equivalent
Equivalent
circuit
circuit

Accurate high and low

frequency model suitable for
computer simulation Frequency
dependent small
Fig.2.1 Approach to device modeling signal Equivalent
circuit

Starting point for modeling for BJT and MOSFET will be a DC model as shown in fig.2.1. From this DC model, a
linear small signal model and equivalent simplified ac and dc circuits will be derived. The models will be
expanded to provide a better aggrement between the theoretical and experimental results for use in
computer simulation.
DC Modeling:
Large signal modeling, which is also known as DC modeling, of MOSFETs deals with the situation when input
signal is large. This is mainly applicable to digital design where the input signal is either low or high .At lower
input signal the gate voltage of MOSFET is less than the threshold voltage and at high input signal the applied
gate voltage is more than threshold voltage . Thus the MOSFET switches operate from cut-off to saturation.
However if the higher side of the input signal is small and less than threshold voltage of the MOSFET, the
transistor remains in cut-off with or without the presence of the input signal.
Small Signal Models:
Small-signal modeling is a normal analysis technique in electronics circuit which is used to show the
performance of electronic circuits contain nonlinear devices with linear equations. A small-signal model is an
AC equivalent circuit in which the nonlinear circuit elements are replaced by linear elements whose values are

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given by the first-order (linear) estimate of their characteristic curve near the bias point. It is relevant to
electronic circuits in which the AC signals, the time-varying currents and voltages in the circuit, have a small
magnitude compared to the DC bias currents and voltages.
A small signal model takes a circuit and based on an operating point (bias) and liberalize all the components.
Nothing changes because the assumption is that the signal is so small that the operating point (gain,
capacitance, etc.) doesn't change.
For the linear small signal four-terminal network shown in Figure 2.2 A, one terminal (terminal 4) is
selected as a reference. With this reference and the assumption of linearity, it follows by definition that
the y-parameter (admittance parameter) relate the terminal voltages and currents by the expressions
1 i1 I1=y11v1 + Y12v2 + Y13v3
2 i2 + I2=y21v1 + Y22v2 + Y23v3
4 –Terminal Small +
Signal Network 3 i3
V2
V1 I3=y31v1 + Y32v2 + Y33v3
+

V3 Where ykj = ik /vj limit vm =0, m1,2,3,
4
mj

Fig.2.2A: Linear small Signal 4-terminal network

Since the small signal voltage and current variables are the time-varying part of the corresponding total
terminal voltage and current variables in the parent network relative to the Q-point figure 2.2.B, then it

by the expression Ykj = Ik /Vj limit vm = quiescent value, m1,2,3.

follows that the Y- parameters can be obtained from the large signal variables and thus from the dc model

A small signal equivalent circuit of the multiport network is often found useful for circuit analysis and
design. It is easy to verify that the circuit shown in Figure 2.2.C has the same i-v characteristics as the
four terminal network of Figure 2.2 A, which is characterized by and hence is electrically indistinguishable.
1 I1
Corresponding 4 – 2 I2 +
Terminal parent +
Network (voltage and 3 I3 V1
+ V2

current represent total
4 V3
values)

Fig.2.2.B: Parent 4-terminal network

1 i1 i2 2
+ +

y13 v13 V2
V1 Y11 y12 v2 Y21 v11 Y22
Y23v3
-
-
i3 3
+

Y33 V3
Y31 v11 Y32v2
-

Fig. 2.2.(C) Equivalent circuit for small signal network

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Use of DC model in circuit analysis:

Designers are interested in controlling the relationship between two or more electrical port variables. A two
port network as shown in fig. 2.3 having both large and small signal port variables. Relationship includes- large
Signal transfer characteristics, such as VO Vs VI or VI Vs II and small signal transfer characteristics such as,
voltage gain AV = vo / vi or input impedance, Zin = vi / ii .
II ii io IO
+ Electrical +


VI vi vo V O ZL

Network

The dc transfer characteristics of a circuit are obtained by using the dc device models to characterize all
devices in the network. To develop the dc performance of simpler networks, it is necessary to make
simplifying assumptions on the device models. Without these assumptions mathematical expressions relating
the electrical parameters of interest are often complicated that they obscure even the basic functionality of
the circuit. The simplified dc analysis is often useful for biasing purposes and can provide useful insight into
the small signal operation of the circuit. The low frequency small signal characteristics of a circuit are obtained
in two ways- 1) replacing all devices and elements with a linear small signal equivalent circuit in which
parameters in the small signal models are a function of the Q-point. Independent dc voltage sources are short
circuits and independent dc current sources are open circuits. 2) is based upon dc transfer characteristics. If x i

these variable are related by expression (xo / xi ) = ( XO /  XI ) where the partial derivative of the large signal is
and xo are small signal input and output variables and X I and XO are corresponding large signal variables, then

evaluated at the Q-point. The result obtained from direct small signal analysis will be identical to those
obtained by differentiation of large signal variables provided that the small signal models of the devices are
obtained from the same dc model used to obtain the dc transfer characteristics.
Advantages offered by obtaining the small signal transfer characteristics directly from a small signal analysis
rather than from differentiation of the dc variables are-
1) Since small signal equivalent circuit is linear , the analysis of the small signal equivalent circuit is typically
less involved than the dc analysis.
2) More accuracy is practically attainable with the direct small signal analysis.
3) Frequency response of a network is expressed in terms of the small signal electrical parameters.

MOS Models:-
The MOS transistor is a majority-carrier device in which the current in a conducting channel between the
source and drain is controlled by a voltage applied to the gate. In an nMOS transistor, the majority carriers are
electrons; in a pMOS transistor, the majority carriers are holes. The behavior of MOS transistors can be
understood by first examining an isolated MOS structure with a gate and body but no source or drain. a simple
MOS structure. The top layer of the structure is a good conductor called the gate. Early transistors used metal
gates. Transistor gates soon changed to use Polysilicon, i.e., silicon formed from many small crystals, although
metal gates are making resurgence at 65 nm .The middle layer is a very thin insulating film of SiO2 called the
gate oxide. The bottom layer is the doped silicon body. The figure shows a p-type body in which the carriers
are holes. The body is grounded and a voltage is applied to the gate. The gate oxide is a good insulator so
almost zero current flows from the gate to the body.
In Figure 2.4 (a) a negative voltage is applied to the gate, so there is negative charge on the gate. The mobile
positively charged holes are attracted to the region beneath the gate. This is called the accumulation mode. In
Figure 2.4 (b), a small positive voltage is applied to the gate, resulting in some positive charge on the gate. The
holes in the body are repelled from the region directly beneath the gate, resulting in a depletion region
forming below the gate. In Figure 2.4 (c), a higher positive potential exceeding a critical threshold voltage Vt is

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applied, attracting more positive charge to the gate. The holes are repelled further and some free electrons in
the body are attracted to the region beneath the gate. This conductive layer of electrons in the p-type body is
called the inversion layer. The threshold voltage depends on the number of dopants in the body and the
thickness tox of the oxide. It is usually positive, as shown in this example, but can be engineered to be negative.

Poly silicon gate

SiO2 INSULATOR
Vg<0 P-TYPE BODY

Fig. a

0<Vg<vt Depletion
Region
Fig. b

Vg>Vt
Inversion region
Fig. c
Depletion Region

DC MOSFET Model:-
Fig.2.4a :MOS
It is desired to obtain structure model
mathematical demonstrating (a) Accumulation,
of the MOSFET (b) Depletion,
that will accurately and (c)
predict theInversion
experimental
characteristics over a wide range of geometrical and process parameters. The starting point will be the dc
model which is introduced by SAH, given by-

ID =
= 0 for VGS < VT ------------------------------------------ 2

IG = 0

Which is derived for small signal values of V DS. Small signal values of VDS corresponds to the ohmic region of
operation. From equatio , L = ha el le gth; W = ha el idth; K = t a s o du ta e pa a ete , VT =
Th eshold oltage. L & W a e desig pa a ete s a d K a d VT are process parameters.
The value of VDS = VGS  VT causes the channel to pinch off. For VDS > VGS VT, the current ID remains constant

evaluating equation 1 at VDS = VGS  VT to obtain

(independent of VDS) at the value obtained when the channel first pinched off. This value can be obtained by

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ID =
Which is good for VDS > VGS  VT and VGS > VT. The operation where equation 3 is valid is termed the saturation
region.
The MOSFET model based upon equation 1 and 3 is termed SAH’S odel.
The more accurate expression for the drain current in the saturation region is given by-
ID =
Where the parameter  ( termed as channel length modulation)

 is the coefficient that represents the linear dependence of I D on VDS, in the saturation region.
The MOSFET model defined by equation 1 and equation 4 is termed the Shichman-Hodges model.

The threshold voltage VT, depends upon the bulk-source voltage. since the bulk channel voltage will affect the
carrier in depletion region under the gate, which in turn affect the voltage applied to the gate to form the
inversion layer. Thus-
--------------------------------- 5
Where, VBS is the bulk to source voltage; VTO,  and  are process parameters.
VTO is threshold voltage for VBS = 0;  is bulk threshold parameter;  is inversion surface potential
For n-channel transistors the devices are termed as enhancement if VTO > 0 and depletion if VTO < 0.
The t a s o du ta e pa a ete K , a e e p essed as
K’ = µ COX
where, COX is capacitance density ( capacitance per unit area) of the gate channel capacitor. µ is channel
mobility.
Equivalent circuit for DC operation of the MOSFET is shown in figure
ID D
G ID D
G +
+ + +
RFET = {L/K’W VGS VT)}
RDS = { L/K’W(VGS VT)}
VGS VDS VDS
VGS
 
S  
S S S
Figure2.5(a): Ohmic region (small VDS) Figure2.5 (b): Saturation region

Assuming linear relationship between ID and VDS result in an equivalent FET resistance of

MOSFET is often used in the ohmic region as a voltage variable resistor (VVR) by using VGS as the controlling
voltage. the equivalent circuit in 2.5 (b) is valid in the saturation region. The effect of RDS in the equivalent
circuits are negligible in most DC applications.

Problem: Using NMOS process parameters determine the output voltage for the circuit shown- if R = 5 kΩ.
6V
VT0 = 0.75V
W=30µ ID R
L=3µ VO
=0.4 V1/2 10V
M1

 = 0.6 V 3V

K’ =

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Answer: (a) Initially the region of operation of M1 is determined. So, obtain VT.
; VT = 1.74 V. Since,

saturation region. Then neglecting  effect-

VGS = 3V, it can be concluded that M1 is in either ohmic or saturation region. So, assuming M1 is in the

ID = = 190.5 µA.
Thus, VO = 6V ─ ID R = 3.14 V
Since, VDS = VO, VDS > VGS ─ VT. Thus the initial assumption an the region of operation was valid and V O = 3.14
volt is correct.
(b) Maximum value of R ( RMAX ) for saturation region operation will be that value which makes V DS = VGS─ VT
So, 6V ─ 190.5 µA RMAX = .9 kΩ.

Problem. Obtain the small signal model of the two port device shown in figure 01 , for V1 > 0 and V2 >0.
Assume a 2-port device is characterized by the equations, I1 = 0 and I2 =
1 I1 I2 2
Fig.01
+ 2-port +

V1 v1 v2 = vO

network

3 4

y21 = I2 / V1 = 2 h V1 (1+VO)

Answer: By definition, the y- parameter relates the terminal voltages and currents by the expressions as

y22 = I2 / V2 = h

2
1
+ +
y11 = y12=0 Y21 V1
Thus small signal device model is V1 Y22 V2

 
3 4

Small Signal MOSFET model:

Small signal MOSFET model can be obtained directly from DC model. Since there are 3-regions of operation
identified in the DC model, hence there are different small signal models for the MOSFET corresponding to
each of these regions.
In cutoff region, ID ≈ 0, resulting in a minor small signal model. Since MOSFET is not biased for small signal
operation in ohmic region. Most small signal applications employ the MOSFET biased in the saturation region.
In saturation region-
ID =
And, IG = IB = 0.
For notational convenience, g, d & b will be used to designate the gate, drain and bulk nodes of the MOSFET.
Parameter, Ydg = gm is a dominant parameter in the model.
Ydg = gm = ID / VGS =
Upon relating VGS ─ VT to the quiescent drain current and noting that the  effects are typically negligible in
this model, it follows that
gmb =  gm where,  =  / 2( - VBSQ )
gds = λ | I DQ |

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rds = 1/gds

Id D
G B
+ +
Vgs Vbs gm vgs gmbv bs gds

─
S

Figure2.6: Small Signal Model equivalent circuit of MOSFET

From the figure 2.6. current gmvgs typically dominates the drain current, it should be apparent that the small
signal MOSFET is inherently a good transconductance amplifier.

MOSFET Models in High Frequency :

At high frequencies both the de and small signal models of the MOSFET introduced in the previous sections
are generally considered inadequate. These limitations are to a large extent attributable to the
unavoidable parasitic capacitances inherent in existing MOS structures. These parasitic capacitances can
be divided into two groups. The first group is composed of those parasitic capacitors formed by
sandwiching an insulating dielectric of fixed geometric dimensions between two conductive regions. The
capacitance of these types of devices remains essentially constant for local changes in the voltage applied to
the plates of the capacitor. Assuming the area of the normally projected intersection of the capacitor
plates is A and that the distance between the plates is constant with thickness d, then this capacitance is
given by the expression
C= ε A /d
Whe e ε the pe itti it of the diele t i ate ial sepa ati g the plates. C d called the capacitance density.
C=Cd A where Cd is a process parameter and A is a design parameter
The second group is composed of the capacitors formed by the separation of charge associated with a pn
junction. The depletion region associated with the semiconductor junction serves as the dielectric. These
junction capacitors are quite voltage dependent. They are typically expressed in terms of the process
parameter qo, which denotes the junction capacitance density at zero volts bias. The capacitance of these
devices can be approximated by
C= Cjo A / (1 – VF /φB)n
Where A is the junction area, VF is forward DC bias voltage , φB barrier potential typically 0.7V range, n is
constant, depending upon the type of junction such as step graded junction, n = ½ whereas linear graded
junction, n=1/3..

Fig.2.7 : Parasitic capacitors in MOS transistor for n channel device

The parasitic capacitors that dominate the high-frequency behavior of MOS transistors are shown in figure
above The capacitors CBD1 , CBC1 CBS1 are all voltage-dependent junction capacitors. The remaining
capacitors are parallel plate capacitors governed by C= C D/A Some of the parasitic capacitors are actually

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distributed devices. In addition, some of the capacitor values are operating region dependent. To simplify
analysis, a model of the MOSFET in each of the three operating regions containing only lumped nodal
capacitors will be presented. Comments about each of the parasitic capacitors follow.

DRAIN

CGD
CBD

CBG

BULK
GATE

CGS CBS

SOURCE

Fig 2.8 : Parasitic Capacitor lumped network

In the above figure show that parasitic capacitance between the source and drain it can be seen from figure
that no physical mechanism exists to create such a capacitor.
Region
Cutoff Ohmic Saturation
CGD COX WLD COX WLD + (1/2) WLCOX COX WLD
COX WLD + (2/3)
CGS COX WLD COX WLD + (1/2) WLCOX WLCOX
CBG COX W L 0 0
CBD CBD1 CBD1 +(CBC1)/2 CBD1
CBS CBS1 CBD1 +(CBC1)/2 CBD1 +(CBC1)/(2/3)
Table 2.1 : Parasitic capacitor value according to operating region

Short channel devices :

A MOSFET device is considered to be short when the channel length is the same order of magnitude as the
depletion-layer widths of the source and drain junction. As the channel length L is reduced to increase both
the operation speed and the number of components per chip, the so-called short-channel effects arise.
As the te h olog s ali g ea hes ha el le gths less tha a i o L< , se o d o de effe ts, that e e
ig o ed i de i es ith lo g ha el le gth L> , e o e e i po ta t.
MOSFET s o i g those di e sio s a e alled short channel devices.
The main second order effects are Velocity Saturation.

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Short-Channel Effects:
The short-channel effects are attributed to two physical phenomena:
1. The limitation imposed on electron drift characteristics in the channel,
2. The modification of the threshold voltage due to the shortening channel length.
In particular five different short-channel effects can be distinguished:
1. drain-induced barrier lowering and punch through
2. Surface scattering
3. Velocity saturation
4. Impact ionization
5. Hot electrons

Noise Sou es i MOSFET’s:

The noise sources in a MOS transistor are:
Thermal noise in the channel
A MOSFET has in normal working order an inverse resistive channel between the drain and the source. The
gate voltage forms with minority carriers the channel. In the extreme case when the drain source voltage = 0
VDS , the channel can be treated as a homogeneous resistor.
1/f Noise in MOS Transistors
1/f noise has been observed in all kind of devices, from homogeneous metal film resistors and different kind
of resistors to semiconductor devices and even in chemical concentrated cells. Because 1/f noise is well spread
over the components, people think that there a fundamental physical mechanism is behind it. Till now such a
mechanism is not yet found. There is a lot of experimental evidence that several mechanisms are involved in
generating 1/f noise.
Diode Models:
DC Diode Model:

The diode is characterized by the low frequencies by the

I
I = IS ( e V/nVt  1 ) where parameters IS, n, and Vt
equation
+ 
V characterize the device. Where Is is saturation
Fig. 2.7: Variable convention for a diode current, n is emission coefficient.

and parameter Vt = kT / q he e k is oltz a s o sta t, T is the a solute te pe atu e i deg ee Kel i a d

q is the charge of an electron. At room temperature (300°K), Vt is 26 mV. The emission coefficient takes on a
value of about 1 for silicon. The saturation current can be expressed as Is = JsA, where Js is a process
parameter equal to the saturation current density and A is the cross sectional area of the junction.

modeling the diode by I = Is . e V/nVt . Likewise, for V <  0.25 V, the diode is accurately modeled by I =  Is.
The diode equation simplifies for V >> nVt. Under forward biased greater than 0.25 V, no accuracy is lost in

The piecewise-linear model shown in fig.2.8, is often used for biasing and/or large signal applications. The
piecewise-linear model is mathematically given by the equations
V = I r + V for I >0 and I = 0 for V < V. Where r ia an ON resistance of the diode and V is diode cut-in
voltage.
I

+ r for I > 0
V
V

Fig. 2.8: Piecewise-linear diode model

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BJT MODEL (DC BJT MODEL):

The starting point will be the dc model introduced by Ebers and Moll in1954.
In this model the relation between the terminal variable is given by
IC = IS(e (VBE /Vt ) -1) –IS/αR ((e (VBc /Vt ) -1)
IE =–IS/αf ((e (VBE /Vt ) -1) + IS(e (VBC /Vt ) -1)
Where IS, αf ,αR and Vt four parameter characterize by device.
IS =transport saturation
αf =large signal forward current gain of common base configuration
αR = large signal Reverse current gain of common base configuration
Vt = kT/q he e, k is oltz a s o sta t, T is a solute te pe atu e i deg ee Kel i a d is the ha ge of
an electron. At room temperature (300°K), Vt = 26mV.
The two Ebers - Moll equation with KVL and KCL ie. IB = −IC − IE ; VCE = VBE - VBC applied to transistor itself
provide four independent equations relating the six terminal variables, IC, IB , IE, VCE, VBC, and VBE.
The BJT is characterized by these four equations. It should be noted that there is complete functional
symmetry in the device model with respect to the collector and emitter terminals. This is comforting
since the NPN transistor can be thought of as a sandwich of a p-type region between two n-channel
layers.
The parameters αF and αR are determined by impurity concentrations and junction depths, and as such
are process parameters. The parameter VI is a function of two physical constants and temperature and
thus cannot be considered a design parameter. The parameter Vt should not be confused with the threshold
voltage for a MOSFET, which uses the symbol VT Because of the temperature dependence, Vt can be
considered an environmental parameter. The transport saturation current can be expressed as
IS = JS A. where A is the area of the emitter and JS, the transport saturation current density.
An equivalent circuit for the bipolar transistor based upon the Ebers-Moll model is sometimes useful. The
circuit of figure below serves as such an equivalent circuit where the currents in the two diodes satisfy the
standard diode equations
IF =IS/αf(e(VBE/VT) − 1); IR =IS/αF(e(VBC/VT) − 1); JS = 6 X10-10 µA/mil2
αF = 0.99; αR = 0.3; VAF =200V; VAR =200V
IC
C

DR αF / F

IR
B
IB IF
DF
αR / R

E
IE
Figure: Equivalent circuit of BJT based upon Ebers-Moll Model

PASSIVE COMPONENT MODELS:

Discrete passive components are quite easy to model. Resistors and capacitors can generally be modeled by
ideal resistors and capacitors respectively. The major limitations are manufacturing tolerances and

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temperature deviations - both of which can be reduced to acceptable levels in most applications through
judicious component selection/specification.
Monolithic resistors and capacitors are far from ideal. They are typically both temperature and voltage
dependent. The practical range of values is seriously limited by area constraints. Large resistor or capacitor
values are impractical. Process deviations preclude accurate control of absolute component values.
Parasitic effects are often quite significant. Relative accuracy between passive components is, however,
often quite good.
The following figure of merits used to characterize passive components.
Resistors
1. Sheet resistance 2. Resistance density 3. Temperature coefficient of resistance
4. Voltage coefficient of resistance 5. Absolute accuracy 6. Relative (ratio) accuracy
Capacitors
1. Capacitance density 2. Temperature coefficient of capacitance
3. Voltage coefficient of capacitance 4. Absolute accuracy 5. Relative (ratio) accuracy
The resistance density is generally a function of the process parameters and layout design rules.
The capacitance density is a process parameter.
The absolute accuracy is a measure of how accurately the actual resistor and capacitor values can be
controlled during processing.
The relative (ratio) accuracy is a measure of how closely two resistors or capacitors can be matched.
The ratio accuracy is affected by component placement on a die, device geometry, the physical size of the
components, and the nominal relative values of the components themselves.
Monolithic Capacitors:
Any structure in which a voltage induced separation of charge occurs can serve as a capacitor.
In a MOS process, the most common capacitors are formed by sandwiching a thin oxide layer between two
conductive polysilicon layers. These capacitors are nearly independent of applied voltage and can be
modeled as ideal capacitors. The major limitation is the large parasitic capacitor that is always formed
between the lower plate and the substrate.
When the luxury of the double polysilicon layers is not present in MOS processes, metal-poly, metal-
diffusion (lower plate formed by a diffused region in the substrate), or poly-diffusion capacitors with an
Si02 dielectric are used. These capacitors typically have a lower capacitance density and/or increased
voltage dependence and/or a less conductive lower plate than the double poly capacitors.
In the bipolar process, the most desirable common capacitors are metal diffusion capacitors with an Si02
dielectric. The heavily doped emitter diffusion is used for the lower diffusion plate. The characteristics are
quite good, but an additional mask step is required for forming the dielectric region.
Alternatives include the voltage-dependent junction capacitances formed by either the B-C or B-E junction.
The B-E junction offers reasonable capacitance density at the expense of a limited reverse breakdown voltage
(typically 5 to 7 V). The B-C junction reverse breakdown voltage is quite high (typically in the 30 V range),
but the capacitance density is quite low. All junction capacitors are limited by requirements that the
junctions remain reverse biased (actually, not forward biased by more than a few tenths of a volt).
Monolithic Resistors:
Monolithic resistors are passive devices and others contain active devices.
Major tradeoffs must be made between linearity, area, biasing complexity, and temperature characteristics
in monolithic resistors.
In standard MOS processes, the most ideal resistors are merely strips of polysilicon. Diffusion strips are
also used for resistors but exhibit an undesirable nonlinear relationship between voltage and current. Ion
implants offer some advantages over depositions for the introduction of impurities to control absolute
resistance values in diffused resistors. Thin film resistors with excellent characteristics are added in some
specialized processes. For each of these types of resistors, a serpentine pattern is often used to improve
packing density. The major limitations of these resistors are the low resistance densities, which limit the total

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resistance to quite small values; the high deviations in resistance due to process variations; and large
temperature coefficients.
In bipolar processes epitaxial strips or diffusion strips are commonly used for resistors. These devices are
quite linear. The base diffusion is often used because of its reasonably high sheet resistance
To prevent forward biasing of the "base-collector" junction, a contact is needed to the epitaxial layer.
This will be typically connected to the most positive power supply voltage used for the circuit.
It can be argued that the resistance of the base-diffused resistor could be increased if the depth of the p-
base diffusion could be decreased. The depth of this diffusion, however, is generally determined to
optimize performance of the BJTs themselves.
An alternative is to place an n emitter diffusion in the p base region. This masking step already exists
and will result in a significant increase of the sheet resistance of the underlying p diffusion. Such a
device, which is termed a pinch resistor
Contact must be made to both the n+ emitter diffusion and the n- epitaxial region. These regions are
typically both connected to the most positive power supply voltage used for the circuit. Although the
resistance increases significantly due to this pinching, the variance in emitter and base diffusion depths
due to process variations makes the tolerances of pinch resistors quite wide. They also exhibit an increased
voltage dependent nonlinearity and are limited in voltage range to circumvent break- down of the reverse-
biased base-emitter junction. Other types of pinch resistors (e.g., epitaxial pinch) can also be made.
Several active resistors often offer considerable reductions in area requirements compared to passive
resistors at the expense of increased nonlinearity and/or reduced signal swing and/or complicated
biasing requirements.

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