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    Department of Electronics and Communication Engineering

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    ece3a MITM
    This document outlines the course outcomes for the subject "Verilog HDL" with course code 18EC56 taught at Maharaja Institute of Technology Mysore. It lists 4 course outcomes describing students' ability to comprehend Verilog syntax and design flow, develop Verilog modules for digital circuits using different modeling techniques, analyze behavior of Verilog models, and design digital blocks using hierarchical modeling. It maps each course outcome to the program outcomes and program specific outcomes to justify how the course outcomes align with the program criteria. The course outcomes were approved on an unspecified date and the mapping is coordinated by faculty members.

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    Department of Electronics and Communication Engineering

    Uploaded by

    ece3a MITM
    141 views2 pages
    This document outlines the course outcomes for the subject "Verilog HDL" with course code 18EC56 taught at Maharaja Institute of Technology Mysore. It lists 4 course outcomes describing students' ability to comprehend Verilog syntax and design flow, develop Verilog modules for digital circuits using different modeling techniques, analyze behavior of Verilog models, and design digital blocks using hierarchical modeling. It maps each course outcome to the program outcomes and program specific outcomes to justify how the course outcomes align with the program criteria. The course outcomes were approved on an unspecified date and the mapping is coordinated by faculty members.

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    18EC56_CO_PO_2021-22

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    This document outlines the course outcomes for the subject "Verilog HDL" with course code 18EC56 taught at Maharaja Institute of Technology Mysore. It lists 4 course outcomes describing students' ability to comprehend Verilog syntax and design flow, develop Verilog modules for digital circuits using different modeling techniques, analyze behavior of Verilog models, and design digital blocks using hierarchical modeling. It maps each course outcome to the program outcomes and program specific outcomes to justify how the course outcomes align with the program criteria. The course outcomes were approved on an unspecified date and the mapping is coordinated by faculty members.

    Copyright:

    © All Rights Reserved
    Download as DOCX, PDF, TXT or read online from Scribd
    Download as docx, pdf, or txt
    141 views2 pages

    Department of Electronics and Communication Engineering

    Uploaded by

    ece3a MITM
    This document outlines the course outcomes for the subject "Verilog HDL" with course code 18EC56 taught at Maharaja Institute of Technology Mysore. It lists 4 course outcomes describing students' ability to comprehend Verilog syntax and design flow, develop Verilog modules for digital circuits using different modeling techniques, analyze behavior of Verilog models, and design digital blocks using hierarchical modeling. It maps each course outcome to the program outcomes and program specific outcomes to justify how the course outcomes align with the program criteria. The course outcomes were approved on an unspecified date and the mapping is coordinated by faculty members.

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    © All Rights Reserved
    Download as DOCX, PDF, TXT or read online from Scribd
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    MAHARAJA INSTITUTE OF TECHNOLOGY MYSORE

    BELAWADI, SRIRANGAPATNA TALUK, MANDYA-571477

    Department of Electronics and Communication Engineering


    Course Outcome Date: / /2021
    Subject: Verilog HDL Subject Code: 18EC56
    CO’s DESCRIPTION OF THE OUTCOMES
    18EC56.1 Present the comprehension of the IC Design flow, syntax, lexical conventions, data
    types, system tasks, compiler directives and logic synthesis in Verilog HDL.
    18EC56.2 Develop Verilog modules for digital circuits using gate level and data flow modeling,
    behavioral modeling using different control structures and related statements and for
    system tasks as well.
    18EC56.3 Analyze the behavior of structural, dataflow and behavior modeling procedures
    written in Verilog.
    18EC56.4 Design digital functional blocks for a given set of specifications using hierarchical
    modeling concepts in Verilog.

    PO No PSO
    CO No
    1 2 3 4 5 6 7 8 9 10 11 12 1 2
    18EC56.1 - - - - - - - - - 2 - - - -
    18EC56.2 3 2 - - - - - - - - - - 3 -
    18EC56.3 2 2 - - - - - - - - - - 2 -
    18EC56.4 2 2 2 - 2 - - - - - - - 2 -
    CO
    2.33 2 2 - 2 - - - - 2 - - 2.33 -
    Average

    Rajesh N Dinesh M.A. Manasa M G Dinesh M.A.


    Faculty Course Coordinator

    Approval of the COs and their mapping with POs and PSOs was given on / /

    Criterion 3 Coordinator NBA coordinator HOD

    Convener Principal
    MAHARAJA INSTITUTE OF TECHNOLOGY MYSORE
    BELAWADI, SRIRANGAPATNA TALUK, MANDYA-571477

    Department of Electronics and Communication Engineering


    Mapped
    CO’s Description of the Outcomes Justification
    to
    Present the comprehension of the IC Design
    18EC56. flow, syntax, lexical conventions, data types,
    PO10 - 2 Main idea is understandable
    1 system tasks, compiler directives and logic
    synthesis in Verilog HDL.
    Demonstrates a comprehensive Understanding of
    PO1 – 3
    Develop Verilog modules for digital circuits underlying theory and application to the problem.
    using gate level and data flow modeling, Demonstrates an ability to identify an appropriate
    18EC56.
    behavioral modeling using different control PO2 – 2 strategy for generating approaches for solving a
    2
    structures and related statements and for problem.
    system tasks as well. Demonstrates a comprehensive understanding of
    PSO1 - 3
    underlying theory and application to the problem.
    Demonstrates an ability to understand the application of
    PO1 – 2
    theory to the problem.
    Demonstrates an ability to identify an appropriate
    Analyze the behavior of structural, dataflow and
    18EC56.3 PO2 – 2 strategy for generating approaches for solving a
    behavior modeling procedures written in Verilog.
    problem.
    PSO1 – Demonstrates an ability to understand the application of
    2 theory to the problem.
    Demonstrates an ability to understand the application of
    PO1 – 2
    theory to the problem.
    Demonstrates an ability to identify an appropriate
    PO2 – 2 strategy for generating approaches for solving a
    Design digital functional blocks for a given set of problem.
    18EC56.4 specifications using hierarchical modeling Considers multiple approaches to solving a problem,
    PO3 – 2
    concepts in Verilog. which is justified and considers consequences.
    Demonstrates an ability to identify and use relevant
    PO5 – 2
    tools for an engineering activity.
    Demonstrates an ability to understand the application of
    PSO1 - 2
    theory to the problem.

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