VO DURE V INTRODUCTION TO MICROELECTRONIC FABRICATION Sree ONO Ebi! OoM RICHARD C. JAEGER Modular Series on Solid State Devices Gerold W. Neudeck © Robert F. Pierret, Series EditorsPHYSICAL CONSTANTS. Symbol Name Value q ‘Magnitude of electronic charge 1.602% 10-"C me Electron rest mass 9.109 10-kg m, Proton rest mass 1.67310 “kg c ‘Speed of light in vacuum 2.998 % 10" m/s & Permittivity of vacuum 8.854 10 "Fim k Boltzmann’s constant 1.381 X10 7 I/K 8617 10 SeV/K h Planck’s constant 6625x108 4.135 10-8 eV-s Ay Avogadio number 6.022 x 10" molecules/kg-mole aT ‘Thermal energy 0.02586 eV (T= 27°C) 0.02526 eV (T= 20°C) E Bandgap of silicon at 300K 1i2ev K Relative permittivity of silicon 17 Ky Relative permittivity of silicon dioxide 39 n Intrinsic carrier density in silicon at 300K 10"%em? CONVERSION FACTORS (0-*cm, mil? 645.2 yum? 10m = 6.45 10cm? lev .602 x 10°F a 24/6 pm (E in eV)MODULAR SERIES ON SOLID STATE DEVICES Gerold W. Neudeck and Robert F. Pierret, Editors Volume V Introduction to Microelectronic Fabrication Second Edition Richard C. Jaeger Auburn University Prentice Hall Upper Saddle River, New Jersey 07458Library of Congress Catatoging-in-Publication Data Jaeger, Richard C. Introduction to microelectronic fabrication / Richard C. Jaeger 2nd Edition pcm, (Modular series on solid state devices: v.5) Includes bibliographical references and index. ISBN 0-201-44494-7 1. Integrated cireuits—Very large scale integration—Design and construction—Congresses. [.Title. IL Series. CIP Data available. ‘Vice President and Editorial Director, ECS: Marcia J. Horton Publisher: Tom Robbins Associate Faitor Alice Dworkin Editorial Assistant: Jody McDonell ‘Vice President and Director of Production and Manufacturing, ESM: Davie! W. Riccardi Executive Managing Editor: Vince O'Brien Managing Editor: David A. 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Ld.To My Family—Joan, Peter, and StephanieContents PREFACE xiii Chapter 1 An Overview of Microelectronic Fabrication 7 ld 12 13 14 15 A Historical Perspective 1 Au Overview of Monolithic Fabrication Processes and Structures 5 Metal-Oxide-Semiconductor (MOS) Processes 7 1.3.1 Basic NMOS Process 7 132 Basic Complementary MOS (CMOS) Process 9 Basic Bipolar Processing 10 Safety References 14 Problems 14 Chapter 2 Lithography 7 21 22 23 24 25 2.6 27 ‘The Photolithographic Process 17 2.1.1 Wafers and Wafer Cleaning 19 2.1.2 Barrier Layer Formation 21 2.1.3, Photoresist Application 21 2.1.4 Soft Baking /Prebaking 22 2.1.5 Mask Alignment 23 2.1.6 Photoresist Exposure and Development 23 2.1.7 Hard Baking 25 Etching‘Techniques 25 2.2.1 Wet Chemical Etching 25 2.22 Dry Etching Plasma Systems 26 22.3 Photoresist Removal 26 2.2.4 Metrology and Critical Dimension Control 28 Photomask Fabrication 28 Exposure Systems 28 Exposure Sources 34 Optical and Electron Microscopy 37 2.6.1 Optical Microscopy 37 2.6.2 Scanning Electron Microscopy 37 2.63 Transmission Electron Microscopy 38 Summary 38 References 40 Further Reading 40 Problems 40vi Contents Chapter 3 Chapter 4 Thermal Oxidation of Silicon 43 3.1 The Oxidation Process 43 3.2 Modeling Oxidation 44 33 Factors Influencing Oxidation Rate 46 3.4 Dopant Redistribution During Oxidation 51 35 Masking Properties of Silicon Dioxide 51 3.6 Technology of Oxidation 52 3.7 Oxide Quality 53 3.8 Selective Oxidation and Shallow Trench Formation 55 3.81 Trench Isolation 56 3.8.2. Chemical Mechanical Polishing (CMP) 57 3.9 Oxide Thickness Characterization 61 3.10 Process Simulation 61 Summary 61 References 63 Problems 64 Diffusion 67 4.1 The Diffusion Process 67 42 Mathematical Model for Diffusion 68 42.1 Constant-Source Diffusion 69 42.2 Limited-Source Diffusion 70 42.3 Two-Step Diffusion 71 4.3 The Diffusion Coefficient 72 44 Successive Diffusions 74 4.5 Solid-Solubility Limits 74 4.6 Junction Formation and Characterization 76 4.6.1 — Vertical Diffusion and Junction Formation 76 462 Lateral Diffusion 78 4.6.3 Concentration-Dependent Diffusion 79 4.7 Sheet Resistance 81 4.7.1 Sheet-Resistance Definition 82 472 Invin’s Curves 85 4.7.3 The Four-Point Probe 88 4.14 Vander Pauw’s Method 88 4.8 Generation-Depth and Impurity Profile Measurement 90 48.1 Grove-and-Stain and Angle-Lap Methods 90 48.2 Impurity-Profile Measurement 91 4.9 Diffusion Simulation 93 4.10 Diffusion Systems 95 4.10.1 Boron Diffusion 97 410.2 Phosphorus Diffusion 98 4.10.3 Arsenic Diffusion 99 4.10.4 Antimony Diffusion 100Chapter 5 Chapter 6 Contents vil 4.11 Gettering 100 Summary 101 References 102 Problems 103 Jon Implantation 109 51 52 53 54 55 5.6 Implantation Technology 109 Mathematical Model for fon Implantation 111 Selective Implantation 114 Junction Depth and Sheet Resistance 117 Channeling, Lattice Damage, and Annealing 118 55.1 Channeling 118 5.5.2 Lattice Damage and Annealing 120 5.5.3 Deviations from the Gaussian Theory 121 Shallow Implantations 121 56.1 Low-Energy Implantation 122 562 Rapid’ Thermal Annealing 123 563. ‘Transient Enhanced Diffusion (TED) 123 Summary 124 References 125 Source Listing 126 Problems 126 Film Deposition 129 6.1 62 63 64 Evaporation 129 6.1.1 Kinetic Gas Theory 130 6.1.2 Filament Evaporation 132 6.13 Electron-Beam Evaporation 132 6.14 Flash Evaporation 134 6.1.5 Shadowing and Step Coverage 134 Sputtering 135 Chemical Vapor Deposition 136 63.1 CVD Reactors 137 63.2. Polysilicon Deposition 138 63.3 Silicon Dioxide Deposition 139 63.4 Silicon Nitride Deposition 140 63.5 CVD Metal Deposition 141 Epitaxy 141 64.1 Vapor-Phase Epitaxy 142 64.2 Doping of Epitaxial Layers 145 643 Buried Layers 145 64.4 Liquid-Phase and Moleculat-Beam Epitaxy 148 Summary 148 References 149 Further Reading 149 Problems 149viii Contents Chapter 7 Chapter 8 Interconnections and Contacts 151 Tm 72 a TA 75 76 Td 78 Interconnections in Integrated Circuits 151 Metal Interconnections and Contact Technology 153 721 Ohmic Contact Formation 153 7.22 Aluminum-Silicon Eutectic Behavior 154 7.23. Aluminum Spiking and Junction Penetration 155 724 Contact Resistance 156 72.5 Electromigration 157 Diffused Interconnections 158 Polysilicon Interconnections and Buried Contacts 159 7.41 Buried Contacts 160 7.42 Butted Contacts 162 Silicides and Multilayer-Contact Technology 162 1.5.1 Silicides, Polycides, and Salicides 162 75.2 Barrier Metals and Multilayer Contacts 164 ‘The Liftoff Process 164 Multilevel Metallization 166. 7.7.1 Basic Multilevel Metallization 166 7.7.2. Planarized Metallization 167 7.13 Low Dielectric Constant Interlevel Dielectrics 167 Copper Interconnects and Damascene Processes 168 78.1 Electroplated Copper Interconnect 168 7.82 Damascene Plating 168 7.83 Dual Damascene structures 169 Summary 172 References 172 Further Reading 173 Problems 174 Packaging and Yield 77 81 82 83 84 BS Testing 177 Wafer Thinning and Die Separation 178 Die Attachment 178 83.1 Epoxy Die Attachment 179 83.2 Eutectic Die Attachment 179 Wire Bonding 179 8.4.1 Thermocompression Bonding 182 84.2 Ultrasonic Bonding 183 843. Thermosonic Bonding 184 Packages 184 85.1. Circular TO-Style Packages 184 85.2 Dual-in-Line Packages (DIPs) 184Chapter 9 8.6 87 Contents ix 8.5.3. Pin-Grid Arrays (PGAs) 185 8.5.4 Leadless Chip Carriers (LCCs) 186 8.5.5 Packages for Surface Mounting 186 Flip-Chip and Tape-Automated-Bonding Processes 187 8.6.1 Flip-Chip Technology 188 86.2 Ball Grid Array (BGA) 190 8.6.3 The Tape-Automated-Bonding (TAB) Process 191 86.4 Chip Scale Packages 193 Yield 194 8.7.1 Uniform Defect Densities 194 87.2 Nonuniform Defect Densities 195 Summary 198 References 198 Further Reading 199 Problems 199 MOS Process Integration 201 ai a 93 94 Basic MOS Device Considerations 201 9.1.1 Gate-Oxide Thickness 202 9.12 Substrate Doping and Threshold Voltage 203 9.1.3 Junction Breakdown 204 9.14 Punch-through 204 9.1.5 Junction Capacitance 205 9.1.6 Threshold Adjustment 206 9.1.7 Field-Region Considerations 208 9.18 MOS Transistor Isolation 208 9.1.9 Lightly Doped Drain structures 210 9.1.10 MOS Transistor Scaling 210 MOS Transistor Layout and Design Rules 212 9.2.1 Metal-Gate Transistor Layout 213 9.2.2 Polysilicon-Gate Transistor Layout 217 9.2.3 More-Aggiessive Desigu Rules 218 9.2.4 Channel Length and Width Biases 219 Complementary MOS (CMOS) Technology 221 93.1 n-Well Process 221 9.3.2 p-Well and Twin Well Processes 221 933 Gate Doping 222 9.3.4 CMOS Isolation 224 93.5 CMOSLatchup 225 9.3.6 Shallow Trench Isolation 225 Silicon on Insulator 226 Summary 227 ‘Reterences 228 Problems 229x Contents Chapter 10 Bipolar Process Integration 233 10.1 10.2 10.3 10.4 10.5 10.6 10.7 108 10.9 ‘The Junction-Isolated Structure 233 Current Gain 235 Transit'Time 236 Basewidth 237 Breakdown Voltages 239 10.5.1 Emitter-Base Breakdown Voltage 239 10.5.2 Circular Emitters 239 10.53 Collector-Base Breakdown Voltage 240 Other Elements In SBC Technology 242 10.6.1 Emitter Resistor 243 10.6.2 Base Resistor 244 10.6.3 Epitaxial Layer Resistor 245 10.6.4 Pinch Resistor 246 10.6.5 Substrate pnp Transit 10.6.6 Lateral pnp Transistors 248 10.6.7 Schottky Diodes 249 Layout Considerations 249 10.7.1 Buried-Layer and Isolation Diffusions 249 10.7.2 Base Diffusion to Isolation Diffusion Spacing 251 10.73 Emitter-Diffusion Design Rules 252 10.7.4 A Layout Example 252 Advanced Bipolar Structures 253 10.8.1 Locos Isolated Self-Aligned Contact Structure 254 10.82. Dual Polysilicon Self-Aligned Process 254 10.83 The Silicon Germanium Epitaxial Base Transistor 257 Other Bipolar Isolation Techniques 259 10.9.1 Collector-Diffusion Isolation (CDI) 259 10.92 Dielectric Isolation 259 10.10 BILMOS 262 Summary 263 References 264 Problems 265 Chapter 11 Processes for MicroElectroMechanical Systems: MEMS 269 11.1 11.2 11.3 Mechanical Properties of Silicon 270 Bulk Micromachining 271 11.2.1 Isotropic and Anisotropic Etching 271 11.22 Diaphragm Formation 273 11.23 Cantilever Beams and Released Structures 275 Silicon Etchants 277 11.3.1 Isotropic Etching 277 113.2 Anisotropic Etching 278Contents xi 114 Surface Micromachining 279 11.4.1 Cantilever Beams, Bridges and Sealed Cavities 279 11.4.2 Movable In-Plane Structures 279 11.4.3 Out-of-Plane Motion 282 11.44 Release Problems 286 11.5. High-Aspect-Ratio Micromachining: ‘The LIGA Molding Process 288 11.6 Silicon Wafer Bonding 289 11.6.1 Adhesive Bonding 289 11.6.2 Silicon Fusion Bonding 289 11.6.3 Anodic Bonding 291 11.7 IC Process Compatibility 292 11.7.1 Preprocessing 292 11.7.2 Postprocessing 292 11.7.3 Merged Processes 294 Summary 295 References 296 Problems 298 AINSWERS TO SELECTED PROBLEMS 301 INDEX 303Preface ‘The spectacular advances in the development and application of integrated circuit (IC) technology have led to the emergence of microelectronics process engineering as an independent discipline. Additionally, the pervasive use of integrated circuits requires a broad range of engineers in the electronics and allied industries to have a basic under- standing of the behavior and limitations of ICs. One of the goals of this buuk is tw address the educational needs of individuals with a wide range of backgrounds. This text presents an introduction to the basic processes common to most IC technologies and provides a base for understanding more advanced processing and design courses, In order to contain the scope of the material, we deal only with mater- ial related to silicon processing and packaging. The details of many problems specifi- cally related to VLSI/ULSI fabrication arc left to texts on advanced processing, although problem areas are mentioned at various points in this text, and goals of the International Technology Roadmap for Semiconductors are discussed as appropriate. Chapter 1 provides an overview of IC processes, and Chapters 2-6 then focus on the basic steps used in fabrication, including lithography, oxidation, diffusion, ion implantation and thin film deposition, and etching. Interconnection technology, packag- ing, and yield are covered in Chapters 7 and 8. It is important to understand interactions between process design, device design, and device layout. For this reason, Chapter 9 and 10. on MOS and bipolar process integration have been included. Chapter 11 provides a brief introduction to the exciting area of Microelectromechanical Systems (MEMS). Major changes in the second edition of this text include new or expanded cover- age of lithography and exposure systems, trench isolation, chemical mechanical polish- ing, shallow junctions, transient-enhanced diffusion, copper Damescene processes, and process simulation. The chapters on MOS and bipolar process integration have been substantially modified, and the chapter on MEMS is entirely new. The problem sets have been expanded, and additional information on measurement techniques has been included, ‘The text evolved from notes originally developed for a course introducing seniors and beginning graduate students to the fabrication of solid-state devices and integrated circuits. A basic knowledge of the material properties of silicon is needed, and we use Volume I of this Series as a companion text. An introductory knowledge of electronic components such as resistors, diodes, and MOS and bipolar transistors is also useful. ‘The material in the book is designed to be covered in one semester. In our case, the microelectronics fabrication course is accompanied by a corequisite laboratory. The students design a simple device or circuit based upon their individual capability, and the designs are combined on a multiproject polysilicon gate NMOS chip. Design, fabrication, and testing are completed within the semester. Students from a variety of disciplines, including electrical, mechanical, chemical, and materials engineering; com- puter science; and physics, are routinely enrolled in the fabrication classes.xiv Preface Before closing, I must recognize a number of other books that have influenced the preparation of this text. These include The Theory and Practice of Microetecirontes and VLSI Fabrication Principles by S.K. Ghandi, Basic Integrated Circuit Engineering by D. J. Hamilton and W. G. Howard, Integrated Circuit Engineering by A. H. Glaser and G. E. Subak-Sharpe, Microelectronic Processing and Device Design by R. A. Colclaser, Semiconductor Devices—Physics and Technology by S. M. Sze, Semiconductor Integrated Circuit Processing Technology by W. R. Runyon and K. E. Bean, and The Science and Engineering of Microelectronic Fabrication by Stephen A. Campbell, Thanks also go to the many colleagues who have provided suggestions and encouragement for the new edition and especially to our laboratory manager Charles Ellis who has been instrumental in molding the laboratory sections of our course. RICHARD C. JAEGER Auburn, Alabama11 CHAPTER 1 An Overview of Microelectronic Fabrication A HISTORICAL PERSPECTIVE In this volume, we will develop an understanding of the basic processes used in mono- lithic integrated-circuit (IC) fabrication. Silicon is the dominant material used through- out the IC industry today, and in order to conserve space, only silicon processing will be discussed in this book. However, all of the hasic processes discussed here are applic- able to the fabrication of compound semiconductor integrated circuits (ICs) such as gallium arsenide or indium phosphide, as well as thick- and thin-film hybrid ICs. Germanium was one of the first materials to receive wide attention for use in semiconductor device fabrication, but it was rapidly replaced by silicon during the early 1960s. Silicon emerged as the dominant material, because it was found to have two major processing advantages Silicon can easily be oxidized to form a high-quality electrical insulator, and this oxide layer also provides an excellent barrier layer for the selective diffusion steps needed in integrated-circuit fabrication. Silicon was also shown to have a number of ancillary advantages. It is a very abundant element in nature, providing the possibility of a low-cost starting material. Tt has a wider bandgap than germanium and can therefore operate at higher tempera- tures than germanium. In retrospect, it appears that the processing advantages were the dominant reasons for the emergence of silicon over other semiconductor materials. The first successful fabrication techniques produced single transistors on a rec- tangular silicon die 1-2 mm on a side. The first integrated circuits, fabricated at Texas Instruments and Fairchild Semiconductor in the early 1960s, included several transis- tors and resistors to make simple logic gates and amplifier circuits. From this modest beginning, the level of integration has been doubling every one to two years, and we have now reached integration levels of billions of components on a 20-mm X 20-mm die [1-3]. For example, one-gigabit dynamic random-access memory (DRAM) chips have more than 10° transistors and more than 10° capacitors in the memory array. as 12 Chapter 1 An Overview of Microelectronic Fabrication well as millions of additional transistors in the access and decoding circuitry. One-giga- bit RAMs are currently being produced with photographic features measuring between 0.13 and 0.18 micron (um). MOS transistors with dimensions below 0.05 jm have been fabricated successfully in research laboratories, and these devices continue to behave as predicted by macroscopic models. So we still have significant increases in integrated-circuit density yet to come, provided that manufacturable fabrication processes can be developed for deep submicron dimensions. “The larger the diameter of the wafer, the more integrated-circuit dice can be pro duced at one time. Many wafers are processed at the same time, and the same silicon chip is replicated as many times as possible on a wafer of a given size. The size of sili- con wafers has steadily increased from 1-, 2-, 3-, 4-, 5-, and 6-in, diameters to the point where 8-in. (200-mm) waters are now in production. (See Fig. 1.1(a).) Wafers with 300- mm diameters will be in full production in the near future, and 450 mm wafers are pro- jected to be in used by the end of the decade. Wafer thicknesses range from approximately 350 to 1250 microns, Large-diameter wafers must be thicker in order to maintain structural integrity and planarity during the wide range of processing steps encountered during IC fabrication. Figure 1.1(c) shows the approximate number of 10-mm x 10-mm dice that fit on a wafer of given diameter. For a given wafer processing cost, the more dice per wafer, the lower the individual die cost becomes. Thus, there are strong economic forces driving the IC industry to continually move to larger and larger wafer sizes. ‘The dramatic progress of IC miniaturization is depicted graphically in Fig. 1.2 [1-3] on pages 4 and 5. The complexities of memory chips and microprocessors have both grown exponentially with time. In the three decades since 1965, memory density has grown by a factor of more than 10 million from the 64-bit chip to the 1-Gb memory chip, as indicated in Fig. 1.2(a). Similarly, the number of transistors on a microproces- sor chip has increased by a factor of more than five thousand since 1970 (Fig 1.2 (b).) Since the commercial introduction of the integrated circuit, these increases in density have been achieved through a continued reduction in the minimum line width, or minimum feature size, that can be defined on the surface of the integrated circuit, as shown in Fig. 1.3 on page 6. Today, most corporate semiconductor laboratories around the world are actively working on deep submicron processes with feature sizes less than 0.1 pm, less than one one-thousandth the diameter of a human hair! ‘These trends and future projections are summarized in Table 1.1 on page 6, which is abstracted from the International Technology Road map for Semiconductors (ITRS) generated by the Semiconductor Industry Association [4]. The TTRS is updated every three years; the projections are mind-boggling, even for those of us who have worked in the industry for many years. By the year 2011, MOS transistor gate lengths are pro- jected to reach 30 nm (0.030 um), multigigabit DRAM chips will be commonplace, and microprocessors will have a billion transistors on die exceeding 25 mm (one inch) on an edge. It remains to be seen whether the industry meets these projections. However, progress will be impressive, even if only a fraction of the projections are achieved " Historically there has been a problem with the units of measure used to describe integrated circuits. Horizontal dimensions were originally specified in mils (1 mil = 0.001 in.), whereas specification of the shallower vertical dimensions commonly made ‘In the past several years, the IC industry has actually managed to exceed the LTRS goals.1.1 AHistorical Perspective 3 EE]-—— Integrated-cireuitcie / Mit 100 mm (4") ui 150 mim (6") Ha SE yin | } ] Silicon wafer 490 mm (167) ~ Se 390mm (12°) (») 10,000 2 100 Ee é x 5 Bo E = £10 < 100, 200 300, 400 500 Wafer diameter (mm) Water diameter (in.) © FIGURE 1.1 (a) Relative size of wafers with diameters ranging from 100 to 450 mm; (b) The same integrated circuit die is repli- cated hundreds of times on a typical silicon wafer; (c) the graph gives the approximate number of 10 x 10 mm dice that can be fabricated on wafers of different diameters.FIGURE 1.2 (@) Dynamic memory den- sity versus year since 1960. FIGURE 1.2 (b) Number of transistors in a microprocessor versus Year. 4 Dynamic mempry density (bitschip) ‘Numbe’ of transistors 102 10" 10 10 0! a 165 1! 16 1) 180 2010 Year 10° rt rd w ae rd 108 72010 1980 1990) Year1.2 An Overview of Monolithic Fabrication Processes and Structures 5 use of the metric system. Today, most of the dimensions are specified using the metric system, although Imperial units are occasionally still used. Throughout the rest of this book, we will attempt to make consistent use of metric units. AN OVERVIEW OF MONOLITHIC FABRICATION PROCESSES (AND STRUCTURES Monolithic IC fabrication can be illustrated by studying the basic cross sections of MOS and bipolar transistors in Figs. 1.4 (on page 7) and 1.5 (on page 8). The n-channel MOS transistor is formed in a p-type substrate. Source/drain regions are formed by selectively converting shallow regions at the surface to n-type material. Thin and thick silicon-dioxide regions on the surface form the gate insulator of the transistor and serve to isolate one device from another. A thin film of polysilicon is used to form the gate of the transistor, and a metal such as aluminum is used to make contact to the source and drain. Interconnections between devices can be made using the diffusions and the layers of polysilicon and metal. ‘The bipolar transistor in Fig, 1.5 has alternating n- and p-type regions selectively fab- ricated on a p-type substrate. Silicon dioxide is again used as an insulator, and aluminum is, used to make electrical contact to the emitter, base, and collector of the transistor. Both the MOS and bipolar structures are fabricated through the repeated appli- cation of a number of basic processing steps: * Oxidation « Photolithography * Etching * Diffusion * Evaporation or sputtering © Chemical vapor deposition (CVD) « — Jonimplantation © Epitaxy + Anncaling Silicon dioxide can be formed by heating a silicon wafer to a high temperature (1000 to 1200 °C) in the presence of oxygen. This process is called oxidation. Metal films can be deposited through evaporation by heating the metal to its melting point in a vacuum. Thin films of silicon nitride, silicon dioxide, polysilicon, and metals can all be formed through a process known as chemical vapor deposition (CVD), in which the material is deposited out of a gaseous mixture onto the surface of the wafer. Metals and insulators may also be deposited by a process called sputtering. Shallow n- and p-type layers are formed by high-temperature (1000 to 1200 °C) diffusion of donor or acceptor impurities into silicon or by ion implantation, in which the wafer is bombarded with high-energy donor or acceptor ions generated in a high- voltage particle accelerator. In order to build devices and circuits, the n- and p-type regions must be formed selectively in the surfacc of the wafer. Silicon dioxide, silicon nitride, polysilicon, photo resist, and other materials can all be used to mask areas of the wafer surface to prevent6 Chapter’ An Overview of Microelectronic Fabrication ra Ew £ e : i : Lio 8 ISSCC Date @ ITRS Gost 10? 10 wS~«RDS*«wSSCSSN Year FIGURE 1.3 Feature size used in fabrication of dynamic memory as a function of time. TABLE 1.1 International Technology Road Map for Semiconductors (ITRS) [4] Selected Projections ‘Year of First Product Shipment 2001 2003 «2005S 2008.-=S 20112014 DRAM Metal Line Half-Pitch (nm) 150 120 100 70 50 35 Microprocessor Gate Widths (nm) 100 80 65 45 30 20 DRAM (G-bits/chip) 22 43 86 py 8 190 ‘Microprocessor (M-transistorsichip) 48 95, 190 540 1500 4300 DRAM Chip Area: Year of Introduction (mm) 4 4052000680750 DRAM Chip Area: Production (mm?) 130 160 170 200 20 260 MPU Chip Size at Introduction (mm?) 340 310 400 470-540 «620 MPU Chip Area: Second “shrink” (mim?) 180 210 © 230 20 © 310 350 ‘Wafer Size (mm) 300 300 300 450 450 4501.3 Metal-Oxide-Semiconductor (MOS) Processes 7 Polysilicon FIGURE 1.4 “The basic structure of an n-channel metal oxide semiconductor (NMOS) transistor structure. (a) ‘The vertical cross section through the transistor; (b) a composite top view of the masks used to fabricate the transistor in (a). The transistor ly doped polysilicon as ‘metal.” penetration of impurities during ion implantation or diffusion. Windows are cut in the masking material by etching with acids or in a plasma. Window patterns are trans- ferred to the wafer surface from a mask through the use of optical techniques. The masks are also produced using photographic reduction techniques. Photolithography includes the overall process of mask fabrication, as well as the process of transferring patterns from the masks to the surface of the wafer. The photolitho- graphic process is critical to the production of integrated circuits, and the number of mask steps is often used as a measure of complexity when comparing fabrication processes. METAL-OXIDE-SEMICONDUCTOR (MOS) PROCESSES Basic NMOS Process A possible process flow for a basic n-channel MOS process (NMOS) is shown in Fig. 1.6 on page 9 and Fig. 1.7 on page 10. The starting wafer is first oxidized to form a thin- pad oxide layer of silicon dioxide (SiO,) that protects the silicon surface. Silicon nitride is then deposited by a low-pressure chemical vapor deposition (LPCVD) process. Mask #1 defines the active transistor areas. The nitride/oxide sandwich is etched away8 Chapter1 An Overview of Microelectronic Fabrication Base Emitter Collector P Contact n region P z a FIGURE 1.5 — “The basie structure of a junction-iso- Al Al Ai lated bipolar transistor. (a) The verti- 7 cal cross section through the 4 transistor; (b) a compesite top view of C the masks used to fabricate the tran- Be eens calkesion sistor in (a). ) everywhere except where transistors are to be formed. A boron implantation is per- formed and followed by an oxidation step. The nitride serves as both an implantation mask and an oxidation mask. After the nitride and thin oxide padding layers are removed, a new thin layer of oxide is grown to serve as the gate oxide for the MOS transistors. Following gate-oxide growth, a boron implantation is commonly used to adjust the threshold voltage to the desired value. Polysilicon is deposited over the complete wafer using a CVD process. The sec- ‘ond mask defines the polysilicon gate region of the transistor. Polysilicon is etched away everywhere except over the gate regions and the areas used for interconnection. Next, the source/drain regions are implanted through the thin oxide regions. The implanted impurity may be driven in deeper with a high-temperature diffusion step. More oxide is deposited on the surface, and contact openings are defined by the third mask step. Metal is deposited over the wafer surface by evaporation or sputtering. ‘The fourth mask step is used to define the interconnection pattern that will be etched in the metal. A passivation layer of phosphosilicate glass or silicon nitride (not shown in Fig, 1.6) is deposited on the wafer surface, and the final mask (#5) is used to define windows so that bonding wires can be attached to pads on the periphery of the IC die.Cross-section view CLS i832 ZZIL p-type silicon “Top view of masks @ Boron implant ait © Phosphorus or arsenic al a tHeott 0; SF OS P o> © SiO Oo Sio, SiO, J a =p ~(0 p © Al SiO, SiO, X a a py -<-|/59 P wo ul 1.3, Metal-Oxide-Semiconductor (MOS) Processes 9 FIGURE 1.6 Process sequence for a semirecessed ‘oxide NMOS process (a) Silicon wafer covered with silicon nitride over a thin adding layer of silicon dioxide: (b) etched wafer after first mask step. A boron implant is used to help con- {fol field oxide threshold; (c) structure following oxidation, nitride removal, and polysilicon deporition: (d) wafer after second mask step and etching of polysilicon; (e) the third mask has been used f0 open contact windows following silicon dioxide deposition; (f final structure following metal deposition and patterning with fourth mask. “This simple process requires five mask steps. Note that these mask steps use sub- tractive processes The entire surface of the wafer is first coated with a desired material, and then most of the material is removed by wet chemical or dry plasma etching, 1.3.2 Basic Complementary MOS (CMOS) Process Figure 1.8 shows the mask sequence for a basic complementary MOS (CMOS) process. One new mask, beyond that of the NMOS process, is used to define the “n- well,” or “n-tub.” which serves as the substrate for the p-channel devices. A second new mask step is used to define the source/drain regions of the p-channel transistors.10 Chapter 1 An Overview of Microelectronic Fabrication [al “Thermal oxidation Gate definition] Mask #2 CVD nitride Source/drain ‘deposition implantation Active area mask] Mask #1 Source/drain 1 diffusion Boron field implant | CVD oie 1 deposition ‘Thermal field 1 oxidation 1 Contact openings | Mask #3 Remove nitride i and oxide pad Metal deposition Regrow thin gate oat metal | Mask #4 | mt Boron threshold adjustment implant t Passivation layer deposition FIGURE 1.7 } Basie NMOS process flowchart. Openiborting pads: | “Maskiig 14 Additional masks may be used to adjust the threshold voltage of the MOS transistors and are very common in state-of-the-art NMOS and CMOS processes. Older CMOS processes use a p-well instead of an n-well. Twin-well processes have also been developed recently. Both a p-well and an n-well are formed in a lightly doped substrate, and the - and p-channel devices can each be optimized for highest perfor- mance. Twin-well very large-scale integration (VLSI) processes use lightly doped layers grown on heavily doped substrates to suppress a CMOS failure mode called latchup. BASIC BIPOLAR PROCESSING Basic bipolar fabrication is somewhat more complex than single-channel MOS processing, as indicated in Figs. 1.9 on page 12 and 1.10 on page 13.A p-type silicon wafer is oxidized, and the first mask is used to define a diffused region called the buried layer, or subcollec~ tor. This diffusion is used to reduce the collector resistance of the bipolar transistor. Following the buried-layer diffusion, a process called epitaxy is used to grow single-crystal re-type silicon on top of the silicon wafer. The epitaxial growth process results in a high-1.4 Basic Bipolar Processing 11 Arsenic implant Ht ot (a) Boron implant re A AL Al. FIGURE 1.8 \ Cross-sectional views at major steps in a basic CMOS process. (a) Following n-well diffusion, (b) following selective oxida- P tion, and (c) following gate oxidation and polysilicon gate definition; (4) NMOS sourceldrain implantation; (e) PMOS «® source/drain implantation: (f) structure following contact and metal mask steps. quality silicon layer with the same crystal structure as the original silicon wafer. An oxide layer is then grown on the wafer. Mack two is used to open windows for a deep p diffusion, which is used to isolate one bipolar transistor from another. Another oxidation follows the isolation diffusion. Mask three opens windows in the oxide for the p-type base diffusion. ‘The wafer is usually oxidized during the base diffusion, and mask four is used to open win- dows for the emitter diffusion. The same diffusion step places ann‘ region under the col- lector contact to ensure that a good ohmic contact will be formed during subsequent metallization. Masks five, six, and seven are used to open contact windows, pattern the metallization layer, and open windows in the passivation layer just as in the NMOS process described in Section 1.3. Thus, the basic bipolar process requires seven mask levels compared with five for the basic NMOS process. After the MOS or bipolar process is completed, each die on the wafer is tested, and bad dice are marked with ink. The wafer is then sawed apart. Good dice are mounted in various packages fur final testing and subsequent sale or use.42 Chapter1 An Overview of Microelectronic Fabrication paiicon O} & ©) SiO, © ‘Top views. Buried-layer mask Yj Isolation mask Base mask Base ) ) (@) a Emitter mask SS FIGURE 1.9 pu Cross-sectional view of the major steps in a basic bipolar process. (a) Wafer with silicon dioxide layer, (b) following buried-layer diffusion using first mask, and subsequent © epitaxial layer growth and oxida- io tion; (¢) following deep isolation Emitter Base Collector 4 dliffusie regions; (f) final structure following contact and metal mask steps. 15 SAFETY james: 2 an L coe Me ee third mask; (e) fourth mask defines ‘emitter and collector contact e @) Collector contact, region In the course of IC fabrication processes described throughout the rest of this text, we shall encounter a wide variety of acids, highly corrosive bases, organic and inorganic solvents, and materials with carcinogenic properties, as well as extremely toxic gases, and this represents a good opportunity to stress the need to exercise a high degree of caution before proceeding with any semiconductor processing, Because of the dangers, most laboratories require individuals to pass a safety test before they are permitted to work in the laboratory.15 Safety 13 [4 ‘Thermal oxidation Emitter mask | Mask #4 Subcollector mask | Mask #1 Emitter diffusion i. (Por As) ‘Antimony diffusion { and oxidation Contact mask | Mask #5 Epitaxial-layer Metal deposition 1 } Trolation mask | Mask #2 oe ee i Boron diffusion Etch metal and oxidation I 1 Pasaton per Base window | Mask #3 — Boron base ‘Open bonding pads | Mask #7 diffusion and oxidation a FIGURE 1.10 Basic bipolar process flowehart. Wet processes, particularly those used for cleaning and etching, involve the use of a wide variety of acids and bases. Both can produce serious burns if they contact the skin, and even the fumes can produce irritation to the skin or serious eye damage. Rubber gloves, an apron, and eye protection should always be worn when handling these materials. However, gloves should not be relied upon to protect one during immersion in liquids, because of pinhole formation in the gloves. Care must be exercised in handling, mixing, and disposing these liquids. Environmental standards often restrict the methods that can be used for disposal. Acids and bases must not be combined during disposal. When diluting bases or acids, concentrated chemicals should be added to water, not the reverse. Many acids will dis- color the skin or give a burning sensation upon contact, However, hydrofluoric acid (HF) is much more insidious. Although a weak acid, HF readily penetrates the skin to produce deep and painful burns that are not detected until after the damage is done. Immediate medical attention is required for such burns. Ion implantation, low-pressure chemical vapor deposition, and epitaxial growth represent just a few of the processes that may involve extremely toxic or explosive gases. For example, extreme caution must be exercised with the delivery of arsine,14 Chapter1 An Overview of Microelectronic Fabrication phosphine, germane, silane, and anhydrous ammonia, to name just a few. In addition, many of the systems, such as ion implanters, plasma reactors, and electron-beam evap- oration systems, involve lethal voltages. Asa general rule before dealing with any new chemical, one must research and study its overall properties to understand toxicity, safe handling practices, and any unusual reactions that may occur or reaction products that can be produced. ‘The rest of this book concentrates on the basic processes used in the fabrica~ tion of monolithic integrated circuits. Chapters 2 through 8 discuss mask making and pattern definition, oxidation, diffusion, ion implantation, film deposition, inter- connections and contacts, and packaging and yield. The last three chapters introduce the integration of process, layout, and device design for MOS, bipolar, and MEMS, technologies. REFERENCES [1] Digest of the IEEE International Solid-State Circuits Conference, held in February of each year. (http:/iwww.sses.orglissce) [2] Digest of the IEEE International Electron Devices Meeting, held in December of each year. (http:/iwww.iece.orgiconference/iedm) 13] Digests of the International VLSI Technology and Circuits Symposia, co-sponsored by the IEEE and JSAP, held in June of each year. (http://www.vlsisymposium.org) [4] The International Technology Roadmap for Semiconductors, The Semiconductor Industry Association (SIA), San Jose, CA, 1999. (http://www.semichips.org) PROBLEMS 1.1 Make a list of two dozen items in your everyday environment that you believe contain IC chips. A PC and its peripherals are considered to be one item. (Do not confuse electro- mechanical timers, common in clothes dryers or the switch in a simple thermostat or cof- fee maker, with electronic circuits) 1.2 (a) Make a table comparing the areas of wafers with the following diameters: 25, 50, 75, 100, 125, 150,200,300 and 450 mm. (b) Approximately how many 1-mm x 1-mm dice are on a 450-mm wafer? (©) How many 25-mm x 25-mm dice? 1.3 (a) Calculate an estimate of the number of 20-mm x 20-mm dice on a 300-mm diameter wafer, in terms of the total wafer and die areas. (b) Calculate the exact number of 20-mm x 20-mm dice that actually fit on the 300-mm wafer. (It may help to draw a picture.) 14 The straight line in Fig. 1.2(a) is described by B = 19.97 x 10°77" ~ ) bits/chip. If a straight-line projection is made using this equation, what will be the number of memory bits/chip in the year 2020? 15 The straight line in Fig. 1.2(b) is described by N= 1027 x10" transistors. Based upon a straight-line projection of this figure, what will be the number of transistors in a microprocessor in the year 2020?Problems 15 1.6 (a) How many years does it take for memory chip density to increase by a factor of two, based upon the equation in Problem 1.47 (b) How about by a factor of 107 1.7 (a) How many years does it take for microprocessor circuit density to increase by a factor of two, based upon the equation in Problem 1.5? (b)_ How about by a factor of 10? 18 If you make a straight-line projection from Fig, 1.3, what will be the minimum feature size in integrated circuits in the year 2020? The curve can be described by F = 8214 X 198%") um, Do you think this is possible? Why or why not? 1.9 The filament of a small vacuum tube uses a power of approximately 0.5 W. Suppose that approximately 300 million of these tubes are used to build the equivalent of a 256-Mb memory. How much power is required for this memory? If this power is supplied from a 220-V ac source, what is the current required by this memory? 1.10 An 18-mm x 25-mm die 0.25-pm-wide spaces. (a) What is the total length of wire on this die? (b) How about 0.1- ym lines and spaces. J.11 The curve in Fig. 1.1(b) represents the approximate number of chips on a wafer of a given diameter. Determine the exact number of 10 x 10 mm dice that will fit on a wafer with a diameter of 200 mm. (The number indicated on the curve is 314.) covered by an array of 0.25-um metal lines separated by ‘L12 The cost of processing a wafer in a particular process is $1,000. Assume that 35% of the fabricated dice are good. Find the number of dice, using Fig. 1.1(b). (a) Determine the cost per good die for a 150 mm wafer. (b) Repeat for 200 mm wafer, 13 A certain silicon-gate NMOS transistor occupies an area of 25 )?, where A is the mini- mum lithographic feature size. (a) How many MOS transistors can fit on a 5X5 mm die if \ = 1 pm? (by 0.25 pm? (©) 0.10pm? 1.14 A simple pn junction diode is shown in cross section in Fig. P1.14. Make a possible process flowchart for fabrication of this structure, including mask steps ae FIGURE P1.14 P SiO;16 Chapter? An Overview of Microelectronic Fabrication 15 Draw a set of contact and metal masks for the bipolar transistor of Fig. 1.9. Use square con- tact windows with one contact to the emitter and two contacts to the base and collector regions.