Computer Architecture, IIIBCA Chap:1

Introduction To Computer Organization And

Architecture
Computer
Computer is a fast electronic calculating machine which accepts digital
input, processes it according to the internally stored instructions (Programs)
and produces the result on the output device.

Computer consists of two functional entities

 Hardware
 Software

Hardware: it consists of all the physical electronic components and

electromechanical devices. It is divided into three major parts.

 Central Processing Unit(CPU)

 Memory
 Input Output module
This can be shown in fallowing figure

Random Access Memory

Central Processing Unit

Input devices Input Output Module Output devices

Fig: Block diagram of digital computer

The central processing unit (CPU) contains

i. an arithmetic and logic unit for manipulating data.
ii. a number of registers for storing data.
iii. control circuits for fetching and executing instructions.

The memory of the computer contains storage for instructions and data. It is
the RAM and the CPU can access any location in memory at random and
retrieve the binary information within a fixed interval of the time.

The Input Output module contains electronic circuits for communicating

and controlling the transfer of information between the computer and the
outside world. The input and output devices connected to the computer
include keyboards, mouse, joysticks, scanners, printers, terminals, magnetic
discs etc.

By Usha Kamala B T,VVFGC,Tumakuru. Page 1

 Computer Architecture, IIIBCA Chap:1

Software

Software consists of instructions and data that the computer manipulates to

perform various data processing tasks. A sequence of instructions is called a
program. The data that are manipulated by the program constitute the
database.

Software is of two types.

i. System software
ii. Application software

System software.

System software of a computer consists of a collection of program that

facilitates more effective use of the computer. Its function is to compensate
for the differences that exist between user needs and the capability of the
hardware.

Application software

It consists of programs written by the user for the purpose of solving

particular problems and user needs.

Computer Organization is concerned with the way the hardware

components operate and the way they are connected together to form the
computer system. Or The components from which computers are built, i.e.,
computer organization.
In contrast, computer architecture is the science of integrating those
components to achieve a level of functionality and performance.
It is as if computer organization examines the lumber, bricks, nails, and other
building material
While computer architecture looks at the design of the house.

Computer architecture refers to those attributes of a system visible to a

programmer or, put another way, those attributes that have a direct impact
on the logical execution of a program.

Computer Architecture in general covers structure and behaviour of the

computer as seen by the user. It includes the fallowing

1. Information.
2. Formats.
3. Instruction sets
4. Addressing modes.

The architectural design of a computer system is concerned with the

specifications of the various functional modules, such as processors and
memories and structuring them together into a computer system.

By Usha Kamala B T,VVFGC,Tumakuru. Page 2

 Computer Architecture, IIIBCA Chap:1

There are two types of computer architectures

1. Von Neumann architecture.

2. Harvard architecture.

Von Neumann architecture: it describes a general framework or structure for

computer’s hardware, programming and data to fallow. Majority of computers
today operate according to Von Neumann architecture. This model is designed
for stored program digital computer that uses a processing unit and a single
separate storage structure to hold both instructions and data. It is named
after the mathematician and early computer scientist John Von Neumann.

According to this architecture the structure of a computer system is composed

of the fallowing components.

i. The Arithmetic Logic Unit(ALU) performs the computer’s

computational and logical functions.
ii. Main memory or fast memory is called the Random Access memory
(RAM).
iii. Control unit (CU) that directs other components of the computer to
perform certain actions such as fetching data or instructions from
memory to be processed by ALU.
iv. Interface between the user and the computer such as input and
output. devices such as keyboard or monitor.

It uses the stored program principle. Both data as well as instructions

used to manipulate that data should be stored together in the same memory
area of the computer. Instructions are carried out sequentially, one
instruction at a time. Since only one instruction at a time can be handled by
the processor, there is a limitation on speed of processing.

For example the CPU cannot do both reading an instruction from memory and
reading/writing data from/to the memory simultaneously because
the instructions and data use the same signal pathways and memory.

Fig: Design of Van Neumann architecture

Memory

Arithmetic Logic
Unit
Control unit
Accumulator
or

Input Output

By Usha Kamala B T,VVFGC,Tumakuru. Page 3

 Computer Architecture, IIIBCA Chap:1

An example of Von Neumann architecture is the desktop personal computer

(PC).

HARVARD ARCHITECTURE

It uses”, physically separate storage and signal pathways for the

instructions and data. The term originated from the Harvard Mark I relay be
computer, which stored instructions on punched tape (24 bits wide) and
data relay latches (23 digits wide).

These early machines had limited data storage, entirely contained within the
data processing unit, and provided no access to the instruction storage as
data , making loading and modifying programs an entirely offline process.

The CPU can read both an instruction and data from memory at the same
time, even without a cache, leading to double the memory bandwidth. A
Harvard architecture computer can thus be faster for a given circuit
complexity because instruction fetches and data access do not contend for a
single memory pathway.

Program CPU Data

Memory
Memory

Design of Harvard architecture

Different program and data bus widths are possible, allowing program and
data memory to be better optimized to the architectural requirements. E.g.: If
the instruction format requires 14 bits then program bus and memory can be
made ”hit wide, while the data bus and data memory remain 8-bit wide.

Examples for Harvard architecture are Microcontroller (single chip

micro computer) based computer systems and Digital Signal Processor (DSP)
beset computer systems. .

Comparison between Von Neumann and Harvard Architecture

Von Neumann architecture Harvard Architecture

program and data are stored in the program and data are stored and
Programs and data are stored and some handled by different subsystem
memory and managed by the handled
by different subsystems.

By Usha Kamala B T,VVFGC,Tumakuru. Page 4

 Computer Architecture, IIIBCA Chap:1

There is increased efficiency in Program handling task and data

designing, implementing and operating handling task are sufficiently different
one memory system resulting in not so efficient system It can
provide distinct operational advantages
particularly in certain embedded
applications where the program is more
or less hard wired.

Can be slower because programs and Can he must faster under certain
data are stored in some memory and are conditions.
to be managed by a single system.

Desktop Personal Computer. Microcontroller based systems, Digit:

Signal Processor based systems.

Functions of computer

Both the structure and functioning of a computer are, in essence, the basic
functions that a computer can perform. In general terms, there are
only four:
• Data processing
• Data storage
• Data movement
• Control
The computer, of course, must be able to process data.The data may take a
wide variety of forms, and the range of processing requirements is broad.
However, we shall see that there are only a few fundamental methods or types
of data processing.

It is also essential that a computer store data. Even if the computer is

processing data on the fly (i.e., data come in and get processed, and the
results go out immediately), the computer must temporarily store at least
those pieces of data that are being worked on at any given moment. Thus,
there is at least a short-term data storage function. Equally important, the
computer performs a long-term data storage function. Files of data are stored
on the computer for subsequent retrieval and update.

The computer must be able to move data between itself and the outside world.
The computer’s operating environment consists of devices that serve as either
sources or destinations of data. When data are received from or delivered to a
device that is directly connected to the computer, the process is known as
input–output(I/O), and the device is referred to as a peripheral. When data
are moved over longer distances, to or from a remote device, the process is
known as data communications.

Finally, there must be control of these three functions. Ultimately, this control
is exercised by the individual(s) who provides the computer with instructions.
Within the computer, a control unit manages the computer’s resources and
orchestrates the performance of its functional parts in response to those
instructions.
By Usha Kamala B T,VVFGC,Tumakuru. Page 5
 Computer Architecture, IIIBCA Chap:1

Structure of computer

The computer interacts in some fashion with its external environment. In

general, all of its linkages to the external environment can be classified as
peripheral devices or communication lines. We will have something to say
about both types of linkages.
But of greater concern in this notes is the internal structure of the computer
itself. There are four main structural components:
• Central processing unit (CPU): Controls the operation of the computer and
performs its data processing functions; often simply referred to as processor.
• Main memory: Stores data.
• I/O: Moves data between the computer and its external environment.
• System interconnection: Some mechanism that provides for communication
among CPU, main memory, and I/O. A common example of system
interconnection is by means of a system bus, consisting of a number of
conducting wires to which all the other components attach.
There may be one or more of each of the aforementioned
components. Traditionally, there has been just a single processor. In recent
years, there has been increasing use of multiple processors in a single
computer.
for our purposes, the most interesting and in some ways the most complex
component is the CPU. Its major structural components are as follows:
• Control unit: Controls the operation of the CPU and hence the computer
• Arithmetic and logic unit (ALU): Performs the computer’s data processing
functions
• Registers: Provides storage internal to the CPU
• CPU interconnection:

The operations of a computer can be summarized as follows:

1. A set of instructions called a program reside in the main memory of
computer.

2. The CPU fetches those instructions sequentially one-by-one from the main
memory, decodes them and performs the specified operation on associated
data operands in ALU.

3. Processed data and results will be displayed on an output unit.

4. All activities pertaining to processing and data movement inside the

computer machine are governed by control unit.

Basic Operational Concepts

An Instruction consists of two parts, an Operation code and operand/s as

shown below:

OPCODE OPERAND/s

Let us see a typical instruction

By Usha Kamala B T,VVFGC,Tumakuru. Page 6

 Computer Architecture, IIIBCA Chap:1

ADD LOCA, R0
This instruction is an addition operation. The following are the steps to
execute the instruction:
Step 1: Fetch the instruction from main memory into the processor
Step 2: Fetch the operand at location LOCA from main memory into the
processor
Step 3: Add the memory operand (i.e. fetched contents of LOCA) to the
contents of register R0 Step 4: Store the result (sum) in R0.

The same instruction can be realized using two instructions as

Load LOCA, R1
Add R1, R0
The steps to execute the instructions can be enumerated as below:
Step 1: Fetch the instruction from main memory into the processor
Step 2: Fetch the operand at location LOCA from main memory into
the processor Register R1
Step 3: Add the content of Register R1 and the contents of register R0
Step 4: Store the result (sum) in R0.

The basic operation cycle of the computer

(1) Fetch the instruction from memory
(2) Decode the instruction
(3) Execute the instruction
Program Counter (PC) keeps track of the instruction in the program stored in
memory. PC holds the address of the instruction to be executed next and in
incremented each time an instruction is fetched from memory.

INSTRUCTIONS

Basic function performed by a computer is the execution of a Program

or instructions. The program which is to be executed is a set of instructions
which are stored in Memory. The central processing unit (CPU) executes
the instruction of the program to complete a task.

The major responsibility of the instruction execution is with the CPU. The i
nstruction execution takes place in the CPU registers. Let us, first discuss f
ew typical registers which are commonly available in some of the machines.

 Memory Address Register (MAR): It specifies the address of memory lo

cation from which data or instruction is to be accessed (for read operat
ion) or to which the data is to be stored (for write operation).
 Memory Buffer Register (MBR): It is a register which contains the data
to be written in the memory (for write operation) or it receives the data
from the memory (for read operation).
 Program Counter (PC): It keeps track of the instruction which is to be e
xecuted next, after the execution of an on-going instruction.
 Instruction Register (IR): Here the instructions are loaded before their
execution.

By Usha Kamala B T,VVFGC,Tumakuru. Page 7

 Computer Architecture, IIIBCA Chap:1

Format of instruction.

Instruction Cycle
The Processing needed for a single instruction (fetch and execution) is ref
erred to as instruction cycle. The instruction cycle consist of the fetch cycl
e and the execute cycle. Program execution terminates if the electric pow
er supply is discontinued or some sort of occurs unrecoverable error, or by a
program itself.
For fetch cycle, in typical CPU program counter is used. Program counter k
eeps track of the Instruction which is to be fetched next. Normally next instr
uction in sequence is fetched next as programs are executed in sequence. T
he fetched instruction is in the form of binary code and is loaded into an in
struction and do the required action. In general, these actions can be div
ided into following categories :

By Usha Kamala B T,VVFGC,Tumakuru. Page 8

 Computer Architecture, IIIBCA Chap:1

 Data transfer
From the CPU to memory or from memory to CPU, or From CPU to I
/O or I/O to CPU.
 Data Processing:
A logic or arithmetic operation may be performed by CPU on the data.
 Sequence control:
This action may require alteration of sequence of execution. For ex
ample, an instruction from location 100 on execution may specifies that the
next instruction should be fetched from location200. On execution of such a
instruction the Program counter which was having location value 101 (he ne
xt instruction to be fetched in case where memory word is equal to register si
ze) will be modified to contain a location value 200

Execution of a instruction may involve any combination of these actions.

The execution cycle for an particular instruction may involve more than one
stages and memory references. In addition, an instruction may ask for an I/
O operation. Considering above situations, let us work out a more detailed v
iew of instruction cycle. Fallowing Figure gives a state diagram of an instruc
tion cycle.
A state is defined as a particular instance of instruction execution.

Figure: Instruction Cycle

Please note that in the above state diagram some states may be bypassed w
hile some may be visited more than once. The instruction cycle shown in abo
ve figure consist of following
states/stages:
First the address of next instruction is calculated based on the width
of instruction and memory organization.For example, if in a computer
an instruction is of 16 bits and if memory is organized as16-bit words

By Usha Kamala B T,VVFGC,Tumakuru. Page 9

 Computer Architecture, IIIBCA Chap:1

, then the address of the next instruction is valued by adding 1 in the

address of previous instruction. In case, the memory is organised as b
ytes which can be addressed individually, then we need to add 2 in
the previous address to get the address of the next instruction.

 Then, an instruction is fetched from a memory location to the CPU.

 The next state decodes the instruction to determine the type of operati
on desired and
what are the operands to be used.
 In case, the operands need to be fetched from memory or via I/O, then
address of
the memory location or I/O device is calculated.
 Next, the operand is fetched from the memory or read from I/o device.
 Now the operation asked by the instruction is performed.
 Finally, the results are written back to memory or I/O wherever desi
red by first calculating the address of the operand and then transferr
ing the value.

Flowchart for instruction cycle

By Usha Kamala B T,VVFGC,Tumakuru. Page 10

 Computer Architecture, IIIBCA Chap:1

Interrupts
The term interrupt is defined loosely to any exceptional event that causes CPU
to temporarily transfer its control from currently executing program to a
different program which provides service to the exceptional event.

An interrupt may be generated by a number of sources which may be either

internal or external to the CPU.

Types of Interrupts :
There are 3 types of interrupts. They are

1. External interrupts.
2. Internal interrupts.
3. Software interrupts.

EXTERNAL INTERRUPTS are initiated from

 Input-output devices(I/o) device
 Timing devices
 Circuit monitoring power supply.
 Any external source.

External interrupts are caused by

1. i/o device requesting transfer of data.

2. i/o device finishing transfer of data.
3. Elapsed time of an event (timeout – program in endless loop).
4. Power failure (state of CPU must be saved in non destructive memory
in few seconds).

INTERNAL INTERRUPTS are also called Traps. They arise from illegal or
erroneous use of an instructions or data. The error condition usually occurs
due to premature termination of instruction execution.

Interrupts caused by internal error conditions are

1. Register overflow
2. Attempt to divide by zero.
3. Invalid operations code.
4. Stack overflow
5. Protection violation.

By Usha Kamala B T,VVFGC,Tumakuru. Page 11

 Computer Architecture, IIIBCA Chap:1

Comparison between Internal and External interrupts

INTERNAL INTERRUPT EXTERNAL INTERRUPT

It is initiated by some exception It is initiated by an external event
condition caused by program
It is synchronous with program (acts It is asynchronous with program(acts
according to the program) independent of program)
If program is re run, it occurs at the It depends on external condition
same place each time. which is independent of program
being executed at that point of time.

SOFTWARE INTERRUPT is initiated by executing an instruction. It is special

call instruction that behaves like an interrupts. It can be used to initiate an
interrupts procedure at any desired point in the program.

For example, a supervisor call instruction provides means for switching from
a CPU user mode to supervisor mode. A complex input output transfer
procedure may be assigned to supervisor mode. But a program written by a
user must run in the user mode. When an input or output transfer is required,
the supervisor mode is requested by means of a supervisor call instruction.
This instruction caused a software interrupt that stores the old CPU state and
brings in a new PSW that belongs to the supervisor mode. The calling program
must pass information to the operating system in order to specify the
particular task requested.

Interrupts are a useful mechanism, for improvement of processing

efficiency. why? the main reason lies in the fact that almost all the external
devices are slower than the processor, therefore, in a typical system a
processor has to continually test the status of I/O device ,in turn wasting lot
of CPU time .With the interrupt facility CPU is freed from the task of testing
status of input/output device and can do useful processing during this time
, thus , increasing the processing efficiency.

How does the CPU know that an interrupt has occurred? the CPU can be
interrupted by providing a control line. this line, also known as Interrupt
request line ,connects the source/sources of interrupts to the CPU. the
interrupt signal is then stored in a register of the CPU. this register is
periodically tested by the CPU to determine the occurrence of an interrupt.
once CPU knows that an interrupt has occurred then the CPU need to execute
an interrupt servicing program which tries to remove/service the
condition/device which has caused the interrupt. In general , each source of
interrupt requires different interrupt servicing program to be executed. The
CPU is normally assigned the address of the interrupt servicing program to

By Usha Kamala B T,VVFGC,Tumakuru. Page 12

 Computer Architecture, IIIBCA Chap:1

be executed. Considering this requirement let us work out the steps which
CPU must take when an interrupt occurs.

 The CPU must find out the source of the interrupt as this will determine
which interrupt service program is to be executed.
 The CPU then acquires the address of the interrupt service routine
which are normally stored in the memory.
 What happens to the program it was executing? this program need to
be interrupted till the CPU executes the interrupt service program.do
we need to do something for this program? Well the context of this
program is to be saved. We will discuss about this a bit later.
 Finally, the interrupt service program is executed by the CPU ,till the
completion of the program. The end of this program is marked by a
RETURN statement. After that the control is passed back to the
interrupted program.

Interrupts And Instruction Cycle

Let us summaries the interrupt process , on the occurrence of an interrupt,
an interrupt request(in the form of a signal) is issued to the CPU. The CPU
immediately suspends the operation of the currently executing program
save the context of this program and starts executive a program which
services that interrupt request. This program is also known as interrupt
handler. After the interrupting condition device has been serviced the
execution of original program is resumed.

A user program can perceive the interrupt as. The interruption of the
execution in between. the execution resumes as soon as the interrupt
processing is completed. Therefore, the user program need not contain any
special code for interrupt handling. This job lies with the processor and
the operating system which in turn are also responsible for suspending the
execution of the user program and later interrupt handling resumes the
user program from the same point.

By Usha Kamala B T,VVFGC,Tumakuru. Page 13

 Computer Architecture, IIIBCA Chap:1

Instruction Cycle with Interrupt Cycle

The interrupts can be added in the instruction cycle (refer figure) as an

additional state. In the interrupt cycle, the responsibility of the
CPU/Processor is to check whether any interrupt have occurred. this is
indicated by the presence of interrupt signal. In case no interrupt needs
service then the processor to the next instruction of the current program. In
case an interrupt needs servicing the interrupt is processed as:

 Suspend the execution of current program and save its context.

 Set the Program counter to the starting address of this interrupt service
program.
 This processor then executes the instructions in the interrupt servicing
program.
 The interrupt servicing programs are normally part of the operating
system.
 After completing the interrupt servicing program the CPU can resume
the program it has suspended earlier.

Multiple interrupts
It is very much possible to have multiple interrupts occurring at the same
time. For example, the data may be received by a program from a
communication line and on the other side it is printing results an interrupt
will be generated by the printer on completion of every print operation, while
the communication line controller will be generating the interrupt on arrival
of a unit of data. Since, these two interrupts are independent, therefore, the
communication interrupt may occur while the printer interrupt is being
processed.

One of the approach to deal with multiple interrupt is to disable interrupts(do

By Usha Kamala B T,VVFGC,Tumakuru. Page 14

 Computer Architecture, IIIBCA Chap:1

not allow other interrupts to be processed).If an interrupt occur while the first
interrupt is being processed then it will remain pending till the interrupts
have been enabled again. Therefore, in this scheme the first few instructions
in the processing of an interrupt is completed, then the processor enables the
interrupts and checks whether any other interrupt has occurred. Thus, in
this approach interrupts are handled in the sequential order.

Interrupt Servicing programs (ISP)

figure : An example of multiple interrupt with priority scheme

The main drawback of this approach is that it does not consider the relative
priority or time critical nature of some interrupts. For example, while
inputting from a communication line, the data needed to be accepted quickly
so that room can be made for more input . In case, the first burst of data
processed before the second burst arrives, data may be lost.

For such cases another scheme in which priorities for interrupts is defined is
followed. This scheme allows the higher priority interrupt a lower priority
interrupt program in between.

For example, let us assume a system with three input/ouput devices :printer,
disk, and communication line. Let us assume that these have priorities of 1,2
and 3 respectively. priority 3 is the highest while 1 is lowest case in our case.
An instance of program execution is shown with multiple interrupt in figure.

initially the user program is being executed by the CPU till the point A where
a printer interrupt occurs. CPU acknowledges the printer interrupt by placing
the context of user program on the system stack and starts executing the
interrupt servicing program (ISP) for the printer, before the ISP of printer is

By Usha Kamala B T,VVFGC,Tumakuru. Page 15

 Computer Architecture, IIIBCA Chap:1

finished at point B communication line interrupt occurs. Since, this is a

higher priority interrupt, therefore CPU acknowledges the interrupt and
pushes the context of ISP of printer from CPU to the system stack and starts
executing ISP (communication line).while processing ISP (communication
line) another interrupt of disk occurs but it is held back as ISP
(communication line) is of higher priority .when the ISP (communication line)
finsheses the context of ISP (printer) is executed again, but as the disk
interrupt has higher priority and is pending, therefore, the disk interrupt is
acknowledged and processed at point B.after completing ISP(disk) the ISP
(printer )is completed and control is passed back to user program,which starts
executing from the point of interruption.

INTERCONNECTION STRUCTURES

A computer consist basic components:

 CPU
 Memory and
 input/output component

If data is to be exchanged among these three component we need to have

interconnection structure which allows transfer of information among all
these. This interconnecting structure must support the transfer of

 An instruction or unit of data from memory to CPU.

 A unit of data from CPU to memory.
 Reading of data from Input /Output device therefore transfer from
input/output device to CPU
 CPU sending data to Input/output device
 Input/output device to memory
 Memory to Input/output device.

To support these transfers several interconnecting structure has been tried

various computer developers. all these structures can be broadly classified as
four basic architectures.

(a) Input/output to central processor :in this structure all exchanges between
Input/output device and memory pass through the CPU. it is a simple and
inexpensive structure but reduces the CPU throughout as CPU is tied up in
doing input-output tasks which are normally considerably slower than that

By Usha Kamala B T,VVFGC,Tumakuru. Page 16

 Computer Architecture, IIIBCA Chap:1

of CPU operations.

(b) Input/output to Memory: this architecture involves direct transfer between

Input/output and memory without involving much time from CPU. the
input/output here can be performed simultaneously along when CPU is doing
other computation but this structure has a complex and inflexible control
mechanism.

(c) Input/Output to central Switch: A central switch is provided here which

controls the access of memory by CPU and input/output device. Here CPU is
freed up to do other computations. It also provide control of input/output
operation through CPU directly therefore, It is a powerful flexible approach is
the complexity of the switch.

(d) Input/Output to bus: it is a flexible and simple structure and used

commonly in micro and mini computers.

Bus Interconnection

A bus is a set of connection between two or more components/devices which

are designed to transfer several/all bits of a word from a specific source to
destination. It is a shared media of information transfer. A bus consist of
multiple communication paths which are also termed as lines. A line is
capable of transferring one bit only. Thus, for transferring a word of 16bits
simultaneously over a bus we need to have 16 lines for transferring data. In
addition, some other lines are needed for controlling this transfer.

Note: A bus may be unidirectional (capable of transmitting data in one

direction)or by-directional .

The Bus Is Used In The Following Way:

Request for sending data
 First the sender grabs the permit o use the bus
 And then transfers the information.

Request for receiving data from other module.

 Grab the bus.

 Transfer the request to other module to send the data.
 Then wait for the other module to send the data.

Shared bus:In a shared bus only one source can transmit at a time while one
or more than one receive that signal. Figure shows the diagram of shared bus.

By Usha Kamala B T,VVFGC,Tumakuru. Page 17

 Computer Architecture, IIIBCA Chap:1

CPU Memory I/O

Figure : A shared bus

System Bus Structure

Figure :System bus structure

A computer system unidirectional a number of buses which provide path ways

among several devices. A shared bus that connects CPU, memory and
Input/output is called a system bus.

A system bus may consist of 50 to 100 separate lines. These lines can be
broadly categorized into three functional groups:

*Data lines these are collectively called as data bus.

*Address lines, these are collectively called as address bus.

*Control lines, these are collectively called as control bus.

The data bus provides path for moving data between the system modules. It
normally consist of 8,16 or 32 bit separate lines. The number of lines in data
bus is called the width of data bus. Thus, a data bus width limits the

By Usha Kamala B T,VVFGC,Tumakuru. Page 18

 Computer Architecture, IIIBCA Chap:1

maximum number of bits which can be transferred simultaneously between

two modules e.g. CPU and memory. The width of data bus also helps in
determining the overall performance of a computer system. for ex ,if the width
of data bus is 8 bits and an instruction is of 16 bits then for fetching each
instruction to memory access will be needed by the CPU.

The address bus is used to designate the source of data for data bus. As the
memory maybe divided into linear array of bytes or words ,therefore ,for
reading or writing any information on to memory CPU need to specify the
address of a particular location.This address is supplied by the address bus.
Thus the width of address bus specifies the maximum possible memory
supported by a system. for ex, if system has 16 bit wide address bus then it
can have main memory size equivalent to 2^16=64k.the role of control line
(bus)is to control for transmission of command and timing signals(which
validate data address)between the system modules.

some of control lines of bus are required for: bus request ,bus grant,
providing clock signal, providing reset signals, reading/writing to I/O devices
or memory etc.

Elements of Bus Design

Physically a bus is a number of parallel electrical conductors. These circuits
are normally imprinted on printed circuit boards. The bus normally extends
across most of the system components which can be tapped into the bus lines.
You can see these wires in the Printed Circuit Board of your Personal
Computer. Let us now discuss some of the aspects or elements related to the
bus design.

1) Bus Types
2) Method of Arbitration
3) Timing
4) Bus Width
5) Data Transfer Type
6) Block Data Transfer
1) Bus Types
A) Dedicated
 A line is permanently assigned either to one function.
 An example of functional dedication is the use of separate dedicated
address and data line.
B) Multiplexed
 Using the same lines for multiple purpose.
 Eg:- Address and data information may be transmitted over the same
set of lines.
 At the beginning of the data transfer the address is placed on the
bus and the address valid line is activated.

By Usha Kamala B T,VVFGC,Tumakuru. Page 19

 Computer Architecture, IIIBCA Chap:1

 The address is then remove from the same bus line is used for data
transfer.
C) Physical Dedication
 The use of multiple buses, each of which connects to only a subset of
modules.

2) Method of Arbitration
 Determining who can use the bus at a particular time.
A) Centralized
 A single hardware device called the bus controller or arbiter allocate
time on the bus.
 The device may be a separate or a part of a processor.
 Some of the arbitration schemes are;daisy chaining, polling,
independent requesting
B) Distributed
 There is no centralized controllers.
 Each module contains assess control logic and the modules act
together.

3) Timing
A) Synchronous Timing
 Bus includes a clock line upon which a clock transmits a regular
sequence of alternating 1's and 0's
 A single 1-0 transition is referred to as a clock cycle or bus cycle.
 All other devices on the bus can read the clock line.
 All events start at the beginning of a clock cycle
B) Asynchronous Timing
 The occurrence of one event on a bus follows and depends on the
occurrence of a previous event.
 Harder to implement and text than synchronous timing.

4) Bus Width
 The width of data bus has an impact on the data bus has an impact
on the system performance.
 The wider data bus, the greater number of bit transferred at one time.
 The wider address bus, the greater range of location that can be
referenced.

5) Data Transfer Type

 Read-Modify-Write : A read followed immediately by a write to the
same address.
 Read-After-Write : Consisting of a write followed immediately by a
read from the same address (for error checking purposes).
6) Block Data Transfer
 One address cycle followed by n data cycles.

By Usha Kamala B T,VVFGC,Tumakuru. Page 20

 Computer Architecture, IIIBCA Chap:1

 First data item to or from specified address.

 Remaining data items to or from subsequent addresses.

[ EXTRA DETAILED NOTES

Dedicated or Multiplexed Buses: A dedicated bus line, as the name
suggests, is assigned Permanently to a function or to a physical subset of the
components of the computer.
The example of a functional dedicated bus is the dedicated address bus and
data bus. As far as physical dedication is concerned a bus is dedicated to only
a subset of modules .For example, an Input/output bus can be used to
connect all the Input/Output modules. The physical dedication increases
the throughput of the bus as only few modules are in contention but it
increases overall size and cost of a system.
In certain computers bus some or all the address lines are also used for data
transfer operation, that is, the same lines are used for address as well as data
lines, but of course, at different times. This is known as time multiplexing and
is a good example of multiplexed bus. This multiplexing reduces the total
number of lines to b used which in turn results in reduction of cost and space.
But the disadvantages of multiplexing are the complex circuitry and potential
reduction in performance as the multiplexed lines cannot be used in parallel.

Synchronous or asynchronous timing: Another important of buses is the

manner in which the data transfer is timed. In synchronous buses the data
is transferred during specific time which is known to source and destination.
Synchronization is normally achieved by using clock pules of the same clock
source for both source and destination or different clocks of same frequency.
Normally the synchronisation source and destination keep a periodic
communication in order to keep step with each other. The Synchronising
buses are easy to implement and test but restricts information transfer rate
to that of the slowest device. Alternative approach to synchronous bus is the
asynchronous buses. In this approach each item which is to be transferred
has a separate control signal. This signal indicate the presence of the item on
the bus to the destination. With the asynchronous buses a variety of fast and
slow devices can share a bus. However, the bus-control circuitry is more
complex and expensive in the case of asynchronous buses.

Bus arbitration: Another important aspect of the system where buses are
used is the control of a bus. In most of the systems more than one module
need control of the bus. For expamle, Input/Output modules may need
control of the bus for transferring data to memory. Similarly, CPU also needs
the bus for various data transfer. Suppose

By Usha Kamala B T,VVFGC,Tumakuru. Page 21

 Computer Architecture, IIIBCA Chap:1

both of these devices wants to transfer information at the same time .

Therefore, there should be a method for resolving the simultaneous data
transfer request on the bus. This has been suggested. These are centralized
and distributed. In the scheme a hardware circuit device which is referred to
as bus controller or bus arbiter process the request to use the bus. The bus
controller may be a separate module or can be constructed as the part of
CPU. On the contrary the distributed scheme has shared access control logic
among the various modules. All these modules work together to share the
bus. Irrespective of the scheme, the main role of arbitration is to designate one
device as master(which controls the bus during the time it is designated as
master ).Some of the arbitration schemes are;

1. daisy chaining
2. polling
3. independent requesting

------END OF EXTRA NOTES]

MICROPROCESSOR ORGANIZATION
Design of instruction set the microprocessor is an important aspect of
computer architecture. The instruction set chosen for a particular computer
determines the way that machine language programs are constructed. Many
computers have instruction sets that include more than 100 and sometimes
even more than 200 instructions. They also employ a variety of data types and
large number of addressing modes.

The factors that influence computer hardware complexity are

 Upgrading existing model to provide more customer applications.

 Adding instructions to translate from high level language into
machine language programs.
 Developing machines that move functions from software
implementation into hardware implementation.

Earlier when programming was done using assembly language, a need was
felt to make instruction do more task because programming in assembly was
tedious and error prone due to which CISC architecture evolved but with up
rise of high level language dependency on assembly reduced RISC
architecture prevailed.

Reduced Set Instruction Set Architecture (RISC) –

The main idea behind is to make hardware simpler by using an instruction
set composed of a few basic steps for loading, evaluating and storing

By Usha Kamala B T,VVFGC,Tumakuru. Page 22

 Computer Architecture, IIIBCA Chap:1

operations just like a load command will load data, store command will
store the data.
Characteristic of RISC –
1. Simpler instruction, hence simple instruction decoding.
2. Instruction come under size of one word.
3. Instruction take single clock cycle to get executed.
4. More number of general purpose register.
5. Simple Addressing Modes.
6. Less Data types.
7. Pipeline can be achieved.
Complex Instruction Set Architecture (CISC) –
The main idea is that a single instruction will do all loading, evaluating and
storing operations just like a multiplication command will do stuff like
loading data, evaluating and storing it, hence it’s complex.
Characteristic of CISC –
1. Complex instruction, hence complex instruction decoding.
2. Instruction are larger than one word size.
3. Instruction may take more than single clock cycle to get executed.
4. Less number of general purpose register as operation get performed in
memory itself.
5. Complex Addressing Modes.
6. More Data types.
Both approaches try to increase the CPU performance
 RISC: Reduce the cycles per instruction at the cost of the number of
instructions per program.
 CISC: The CISC approach attempts to minimize the number of
instructions per program but at the cost of increase in number of cycles
per instruction.

By Usha Kamala B T,VVFGC,Tumakuru. Page 23

 Computer Architecture, IIIBCA Chap:1

COMPARSION BETWEEN CISC AND RISE PROCESSOR ORANIZATION

CISE RISC
1. Large number of instructions 1. Fewer instructions.
2. Emphasis is in hardware 2. Emphasis is on software
3. It includes multi-clock 3. It includes single-clock,
complex instruction reduced instruction only
4. Memory-to-memory: “LOAD” 4. Register to register: “LOAD”
and “STORE” incorporated in and Store” are independent
instructions instructions
5. Code size is small but 5. Code size is large but
complex. High cycles per simple. Low cycles per
second. second
6. Transistors are used for 6. More transistors are used
storing complex instructions for memory registers
7. Variable length instruction 7. Fixed length instruction
format format
8. Large variety of addressing 8. Few addressing modes
modes

Parallel Processing
Parallel processing is a method of simultaneously breaking up and running
program tasks on multiple microprocessors, thereby reducing processing
time. Parallel processing may be accomplished via a computer with two or
more processors or via a computer network. Parallel processing is also called
parallel computing.
Parallel processing is particularly useful when running programs that perform
complex computations, and it provides a viable option to the quest for cheaper
computing alternatives. Supercomputers commonly have hundreds of
thousands of microprocessors for this purpose. Parallel processing should not
be confused with concurrency, which refers to multiple tasks that run
simultaneously.

Parallel System
 These systems are also called as tightly –coupled systems due to the
high degree of resource sharing.
 In parallel system, multiple CPUs are used simultaneously to execute
a program.
 A program is broken into discrete parts that can be solved
concurrently.
 Each part is further broken down to a series of instructions and
instructions from each part execute simultaneously on different CPUs.
 Multi processing systems are available in two types- asymmetric
multiprocessing and symmetric multi processing.

By Usha Kamala B T,VVFGC,Tumakuru. Page 24

 Computer Architecture, IIIBCA Chap:1

Asymmetric multiprocessing:
-In this system there is a master slave relationship.
-A master CPU can execute the operating system routines and handle I/O.
-The remaining CPUs have no I/O capability and thus are called attached
processors.
Symmetric multiprocessing:
-All the CPUs are equally capable of running the system programs such as
the operating system kernel and I/O service routines.
Advantages of Parallel System:
1. Saves money
2. Increased reliability
3. Increased throughput
Disadvantages of Parallel System:
1. Implementation is complex
2. Requires resource management and protection

Pentium and PowerPC

The Pentium series is an excellent example of Complex Instruction Set
Computer (CISC) design. The PowerPC is a direct descendant of IBM 801, one
of the best designed RISC systems on the market.
Pentium
Intel has ranked the number one maker of microprocessors for decades. Here
is a brief history of the evolution of microprocessors that Intel has been
manufacturing.

Pre x86 series processors

 4004, 4040, 8008: 4 bits processor
 8080: first general purpose 8 bit microprocessor used in Altair PC.
 8085: binary compatible with 8080, simpler and less expensive.

x86 series - 16 bit processors

 8086: 16 bit powerful machine, support instruction cache that pre-fetch few
instructions before they executed.
 8088: has 8 bit external bus, used in first IBM PC
 80286: enabled addressing a 16 MB memory instead of 1MB.
 80386: 32 bit, support for multitasking

x86 series - 32 bit processors

 80486: introduced sophisticated powerful cache and instruction pipelining.
Also offered built in math co-processor, offloading complex math operations
from the main CPU.
 Pentium: introduced super-scalar technique which allows multiple
instructions to execute in parallel.
 Pentium Pro: Increased super-scalar organization with Aggressive register
renaming, branch prediction, data flow analysis and speculative execution.

By Usha Kamala B T,VVFGC,Tumakuru. Page 25

 Computer Architecture, IIIBCA Chap:1

 Pentium II: introduced the MMX technology which is designed specifically to

process video, audio and graphics data efficiently.
 Pentium III: provides additional floating point instructions for 3D graphics
s/w.
 Pentium 4: provides further floating point and multimedia enhancements.
 Core Series: the first x86 microprocessor with dual core, implementation of
two processors on a single chip.

x86 64 bit series: Pentium D, Pentium Extreme Edition (EE)

Core 2 series: The Core 2 extends the architecture to 64 bits. The Core 2 Quad
processor provides 4 processors on a single chip.
Itanium series:
 64 bit architecture, examples: Itanium I and Itanium II.
 Itanium II has hardware enhancements to increase the speed.

PowerPC
In 1975, IBM started the 801 minicomputer project that launched the RISC
movement.
In 1975, 801 minicomputer projects by IBM introduced the RISC. Then the
Berkeley RISC I processor was introduced.
In 1986, IBM introduced the commercial RISC workstation product called RT
PC which was not commercially successful due to performance of other
competitors.
In 1990, IBM introduced IBM RISC System/6000 which has
 RISC-like superscalar machine.
 POWER architecture.
IBM alliance with Motorola (68000 microprocessors), and Apple, (used 68000
in Macintosh) and produced PowerPC architecture which was
 Derived from the POWER architecture.
 Superscalar RISC
PowerPC Family is:
 601: Quickly to market. 32-bit machine.
 603: 32 bit low-end desktop and portable.
Lower cost and more efficient implementation
 604: Desktop and low-end servers, 32-bit machine.
Much more advanced superscalar design. Greater performance
 620: High-end servers, 64-bit architecture.
 740/750: Also known as G3, two levels of cache on chip.
 G4: Increases parallelism and internal speed.
 G5: Improvements in parallelism and internal speed, 64-bit organization.

By Usha Kamala B T,VVFGC,Tumakuru. Page 26

 Computer Architecture, IIIBCA Chap:1

QUESTIONS
One Mark Questions

a) Define computer architecture.

b) Define computer organization.
c) What are the functional entities of computer?
d) Mention the types of software?
e) Mention the types of computer architecture>?
f) Define interrupt.
g) What are the basic components of computer?
h) What is instruction?
i) Define bus arbitration?
j) What is bus?
k) Mention bus arbitration schemes?
l) What is dedicated bus?
m) What is multiplexed bus?

Three Mark Questions

a) Explain digital computer components with block diagram.

b) Explain von Neumann architecture?
c) Explain Harvard architecture?
d) Differentiate between von Neumann architecture and Harvard
architecture.
e) Explain structure of computer?
f) Explain software interrupts.
g) What are the basic operation cycles of computer? Explain
h) Explain basic registers used in instruction execution.
i) Differentiate between internal and external interrupts.
j) Explain CISC.
k) Explain RISC?

Long Answer Questions

a) What are the functions of computer? Explain.

b) Explain Instruction cycle?
c) Explain instruction cycle with interrupts.
d) Explain different types of interrupts.

By Usha Kamala B T,VVFGC,Tumakuru. Page 27

 Computer Architecture, IIIBCA Chap:1

e) Write a note on multiple interrupts?

f) Explain system bus structure.
g) Explain bus interconnection structure.
h) Write a note on elements of bus design
i) Differentiate between RISC and CISC
j) Explain Pentium evolution.
k) Write a note on power pc evolution.
l) Write a note on parallel processing.

By Usha Kamala B T,VVFGC,Tumakuru. Page 28