Chapter # 1: Introduction

Contemporary Logic Design

서울대학교 컴퓨터공학부
Logic Design Chap1.1
 Chapter Overview

• Process of Design

• Digital Systems

• Design Representations

• Rapid Prototyping

서울대학교 컴퓨터공학부
Logic Design Chap1.2
 The Process Of Design

Design

Implementation

Debug

Design
• Initial concept: what is the function performed by the object?
• Constraints: How fast? How much area? How much cost?

• Refine abstract functional blocks into more concrete realizations

서울대학교 컴퓨터공학부
Logic Design Chap1.3
 Implementation
• Assemble primitives into more complex building blocks

• Composition via wiring

• Choose among alternatives to improve the design

Debug

• Faulty systems: design flaws, composition flaws, component flaws

• Design to make debugging easier

• Hypothesis formation and troubleshooting skills

서울대학교 컴퓨터공학부
Logic Design Chap1.4
서울대학교 컴퓨터공학부
Logic Design Chap1.5
 The Art Of Design: Refinement of Representations

1. Functional Specification/What the System Does

Ex: Traffic Light Controller

Lights point in the directions N, S, E, W

Illuminates the same lights N as S and E as W

Cycles thru the sequence GREEN-YELLOW-RED

N-S and E-W never GREEN or YELLOW at the same time

Stay GREEN for 45 seconds, yellow for 15, red for 60

서울대학교 컴퓨터공학부
Logic Design Chap1.6
 2. Performance Constraints/Requirements to be Met

speed: compute changes in under 100 ms

power: consume less than 20 watts

area: implementation in less than 20 square cm

cost: less than $20 in manufacturing costs

서울대학교 컴퓨터공학부
Logic Design Chap1.7
 The Art of Design: "To Design Is To Represent"

1. English language specification

easy to write, but not precise and subject to ambiguity

2. Functional description Start

more precise specification
N-S Green
flow charts, program fragments E-W Red
af ter 45 seconds
3. Structural description N-S Yellow
complex components decomposed into E-W Red
compositions of less complex components af ter 15 seconds
N-S Red

4. Physical description
E-W Green
af ter 45 seconds
the design in terms of most primitive
N-S Red
building blocks, e. g., logic gates or E-W Yellow
transistors
af ter 15 seconds

서울대학교 컴퓨터공학부
Logic Design Chap1.8
 The Process of Design

Implementation as Assembly

Top Down Design:

Complex functions replaced by more primitive functions

Bottom Up Design:
Primitives composed to build more and more complex assemblies

Rules of Composition and Correctness by Construction:

• Electrical Rules: how many components can be cascaded?

• Timing Rules: how does the system change in conjunction with

periodic triggering events?

서울대학교 컴퓨터공학부
Logic Design Chap1.9
 The Process of Design

Top Down Decomposition

Structural N-S Green

Representation N-S Yellow
Start Traf fic Light N-S Red
Subs y stem E-W Green
E-W Yellow
E-W Red
45 s ec onds N-S Green
Light N-S Yellow
Start Timer N-S Red
Sequenc er E-W Green
E-W Yellow
15 s ec onds E-W Red
45 s ec onds N-S Lights N-S Green
N-S Yellow
Start Primitiv e N-S Red
Timer Sequenc er Decoder
E-W Green
E-W Yellow
15 s ec onds E-W Lights E-W Red

decomposition of high level functions into more primitive functions

서울대학교 컴퓨터공학부
Logic Design Chap1.10
 N-S Green
N-S Yellow
Start Traf fic Light N-S Red
Subs y stem E-W Green
E-W Yellow
E-W Red
45 s ec onds N-S Green
Light N-S Yellow
Start Timer N-S Red
Sequenc er E-W Green
E-W Yellow
15 s ec onds E-W Red
45 s ec onds N-S Lights N-S Green
N-S Yellow
art Primitiv e N-S Red
Timer Sequenc er Decoder
E-W Green
E-W Yellow
15 s ec onds E-W Lights E-W Red

서울대학교 컴퓨터공학부
Logic Design Chap1.11
 N-S Green
N-S Yellow
Start Traf fic Light N-S Red
Subsystem E-W Green
E-W Yellow
E-W Red
45 seconds N-S Green
Light N-S Yellow
Start Timer N-S Red
Sequencer E-W Green
E-W Yellow
15 seconds E-W Red
45 seconds N-S Lights N-S Green
N-S Yellow
Start Primitive N-S Red
Timer Sequencer Decoder
E-W Green
E-W Yellow
15 seconds E-W Lights E-W Red

서울대학교 컴퓨터공학부
Logic Design Chap1.12
 The Process of Design

Bottom Up Assembly
Building
Primitives composed to build
more and more complex assemblies

e.g., a group of rooms form a floor

a group of floors form a bldg.

Floor
e.g., a group of transistors form a gate

a group of gates form an addition circuit

addition circuits plus storage circuits

form a processor datapath Rooms

서울대학교 컴퓨터공학부
Logic Design Chap1.13
 The Process of Design: Debugging the System
What Can Go Wrong
• Design Flaws
Implementation does not meet functional specification

Logic design is incorrect (wrong function implemented)

Misinterpretation or corner cases ignored

• Implementation Flaws
Individual modules function correctly but their compositions do not

Misunderstanding of interface and timing behavior

Wiring mistakes, Electrical mistakes

• Component Flaws
Logically correct and correctly wired

Not all hardware components are guaranteed to work!

E.g., burnt out component

서울대학교 컴퓨터공학부
Logic Design Chap1.14
 The Process of Design

Debugging via Simulation Before Construction

Debugging Skills:

• Improving the testability of the design

• Formulating a testing plan and choosing test cases

• Hypothesizing about the cause of the problem

• Isolating portions of the implementation for testing

• Effective use of laboratory instruments for troubleshooting

서울대학교 컴퓨터공학부
Logic Design Chap1.15
 Digital Hardware Systems
Digital Systems
Digital vs. Analog Waveforms

+5 +5

1 0 1
V V
Time Time

?0 ?0

Digital: Analog:
only assumes discrete values values vary over a broad range
continuously

서울대학교 컴퓨터공학부
Logic Design Chap1.16
 Digital Hardware Systems

Advantages of Digital Systems

• Analog systems: slight error in input yields large error in output

• Digital systems: more accurate and reliable

Readily available as self-contained, easy to cascade building blocks

Computers use digital circuits internally

Interface circuits (i.e., sensors & actuators) often analog

This course is about logic design, not system design (processor

architecture), not circuit design (transistor level)

서울대학교 컴퓨터공학부
Logic Design Chap1.17
 Digital Hardware Systems

Digital Binary Systems

• Two discrete values:
yes, on, 5 volts, current flowing, magnetized North, "1"
no, off, 0 volts, no current flowing, magnetized South, "0"

• Advantage of binary systems:

rigorous mathematical foundation based on logic

IF the garage door is open both the door must

be open and the car
AND the car is running running before I can
THEN the car can be backed out of the garage back out

IF N-S is green
AND E-W is red
AND 45 seconds has expired since the last light change
THEN we can advance to the next light configuration

the three preconditions must be true to imply the conclusion

서울대학교 컴퓨터공학부
Logic Design Chap1.18
 Digital Hardware Systems
Boolean Algebra and Logical Operators

Algebra: variables, values, operations

In Boolean algebra, the values are the symbols 0 and 1

If a logic statement is false, it has value 0
If a logic statement is true, it has value 1

Operations: AND, OR, NOT

X Y X AND Y X Y X OR Y X NOT X
0 0 0 0 0 0 0 1
0 1 0 0 1 1 1 0
1 0 0 1 0 1
1 1 1 1 1 1

서울대학교 컴퓨터공학부
Logic Design Chap1.19
 George Boole (1815 – 1864)

• 영국 수학자.
• The Mathematical Analysis of
Logic, 1847
– AND, OR & NOT can perform all
logic functions
– No practical use
» Forgotten until 1930s

Source: www.computerhistory.org

서울대학교 컴퓨터공학부
Logic Design Chap1.20
 Claude Shannon (1916 – 2001)

• Encountered G. Boole’s ideas

in a college philosophy class
in 1930s.
• 1937 MIT 석사학위논문:
A Symbolic Analysis of Relay and
Switching Circuits

– Applied Boolean Algebra to the

design of logic circuits

Source: www.computerhistory.org

서울대학교 컴퓨터공학부
Logic Design Chap1.21
 Digital Hardware Systems

Hardware Systems and Logical Operators

IF the garage door is open

AND the car is running
THEN the car can be backed out of the garage

door open? car running? back out car?

false/0 false/0 false/0
false/0 true/1 false/0
true/1 false/0 false/0
true/1 true/1 TRUE/1

서울대학교 컴퓨터공학부
Logic Design Chap1.22
 Digital Hardware Systems
The Real World
Physical electronic components are continuous, not discrete!

These are the building blocks of all digital components!

+5
Logic 1 Transition from logic 1 to logic 0
does not take place instantaneously
V in real digital systems

Logic 0 Intermediate values may be visible

for an instant
0

Boolean algebra useful for describing the steady state behavior of

digital systems

Be aware of the dynamic, time varying behavior too!

서울대학교 컴퓨터공학부
Logic Design Chap1.23
 Digital Hardware Systems

Digital Circuit Technologies

Integrated circuit technology

choice of conducting, non-conducting, sometimes conducting

("semiconductor") materials

whether or not their interaction allows electrons to flow forms

the basis for electrically controlled switches

Main technologies

MOS: Metal-Oxide-Silicon

Bipolar
Transistor-Transistor Logic
Emitter Coupled Logic

서울대학교 컴퓨터공학부
Logic Design Chap1.24
 Digital Hardware Systems
MOS Technology
Transistor
basic electrical switch
Gate

Drain Source

three terminals: gate, source, drain

voltage between gate and source exceeds threshold

switch is conducting or "closed"
electrons flow between source and drain

when voltage is removed,

the switch is "open" or non-conducting
connection between source and drain is broken

서울대학교 컴퓨터공학부
Logic Design Chap1.25
 Transistor as a Switch

서울대학교 컴퓨터공학부
Logic Design Chap1.26
 Digital Hardware Systems
Circuit that implements logical negation (NOT)

Logic 0 Input 1 at input yields 0 at output

+5 Voltage 0 at input yields 1 at output

Inverter behavior as a function of input voltage

input ramps from 0V to 5V
VOu t output holds at 5V for some range of small
Logic 1 Input input voltages
Voltage then changes rapidly, but not instantaneously!

0 V In +5

remember distinction between

steady state and dynamic behavior

서울대학교 컴퓨터공학부
Logic Design Chap1.27
 Digital Hardware Systems

Combinational vs. Sequential Logic

X1 Z1 Network implemented from

X2 Z2 switching elements or logic
- Switching -
gates.
- Network -
- - The presence of feedback
Xn Zm
distinguishes between sequential
and combinational networks.

Combinational logic
• no feedback among inputs and outputs
• outputs are a pure function of the inputs
• e.g., full adder circuit:
(A, B, Carry In) mapped into (Sum, Carry Out)

A
B Full Sum
Cin Adder Cout

서울대학교 컴퓨터공학부
Logic Design Chap1.28
 Digital Hardware Systems
Sequential logic
inputs and outputs overlap
outputs depend on inputs and the entire history of execution!

network typically has only a limited number of unique configurations

these are called states
e.g., traffic light controller sequences infinitely through four states

new component in sequential logic networks:

storage elements to remember the current state

output and new state is a function of the inputs and the old state
i.e., the feedback inputs are the state!

Synchronous systems
period reference signal, the clock, causes the storage elements to
accept new values and to change state

Asynchronous systems
no single indication of when to change state

서울대학교 컴퓨터공학부
Logic Design Chap1.29
 Digital Hardware Systems

Combinational vs Sequential Logic

Other Inputs ,
Lik e Timer Alarms
Traffic Light Example
Traf fic Light New Traf fic Light
Controller Controller Configuration

Current Traf fic

Light Controller
Conf iguration
Cloc k
Timer
Alarms
S
Next State T Output Detailed Light
Combinational A Combinational Control Signals
Logic T Logic
E
Current State

Next State Logic Current State Output Logic

Maps current Storage elements Current state mapped
state and alarm replaced by next state into control signals
events into the when the clock signal to change the lights
next state arrives and to start the event
IF controller in state N-S green, E-W red timers
AND the 45 second timer alarm is asserted
THEN the next state becomes N-S yellow,
E-W red when the clk signal is next asserted
서울대학교 컴퓨터공학부
Logic Design Chap1.30
 Representations of a Digital Design

Switches
A switch connects two points under control signal.

Normally Open when the control signal is 0 (false), the switch is open

when it is 1 (true), the switch is closed

Normally Closed when control is 1 (true), switch is open

when control is 0 (false), switch is closed

True True

Control Clos ed Control Open

Switch Switch

Fals e Fals e
Normally Open Normally Closed
Switch Switch

Open Clos ed
Switch Switch
서울대학교 컴퓨터공학부
Logic Design Chap1.31
 Representations of a Digital Design

Truth Tables
tabulate all possible input combinations and their associated
output values
Example: half adder Example: full adder
adds two binary digits adds two binary digits and
to form Sum and Carry Carry in to form Sum and
Carry Out
A B Sum Carry A B Cin Sum Cout
0 0 0 0 0 0 0 0 0
0 1 1 0 0 0 1 1 0
1 0 1 0 0 1 0 1 0
1 1 0 1 0 1 1 0 1
1 0 0 1 0
1 0 1 0 1
1 1 0 0 1
NOTE: 1 plus 1 is 0 with a 1 1 1 1 1
carry of 1 in binary

서울대학교 컴퓨터공학부
Logic Design Chap1.32
 Representations of a Digital Design
Boolean Algebra
values: 0, 1
variables: A, B, C, . . ., X, Y, Z
operations: NOT, AND, OR, . . .

NOT X is written as X
X AND Y is written as X & Y, or sometimes X Y
X OR Y is written as X + Y

Deriving Boolean equations from truth tables:

Sum = A B + A B
A B Sum Carry
OR'd together product terms
0 0 0 0 for each truth table
0 1 1 0 row where the function is 1
1 0 1 0
1 1 0 1 if input variable is 0, it appears in
complemented form;
if 1, it appears uncomplemented
Carry = A B
서울대학교 컴퓨터공학부
Logic Design Chap1.33
 Representations of a Digital Design
Gates
most widely used primitive building block in digital system design

Standard Half Adder Schematic

Logic Gate
Representation
A
Inv erter

AND
Net 1 SUM

B
OR

Net 2

CAR RY

Net: electrically connected collection of wires

Netlist: tabulation of gate inputs & outputs

and the nets they are connected to
서울대학교 컴퓨터공학부
Logic Design Chap1.34
 Representations of a Digital Design: Gates

Full Adder Schematic

\Cin \ B \ A
Cin B A
A

SUM
Cin

A
B

Cout B Cout
Cin

A
Cin

Fan-in: number of inputs to a gate

Fan-out: number of gate inputs an output is connected to
Technology "Rules of Composition" place limits on fan-in/fan-out
서울대학교 컴퓨터공학부
Logic Design Chap1.35
 Representations of a Digital Design
Waveforms
dynamic behavior of a circuit
real circuits have non-zero delays
Timing Diagram of the Half Adder
100 200
A
B
SUM
CAR RY

sum sum
propagation propagation
delay delay
circuit hazard: 1 plus 0 is 1, not 0!

Output changes are delayed from input changes

The propagation delay is sensitive to paths in the circuit

Outputs may temporarily change from the correct value to the

wrong value back again to the correct value: this is called
a glitch or hazard
서울대학교 컴퓨터공학부
Logic Design Chap1.36
 Representations of a Digital Design

Blocks
structural organization of the design

black boxes with input and output connections

corresponds to well defined functions

concentrates on how the components are composed by wiring

Sum A Sum
A A Sum A Sum A Sum
HA HA B
B B Carry B Carry B FA
Cout
Cin Cout
Cin Cin Cout

Full Adder realized in terms of Block diagram representation

composition of half adder blocks of the Full Adder

서울대학교 컴퓨터공학부
Logic Design Chap1.37
 Representations of a Digital Design

Waveform Verification
Does the composed full adder behave the same as the full gate
implementation?
100 Glitc h 200
A
B
Cin
Sum
Cout

Sum, Cout waveforms lag input changes in time

How many time units after input change is it safe to examine

the outputs?

서울대학교 컴퓨터공학부
Logic Design Chap1.38
 Representation of a Digital Design:
ABEL Hardware Description Language Behaviors
MODULE half_adder;
a, b, sum, carry PIN 1, 2, 3, 4;
TRUTH_TABLE {[a, b] -> [sum, carry]}
Truth Table [0, 0] -> [0, 0];
Specification [0, 1] -> [1, 0];
[1, 0] -> [1, 0];
[1, 1] -> [0, 1];
END half_adder;

MODULE half_adder;
a, b, sum, carry PIN 1, 2, 3, 4;
Equation EQUATIONS
Specification SUM = (A & !B) # (!A & B);
CARRY = A & B;
END half_adder;

AND OR NOT

서울대학교 컴퓨터공학부
Logic Design Chap1.39
 Representations of a Digital Design
Behaviors
Hardware description languages
structure and function of the digital design

Example: Half Adder in VHDL

-- ***** inverter gate model *****
-- external ports Black Box View
ENTITY inverter_gate; as seen by outside
PORT (a: IN BIT; z: OUT BIT); world
END inverter_gate;

-- internal behavior
ARCHITECTURE behavioral OF inverter_gate IS
BEGIN Internal Behavior
z <= NOT a AFTER 10 ns; Note delay statement
END behavioral;

-- ***** and gate model *****

-- external ports
ENTITY and_gate;
PORT (a, b: IN BIT; z: OUT BIT);
END and_gate;

-- internal behavior
ARCHITECTURE behavioral OF and_gate IS
BEGIN
z <= a AND b AFTER 10 ns;
END behavioral;
서울대학교 컴퓨터공학부
Logic Design Chap1.40
 Representation of a Digital Design: Behaviors
-- ***** or gate model *****
-- external ports
ENTITY or_gate;
AND, OR, NOT models
PORT (a, b: IN BIT; z: OUT BIT); typically included in a
END or_gate; library
-- internal behavior
ARCHITECTURE behavioral OF or_gate IS
BEGIN
z <= a OR b AFTER 10 ns;
END behavioral;

-- ***** half adder model *****

-- external ports
ENTITY half_adder;
PORT (a_in, b_in: INPUT; sum, c_out: OUTPUT);
END half_adder;
Particular components
-- internal structure to be used within the
ARCHITECTURE structural of half_adder IS
-- component types to use model of the half adder
COMPONENT inverter_gate
PORT (a: IN BIT; z: OUT BIT); END COMPONENT;
COMPONENT and_gate
PORT (a, b: IN BIT; z: OUT BIT); END COMPONENT;
COMPONENT or_gate
PORT (a, b: IN BIT; z: OUT BIT); END COMPONENT;

-- internal signal wires

서울대학교 컴퓨터공학부 SIGNAL s1, s2, s3, s4: BIT;
Logic Design Chap1.41
 Representation of a Digital Design: Behaviors
BEGIN
-- one line for each gate, describing its type and connections
i1: inverter_gate PORT MAP (a_in, s1);
i2: inverter_gate PORT MAP (b_in, s2);
a1: and_gate PORT MAP (b_in, s1, s3); Textual description
a2: and_gate PORT MAP (a_in, s2, s4); of the netlist
o1: or_gate PORT MAP (s3, s4, sum);
END structural;

This VHDL specification corresponds to the following labeled schematic

A s1
i1 s3
a1

o1
SUM
B a2
i2 s4
s2

Carry
a3
서울대학교 컴퓨터공학부
Logic Design Chap1.42
 Rapid Electronic System Prototyping
Goals:
• quick construction of digital systems to prove concept

• rapid exploration of alternative design approaches

• performance traded off for faster path to implementation

Techniques:

computer-aided design tools

• simulation: find out how the design will behave
before constructing it
• synthesis: generate detailed descriptions, like schematics,
from high level descriptions, like Boolean equations

quick turnaround implementation technologies

programmable logic

서울대학교 컴퓨터공학부
Logic Design Chap1.43
 Rapid Electronic System Prototyping:

Computer-Aided Design
Synthesis tools
• create a portion of the design from other portions

• map more abstract representation to more physical

representation

VHDL
Behavioral Boolean Logic
Verilog Schematics
… Synthesis Equations Synthesis

ABEL Gate
Libraries

• map a representation into a more optimized form of

that representation, e.g., espresso

서울대학교 컴퓨터공학부
Logic Design Chap1.44
 Rapid Electronic System Prototyping
Simulation
• program which dynamically executes an abstract design description

• obtain verification of functional correctness and some timing

information before the design is physically constructed

• easier to probe and debug a simulation than an implemented design

• simulation cannot guarantee that a design will work

only as good as the test cases attempted
does not check electrical errors
abstracts away some of the realities of a real system

Logic Simulation
design described in terms of logic gates
values are 0, 1 (plus others to be introduced)
good for truth table verification

Timing Simulation
waveform inputs and outputs
model of gate delays
are the waveform shapes what was expected?
서울대학교 컴퓨터공학부
identification of performance bottlenecks
Logic Design Chap1.45
 Rapid Electronic System Implementation

Rapid Implementation Technologies

• the function and interconnect of a component can be "personalized"

• alternative to discrete logic gates and wires

• reduces wiring complexity and parts count

• facilitates more rapid design changes and enhancements

Programming with 1's and 0's

• component function configured through truth table

• interconnect among internal modules also configured in this way

selectively blown fuses
programmable switching matrix configured by 1's and 0's

서울대학교 컴퓨터공학부
Logic Design Chap1.46
 Rapid Electronic System Prototyping
Example: Read-Only Memories
• hardware implementation of a two dimensional array

• inputs form the index into the array

• the binary word at the indexed memory location contains the

output values

• contents are programmed once, read many times

Half Adder Realized as a ROM: Full Adder Realized as a ROM:

Index contents
Index contents
00 0 0 0
00 0 0 00 1 1 0
01 1 0 01 0 1 0
Half adder 10 1 0 01 1 0 1
11 0 1 Full adder 1 0 0 1 0
10 1 0 1
A
11 0 0 1
B S C 11 1 1 1
U A A
M R B S C
R Cin
Y U o
서울대학교 컴퓨터공학부
M u
t
Logic Design Chap1.47
 Chapter Review

• the process of design:

functional decomposition and design by assembly

• the kinds of systems we will be designing:

combinational and sequential logic

binary digital systems
implemented in MOS and bipolar technology

• the many levels of design representation:

from switches to behavioral descriptions

• the changing technological landscape:

rapid electronic system implementation

facilitated by computer-aided design tools
(in particular, synthesis and simulation tools)
and programmable logic devices
서울대학교 컴퓨터공학부
Logic Design Chap1.48