Verilog Weekly Quiz 1 - : Questions Right Wrong Unattended Accuracy Time Taken

4/13/2021 Maven Silicon - Online VLSI Courses
Apr 13 2021
Verilog Weekly Quiz 1 -
20 10 10 0 50% 09:12
Questions Right Wrong Unattended Accuracy Time Taken
10
Marks Scored
OFFER
View rank list (https://elearn.maven-silicon.com/report/assessment/998)
No.of
Topics Qns Right Wrong Unattended Accuracy Remarks
BA 1 1 0 0 100% Excellent
Process 3 2 1 0 66.67% Average
https://elearn.maven-silicon.com/material/assesment_report_item/87854 1/28
No.of
Synthesis 1 0 1 0 0% Needs
Improvement
Race 1 0 1 0 0% Needs
Improvement
Function 1 0 1 0 0% Needs
OFFER
Improvement
Data-types 2 1 1 0 50% Needs

Improvement
Compiler 2 2 0 0 100% Excellent

directive
System function 1 0 1 0 0% Needs

Improvement
Operators 1 1 0 0 100% Excellent
No.of
Delays 1 0 1 0 0% Needs
Improvement
System task 2 2 0 0 100% Excellent
Testbench 1 1 0 0 100% Excellent

OFFER
Task 1 0 1 0 0% Needs
Improvement
NBA 1 0 1 0 0% Needs
Improvement
Branch 1 0 1 0 0% Needs
Improvement
Easy Medium Hard

Questions Questions Questions
Right Answers Right Answers 0 Right Answers 0

10
OFFER
Wrong Answers Wrong Answers

Wrong Answers 0 0
10
Unattended 0 Unattended 0
Unattended 0
All questions Compare (https://elearn.maven-silicon.com/report/assessment/998)
1 Single choice
Find out the final value of out2 at every pos-edge of the clock and
choose right answer?
module ab(clk,in1,in2,out2);
input clk,in1,in2;
output out2;
reg temp,temp1,temp;
always@(posedge clk)
begin
temp = (in1în2);
OFFER
temp1= temp;
temp2 = temp1;
end
assign out2=temp2;
endmodule
a) Previous value of temp1 b) Previous value of temp2

c) in1 ^ in2 d) concurrent execution (un
predictable)
e) compilation error
Your answer c Right Time Taken 48s Marks 1 Answer Explanation
Blocking updates are immediate assignments.
2
OFFER
Single choice
What is the reset type from the below Verilog snippet?
a) Active high synchronous re b) Active low synchronous re

set set
c) Active high asynchronous d) Active low asynchronous c

clear lear
e) None of the above
Your answer b Right Time Taken 8s Marks 1 Answer Explanation
Since the design resets wrt posedge clock only hence the reset is synchronous.
OFFER
3 Single choice
For combinational circuit synthesis, which of the following are

recommended?
a) Feedback connections from b) If “if…else” construct is us

output to input may be allo ed, value must be assigned
wed. to the output variable for al
l possible combinations of
the inputs.
c) Procedural assignment mus d) All of the above.
t not be used.
Your answer d Wrong Right answer b

Time Taken 31s Marks 0 Answer Explanation
Feedback connection from output to input results in sequential behavior and must not
be present in a combinational circuit. Thus option (a) is correct. If values of output vari
ables are not speci ed for all input permutation, the circuit may be realized sequential
latch. Thus option (b) is also correct. Continuous as well as procedural assignment bot
h can be used in realizing combinational circuit. Thus option (c) is not correct.
OFFER
4 Single choice
What will the following code segment do?

initial
begin int1=42; int2=17; end
always @(posedge clock)
int2 = int1;
always @(posedge clock)
int1 = int2;
a) A race condition will occu b) Swaps the values of the var

r, i.e. both the integer varia iables “int1” and “int2”.
bles will update with either
value of “int1” or “int2”.
c) Both variables will get upd d) Both variables will get upd
ated with the value 42. ated with the value 17.
e) None of these
Your answer b Wrong Right answer a

OFFER
Both the variable int1 and int2 will be updated with the same value of int1 or int2 base
d on order of execution of the two procedural blocks, which is a race condition. Thus o
ption (a) is true and option (b), (c) and (d) are false.
5 Multiple choice
Which is a valid bug in the below code?
OFFER
a) Function should have outp b) The width of the function s

ut argument to return the su hould be 2bits wide.
m output.
c) The width of the function s d) The width of the function
hould be 3bits wide. & Size of the variable “y”
should be 3bits wide.
Your answer a Wrong Right answer d

NA
6 Single choice
What is the correct syntax for declaring a real number?
a) real r[1:0]; b) real r;

c) real [1:0] r; d) All of the above
e) None of above
OFFER
NA
7 Single choice
Which of the following is used to customize simulation time?
a) ìfdef b) `timescale
c) `define d) delays
e) None of above
Timescale has Time-unit and Time-precision which is used for customization.
8 Single choice
Which of the following is also called as conditional compiler

OFFER
directive?
a) ìfdef b) $test$plusargs
c) if else d) All of the above
e) None of above
Your answer a Right Time Taken 14s Marks 1 Answer Explanation
ìfdef returns either True or False as per the macro de nition.
9 Single choice
Which system function returns a 64bit simulation time?
a) $realtime b) $time
c) $stime d) All of the above
e) None of above
OFFER

NA
10 Single choice
What should be the data-type for the net a in the below snippet
such that it is driven with a value 1 only if all the 3 drivers “b, c, d”
are driving 1.
a) wor b) trireg
c) wand d) All of the above
OFFER
e) None of above
Your answer a Wrong Right answer c

Wired and is used in continuous concurrent assignments in multiple parallel drivers driving
common node. The wired output goes 1 if all the drivers are driving 1.
11 Single choice
What has to be done in the below code in order to get the shifted
output as 4’b1100? In the existing code the output is evaluated as
4’b0100.
OFFER
a) sum = a + (b >> 1); b) sum = a+b;

c) sum = (a+b+0)>>1; d) All of the above
e) None of above
a+b+0 converts the expression length to 32bit length hence the carry bit is preserved and w
hen shifted by 1 towards right results in 4’b1100.
12 Single choice
What is the output displayed from the below snippet?

OFFER
b) Depends on simulator henc

e output can be A or C
a)
d) Can’t predict
c)
e) None of above
OFFER

When you have processes executing in parallel, there is no deterministic ordering between s
tatements executing at the same time. Both are valid possibilities. Another simulator might
have picked the second for-loop to execute first.
13 Single choice
W hat is the name of the delay used in the below assignment?
a) Inertial delay
b) Regular delay
c) Net delay
d) Inter delay
e) None of above
Your answer b Wrong Right answer a

OFFER
Inertial delay acts like gate component delay.
14 Single choice
What is the display output in the following snippet?
OFFER
a) b)
c) d)
$monitor is called at 10time unit hence will be monitoring the events from current time slot
i.e 10ns.
15 Single choice
OFFER
What is true for the following snippet?
a) It infers a MUX
b) It infers a transparent latch
c) always@* is not a valid sy

ntax
d) Its non-synthesizable
A latch is inferred since else part is missing. iytyuitr

16 Single choice
Which is a valid syntax for $timeformat?
a) $timeformat("String to be b) $timeformat($time);
displayed");
OFFER
c) $timeformat(time_unit,prec d) $timeformat($realtime);
ision_num,suffix string,min
imum field width);
$timeformat is a system task used to set a uniform time for all sub-modules taking part in si
mulation in the display console.
17 Single choice
Which is true for a self-checking testbench?
a) A self-checking Test-Benc b) A self-checking Test-Benc

h checks expected results a h is not allowed in Verilog
gainst actual results (DUT) HDL simulation.
obtained from the simulatio
n.
c) A self-checking Test-Benc d) There is no such concept of
h is similar to Linear task b Self-checking Testbench.
OFFER
ased Testbench.
Your answer a Right Time Taken 24s Marks 1 Answer Explanation
Self-checking Testbenches are testbenches used to compare actual DUT simulation results
with expected values.
18 Single choice
Which of the following is syntactically correct in Verilog HDL?

a) b)
OFFER
c) d)
Your answer b Wrong Right answer c

Automatic tasks are supported in Verilog HDL with automatic keyword before task identifi
er and after task keyword.
19 Single choice
Which of the following are defined regions in a Verilog stratified

event queue?
OFFER
a) Preponed->Active->Inactiv b) Preponed->Active->Inactiv
e->NBA->Postponed e->NBA->Reactive->Postp
oned
c) Active->Inactive->NBA-> d) Active->Inactive->NBA->
Postponed Reactive->Postponed
Your answer b Wrong Right answer c

Verilog has 4 regions which are static: Active->Inactive->NBA->Postponed

20 Single choice
What changes have to be done in the top module in-order to

display “I am b” conditionally?
OFFER
a) b)
OFFER
c) d)
Your answer e Wrong Right answer a

Generate if-else can be used to instantiate module conditionally.
Address Quick links Contact Us
MAVEN SILICON Terms and Call Us +91 9513398555

# 21/1A, III Floor, Marudhar Conditions Email elearn@maven-silicon.com
Avenue, (https://elearn.maven-
Gottigere, Uttarahalli Hobli, silicon.com/policies)
South Taluk, About Us (https://www.facebook.com/Maven-Silicon-
Bannerghatta Road, Bangalore - (https://www.maven- 326974926639)
560076 silicon.com/about-
us) (https://twitter.com/MavenSilicon)
FAQs
(https://elearn.maven-
OFFER
silicon.com/faqs) (https://www.youtube.com/channel/UCu19H6thv_ad_Sl2cG-
Free VLSI Workshop t-jA)
for Freshers
silicon.com/free-
vlsi-workshop-
freshers)
Privacy Policy
silicon.com/privacy-
policy)
VLSI Internship
(https://www.maven-
silicon.com/vlsi-
design-internship)
Enquiry Form
silicon.com/enquiry-
form)
Copyright © 2021 Maven Silicon - Online VLSI Courses
OFFER

Verilog Weekly Quiz 1 - : Questions Right Wrong Unattended Accuracy Time Taken

Uploaded by

Copyright:

Available Formats

Verilog Weekly Quiz 1 - : Questions Right Wrong Unattended Accuracy Time Taken

Uploaded by

Document Information

Original Title

Copyright

Available Formats

Share this document

Share or Embed Document

Sharing Options

Did you find this document useful?

Is this content inappropriate?

Copyright:

Available Formats

Verilog Weekly Quiz 1 - : Questions Right Wrong Unattended Accuracy Time Taken

Uploaded by

Copyright:

Available Formats

4/13/2021 Maven Silicon - Online VLSI Courses

Verilog Weekly Quiz 1 -

View rank list (https://elearn.maven-silicon.com/report/assessment/998)

Process 3 2 1 0 66.67% Average

Data-types 2 1 1 0 50% Needs

Compiler 2 2 0 0 100% Excellent

System function 1 0 1 0 0% Needs

Operators 1 1 0 0 100% Excellent

System task 2 2 0 0 100% Excellent

Testbench 1 1 0 0 100% Excellent

Easy Medium Hard

Right Answers Right Answers 0 Right Answers 0

Wrong Answers Wrong Answers

All questions Compare (https://elearn.maven-silicon.com/report/assessment/998)

a) Previous value of temp1 b) Previous value of temp2

Your answer c Right Time Taken 48s Marks 1 Answer Explanation

Blocking updates are immediate assignments.

What is the reset type from the below Verilog snippet?

a) Active high synchronous re b) Active low synchronous re

c) Active high asynchronous d) Active low asynchronous c

Your answer b Right Time Taken 8s Marks 1 Answer Explanation

For combinational circuit synthesis, which of the following are

a) Feedback connections from b) If “if…else” construct is us

Your answer d Wrong Right answer b

What will the following code segment do?

a) A race condition will occu b) Swaps the values of the var

Your answer b Wrong Right answer a

Time Taken 43s Marks 0 Answer Explanation

Which is a valid bug in the below code?

a) Function should have outp b) The width of the function s

Your answer a Wrong Right answer d

What is the correct syntax for declaring a real number?

a) real r[1:0]; b) real r;

Your answer b Right Time Taken 14s Marks 1 Answer Explanation

Which of the following is used to customize simulation time?

Your answer b Right Time Taken 16s Marks 1 Answer Explanation

Timescale has Time-unit and Time-precision which is used for customization.

Which of the following is also called as conditional compiler

Your answer a Right Time Taken 14s Marks 1 Answer Explanation

`ifdef returns either True or False as per the macro de nition.

Which system function returns a 64bit simulation time?

Your answer d Wrong Right answer b

Your answer a Wrong Right answer c

a) sum = a + (b >> 1); b) sum = a+b;

Your answer c Right Time Taken 17s Marks 1 Answer Explanation

What is the output displayed from the below snippet?

b) Depends on simulator henc

Your answer d Wrong Right answer b

W hat is the name of the delay used in the below assignment?

Your answer b Wrong Right answer a

Time Taken 16s Marks 0 Answer Explanation

Inertial delay acts like gate component delay.

What is the display output in the following snippet?

e) None of the above

Your answer b Right Time Taken 17s Marks 1 Answer Explanation

What is true for the following snippet?

c) always@* is not a valid sy

e) None of the above

Your answer b Right Time Taken 15s Marks 1 Answer Explanation