Addressing modes

The CPU can access operands (data) in various ways, called addressing modes. The number of
addressing modes is determined when microprocessor is designed and cannot be changed. The
80x86 provides a total of seven distinct addressing modes:
1. Register
2. Immediate
3. Direct
4. Register indirect
5. Based relative
6. Indexed relative
7. Based indexed relative
1. Register addressing mode
The register addressing mode involves the use of registers to hold the data to be manipulated.
Memory is not accessed when this addressing mode is executed; therefore, it is relatively fast.
MOV BX, DX
ADD AL, BH
It should be noted that the source and destination registers must match in size.

2.Immediate addressing mode

In the immediate addressing mode, the source operand is a constant. Immediate addressing mode
can be used to load information into any of the registers except the segment registers and flag
registers. Examples:
MOV AX, 2550H : move 2550H into AX
MOV BL, 40H : load 40H into BL
To move information to the segment registers, the data must first be moved to a general-purpose
registers and then to the segment register.
Example: MOV AX, 2550H
MOV DS, AX

3.Direct addressing mode

In direct addressing mode instead of register or direct content, the memory location will be
given. That memory location is the 16 bit offset address. From that address we have to find out
the 20 bit physical address.

MOV DL, [2400] ;mov contents of DS:2400 into DL

Here 2400 is the offset address.
For example: DS=3456 then Physical address=DSx10H+2400
=3456x10H+2400
=36960
So content from the memory location 36960 will be moved to DL.

4.Register indirect addressing mode

The register used for this purposes are SI,DI and BX. If these registers are used as pointers then
they have the offset address that must be combined with DS to generate 20 bit physical address.

MOV AL, [BX] ;mov the content from DS:BX location to AL.
For example: DS=1256 and BX= 1546 then
PA=1256x10+1546=14106.
so the content from memory location 14106 will be moved to AL

5.Based Relative addressing mode

In this addressing mode, the base registers are BX and BP. These register has offset address.

In the case of BX register, DS will be used

MOV CX,[BX]+10 PA=(DSx10H)+BX+10
It can be written as
MOV CX, 10[BX] (or) MOV CX, [BX+10]

In the case of BP register, SS will be used

MOV AL, [BP]+5 PA=(SSx10H)+BP+5

6.Indexed relative addressing mode

Indexed relative addressing mode works the same as based relative addressing mode, except that
register DI and SI holds the offset address
MOV DX, [DI]+5 PA=(ES x10H)+DI+5
MOV CL, [SI]+20 PA=(DS x10H)+SI+20

7.Based Indexed addressing mode

By combining based and indexed addressing modes, a new addressing mode is derived called the
based indexed addressing mode,
MOV CL,[BX][DI]+8 PA=DSx10H+BX+DI+8
MOV CH,[BX][SI]+20 PA=DSx10H+BX+SI+20
MOV AH,[BP][DI]+12 PA=SSx10H+BP+DI+12
MOV AH,[BP][SI]+29 PA=SSx10H+BP+SI+29

8086 Instructions set

1.Data Transfer instructions:
a.MOV instruction
Simply stated that the MOV instruction copies data from one location to another. It has the
following format:
MOV destination, source : copy source operand to destination
The following program first loads CL with value 55H, then moves this value around to various
registers inside the CPU.
MOV CL, 55H
MOV DL, CL

b.XCHG instruction-This instruction is mainly for exchanging the data values between two
registers or between one register and one memory location. The register size must be same.
XCHG destination,source : exchange between source and destination
XCHG AX, DX
c.PUSH instruction
This is used for pushing particular operand on the top of the stack.
PUSH operand
PUSH BX

d.POP instruction
This is used for taking particular operand from the top of the stack and stores it in destination
register
POP destination
POP AX

2,Arithmetic Instructions
a.ADD instruction
These instructions add a number from some source to a number in some destination and put the
result in the specified destination. The source may be an immediate number, a register, or a
memory location. The destination may be a register or a memory location. The source and the
destination in an instruction cannot both be memory locations.
ADD Destination, Source
ADD AL, 74H
ADD DX, AX

b.SUB instruction
These instructions subtract The number in some source from the number in some destination and
put the result in the destination.
SUB Destination, Source
SUB AL, 74H
SUB DX, AX

c.MUL instruction
This instruction multiplies a 8 bit value in some source with a 8 bit value in AL register or a 16
bit value in some source with a 16 bit value in AX register. The source can be a register or a
memory location. When a byte is multiplied by the content of AL. the result (product) is put in
AX. When a word is multiplied by the content of AX, the result is put in DX and AX registers.
MUL Source
MUL BH Multiply signed byte in AL with signed byte in BH; result in AX.
MUL BX Multiply BX with AX ,result in DX and AX registers

d.DIV instruction
This instruction is used to divide a word by a byte .When a word is divided by a byte, the word
must be in the AX register. The divisor can be in a register or a memory location. After the
division.AL will contain the 8-bit quotient, and AH will contain the 8-bit remainder.
DIV Source
DIV BL ; Divide word in AX by byte in BL: Quotient in AL. remainder in AH

e.INC instruction
It increments the byte or word by one.The operand can be a register or memory location.
INC Src
INC AX

f.DEC instruction
It decrements the byte or word by one.The operand can be a register or memory location.
DEC Src
DEC AX

3.Logical Instruction
a. AND instruction
This instruction ANDs each bit in a source byte or word with the same numbered bit in a
destination byte or word. The result is put in the specified destination.

AND Destination, Source

AND BH, CL AND byte in CL with byte in BH: Result in BH

b.OR instruction
This instruction ORs each bit in a source byte or word with the same numbered bit in a
destination byte or word. The result is put in the specified destination.
OR Destination, Source
OR AH, CL ; CL OR ed with AH. Result in AH. CL not changed

c.XOR instruction
This instruction Exclusive-ORs each bit in a source byte or word with the same numbered bit in
a destination byte or word. The result is put in the specified destination.
XOR Destination, Source
XOR CL, BH ;Byte in BH exclusive-ORed with byte in CL. Result in CL. BH not changed.

d.NOT instruction
The NOT instruction inverts each bit (forms the l's complement) of a byte or word in the
specified destination. The destination can be a register or a memory location.
NOT Destination
NOT BX Complement content or BX register

e.NEG instruction
This instruction replaces the number in a destination with its 2's complement. The destination
can be a register or a memory location.
NEG Destination
NEG AL Replace number in AL with its 2's complement

4.Branch Instructions

CALL procedure name

JUMP instruction
This instruction is used to jump to the desired address to proceed to the next instruction.
JMP NEXT -Execute next instruction from the label NEXT

5. Shift Instructions
a. SHR-Shift Right
This instruction simply shifts the mentioned bits in the register to the right side one by one by
inserting the same number of zeroes from the left end. The rightmost bit that is being shifted is
stored in the Carry Flag (CF).
Syntax: SHR Register, Bits
Example: SHR AX, 2

b.SHL-Shift Left
This instruction simply shifts the mentioned bits in the register to the left side one by one by
inserting the same number (bits that are being shifted) of zeroes from the right end. The leftmost
bit that is being shifted is stored in the Carry Flag (CF).
Syntax: SHL Register, Bits
Example: SHL AX, 2

6.Rotate Instruction
a. RCL-Rotate carry left
This instruction rotates the mentioned bits in the register to the left side one by one such that
leftmost bit that is being rotated it is stored in the carry flag(CF), and the bit in the CF moved as
the LSB in the register.
Syntax: RCL Register, Bits
Example: RCL AH, 2

b. RCR-Rotate carry right

This instruction rotates the mentioned bits in the register to the right side one by one such that
rightmost bit that is being rotated it is stored in the carry flag(CF), and the bit in the CF moved as
the MSB in the register.
Syntax: RCR Register, Bits
Example: RCR AH, 2

7.LOOP instruction
This instruction is mainly for repeating the particular block of instruction CX number of times.
After each iteration CX value ll be decremented by one.
LOOP label name
MOV CX,0005H
welcome
ADD AX,0002H
LOOP welcome Here CX=5 then 5 times the loop will be executed.
 8086 PIN CONFIGURATION

8086 is a 16 bit microprocessor. It can handles 16 bit data with the help of 16 bit data bus and 20
bit address bus. Its pin configuration is as follows

AD15-AD0: These are the time multiplexed memory I/O address and data lines. Address
remains on the lines during T1 state, while the data is available on the data bus during T2. T3,
Tw and T4. Here T1, T2. T3, T4 and Tw are the clock states of a machine cycle. Tw is a wait
state.

A19/S6, A18/S5, A17/S4, A16/S3: These are the time multiplexed address and status lines.
During T1 remaining address bits will be transferred. During memory or I/O operations, status
information is available on those lines for T2, T3, Tw and T4 .The status of the interrupt enable
flag bit(displayed on S5) is updated at the beginning of each clock cycle. The S4 and S3
combinedly indicate which segment register is presently being used for memory accesses. S6 bit
always 0.

S4 S3 Indication
0 0 Extra segment
0 1 Stack segment
1 0 Code segment
1 1 Data segment
____
BHE/S7- The bus high enable signal is used to indicate the transfer of data over the higher order
(D15 – D8 ) data bus. It goes low for the data transfers over D15-D8 .S7 bit always 1.
RD-Read: Read signal, when 0 indicates the peripherals that the processor is performing a
memory or I/O read operation. When 1, no read operation
___
WR-Write signal when 0 indicates the peripherals that the processor is performing a memory or
I/O write operation. When 1, no write operation.

READY: This is the acknowledgement from the slow devices or memory that they have
completed the data transfer. When 0, slow devices not ready. when 1,slow devices are ready to
communicate .

INTR-lnterrupt Request: This is sampled during the last clock cycle of each instruction to
determine the availability of the request. when 0, no interrupt request. When 1, interrupt request
has arrived. This can be internally masked by resetting the interrupt enable flag.

TEST: This input is examined by a 'WAIT instruction. If the TEST input goes 0, execution will
continue. When 1, the processor remains in an idle state.

NMI-Non-maskable Interrupt: The NMI is not maskable internally by software. A transition

from 0 to 1 initiates the interrupt response at the end of the current instruction. This input is
internally synchronized.

RESET: This input causes the processor to terminate the current activity and start execution
from FFFFFH. The signal is 1 and must be active for at least four clock cycles. It restarts
execution when the RESET returns 0. RESET is also internally synchronized.

CLK-Clock Input: The clock input provides the basic timing for processor operation and bus
control activity. The range of frequency for different 8086 versions is from 5 MHz to 10MHz.

Vcc : +5V power supply for the operation of the internal circuit. GND ground for the internal
circuit.
___
MN/MX :The logic level at this pin decides whether the processor is to operate in either
minimum (single processor) or maximum (multiprocessor) mode. When 0,maximum mode.
When 1. Minimum mode.

The following pin functions are for the minimum mode operation of 8086.
__ __
M/IO -Memory/IO:. When it is 0, it indicates the CPU is having an I/O operation, and when it
is 1, it indicates that the CPU is having a memory operation.
_____
INTA -Interrupt Acknowledge: This signal is used for interrupt acknowledge cycles. In other
words, when it goes 0, it means that the processor has accepted the interrupt. When 1, it indicates
the interrupt rejection.

ALE-Address latch Enable: This output signal indicates the availability of the valid address on
the address/data lines. When 1,indicates address transfer. When 0, no address transfer.
 __
DT /R -Data Transmit/Receive: This pin is used to decide the direction of data flow through
the transreceivers (bidirectional buffers). When the processor sends out data, this signal is 1 and
when the processor is receiving data, this signal is 0.
____
DEN-Data Enable This signal indicates the availability of valid data over the address/data lines.
When 0, indicates data transfer. When 1, indicates no data.

HOLD, HLDA-Hold/Hold Acknowledge: When the HOLD line is 1, it indicates to the

processor that another master is requesting the bus access. When the HOLD line is 0,no bus
request
The processor, after receiving the HOLD request, issues the hold acknowledge signal on HLDA
pin, in the middle of the next clock cycle after completing the current bus (instruction) cycle.
When 0,request accepted. When 1, request rejected. At the same time, the processor floats the
local bus and control lines.
The following pin functions are applicable for maximum mode operation of 8086.
__ __ __
S2, S1, S0 -Status Lines: These are the status lines which reflect the type of operation, being
carried out by the processor. These become active during T4 of the previous cycle
__ __ __
S2 S1 S0 Indication
0 0 0 INTA
0 0 1 Read I/O
0 1 0 Write I/O
0 1 1 Halt
1 0 0 Code access
1 0 1 Read memory
1 1 0 Write memory
1 1 1 None

______
LOCK: When ‘0’, This output pin indicates that other system bus masters will be prevented
from gaining the system bus. When ‘1’, the lock is disabled.The LOCK_signal is activated by the
'LOCK' prefix instruction and remains active until the completion of the next instruction.

QS1, QSo-Queue Status: These lines give information about the status of the code-prefetch
queue. These are active during the CLK cycle after which the queue operation is performed.

_______ _______
RQ/GT0, RQ/GT1-ReQuest/Grant: These pins are used by other local bus masters, in maximum
mode, to force the processor to release the local bus at the end of the processor's current bus
cycle. Each of the pins is bidirectional with RQ/GTo having higher priority than RQ/ GT1.
 SYSTEM BUS TIMING
□ T-State:
— One clock period is referred to as a T-State

'
— An operation takes an integer number of T-States.

□ CPU Bus Cycle:

— A bus cycle consists of 4 or more T-States

WAIT STATE

 A wait state(Tw) is an extra clocking period, inserted between T2 and T3, to lengthen the
bus cycle, allowing slower memory and I/O components to respond.
 The READY input is sampled at the end of T2 and again, if necessary in the middle of
Tw. If READY is ‘0’ then Tw is inserted.
COPROCESSOR

 A coprocessor is a computer processor used to supplement the functions of the primary

processor (the CPU). Operations performed by the coprocessor may be floating point
arithmetic, graphics, signal processing, string processing, encryption or I/O Interfacing
with peripheral devices. By offloading processor-intensive tasks from the main processor,
coprocessors can accelerate system performance.
 A coprocessor is a specially designed microprocessor, which can handle its particular
function many times faster than the ordinary microprocessor. The coprocessor shares the
same memory, IO system, bus, control logic and clock generator.

Block Diagram of Coprocessor Configuration

 INTERRUPT
• Interrupts' is to break the sequence of operation.
• While the CPU is executing a program, on 'interrupt' breaks the normal sequence of execution
of instructions, diverts its execution to some other program called Interrupt Service Routine
(ISR)
An interrupt is an external or internal event that interrupts the microcontroller to inform it that a
device needs its service

Ty
pes of interrupts

Hardware Interrupts-This interrupts are used to handle hardware peripheral devices such as
mouse, keyboard, hard disk, Floppy disk and printer.

• Maskable Interrupt: An Interrupt that can be disabled or ignored by the instructions of

CPU by setting IF=0 are called as Maskable Interrupt.

• Non- Maskable Interrupt: An interrupt that cannot be disabled or ignored by the

instructions of CPU by setting IF=0 are called as Non- Maskable Interrupt.
Software Interrupts -Software interrupts are machine instructions that amount to a call to the
designated interrupt subroutine, usually identified by interrupt number. Ex: INT0 - INT255

Interrupt controller-INTEL 8259

If we are working with an 8086, we have a problem here because the 8086 has only two interrupt
inputs, NMI and INTR.
For applications where we have interrupts from multiple source, we use an external device called
a priority interrupt controller (PIC ) to the interrupt signals into a single interrupt input on the
processor.
Architecture and Signal Descriptions of 8259
Interrupt Request Register (IRR): The interrupts at IR0-IR7 input lines are handled by
Interrupt Request register internally. IRR stores the entire interrupt request in it in order to serve
them one by one on the priority basis.
In-Service Register (ISR): This stores all the interrupt requests those are being served, i.e. ISR
keeps a track of the requests being served.
Priority Resolver: This unit determines that among all the interrupt requests present in the IRR
which holds the highest priority and needs to be executed first. The IR0 has the highest priority
while the IR7 has the lowest one, normally in fixed priority mode.

Interrupt Mask Register (IMR): This register stores the bits required to mask the interrupt
inputs. Through operation command word(OCW), the processor sends the required information
and programs the IMR.

Interrupt Control Logic: It is the center of the microprocessor and controls the functioning of
every block. This block controls overall operation of the system by sending INTR signal to the
processor whenever an interrupt request is generated. This also accepts the interrupt
acknowledge (INTA) signal from CPU that causes the 8259 to release address of the ISR on to
the data bus.
Data Bus Buffer: This block is used as mediator between 8086 and 8259 by acting as a buffer. It
takes the control word from the 8086 and transfers it to the control logic of 8259. Then it
transfers the opcode of the interrupt and address of the ISR from the 8259 to the 8086
microprocessor This block contains of 8 bits represented as D0-D7.so it can transfer 8 bits at a
time.
Read/Write Control Logic: This block works when the value of CS pin is 0. This circuit
accepts and decodes commands from the 8086 after having 0 in WR pin. This block also allows
the status of the 8259 to be transferred on to the data bus to 8086 after having 0 in RD pin. The
processor selects low port when A0=0 and selects high port when A0=1.

Cascade Buffer/Comparator: This block used to connect two or more 8259 microprocessor
with 8086 so that the interrupt handled by 8259 can be expanded upto 64. The unit allows the
comparison of IDs of different 8259s cascaded together . The three I/O pins CASO-2 are outputs
when the 8259 is used as a master. The same pins act as inputs when the 8259 is in slave mode.
The 8259 in master mode sends the ID of the interrupting slave device on these lines. When
SP/EN pin is 0 then that 8259 is a slave or else that 8259 is a master.
 Modular Programming
Modular programming is the process of subdividing a computer program into separate sub
programs. Program is composed from several smaller modules. Modules could be developed by
separate teams concurrently. Each module is produced from a separate Assembly Language
program. The source modules are get converted .OBJ modules (Object modules) by the
assembler.
The .OBJ modules so produced are combined using a LINK program. Frequently used
procedures could be assembled into object modules and these object modules are placed in a
Library file that is linked into the application. Note that only the required object modules are
pulled from the Library to be linked to the final application.
LIBRARIES:

A function or procedure is a group of statements with a unique name that performs a specific
task. Frequently used functions or procedures for a given application domain may be placed in a
Library File as .OBJ files. The Library file can be specified at LINK time. Library files in our
program are included in last stage by special software called as linker. Only the required .OBJ
files are extracted from the Library File and linked to the program. Thus, Libraries provide a
powerful reuse mechanism.

Types of Library

There are two types of libraries. They are

1. Static library

When using static library, code from the library will be written into your program. So it takes
less time for execution because the code is already available. Object code files will be larger
when using Static libraries so it needs more space. If you need to update any files in static
library, you have to recompile all the programs which contain library file’s code in it. It will have
.lib extension.

2. Dynamic library

When using Dynamic library, only the memory address of the code from the library will be
written into your program. So the necessary code can be retrieved from the Dynamic library at
run time. It takes more time for execution because during run time only the code will be retrieved
from memory. But it requires less space. If you need to update any files in Dynamic library,
instead of recompiling all the programs, simply update the files in Dynamic library. It will have
.dll extension.

Linking
LINKER
• A linker is a program used to join together several object files into one large object file.
• The linker produces a link file which contains the binary codes for all the combined modules.
The linker program is invoked using the following options. LINK or LINK MS.OBJ
LOADER
 Loader is a utility program which takes object code as input prepares it for execution and
loads the executable code into the memory.
 Loader is actually responsible for initializing the process of execution.
 Programmers usually define the program to be loaded at some predefined location in the
memory.
 But this loading address given by the programmer is not being coordinated with the OS.
 The loader does the job of coordinating with the OS to get initial loading address for
the .exe file and load it into the memory.
 It reallocates the linked file and creates a file for permanent location of codes in a
standard format.

Functions of loaders:
1.Allocation
It allocates the space for program in the memory by calculating the size of the program.
2.Relocation
It modifies the object program by changing the certain instructions so that it can be loaded at
different address from location originally specified.
3. Loading
It brings the object program into the memory for execution. It also places all the machine
instructions and data of corresponding programs and subroutines into the memory.

Creation and execution of a program

 MICROCONTROLLER

A microcontroller is a computer present in a single integrated circuit which is dedicated to

perform one task and execute one specific application.
It contains memory, programmable input/output peripherals as well a processor. Microcontrollers
are mostly designed for embedded applications and are heavily used in automatically controlled
electronic devices such as cellphones, cameras, microwave ovens, washing machines, etc.