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    Verilog Single Port RAM

    Uploaded by

    Suhas Shirol
    This document provides an overview of Verilog concepts and code examples. It introduces Verilog basics like data types and building blocks such as modules and ports. It also covers behavioral modeling, gate/switch modeling, simulation, system tasks and functions, and includes examples for common components like flip-flops, counters, and a single-port RAM.

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    © All Rights Reserved
    Download as PDF, TXT or read online from Scribd

    Verilog Single Port RAM

    Uploaded by

    Suhas Shirol
    48 views10 pages
    This document provides an overview of Verilog concepts and code examples. It introduces Verilog basics like data types and building blocks such as modules and ports. It also covers behavioral modeling, gate/switch modeling, simulation, system tasks and functions, and includes examples for common components like flip-flops, counters, and a single-port RAM.

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    Verilog Single Port RAM

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    This document provides an overview of Verilog concepts and code examples. It introduces Verilog basics like data types and building blocks such as modules and ports. It also covers behavioral modeling, gate/switch modeling, simulation, system tasks and functions, and includes examples for common components like flip-flops, counters, and a single-port RAM.

    Copyright:

    © All Rights Reserved
    Download as PDF, TXT or read online from Scribd
    Download as pdf or txt
    48 views10 pages

    Verilog Single Port RAM

    Uploaded by

    Suhas Shirol
    This document provides an overview of Verilog concepts and code examples. It introduces Verilog basics like data types and building blocks such as modules and ports. It also covers behavioral modeling, gate/switch modeling, simulation, system tasks and functions, and includes examples for common components like flip-flops, counters, and a single-port RAM.

    Copyright:

    © All Rights Reserved
    Download as PDF, TXT or read online from Scribd
    Download as pdf or txt
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    Verilog Posts

    Introduction

      What is Verilog? (/verilog/verilog-tutorial)

      Introduction to Verilog (/verilog/verilog-introduction)

      Chip Design Flow (/verilog/asic-soc-chip-design-flow)

      Chip Abstraction Layers (/verilog/verilog-design-abstraction-layers)

    Data Types

      Verilog Syntax (/verilog/verilog-syntax)

      Verilog Data types (/verilog/verilog-data-types)

      Verilog Scalar/Vector (/verilog/verilog-scalar-vector)

      Verilog Arrays (/verilog/verilog-arrays)

    Building Blocks

      Verilog Module (/verilog/verilog-modules)

      Verilog Port (/verilog/verilog-ports)

      Verilog Module Instantiations (/verilog/verilog-module-instantiations)

      Verilog assign statements (/verilog/verilog-assign-statement)

      Verilog assign examples (/verilog/verilog-combinational-logic-


    assign)

      Verilog Operators (/verilog/verilog-operators)

      Verilog Concatenation (/verilog/verilog-concatenation)

      Verilog always block (/verilog/verilog-always-block)

      Combo Logic with always (/verilog/verilog-combinational-logic-


    always)

      Sequential Logic with always (/verilog/verilog-always-sequential-


    logic)

      Verilog initial block (/verilog/verilog-initial-block)

      Verilog in a nutshell (/verilog/verilog-in-a-nutshell)

      Verilog generate (/verilog/verilog-generate-block)

      Verilog Sequence Detector (/verilog/verilog-sequence-detector)

      Verilog Pattern Detector (/verilog/verilog-pattern-detector)

    Behavioral modeling

      Verilog Block Statements (/verilog/verilog-block-statements)

      Verilog Assignment Types (/verilog/verilog-assignments)

      Verilog Blocking/Non-blocking (/verilog/verilog-blocking-non-blocking-


    statements)

      Verilog Control Flow (/verilog/verilog-control-block)

      Verilog for Loop (/verilog/verilog-for-loop)

      Verilog case Statement (/verilog/verilog-case-statement)

      Verilog Functions (/verilog/verilog-functions)

      Verilog Tasks (/verilog/verilog-task)

      Verilog Parameters (/verilog/verilog-parameters)

      Verilog `ifdef `elsif (/verilog/verilog-ifdef-conditional-compilation)

      Verilog Delay Control (/verilog/verilog-timing-control)

      Verilog Inter/Intra Delay (/verilog/verilog-inter-and-intra-assignment-


    delay)

      Verilog Hierarchical Reference (/verilog/verilog-hierarchical-


    reference-scope)

    Gate/Switch modeling

      Gate Level Modeling (/verilog/verilog-gate-level-modeling)

      Gate Level Examples (/verilog/verilog-gate-level-examples)

      Gate Delays (/verilog/verilog-gate-delay)

      Switch Level Modeling (/verilog/verilog-switch-level-modeling)

      User-Defined Primitives (/verilog/verilog-udp)

    Simulation

      Verilog Simulation Basics (/verilog/verilog-simulation)

      Verilog Timescale (/verilog/verilog-timescale)

      Verilog Scheduling Regions (/verilog/verilog-scheduling-semantics)

      Verilog Clock Generator (/verilog/verilog-clock-generator)

    System Tasks and Functions

      Verilog Display tasks (/verilog/verilog-display-tasks)

      Verilog Math Functions (/verilog/verilog-math-functions)

      Verilog Timeformat (/verilog/verilog-timeformat)

      Verilog Timescale Scope (/verilog/verilog-timescale-scope)

      Verilog File Operations (/verilog/verilog-file-io-operations)

    Code Examples

      Hello World! (/verilog/verilog-hello-world)

      Flops and Latches

      JK Flip-Flop (/verilog/verilog-jk-flip-flop)

      D Flip-Flop (/verilog/verilog-d-flip-flop-async-reset)

      T Flip-Flop (/verilog/verilog-tff)

      D Latch (/verilog/verilog-d-latch)

      Counters

      4-bit counter (/verilog/verilog-4-bit-counter)

      Ripple Counter (/verilog/verilog-ripple-counter-dff)

      Straight Ring Counter (/verilog/verilog-ring-counter)

      Johnson Counter (/verilog/verilog-johnson-counter)

      Mod-N Counter (/verilog/verilog-modn-counter)

      Gray Counter (/verilog/verilog-gray-counter)

      Misc

      n-bit Shift Register (/verilog/verilog-n-bit-shift-register)

      Priority Encoder (/verilog/verilog-priority-encoder)

      4x1 multiplexer (/verilog/verilog-4to1-mux)

      Full adder (/verilog/verilog-full-adder)

      Single Port RAM (/verilog/verilog-single-port-ram)

    Verilog Single Port RAM

    D i
    Design

    1 module single_port_sync_ram
    2 # (parameter ADDR_WIDTH = 4,

    3 parameter DATA_WIDTH = 32,

    4 parameter DEPTH = 16

    5 )

    7 ( input clk,

    8 input [ADDR_WIDTH-1:0] addr,

    9 inout [DATA_WIDTH-1:0] data,

    10 input cs,

    11 input we,

    12 input oe

    13 );

    14

    15 reg [DATA_WIDTH-1:0] tmp_data;

    16 reg [DATA_WIDTH-1:0] mem [DEPTH];

    17

    18 always @ (posedge clk) begin

    19 if (cs & we)

    20 mem[addr] <= data;

    21 end

    22

    23 always @ (posedge clk) begin

    24 if (cs & !we)

    25 tmp_data <= mem[addr];

    26 end

    27

    28 assign data = cs & oe & !wr ? tmp_data : 'hz;

    29 endmodule

    (/images/verilog/schematic/single_port_ram_ar_aw.png)

    T tb h
    Testbench

    1 module tb;

    2 parameter ADDR_WIDTH = 4;

    3 parameter DATA_WIDTH = 16;

    4 parameter DEPTH = 16;

    6 reg clk;

    7 reg cs;

    8 reg we;

    9 reg oe;

    10 reg [ADDR_WIDTH-1:0] addr;

    11 wire [DATA_WIDTH-1:0] data;

    12 reg [DATA_WIDTH-1:0] tb_data;

    13

    14 single_port_sync_ram #(.DATA_WIDTH(DATA_WIDTH))
    15 ( .clk(clk),

    16 .addr(addr),

    17 .data(data),

    18 .cs(cs),

    19 .we(we),

    20 .oe(oe)

    21 );

    22

    23

    24 always #10 clk = ~clk;

    25 assign data = !oe ? tb_data : 'hz;

    26

    27 initial begin

    28 {clk, cs, we, addr, tb_data, oe} <= 0;

    29

    30 repeat (2) @ (posedge clk);

    31

    32 for (integer i = 0; i < 2**ADDR_WIDTH; i= i+1


    33 repeat (1) @(posedge clk) addr <= i; we <=
    34 end

    35

    36 for (integer i = 0; i < 2**ADDR_WIDTH; i= i+1


    37 repeat (1) @(posedge clk) addr <= i; we <=
    38 end

    39

    40 #20 $finish;

    41 end

    42 endmodule
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